drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28 #include "dc_bios_types.h"
  29 #include "core_types.h"
  30 #include "core_status.h"
  31 #include "resource.h"
  32 #include "dm_helpers.h"
  33 #include "dce110_hwseq.h"
  34 #include "dce110/dce110_timing_generator.h"
  35 #include "dce/dce_hwseq.h"
  36 #include "gpio_service_interface.h"
  37
  38 #include "dce110/dce110_compressor.h"
  39
  40 #include "bios/bios_parser_helper.h"
  41 #include "timing_generator.h"
  42 #include "mem_input.h"
  43 #include "opp.h"
  44 #include "ipp.h"
  45 #include "transform.h"
  46 #include "stream_encoder.h"
  47 #include "link_encoder.h"
  48 #include "link_enc_cfg.h"
  49 #include "link_hwss.h"
  50 #include "link.h"
  51 #include "dccg.h"
  52 #include "clock_source.h"
  53 #include "clk_mgr.h"
  54 #include "abm.h"
  55 #include "audio.h"
  56 #include "reg_helper.h"
  57 #include "panel_cntl.h"
  58 #include "dpcd_defs.h"
  59 /* include DCE11 register header files */
  60 #include "dce/dce_11_0_d.h"
  61 #include "dce/dce_11_0_sh_mask.h"
  62 #include "custom_float.h"
  63
  64 #include "atomfirmware.h"
  65
  66 #include "dcn10/dcn10_hwseq.h"
  67
  68 #define GAMMA_HW_POINTS_NUM 256
  69
  70 /*
  71  * All values are in milliseconds;
  72  * For eDP, after power-up/power/down,
  73  * 300/500 msec max. delay from LCDVCC to black video generation
  74  */
  75 #define PANEL_POWER_UP_TIMEOUT 300
  76 #define PANEL_POWER_DOWN_TIMEOUT 500
  77 #define HPD_CHECK_INTERVAL 10
  78 #define OLED_POST_T7_DELAY 100
  79 #define OLED_PRE_T11_DELAY 150
  80
  81 #define CTX \
  82         hws->ctx
  83
  84 #define DC_LOGGER \
  85         ctx->logger
  86 #define DC_LOGGER_INIT() \
  87         struct dc_context *ctx = dc->ctx
  88
  89 #define REG(reg)\
  90         hws->regs->reg
  91
  92 #undef FN
  93 #define FN(reg_name, field_name) \
  94         hws->shifts->field_name, hws->masks->field_name
  95
  96 struct dce110_hw_seq_reg_offsets {
  97         uint32_t crtc;
  98 };
  99
 100 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
 101 {
 102         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 103 },
 104 {
 105         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 106 },
 107 {
 108         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 109 },
 110 {
 111         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 112 }
 113 };
 114
 115 #define HW_REG_BLND(reg, id)\
 116         (reg + reg_offsets[id].blnd)
 117
 118 #define HW_REG_CRTC(reg, id)\
 119         (reg + reg_offsets[id].crtc)
 120
 121 #define MAX_WATERMARK 0xFFFF
 122 #define SAFE_NBP_MARK 0x7FFF
 123
 124 /*******************************************************************************
 125  * Private definitions
 126  ******************************************************************************/
 127 /***************************PIPE_CONTROL***********************************/
 128 static void dce110_init_pte(struct dc_context *ctx)
 129 {
 130         uint32_t addr;
 131         uint32_t value = 0;
 132         uint32_t chunk_int = 0;
 133         uint32_t chunk_mul = 0;
 134
 135         addr = mmUNP_DVMM_PTE_CONTROL;
 136         value = dm_read_reg(ctx, addr);
 137
 138         set_reg_field_value(
 139                 value,
 140                 0,
 141                 DVMM_PTE_CONTROL,
 142                 DVMM_USE_SINGLE_PTE);
 143
 144         set_reg_field_value(
 145                 value,
 146                 1,
 147                 DVMM_PTE_CONTROL,
 148                 DVMM_PTE_BUFFER_MODE0);
 149
 150         set_reg_field_value(
 151                 value,
 152                 1,
 153                 DVMM_PTE_CONTROL,
 154                 DVMM_PTE_BUFFER_MODE1);
 155
 156         dm_write_reg(ctx, addr, value);
 157
 158         addr = mmDVMM_PTE_REQ;
 159         value = dm_read_reg(ctx, addr);
 160
 161         chunk_int = get_reg_field_value(
 162                 value,
 163                 DVMM_PTE_REQ,
 164                 HFLIP_PTEREQ_PER_CHUNK_INT);
 165
 166         chunk_mul = get_reg_field_value(
 167                 value,
 168                 DVMM_PTE_REQ,
 169                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 170
 171         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 172
 173                 set_reg_field_value(
 174                         value,
 175                         255,
 176                         DVMM_PTE_REQ,
 177                         MAX_PTEREQ_TO_ISSUE);
 178
 179                 set_reg_field_value(
 180                         value,
 181                         4,
 182                         DVMM_PTE_REQ,
 183                         HFLIP_PTEREQ_PER_CHUNK_INT);
 184
 185                 set_reg_field_value(
 186                         value,
 187                         4,
 188                         DVMM_PTE_REQ,
 189                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 190
 191                 dm_write_reg(ctx, addr, value);
 192         }
 193 }
 194 /**************************************************************************/
 195
 196 static void enable_display_pipe_clock_gating(
 197         struct dc_context *ctx,
 198         bool clock_gating)
 199 {
 200         /*TODO*/
 201 }
 202
 203 static bool dce110_enable_display_power_gating(
 204         struct dc *dc,
 205         uint8_t controller_id,
 206         struct dc_bios *dcb,
 207         enum pipe_gating_control power_gating)
 208 {
 209         enum bp_result bp_result = BP_RESULT_OK;
 210         enum bp_pipe_control_action cntl;
 211         struct dc_context *ctx = dc->ctx;
 212         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 213
 214         if (power_gating == PIPE_GATING_CONTROL_INIT)
 215                 cntl = ASIC_PIPE_INIT;
 216         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 217                 cntl = ASIC_PIPE_ENABLE;
 218         else
 219                 cntl = ASIC_PIPE_DISABLE;
 220
 221         if (controller_id == underlay_idx)
 222                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 223
 224         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
 225
 226                 bp_result = dcb->funcs->enable_disp_power_gating(
 227                                                 dcb, controller_id + 1, cntl);
 228
 229                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 230                  * by default when command table is called
 231                  *
 232                  * Bios parser accepts controller_id = 6 as indicative of
 233                  * underlay pipe in dce110. But we do not support more
 234                  * than 3.
 235                  */
 236                 if (controller_id < CONTROLLER_ID_MAX - 1)
 237                         dm_write_reg(ctx,
 238                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 239                                 0);
 240         }
 241
 242         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 243                 dce110_init_pte(ctx);
 244
 245         if (bp_result == BP_RESULT_OK)
 246                 return true;
 247         else
 248                 return false;
 249 }
 250
 251 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 252                 const struct dc_plane_state *plane_state)
 253 {
 254         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 255
 256         switch (plane_state->format) {
 257         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 258                 prescale_params->scale = 0x2082;
 259                 break;
 260         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 261         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 262                 prescale_params->scale = 0x2020;
 263                 break;
 264         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 265         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 266                 prescale_params->scale = 0x2008;
 267                 break;
 268         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 269         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 270         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 271                 prescale_params->scale = 0x2000;
 272                 break;
 273         default:
 274                 ASSERT(false);
 275                 break;
 276         }
 277 }
 278
 279 static bool
 280 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 281                                const struct dc_plane_state *plane_state)
 282 {
 283         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 284         const struct dc_transfer_func *tf = NULL;
 285         struct ipp_prescale_params prescale_params = { 0 };
 286         bool result = true;
 287
 288         if (ipp == NULL)
 289                 return false;
 290
 291         if (plane_state->in_transfer_func)
 292                 tf = plane_state->in_transfer_func;
 293
 294         build_prescale_params(&prescale_params, plane_state);
 295         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 296
 297         if (plane_state->gamma_correction &&
 298                         !plane_state->gamma_correction->is_identity &&
 299                         dce_use_lut(plane_state->format))
 300                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 301
 302         if (tf == NULL) {
 303                 /* Default case if no input transfer function specified */
 304                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 305         } else if (tf->type == TF_TYPE_PREDEFINED) {
 306                 switch (tf->tf) {
 307                 case TRANSFER_FUNCTION_SRGB:
 308                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 309                         break;
 310                 case TRANSFER_FUNCTION_BT709:
 311                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 312                         break;
 313                 case TRANSFER_FUNCTION_LINEAR:
 314                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 315                         break;
 316                 case TRANSFER_FUNCTION_PQ:
 317                 default:
 318                         result = false;
 319                         break;
 320                 }
 321         } else if (tf->type == TF_TYPE_BYPASS) {
 322                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 323         } else {
 324                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 325                 result = false;
 326         }
 327
 328         return result;
 329 }
 330
 331 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 332                                     struct curve_points *arr_points,
 333                                     uint32_t hw_points_num)
 334 {
 335         struct custom_float_format fmt;
 336
 337         struct pwl_result_data *rgb = rgb_resulted;
 338
 339         uint32_t i = 0;
 340
 341         fmt.exponenta_bits = 6;
 342         fmt.mantissa_bits = 12;
 343         fmt.sign = true;
 344
 345         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 346                                             &arr_points[0].custom_float_x)) {
 347                 BREAK_TO_DEBUGGER();
 348                 return false;
 349         }
 350
 351         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 352                                             &arr_points[0].custom_float_offset)) {
 353                 BREAK_TO_DEBUGGER();
 354                 return false;
 355         }
 356
 357         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 358                                             &arr_points[0].custom_float_slope)) {
 359                 BREAK_TO_DEBUGGER();
 360                 return false;
 361         }
 362
 363         fmt.mantissa_bits = 10;
 364         fmt.sign = false;
 365
 366         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 367                                             &arr_points[1].custom_float_x)) {
 368                 BREAK_TO_DEBUGGER();
 369                 return false;
 370         }
 371
 372         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 373                                             &arr_points[1].custom_float_y)) {
 374                 BREAK_TO_DEBUGGER();
 375                 return false;
 376         }
 377
 378         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 379                                             &arr_points[1].custom_float_slope)) {
 380                 BREAK_TO_DEBUGGER();
 381                 return false;
 382         }
 383
 384         fmt.mantissa_bits = 12;
 385         fmt.sign = true;
 386
 387         while (i != hw_points_num) {
 388                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 389                                                     &rgb->red_reg)) {
 390                         BREAK_TO_DEBUGGER();
 391                         return false;
 392                 }
 393
 394                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 395                                                     &rgb->green_reg)) {
 396                         BREAK_TO_DEBUGGER();
 397                         return false;
 398                 }
 399
 400                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 401                                                     &rgb->blue_reg)) {
 402                         BREAK_TO_DEBUGGER();
 403                         return false;
 404                 }
 405
 406                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 407                                                     &rgb->delta_red_reg)) {
 408                         BREAK_TO_DEBUGGER();
 409                         return false;
 410                 }
 411
 412                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 413                                                     &rgb->delta_green_reg)) {
 414                         BREAK_TO_DEBUGGER();
 415                         return false;
 416                 }
 417
 418                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 419                                                     &rgb->delta_blue_reg)) {
 420                         BREAK_TO_DEBUGGER();
 421                         return false;
 422                 }
 423
 424                 ++rgb;
 425                 ++i;
 426         }
 427
 428         return true;
 429 }
 430
 431 #define MAX_LOW_POINT      25
 432 #define NUMBER_REGIONS     16
 433 #define NUMBER_SW_SEGMENTS 16
 434
 435 static bool
 436 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 437                                       struct pwl_params *regamma_params)
 438 {
 439         struct curve_points *arr_points;
 440         struct pwl_result_data *rgb_resulted;
 441         struct pwl_result_data *rgb;
 442         struct pwl_result_data *rgb_plus_1;
 443         struct fixed31_32 y_r;
 444         struct fixed31_32 y_g;
 445         struct fixed31_32 y_b;
 446         struct fixed31_32 y1_min;
 447         struct fixed31_32 y3_max;
 448
 449         int32_t region_start, region_end;
 450         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 451
 452         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 453                 return false;
 454
 455         arr_points = regamma_params->arr_points;
 456         rgb_resulted = regamma_params->rgb_resulted;
 457         hw_points = 0;
 458
 459         memset(regamma_params, 0, sizeof(struct pwl_params));
 460
 461         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 462                 /* 16 segments
 463                  * segments are from 2^-11 to 2^5
 464                  */
 465                 region_start = -11;
 466                 region_end = region_start + NUMBER_REGIONS;
 467
 468                 for (i = 0; i < NUMBER_REGIONS; i++)
 469                         seg_distr[i] = 4;
 470
 471         } else {
 472                 /* 10 segments
 473                  * segment is from 2^-10 to 2^1
 474                  * We include an extra segment for range [2^0, 2^1). This is to
 475                  * ensure that colors with normalized values of 1 don't miss the
 476                  * LUT.
 477                  */
 478                 region_start = -10;
 479                 region_end = 1;
 480
 481                 seg_distr[0] = 4;
 482                 seg_distr[1] = 4;
 483                 seg_distr[2] = 4;
 484                 seg_distr[3] = 4;
 485                 seg_distr[4] = 4;
 486                 seg_distr[5] = 4;
 487                 seg_distr[6] = 4;
 488                 seg_distr[7] = 4;
 489                 seg_distr[8] = 4;
 490                 seg_distr[9] = 4;
 491                 seg_distr[10] = 0;
 492                 seg_distr[11] = -1;
 493                 seg_distr[12] = -1;
 494                 seg_distr[13] = -1;
 495                 seg_distr[14] = -1;
 496                 seg_distr[15] = -1;
 497         }
 498
 499         for (k = 0; k < 16; k++) {
 500                 if (seg_distr[k] != -1)
 501                         hw_points += (1 << seg_distr[k]);
 502         }
 503
 504         j = 0;
 505         for (k = 0; k < (region_end - region_start); k++) {
 506                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 507                 start_index = (region_start + k + MAX_LOW_POINT) *
 508                                 NUMBER_SW_SEGMENTS;
 509                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 510                                 i += increment) {
 511                         if (j == hw_points - 1)
 512                                 break;
 513                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 514                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 515                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 516                         j++;
 517                 }
 518         }
 519
 520         /* last point */
 521         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 522         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 523         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 524         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 525
 526         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 527                                              dc_fixpt_from_int(region_start));
 528         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 529                                              dc_fixpt_from_int(region_end));
 530
 531         y_r = rgb_resulted[0].red;
 532         y_g = rgb_resulted[0].green;
 533         y_b = rgb_resulted[0].blue;
 534
 535         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 536
 537         arr_points[0].y = y1_min;
 538         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 539                                                  arr_points[0].x);
 540
 541         y_r = rgb_resulted[hw_points - 1].red;
 542         y_g = rgb_resulted[hw_points - 1].green;
 543         y_b = rgb_resulted[hw_points - 1].blue;
 544
 545         /* see comment above, m_arrPoints[1].y should be the Y value for the
 546          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 547          */
 548         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 549
 550         arr_points[1].y = y3_max;
 551
 552         arr_points[1].slope = dc_fixpt_zero;
 553
 554         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 555                 /* for PQ, we want to have a straight line from last HW X point,
 556                  * and the slope to be such that we hit 1.0 at 10000 nits.
 557                  */
 558                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 559
 560                 arr_points[1].slope = dc_fixpt_div(
 561                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 562                                 dc_fixpt_sub(end_value, arr_points[1].x));
 563         }
 564
 565         regamma_params->hw_points_num = hw_points;
 566
 567         k = 0;
 568         for (i = 1; i < 16; i++) {
 569                 if (seg_distr[k] != -1) {
 570                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 571                         regamma_params->arr_curve_points[i].offset =
 572                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 573                 }
 574                 k++;
 575         }
 576
 577         if (seg_distr[k] != -1)
 578                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 579
 580         rgb = rgb_resulted;
 581         rgb_plus_1 = rgb_resulted + 1;
 582
 583         i = 1;
 584
 585         while (i != hw_points + 1) {
 586                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 587                         rgb_plus_1->red = rgb->red;
 588                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 589                         rgb_plus_1->green = rgb->green;
 590                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 591                         rgb_plus_1->blue = rgb->blue;
 592
 593                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 594                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 595                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 596
 597                 ++rgb_plus_1;
 598                 ++rgb;
 599                 ++i;
 600         }
 601
 602         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 603
 604         return true;
 605 }
 606
 607 static bool
 608 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 609                                 const struct dc_stream_state *stream)
 610 {
 611         struct transform *xfm = pipe_ctx->plane_res.xfm;
 612
 613         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 614         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 615
 616         if (stream->out_transfer_func &&
 617             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 618             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 619                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 620         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 621                                                          &xfm->regamma_params)) {
 622                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 623                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 624         } else {
 625                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 626         }
 627
 628         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 629
 630         return true;
 631 }
 632
 633 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 634 {
 635         bool is_hdmi_tmds;
 636         bool is_dp;
 637
 638         ASSERT(pipe_ctx->stream);
 639
 640         if (pipe_ctx->stream_res.stream_enc == NULL)
 641                 return;  /* this is not root pipe */
 642
 643         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 644         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 645
 646         if (!is_hdmi_tmds && !is_dp)
 647                 return;
 648
 649         if (is_hdmi_tmds)
 650                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 651                         pipe_ctx->stream_res.stream_enc,
 652                         &pipe_ctx->stream_res.encoder_info_frame);
 653         else {
 654                 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
 655                         pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
 656                                 pipe_ctx->stream_res.stream_enc,
 657                                 &pipe_ctx->stream_res.encoder_info_frame);
 658
 659                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 660                         pipe_ctx->stream_res.stream_enc,
 661                         &pipe_ctx->stream_res.encoder_info_frame);
 662         }
 663 }
 664
 665 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 666 {
 667         enum dc_lane_count lane_count =
 668                 pipe_ctx->stream->link->cur_link_settings.lane_count;
 669         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 670         struct dc_link *link = pipe_ctx->stream->link;
 671         const struct dc *dc = link->dc;
 672         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
 673         uint32_t active_total_with_borders;
 674         uint32_t early_control = 0;
 675         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 676
 677         link_hwss->setup_stream_encoder(pipe_ctx);
 678
 679         dc->hwss.update_info_frame(pipe_ctx);
 680
 681         /* enable early control to avoid corruption on DP monitor*/
 682         active_total_with_borders =
 683                         timing->h_addressable
 684                                 + timing->h_border_left
 685                                 + timing->h_border_right;
 686
 687         if (lane_count != 0)
 688                 early_control = active_total_with_borders % lane_count;
 689
 690         if (early_control == 0)
 691                 early_control = lane_count;
 692
 693         tg->funcs->set_early_control(tg, early_control);
 694 }
 695
 696 static enum bp_result link_transmitter_control(
 697                 struct dc_bios *bios,
 698         struct bp_transmitter_control *cntl)
 699 {
 700         enum bp_result result;
 701
 702         result = bios->funcs->transmitter_control(bios, cntl);
 703
 704         return result;
 705 }
 706
 707 /*
 708  * @brief
 709  * eDP only.
 710  */
 711 void dce110_edp_wait_for_hpd_ready(
 712                 struct dc_link *link,
 713                 bool power_up)
 714 {
 715         struct dc_context *ctx = link->ctx;
 716         struct graphics_object_id connector = link->link_enc->connector;
 717         struct gpio *hpd;
 718         bool edp_hpd_high = false;
 719         uint32_t time_elapsed = 0;
 720         uint32_t timeout = power_up ?
 721                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 722
 723         if (dal_graphics_object_id_get_connector_id(connector)
 724                         != CONNECTOR_ID_EDP) {
 725                 BREAK_TO_DEBUGGER();
 726                 return;
 727         }
 728
 729         if (!power_up)
 730                 /*
 731                  * From KV, we will not HPD low after turning off VCC -
 732                  * instead, we will check the SW timer in power_up().
 733                  */
 734                 return;
 735
 736         /*
 737          * When we power on/off the eDP panel,
 738          * we need to wait until SENSE bit is high/low.
 739          */
 740
 741         /* obtain HPD */
 742         /* TODO what to do with this? */
 743         hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 744
 745         if (!hpd) {
 746                 BREAK_TO_DEBUGGER();
 747                 return;
 748         }
 749
 750         if (link != NULL) {
 751                 if (link->panel_config.pps.extra_t3_ms > 0) {
 752                         int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
 753
 754                         msleep(extra_t3_in_ms);
 755                 }
 756         }
 757
 758         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 759
 760         /* wait until timeout or panel detected */
 761
 762         do {
 763                 uint32_t detected = 0;
 764
 765                 dal_gpio_get_value(hpd, &detected);
 766
 767                 if (!(detected ^ power_up)) {
 768                         edp_hpd_high = true;
 769                         break;
 770                 }
 771
 772                 msleep(HPD_CHECK_INTERVAL);
 773
 774                 time_elapsed += HPD_CHECK_INTERVAL;
 775         } while (time_elapsed < timeout);
 776
 777         dal_gpio_close(hpd);
 778
 779         dal_gpio_destroy_irq(&hpd);
 780
 781         /* ensure that the panel is detected */
 782         if (!edp_hpd_high)
 783                 DC_LOG_DC("%s: wait timed out!\n", __func__);
 784 }
 785
 786 void dce110_edp_power_control(
 787                 struct dc_link *link,
 788                 bool power_up)
 789 {
 790         struct dc_context *ctx = link->ctx;
 791         struct bp_transmitter_control cntl = { 0 };
 792         enum bp_result bp_result;
 793         uint8_t pwrseq_instance;
 794
 795
 796         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 797                         != CONNECTOR_ID_EDP) {
 798                 BREAK_TO_DEBUGGER();
 799                 return;
 800         }
 801
 802         if (!link->panel_cntl)
 803                 return;
 804         if (power_up !=
 805                 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
 806
 807                 unsigned long long current_ts = dm_get_timestamp(ctx);
 808                 unsigned long long time_since_edp_poweroff_ms =
 809                                 div64_u64(dm_get_elapse_time_in_ns(
 810                                                 ctx,
 811                                                 current_ts,
 812                                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
 813                 unsigned long long time_since_edp_poweron_ms =
 814                                 div64_u64(dm_get_elapse_time_in_ns(
 815                                                 ctx,
 816                                                 current_ts,
 817                                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000);
 818                 DC_LOG_HW_RESUME_S3(
 819                                 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
 820                                 __func__,
 821                                 power_up,
 822                                 current_ts,
 823                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
 824                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link),
 825                                 time_since_edp_poweroff_ms,
 826                                 time_since_edp_poweron_ms);
 827
 828                 /* Send VBIOS command to prompt eDP panel power */
 829                 if (power_up) {
 830                         /* edp requires a min of 500ms from LCDVDD off to on */
 831                         unsigned long long remaining_min_edp_poweroff_time_ms = 500;
 832
 833                         /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
 834                         if (link->local_sink != NULL)
 835                                 remaining_min_edp_poweroff_time_ms +=
 836                                         link->panel_config.pps.extra_t12_ms;
 837
 838                         /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
 839                         if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
 840                                 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
 841                                         remaining_min_edp_poweroff_time_ms =
 842                                                 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
 843                                 else
 844                                         remaining_min_edp_poweroff_time_ms = 0;
 845                         }
 846
 847                         if (remaining_min_edp_poweroff_time_ms) {
 848                                 DC_LOG_HW_RESUME_S3(
 849                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
 850                                                 __func__, remaining_min_edp_poweroff_time_ms);
 851                                 msleep(remaining_min_edp_poweroff_time_ms);
 852                                 DC_LOG_HW_RESUME_S3(
 853                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
 854                                                 __func__, remaining_min_edp_poweroff_time_ms);
 855                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 856                                                 __func__, remaining_min_edp_poweroff_time_ms);
 857                         } else {
 858                                 DC_LOG_HW_RESUME_S3(
 859                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
 860                                                 __func__, remaining_min_edp_poweroff_time_ms);
 861                         }
 862                 }
 863
 864                 DC_LOG_HW_RESUME_S3(
 865                                 "%s: BEGIN: Panel Power action: %s\n",
 866                                 __func__, (power_up ? "On":"Off"));
 867
 868                 cntl.action = power_up ?
 869                         TRANSMITTER_CONTROL_POWER_ON :
 870                         TRANSMITTER_CONTROL_POWER_OFF;
 871                 cntl.transmitter = link->link_enc->transmitter;
 872                 cntl.connector_obj_id = link->link_enc->connector;
 873                 cntl.coherent = false;
 874                 cntl.lanes_number = LANE_COUNT_FOUR;
 875                 cntl.hpd_sel = link->link_enc->hpd_source;
 876                 pwrseq_instance = link->panel_cntl->pwrseq_inst;
 877
 878                 if (ctx->dc->ctx->dmub_srv &&
 879                                 ctx->dc->debug.dmub_command_table) {
 880
 881                         if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) {
 882                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 883                                                 LVTMA_CONTROL_POWER_ON,
 884                                                 pwrseq_instance, link->link_powered_externally);
 885                         } else {
 886                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 887                                                 LVTMA_CONTROL_POWER_OFF,
 888                                                 pwrseq_instance, link->link_powered_externally);
 889                         }
 890                 }
 891
 892                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 893
 894                 DC_LOG_HW_RESUME_S3(
 895                                 "%s: END: Panel Power action: %s bp_result=%u\n",
 896                                 __func__, (power_up ? "On":"Off"),
 897                                 bp_result);
 898
 899                 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up);
 900
 901                 DC_LOG_HW_RESUME_S3(
 902                                 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
 903                                 __func__,
 904                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
 905                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link));
 906
 907                 if (bp_result != BP_RESULT_OK)
 908                         DC_LOG_ERROR(
 909                                         "%s: Panel Power bp_result: %d\n",
 910                                         __func__, bp_result);
 911         } else {
 912                 DC_LOG_HW_RESUME_S3(
 913                                 "%s: Skipping Panel Power action: %s\n",
 914                                 __func__, (power_up ? "On":"Off"));
 915         }
 916 }
 917
 918 void dce110_edp_wait_for_T12(
 919                 struct dc_link *link)
 920 {
 921         struct dc_context *ctx = link->ctx;
 922
 923         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 924                         != CONNECTOR_ID_EDP) {
 925                 BREAK_TO_DEBUGGER();
 926                 return;
 927         }
 928
 929         if (!link->panel_cntl)
 930                 return;
 931
 932         if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
 933                         ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
 934                 unsigned int t12_duration = 500; // Default T12 as per spec
 935                 unsigned long long current_ts = dm_get_timestamp(ctx);
 936                 unsigned long long time_since_edp_poweroff_ms =
 937                                 div64_u64(dm_get_elapse_time_in_ns(
 938                                                 ctx,
 939                                                 current_ts,
 940                                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
 941
 942                 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12
 943
 944                 if (time_since_edp_poweroff_ms < t12_duration)
 945                         msleep(t12_duration - time_since_edp_poweroff_ms);
 946         }
 947 }
 948 /*todo: cloned in stream enc, fix*/
 949 /*
 950  * @brief
 951  * eDP only. Control the backlight of the eDP panel
 952  */
 953 void dce110_edp_backlight_control(
 954                 struct dc_link *link,
 955                 bool enable)
 956 {
 957         struct dc_context *ctx = link->ctx;
 958         struct bp_transmitter_control cntl = { 0 };
 959         uint8_t pwrseq_instance;
 960         unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;
 961         unsigned int post_T7_delay = OLED_POST_T7_DELAY;
 962
 963         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 964                 != CONNECTOR_ID_EDP) {
 965                 BREAK_TO_DEBUGGER();
 966                 return;
 967         }
 968
 969         if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled ||
 970                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
 971                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
 972                 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
 973
 974                 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
 975                         DC_LOG_HW_RESUME_S3(
 976                                 "%s: panel already powered up/off. Do nothing.\n",
 977                                 __func__);
 978                         return;
 979                 }
 980         }
 981
 982         /* Send VBIOS command to control eDP panel backlight */
 983
 984         DC_LOG_HW_RESUME_S3(
 985                         "%s: backlight action: %s\n",
 986                         __func__, (enable ? "On":"Off"));
 987
 988         cntl.action = enable ?
 989                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 990                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 991
 992         /*cntl.engine_id = ctx->engine;*/
 993         cntl.transmitter = link->link_enc->transmitter;
 994         cntl.connector_obj_id = link->link_enc->connector;
 995         /*todo: unhardcode*/
 996         cntl.lanes_number = LANE_COUNT_FOUR;
 997         cntl.hpd_sel = link->link_enc->hpd_source;
 998         cntl.signal = SIGNAL_TYPE_EDP;
 999
1000         /* For eDP, the following delays might need to be considered
1001          * after link training completed:
1002          * idle period - min. accounts for required BS-Idle pattern,
1003          * max. allows for source frame synchronization);
1004          * 50 msec max. delay from valid video data from source
1005          * to video on dislpay or backlight enable.
1006          *
1007          * Disable the delay for now.
1008          * Enable it in the future if necessary.
1009          */
1010         /* dc_service_sleep_in_milliseconds(50); */
1011                 /*edp 1.2*/
1012         pwrseq_instance = link->panel_cntl->pwrseq_inst;
1013
1014         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
1015                 if (!link->dc->config.edp_no_power_sequencing)
1016                 /*
1017                  * Sometimes, DP receiver chip power-controlled externally by an
1018                  * Embedded Controller could be treated and used as eDP,
1019                  * if it drives mobile display. In this case,
1020                  * we shouldn't be doing power-sequencing, hence we can skip
1021                  * waiting for T7-ready.
1022                  */
1023                         ctx->dc->link_srv->edp_receiver_ready_T7(link);
1024                 else
1025                         DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
1026         }
1027
1028         /* Setting link_powered_externally will bypass delays in the backlight
1029          * as they are not required if the link is being powered by a different
1030          * source.
1031          */
1032         if (ctx->dc->ctx->dmub_srv &&
1033                         ctx->dc->debug.dmub_command_table) {
1034                 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1035                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1036                                         LVTMA_CONTROL_LCD_BLON,
1037                                         pwrseq_instance, link->link_powered_externally);
1038                 else
1039                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1040                                         LVTMA_CONTROL_LCD_BLOFF,
1041                                         pwrseq_instance, link->link_powered_externally);
1042         }
1043
1044         link_transmitter_control(ctx->dc_bios, &cntl);
1045
1046         if (enable && link->dpcd_sink_ext_caps.bits.oled &&
1047             !link->dc->config.edp_no_power_sequencing) {
1048                 post_T7_delay += link->panel_config.pps.extra_post_t7_ms;
1049                 msleep(post_T7_delay);
1050         }
1051
1052         if (link->dpcd_sink_ext_caps.bits.oled ||
1053                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1054                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1055                 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);
1056
1057         /*edp 1.2*/
1058         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
1059                 if (!link->dc->config.edp_no_power_sequencing)
1060                 /*
1061                  * Sometimes, DP receiver chip power-controlled externally by an
1062                  * Embedded Controller could be treated and used as eDP,
1063                  * if it drives mobile display. In this case,
1064                  * we shouldn't be doing power-sequencing, hence we can skip
1065                  * waiting for T9-ready.
1066                  */
1067                         ctx->dc->link_srv->edp_add_delay_for_T9(link);
1068                 else
1069                         DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
1070         }
1071
1072         if (!enable && link->dpcd_sink_ext_caps.bits.oled) {
1073                 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;
1074                 msleep(pre_T11_delay);
1075         }
1076 }
1077
1078 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1079 {
1080         /* notify audio driver for audio modes of monitor */
1081         struct dc *dc;
1082         struct clk_mgr *clk_mgr;
1083         unsigned int i, num_audio = 1;
1084         const struct link_hwss *link_hwss;
1085
1086         if (!pipe_ctx->stream)
1087                 return;
1088
1089         dc = pipe_ctx->stream->ctx->dc;
1090         clk_mgr = dc->clk_mgr;
1091         link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1092
1093         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1094                 return;
1095
1096         if (pipe_ctx->stream_res.audio) {
1097                 for (i = 0; i < MAX_PIPES; i++) {
1098                         /*current_state not updated yet*/
1099                         if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1100                                 num_audio++;
1101                 }
1102
1103                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1104
1105                 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1106                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1107                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1108
1109                 link_hwss->enable_audio_packet(pipe_ctx);
1110
1111                 if (pipe_ctx->stream_res.audio)
1112                         pipe_ctx->stream_res.audio->enabled = true;
1113         }
1114 }
1115
1116 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1117 {
1118         struct dc *dc;
1119         struct clk_mgr *clk_mgr;
1120         const struct link_hwss *link_hwss;
1121
1122         if (!pipe_ctx || !pipe_ctx->stream)
1123                 return;
1124
1125         dc = pipe_ctx->stream->ctx->dc;
1126         clk_mgr = dc->clk_mgr;
1127         link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1128
1129         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1130                 return;
1131
1132         link_hwss->disable_audio_packet(pipe_ctx);
1133
1134         if (pipe_ctx->stream_res.audio) {
1135                 pipe_ctx->stream_res.audio->enabled = false;
1136
1137                 if (clk_mgr->funcs->enable_pme_wa)
1138                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1139                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1140
1141                 /* TODO: notify audio driver for if audio modes list changed
1142                  * add audio mode list change flag */
1143                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1144                  * stream->stream_engine_id);
1145                  */
1146         }
1147 }
1148
1149 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1150 {
1151         struct dc_stream_state *stream = pipe_ctx->stream;
1152         struct dc_link *link = stream->link;
1153         struct dc *dc = pipe_ctx->stream->ctx->dc;
1154         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1155         struct dccg *dccg = dc->res_pool->dccg;
1156         struct timing_generator *tg = pipe_ctx->stream_res.tg;
1157         struct dtbclk_dto_params dto_params = {0};
1158         int dp_hpo_inst;
1159         struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
1160         struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
1161
1162         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1163                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1164                         pipe_ctx->stream_res.stream_enc);
1165                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1166                         pipe_ctx->stream_res.stream_enc);
1167         }
1168
1169         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1170                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
1171                                         pipe_ctx->stream_res.hpo_dp_stream_enc);
1172         } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
1173                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1174                         pipe_ctx->stream_res.stream_enc);
1175
1176         dc->hwss.disable_audio_stream(pipe_ctx);
1177
1178         link_hwss->reset_stream_encoder(pipe_ctx);
1179
1180         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {
1181                 dto_params.otg_inst = tg->inst;
1182                 dto_params.timing = &pipe_ctx->stream->timing;
1183                 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
1184                 if (dccg) {
1185                         dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
1186                         dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
1187                         dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
1188                 }
1189         } else if (dccg && dccg->funcs->disable_symclk_se) {
1190                 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
1191                                                link_enc->transmitter - TRANSMITTER_UNIPHY_A);
1192         }
1193
1194         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1195                 /* TODO: This looks like a bug to me as we are disabling HPO IO when
1196                  * we are just disabling a single HPO stream. Shouldn't we disable HPO
1197                  * HW control only when HPOs for all streams are disabled?
1198                  */
1199                 if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control)
1200                         pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control(
1201                                         pipe_ctx->stream->ctx->dc->hwseq, false);
1202         }
1203 }
1204
1205 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1206                 struct dc_link_settings *link_settings)
1207 {
1208         struct encoder_unblank_param params = { { 0 } };
1209         struct dc_stream_state *stream = pipe_ctx->stream;
1210         struct dc_link *link = stream->link;
1211         struct dce_hwseq *hws = link->dc->hwseq;
1212
1213         /* only 3 items below are used by unblank */
1214         params.timing = pipe_ctx->stream->timing;
1215         params.link_settings.link_rate = link_settings->link_rate;
1216
1217         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1218                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1219
1220         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1221                 hws->funcs.edp_backlight_control(link, true);
1222         }
1223 }
1224
1225 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1226 {
1227         struct dc_stream_state *stream = pipe_ctx->stream;
1228         struct dc_link *link = stream->link;
1229         struct dce_hwseq *hws = link->dc->hwseq;
1230
1231         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1232                 if (!link->skip_implict_edp_power_control)
1233                         hws->funcs.edp_backlight_control(link, false);
1234                 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1235         }
1236
1237         if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1238                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1239                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
1240                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1241         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1242                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
1243
1244                 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1245                         /*
1246                          * After output is idle pattern some sinks need time to recognize the stream
1247                          * has changed or they enter protection state and hang.
1248                          */
1249                         msleep(60);
1250                 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1251                         if (!link->dc->config.edp_no_power_sequencing) {
1252                                 /*
1253                                  * Sometimes, DP receiver chip power-controlled externally by an
1254                                  * Embedded Controller could be treated and used as eDP,
1255                                  * if it drives mobile display. In this case,
1256                                  * we shouldn't be doing power-sequencing, hence we can skip
1257                                  * waiting for T9-ready.
1258                                  */
1259                                 link->dc->link_srv->edp_receiver_ready_T9(link);
1260                         }
1261                 }
1262         }
1263
1264 }
1265
1266
1267 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1268 {
1269         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1270                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1271 }
1272
1273 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1274 {
1275         switch (crtc_id) {
1276         case CONTROLLER_ID_D0:
1277                 return DTO_SOURCE_ID0;
1278         case CONTROLLER_ID_D1:
1279                 return DTO_SOURCE_ID1;
1280         case CONTROLLER_ID_D2:
1281                 return DTO_SOURCE_ID2;
1282         case CONTROLLER_ID_D3:
1283                 return DTO_SOURCE_ID3;
1284         case CONTROLLER_ID_D4:
1285                 return DTO_SOURCE_ID4;
1286         case CONTROLLER_ID_D5:
1287                 return DTO_SOURCE_ID5;
1288         default:
1289                 return DTO_SOURCE_UNKNOWN;
1290         }
1291 }
1292
1293 static void build_audio_output(
1294         struct dc_state *state,
1295         const struct pipe_ctx *pipe_ctx,
1296         struct audio_output *audio_output)
1297 {
1298         const struct dc_stream_state *stream = pipe_ctx->stream;
1299         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1300
1301         audio_output->signal = pipe_ctx->stream->signal;
1302
1303         /* audio_crtc_info  */
1304
1305         audio_output->crtc_info.h_total =
1306                 stream->timing.h_total;
1307
1308         /*
1309          * Audio packets are sent during actual CRTC blank physical signal, we
1310          * need to specify actual active signal portion
1311          */
1312         audio_output->crtc_info.h_active =
1313                         stream->timing.h_addressable
1314                         + stream->timing.h_border_left
1315                         + stream->timing.h_border_right;
1316
1317         audio_output->crtc_info.v_active =
1318                         stream->timing.v_addressable
1319                         + stream->timing.v_border_top
1320                         + stream->timing.v_border_bottom;
1321
1322         audio_output->crtc_info.pixel_repetition = 1;
1323
1324         audio_output->crtc_info.interlaced =
1325                         stream->timing.flags.INTERLACE;
1326
1327         audio_output->crtc_info.refresh_rate =
1328                 (stream->timing.pix_clk_100hz*100)/
1329                 (stream->timing.h_total*stream->timing.v_total);
1330
1331         audio_output->crtc_info.color_depth =
1332                 stream->timing.display_color_depth;
1333
1334         audio_output->crtc_info.requested_pixel_clock_100Hz =
1335                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1336
1337         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1338                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1339
1340 /*for HDMI, audio ACR is with deep color ratio factor*/
1341         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1342                 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1343                                 (stream->timing.pix_clk_100hz)) {
1344                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1345                         audio_output->crtc_info.requested_pixel_clock_100Hz =
1346                                         audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1347                         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1348                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1349
1350                 }
1351         }
1352
1353         if (state->clk_mgr &&
1354                 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1355                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1356                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1357                                 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1358                                                 state->clk_mgr);
1359         }
1360
1361         audio_output->pll_info.feed_back_divider =
1362                         pipe_ctx->pll_settings.feedback_divider;
1363
1364         audio_output->pll_info.dto_source =
1365                 translate_to_dto_source(
1366                         pipe_ctx->stream_res.tg->inst + 1);
1367
1368         /* TODO hard code to enable for now. Need get from stream */
1369         audio_output->pll_info.ss_enabled = true;
1370
1371         audio_output->pll_info.ss_percentage =
1372                         pipe_ctx->pll_settings.ss_percentage;
1373 }
1374
1375 static void program_scaler(const struct dc *dc,
1376                 const struct pipe_ctx *pipe_ctx)
1377 {
1378         struct tg_color color = {0};
1379
1380         /* TOFPGA */
1381         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1382                 return;
1383
1384         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1385                 get_surface_visual_confirm_color(pipe_ctx, &color);
1386         else
1387                 color_space_to_black_color(dc,
1388                                 pipe_ctx->stream->output_color_space,
1389                                 &color);
1390
1391         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1392                 pipe_ctx->plane_res.xfm,
1393                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1394                 &pipe_ctx->stream->bit_depth_params);
1395
1396         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1397                 /*
1398                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1399                  * alternate between Cb and Cr, so both channels need the pixel
1400                  * value for Y
1401                  */
1402                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1403                         color.color_r_cr = color.color_g_y;
1404
1405                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1406                                 pipe_ctx->stream_res.tg,
1407                                 &color);
1408         }
1409
1410         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1411                 &pipe_ctx->plane_res.scl_data);
1412 }
1413
1414 static enum dc_status dce110_enable_stream_timing(
1415                 struct pipe_ctx *pipe_ctx,
1416                 struct dc_state *context,
1417                 struct dc *dc)
1418 {
1419         struct dc_stream_state *stream = pipe_ctx->stream;
1420         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1421                         pipe_ctx[pipe_ctx->pipe_idx];
1422         struct tg_color black_color = {0};
1423
1424         if (!pipe_ctx_old->stream) {
1425
1426                 /* program blank color */
1427                 color_space_to_black_color(dc,
1428                                 stream->output_color_space, &black_color);
1429                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1430                                 pipe_ctx->stream_res.tg,
1431                                 &black_color);
1432
1433                 /*
1434                  * Must blank CRTC after disabling power gating and before any
1435                  * programming, otherwise CRTC will be hung in bad state
1436                  */
1437                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1438
1439                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1440                                 pipe_ctx->clock_source,
1441                                 &pipe_ctx->stream_res.pix_clk_params,
1442                                 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
1443                                 &pipe_ctx->pll_settings)) {
1444                         BREAK_TO_DEBUGGER();
1445                         return DC_ERROR_UNEXPECTED;
1446                 }
1447
1448                 if (dc_is_hdmi_tmds_signal(stream->signal)) {
1449                         stream->link->phy_state.symclk_ref_cnts.otg = 1;
1450                         if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
1451                                 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1452                         else
1453                                 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
1454                 }
1455
1456                 pipe_ctx->stream_res.tg->funcs->program_timing(
1457                                 pipe_ctx->stream_res.tg,
1458                                 &stream->timing,
1459                                 0,
1460                                 0,
1461                                 0,
1462                                 0,
1463                                 pipe_ctx->stream->signal,
1464                                 true);
1465         }
1466
1467         if (!pipe_ctx_old->stream) {
1468                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1469                                 pipe_ctx->stream_res.tg)) {
1470                         BREAK_TO_DEBUGGER();
1471                         return DC_ERROR_UNEXPECTED;
1472                 }
1473         }
1474
1475         return DC_OK;
1476 }
1477
1478 static enum dc_status apply_single_controller_ctx_to_hw(
1479                 struct pipe_ctx *pipe_ctx,
1480                 struct dc_state *context,
1481                 struct dc *dc)
1482 {
1483         struct dc_stream_state *stream = pipe_ctx->stream;
1484         struct dc_link *link = stream->link;
1485         struct drr_params params = {0};
1486         unsigned int event_triggers = 0;
1487         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1488         struct dce_hwseq *hws = dc->hwseq;
1489         const struct link_hwss *link_hwss = get_link_hwss(
1490                         link, &pipe_ctx->link_res);
1491
1492
1493         if (hws->funcs.disable_stream_gating) {
1494                 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1495         }
1496
1497         if (pipe_ctx->stream_res.audio != NULL) {
1498                 struct audio_output audio_output;
1499
1500                 build_audio_output(context, pipe_ctx, &audio_output);
1501
1502                 link_hwss->setup_audio_output(pipe_ctx, &audio_output,
1503                                 pipe_ctx->stream_res.audio->inst);
1504
1505                 pipe_ctx->stream_res.audio->funcs->az_configure(
1506                                 pipe_ctx->stream_res.audio,
1507                                 pipe_ctx->stream->signal,
1508                                 &audio_output.crtc_info,
1509                                 &pipe_ctx->stream->audio_info);
1510         }
1511
1512         /* make sure no pipes syncd to the pipe being enabled */
1513         if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
1514                 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
1515
1516         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1517                 pipe_ctx->stream_res.opp,
1518                 &stream->bit_depth_params,
1519                 &stream->clamping);
1520
1521         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1522                         pipe_ctx->stream_res.opp,
1523                         COLOR_SPACE_YCBCR601,
1524                         stream->timing.display_color_depth,
1525                         stream->signal);
1526
1527         while (odm_pipe) {
1528                 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1529                                 odm_pipe->stream_res.opp,
1530                                 COLOR_SPACE_YCBCR601,
1531                                 stream->timing.display_color_depth,
1532                                 stream->signal);
1533
1534                 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1535                                 odm_pipe->stream_res.opp,
1536                                 &stream->bit_depth_params,
1537                                 &stream->clamping);
1538                 odm_pipe = odm_pipe->next_odm_pipe;
1539         }
1540
1541         /* DCN3.1 FPGA Workaround
1542          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1543          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1544          * function core_link_enable_stream
1545          */
1546         if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))
1547                 /*  */
1548                 /* Do not touch stream timing on seamless boot optimization. */
1549                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1550                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1551
1552         if (hws->funcs.setup_vupdate_interrupt)
1553                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1554
1555         params.vertical_total_min = stream->adjust.v_total_min;
1556         params.vertical_total_max = stream->adjust.v_total_max;
1557         if (pipe_ctx->stream_res.tg->funcs->set_drr)
1558                 pipe_ctx->stream_res.tg->funcs->set_drr(
1559                         pipe_ctx->stream_res.tg, &params);
1560
1561         // DRR should set trigger event to monitor surface update event
1562         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1563                 event_triggers = 0x80;
1564         /* Event triggers and num frames initialized for DRR, but can be
1565          * later updated for PSR use. Note DRR trigger events are generated
1566          * regardless of whether num frames met.
1567          */
1568         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1569                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1570                                 pipe_ctx->stream_res.tg, event_triggers, 2);
1571
1572         if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1573                 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1574                         pipe_ctx->stream_res.stream_enc,
1575                         pipe_ctx->stream_res.tg->inst);
1576
1577         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1578                 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
1579
1580         if (!stream->dpms_off)
1581                 dc->link_srv->set_dpms_on(context, pipe_ctx);
1582
1583         /* DCN3.1 FPGA Workaround
1584          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1585          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1586          * function core_link_enable_stream
1587          */
1588         if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1589                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1590                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1591         }
1592
1593         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
1594
1595         /* Phantom and main stream share the same link (because the stream
1596          * is constructed with the same sink). Make sure not to override
1597          * and link programming on the main.
1598          */
1599         if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1600                 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1601                 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;
1602         }
1603         return DC_OK;
1604 }
1605
1606 /******************************************************************************/
1607
1608 static void power_down_encoders(struct dc *dc)
1609 {
1610         int i;
1611
1612         for (i = 0; i < dc->link_count; i++) {
1613                 enum signal_type signal = dc->links[i]->connector_signal;
1614
1615                 dc->link_srv->blank_dp_stream(dc->links[i], false);
1616
1617                 if (signal != SIGNAL_TYPE_EDP)
1618                         signal = SIGNAL_TYPE_NONE;
1619
1620                 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)
1621                         dc->links[i]->link_enc->funcs->disable_output(
1622                                         dc->links[i]->link_enc, signal);
1623
1624                 dc->links[i]->link_status.link_active = false;
1625                 memset(&dc->links[i]->cur_link_settings, 0,
1626                                 sizeof(dc->links[i]->cur_link_settings));
1627         }
1628 }
1629
1630 static void power_down_controllers(struct dc *dc)
1631 {
1632         int i;
1633
1634         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1635                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1636                                 dc->res_pool->timing_generators[i]);
1637         }
1638 }
1639
1640 static void power_down_clock_sources(struct dc *dc)
1641 {
1642         int i;
1643
1644         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1645                 dc->res_pool->dp_clock_source) == false)
1646                 dm_error("Failed to power down pll! (dp clk src)\n");
1647
1648         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1649                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1650                                 dc->res_pool->clock_sources[i]) == false)
1651                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1652         }
1653 }
1654
1655 static void power_down_all_hw_blocks(struct dc *dc)
1656 {
1657         power_down_encoders(dc);
1658
1659         power_down_controllers(dc);
1660
1661         power_down_clock_sources(dc);
1662
1663         if (dc->fbc_compressor)
1664                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1665 }
1666
1667 static void disable_vga_and_power_gate_all_controllers(
1668                 struct dc *dc)
1669 {
1670         int i;
1671         struct timing_generator *tg;
1672         struct dc_context *ctx = dc->ctx;
1673
1674         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1675                 tg = dc->res_pool->timing_generators[i];
1676
1677                 if (tg->funcs->disable_vga)
1678                         tg->funcs->disable_vga(tg);
1679         }
1680         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1681                 /* Enable CLOCK gating for each pipe BEFORE controller
1682                  * powergating. */
1683                 enable_display_pipe_clock_gating(ctx,
1684                                 true);
1685
1686                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1687                 dc->hwss.disable_plane(dc,
1688                         &dc->current_state->res_ctx.pipe_ctx[i]);
1689         }
1690 }
1691
1692
1693 static void get_edp_streams(struct dc_state *context,
1694                 struct dc_stream_state **edp_streams,
1695                 int *edp_stream_num)
1696 {
1697         int i;
1698
1699         *edp_stream_num = 0;
1700         for (i = 0; i < context->stream_count; i++) {
1701                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1702                         edp_streams[*edp_stream_num] = context->streams[i];
1703                         if (++(*edp_stream_num) == MAX_NUM_EDP)
1704                                 return;
1705                 }
1706         }
1707 }
1708
1709 static void get_edp_links_with_sink(
1710                 struct dc *dc,
1711                 struct dc_link **edp_links_with_sink,
1712                 int *edp_with_sink_num)
1713 {
1714         int i;
1715
1716         /* check if there is an eDP panel not in use */
1717         *edp_with_sink_num = 0;
1718         for (i = 0; i < dc->link_count; i++) {
1719                 if (dc->links[i]->local_sink &&
1720                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1721                         edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1722                         if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1723                                 return;
1724                 }
1725         }
1726 }
1727
1728 /*
1729  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1730  *  1. Power down all DC HW blocks
1731  *  2. Disable VGA engine on all controllers
1732  *  3. Enable power gating for controller
1733  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1734  */
1735 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1736 {
1737         struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1738         struct dc_link *edp_links[MAX_NUM_EDP];
1739         struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1740         struct dc_link *edp_link_with_sink = NULL;
1741         struct dc_link *edp_link = NULL;
1742         struct dce_hwseq *hws = dc->hwseq;
1743         int edp_with_sink_num;
1744         int edp_num;
1745         int edp_stream_num;
1746         int i;
1747         bool can_apply_edp_fast_boot = false;
1748         bool can_apply_seamless_boot = false;
1749         bool keep_edp_vdd_on = false;
1750         DC_LOGGER_INIT();
1751
1752
1753         get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1754         dc_get_edp_links(dc, edp_links, &edp_num);
1755
1756         if (hws->funcs.init_pipes)
1757                 hws->funcs.init_pipes(dc, context);
1758
1759         get_edp_streams(context, edp_streams, &edp_stream_num);
1760
1761         // Check fastboot support, disable on DCE8 because of blank screens
1762         if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1763                     dc->ctx->dce_version != DCE_VERSION_8_1 &&
1764                     dc->ctx->dce_version != DCE_VERSION_8_3) {
1765                 for (i = 0; i < edp_num; i++) {
1766                         edp_link = edp_links[i];
1767                         if (edp_link != edp_streams[0]->link)
1768                                 continue;
1769                         // enable fastboot if backend is enabled on eDP
1770                         if (edp_link->link_enc->funcs->is_dig_enabled &&
1771                             edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
1772                             edp_link->link_status.link_active) {
1773                                 struct dc_stream_state *edp_stream = edp_streams[0];
1774
1775                                 can_apply_edp_fast_boot = dc_validate_boot_timing(dc,
1776                                         edp_stream->sink, &edp_stream->timing);
1777                                 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1778                                 if (can_apply_edp_fast_boot)
1779                                         DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");
1780
1781                                 break;
1782                         }
1783                 }
1784                 // We are trying to enable eDP, don't power down VDD
1785                 if (can_apply_edp_fast_boot)
1786                         keep_edp_vdd_on = true;
1787         }
1788
1789         // Check seamless boot support
1790         for (i = 0; i < context->stream_count; i++) {
1791                 if (context->streams[i]->apply_seamless_boot_optimization) {
1792                         can_apply_seamless_boot = true;
1793                         break;
1794                 }
1795         }
1796
1797         /* eDP should not have stream in resume from S4 and so even with VBios post
1798          * it should get turned off
1799          */
1800         if (edp_with_sink_num)
1801                 edp_link_with_sink = edp_links_with_sink[0];
1802
1803         if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1804                 if (edp_link_with_sink && !keep_edp_vdd_on) {
1805                         /*turn off backlight before DP_blank and encoder powered down*/
1806                         hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1807                 }
1808                 /*resume from S3, no vbios posting, no need to power down again*/
1809                 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1810
1811                 power_down_all_hw_blocks(dc);
1812                 disable_vga_and_power_gate_all_controllers(dc);
1813                 if (edp_link_with_sink && !keep_edp_vdd_on)
1814                         dc->hwss.edp_power_control(edp_link_with_sink, false);
1815                 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1816         }
1817         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1818 }
1819
1820 static uint32_t compute_pstate_blackout_duration(
1821         struct bw_fixed blackout_duration,
1822         const struct dc_stream_state *stream)
1823 {
1824         uint32_t total_dest_line_time_ns;
1825         uint32_t pstate_blackout_duration_ns;
1826
1827         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1828
1829         total_dest_line_time_ns = 1000000UL *
1830                 (stream->timing.h_total * 10) /
1831                 stream->timing.pix_clk_100hz +
1832                 pstate_blackout_duration_ns;
1833
1834         return total_dest_line_time_ns;
1835 }
1836
1837 static void dce110_set_displaymarks(
1838         const struct dc *dc,
1839         struct dc_state *context)
1840 {
1841         uint8_t i, num_pipes;
1842         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1843
1844         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1845                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1846                 uint32_t total_dest_line_time_ns;
1847
1848                 if (pipe_ctx->stream == NULL)
1849                         continue;
1850
1851                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1852                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1853                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1854                         pipe_ctx->plane_res.mi,
1855                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1856                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1857                         context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1858                         context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1859                         total_dest_line_time_ns);
1860                 if (i == underlay_idx) {
1861                         num_pipes++;
1862                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1863                                 pipe_ctx->plane_res.mi,
1864                                 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1865                                 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1866                                 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1867                                 total_dest_line_time_ns);
1868                 }
1869                 num_pipes++;
1870         }
1871 }
1872
1873 void dce110_set_safe_displaymarks(
1874                 struct resource_context *res_ctx,
1875                 const struct resource_pool *pool)
1876 {
1877         int i;
1878         int underlay_idx = pool->underlay_pipe_index;
1879         struct dce_watermarks max_marks = {
1880                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1881         struct dce_watermarks nbp_marks = {
1882                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1883         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1884
1885         for (i = 0; i < MAX_PIPES; i++) {
1886                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1887                         continue;
1888
1889                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1890                                 res_ctx->pipe_ctx[i].plane_res.mi,
1891                                 nbp_marks,
1892                                 max_marks,
1893                                 min_marks,
1894                                 max_marks,
1895                                 MAX_WATERMARK);
1896
1897                 if (i == underlay_idx)
1898                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1899                                 res_ctx->pipe_ctx[i].plane_res.mi,
1900                                 nbp_marks,
1901                                 max_marks,
1902                                 max_marks,
1903                                 MAX_WATERMARK);
1904
1905         }
1906 }
1907
1908 /*******************************************************************************
1909  * Public functions
1910  ******************************************************************************/
1911
1912 static void set_drr(struct pipe_ctx **pipe_ctx,
1913                 int num_pipes, struct dc_crtc_timing_adjust adjust)
1914 {
1915         int i = 0;
1916         struct drr_params params = {0};
1917         // DRR should set trigger event to monitor surface update event
1918         unsigned int event_triggers = 0x80;
1919         // Note DRR trigger events are generated regardless of whether num frames met.
1920         unsigned int num_frames = 2;
1921
1922         params.vertical_total_max = adjust.v_total_max;
1923         params.vertical_total_min = adjust.v_total_min;
1924
1925         /* TODO: If multiple pipes are to be supported, you need
1926          * some GSL stuff. Static screen triggers may be programmed differently
1927          * as well.
1928          */
1929         for (i = 0; i < num_pipes; i++) {
1930                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1931                         pipe_ctx[i]->stream_res.tg, &params);
1932
1933                 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1934                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1935                                         pipe_ctx[i]->stream_res.tg,
1936                                         event_triggers, num_frames);
1937         }
1938 }
1939
1940 static void get_position(struct pipe_ctx **pipe_ctx,
1941                 int num_pipes,
1942                 struct crtc_position *position)
1943 {
1944         int i = 0;
1945
1946         /* TODO: handle pipes > 1
1947          */
1948         for (i = 0; i < num_pipes; i++)
1949                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1950 }
1951
1952 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1953                 int num_pipes, const struct dc_static_screen_params *params)
1954 {
1955         unsigned int i;
1956         unsigned int triggers = 0;
1957
1958         if (params->triggers.overlay_update)
1959                 triggers |= 0x100;
1960         if (params->triggers.surface_update)
1961                 triggers |= 0x80;
1962         if (params->triggers.cursor_update)
1963                 triggers |= 0x2;
1964         if (params->triggers.force_trigger)
1965                 triggers |= 0x1;
1966
1967         if (num_pipes) {
1968                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1969
1970                 if (dc->fbc_compressor)
1971                         triggers |= 0x84;
1972         }
1973
1974         for (i = 0; i < num_pipes; i++)
1975                 pipe_ctx[i]->stream_res.tg->funcs->
1976                         set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1977                                         triggers, params->num_frames);
1978 }
1979
1980 /*
1981  *  Check if FBC can be enabled
1982  */
1983 static bool should_enable_fbc(struct dc *dc,
1984                 struct dc_state *context,
1985                 uint32_t *pipe_idx)
1986 {
1987         uint32_t i;
1988         struct pipe_ctx *pipe_ctx = NULL;
1989         struct resource_context *res_ctx = &context->res_ctx;
1990         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1991
1992
1993         ASSERT(dc->fbc_compressor);
1994
1995         /* FBC memory should be allocated */
1996         if (!dc->ctx->fbc_gpu_addr)
1997                 return false;
1998
1999         /* Only supports single display */
2000         if (context->stream_count != 1)
2001                 return false;
2002
2003         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2004                 if (res_ctx->pipe_ctx[i].stream) {
2005
2006                         pipe_ctx = &res_ctx->pipe_ctx[i];
2007
2008                         /* fbc not applicable on underlay pipe */
2009                         if (pipe_ctx->pipe_idx != underlay_idx) {
2010                                 *pipe_idx = i;
2011                                 break;
2012                         }
2013                 }
2014         }
2015
2016         if (i == dc->res_pool->pipe_count)
2017                 return false;
2018
2019         if (!pipe_ctx->stream->link)
2020                 return false;
2021
2022         /* Only supports eDP */
2023         if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
2024                 return false;
2025
2026         /* PSR should not be enabled */
2027         if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
2028                 return false;
2029
2030         /* Replay should not be enabled */
2031         if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)
2032                 return false;
2033
2034         /* Nothing to compress */
2035         if (!pipe_ctx->plane_state)
2036                 return false;
2037
2038         /* Only for non-linear tiling */
2039         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2040                 return false;
2041
2042         return true;
2043 }
2044
2045 /*
2046  *  Enable FBC
2047  */
2048 static void enable_fbc(
2049                 struct dc *dc,
2050                 struct dc_state *context)
2051 {
2052         uint32_t pipe_idx = 0;
2053
2054         if (should_enable_fbc(dc, context, &pipe_idx)) {
2055                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2056                 struct compr_addr_and_pitch_params params = {0, 0, 0};
2057                 struct compressor *compr = dc->fbc_compressor;
2058                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2059
2060                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2061                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2062                 params.inst = pipe_ctx->stream_res.tg->inst;
2063                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2064
2065                 compr->funcs->surface_address_and_pitch(compr, &params);
2066                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2067
2068                 compr->funcs->enable_fbc(compr, &params);
2069         }
2070 }
2071
2072 static void dce110_reset_hw_ctx_wrap(
2073                 struct dc *dc,
2074                 struct dc_state *context)
2075 {
2076         int i;
2077
2078         /* Reset old context */
2079         /* look up the targets that have been removed since last commit */
2080         for (i = 0; i < MAX_PIPES; i++) {
2081                 struct pipe_ctx *pipe_ctx_old =
2082                         &dc->current_state->res_ctx.pipe_ctx[i];
2083                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2084
2085                 /* Note: We need to disable output if clock sources change,
2086                  * since bios does optimization and doesn't apply if changing
2087                  * PHY when not already disabled.
2088                  */
2089
2090                 /* Skip underlay pipe since it will be handled in commit surface*/
2091                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2092                         continue;
2093
2094                 if (!pipe_ctx->stream ||
2095                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2096                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2097
2098                         /* Disable if new stream is null. O/w, if stream is
2099                          * disabled already, no need to disable again.
2100                          */
2101                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2102                                 dc->link_srv->set_dpms_off(pipe_ctx_old);
2103
2104                                 /* free acquired resources*/
2105                                 if (pipe_ctx_old->stream_res.audio) {
2106                                         /*disable az_endpoint*/
2107                                         pipe_ctx_old->stream_res.audio->funcs->
2108                                                         az_disable(pipe_ctx_old->stream_res.audio);
2109
2110                                         /*free audio*/
2111                                         if (dc->caps.dynamic_audio == true) {
2112                                                 /*we have to dynamic arbitrate the audio endpoints*/
2113                                                 /*we free the resource, need reset is_audio_acquired*/
2114                                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2115                                                                 pipe_ctx_old->stream_res.audio, false);
2116                                                 pipe_ctx_old->stream_res.audio = NULL;
2117                                         }
2118                                 }
2119                         }
2120
2121                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2122                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2123                                 dm_error("DC: failed to blank crtc!\n");
2124                                 BREAK_TO_DEBUGGER();
2125                         }
2126                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2127                         pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
2128                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2129                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2130
2131                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2132                                                                                 dc->res_pool,
2133                                                                                 old_clk))
2134                                 old_clk->funcs->cs_power_down(old_clk);
2135
2136                         dc->hwss.disable_plane(dc, pipe_ctx_old);
2137
2138                         pipe_ctx_old->stream = NULL;
2139                 }
2140         }
2141 }
2142
2143 static void dce110_setup_audio_dto(
2144                 struct dc *dc,
2145                 struct dc_state *context)
2146 {
2147         int i;
2148
2149         /* program audio wall clock. use HDMI as clock source if HDMI
2150          * audio active. Otherwise, use DP as clock source
2151          * first, loop to find any HDMI audio, if not, loop find DP audio
2152          */
2153         /* Setup audio rate clock source */
2154         /* Issue:
2155         * Audio lag happened on DP monitor when unplug a HDMI monitor
2156         *
2157         * Cause:
2158         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2159         * is set to either dto0 or dto1, audio should work fine.
2160         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2161         * set to dto0 will cause audio lag.
2162         *
2163         * Solution:
2164         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2165         * find first available pipe with audio, setup audio wall DTO per topology
2166         * instead of per pipe.
2167         */
2168         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2169                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2170
2171                 if (pipe_ctx->stream == NULL)
2172                         continue;
2173
2174                 if (pipe_ctx->top_pipe)
2175                         continue;
2176                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2177                         continue;
2178                 if (pipe_ctx->stream_res.audio != NULL) {
2179                         struct audio_output audio_output;
2180
2181                         build_audio_output(context, pipe_ctx, &audio_output);
2182
2183                         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2184                                 struct dtbclk_dto_params dto_params = {0};
2185
2186                                 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
2187                                         dc->res_pool->dccg, &dto_params);
2188
2189                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2190                                                 pipe_ctx->stream_res.audio,
2191                                                 pipe_ctx->stream->signal,
2192                                                 &audio_output.crtc_info,
2193                                                 &audio_output.pll_info);
2194                         } else
2195                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2196                                         pipe_ctx->stream_res.audio,
2197                                         pipe_ctx->stream->signal,
2198                                         &audio_output.crtc_info,
2199                                         &audio_output.pll_info);
2200                         break;
2201                 }
2202         }
2203
2204         /* no HDMI audio is found, try DP audio */
2205         if (i == dc->res_pool->pipe_count) {
2206                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2207                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2208
2209                         if (pipe_ctx->stream == NULL)
2210                                 continue;
2211
2212                         if (pipe_ctx->top_pipe)
2213                                 continue;
2214
2215                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2216                                 continue;
2217
2218                         if (pipe_ctx->stream_res.audio != NULL) {
2219                                 struct audio_output audio_output;
2220
2221                                 build_audio_output(context, pipe_ctx, &audio_output);
2222
2223                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2224                                         pipe_ctx->stream_res.audio,
2225                                         pipe_ctx->stream->signal,
2226                                         &audio_output.crtc_info,
2227                                         &audio_output.pll_info);
2228                                 break;
2229                         }
2230                 }
2231         }
2232 }
2233
2234 enum dc_status dce110_apply_ctx_to_hw(
2235                 struct dc *dc,
2236                 struct dc_state *context)
2237 {
2238         struct dce_hwseq *hws = dc->hwseq;
2239         struct dc_bios *dcb = dc->ctx->dc_bios;
2240         enum dc_status status;
2241         int i;
2242
2243         /* reset syncd pipes from disabled pipes */
2244         if (dc->config.use_pipe_ctx_sync_logic)
2245                 reset_syncd_pipes_from_disabled_pipes(dc, context);
2246
2247         /* Reset old context */
2248         /* look up the targets that have been removed since last commit */
2249         hws->funcs.reset_hw_ctx_wrap(dc, context);
2250
2251         /* Skip applying if no targets */
2252         if (context->stream_count <= 0)
2253                 return DC_OK;
2254
2255         /* Apply new context */
2256         dcb->funcs->set_scratch_critical_state(dcb, true);
2257
2258         /* below is for real asic only */
2259         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2260                 struct pipe_ctx *pipe_ctx_old =
2261                                         &dc->current_state->res_ctx.pipe_ctx[i];
2262                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2263
2264                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2265                         continue;
2266
2267                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2268                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2269                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2270                                                 pipe_ctx->clock_source, i);
2271                         continue;
2272                 }
2273
2274                 hws->funcs.enable_display_power_gating(
2275                                 dc, i, dc->ctx->dc_bios,
2276                                 PIPE_GATING_CONTROL_DISABLE);
2277         }
2278
2279         if (dc->fbc_compressor)
2280                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2281
2282         dce110_setup_audio_dto(dc, context);
2283
2284         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2285                 struct pipe_ctx *pipe_ctx_old =
2286                                         &dc->current_state->res_ctx.pipe_ctx[i];
2287                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2288
2289                 if (pipe_ctx->stream == NULL)
2290                         continue;
2291
2292                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2293                         pipe_ctx->stream->link->link_state_valid) {
2294                         continue;
2295                 }
2296
2297                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2298                         continue;
2299
2300                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2301                         continue;
2302
2303                 status = apply_single_controller_ctx_to_hw(
2304                                 pipe_ctx,
2305                                 context,
2306                                 dc);
2307
2308                 if (DC_OK != status)
2309                         return status;
2310
2311 #ifdef CONFIG_DRM_AMD_DC_FP
2312                 if (hws->funcs.resync_fifo_dccg_dio)
2313                         hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
2314 #endif
2315         }
2316
2317         if (dc->fbc_compressor)
2318                 enable_fbc(dc, dc->current_state);
2319
2320         dcb->funcs->set_scratch_critical_state(dcb, false);
2321
2322         return DC_OK;
2323 }
2324
2325 /*******************************************************************************
2326  * Front End programming
2327  ******************************************************************************/
2328 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2329 {
2330         struct default_adjustment default_adjust = { 0 };
2331
2332         default_adjust.force_hw_default = false;
2333         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2334         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2335         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2336         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2337
2338         /* display color depth */
2339         default_adjust.color_depth =
2340                 pipe_ctx->stream->timing.display_color_depth;
2341
2342         /* Lb color depth */
2343         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2344
2345         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2346                                         pipe_ctx->plane_res.xfm, &default_adjust);
2347 }
2348
2349
2350 /*******************************************************************************
2351  * In order to turn on/off specific surface we will program
2352  * Blender + CRTC
2353  *
2354  * In case that we have two surfaces and they have a different visibility
2355  * we can't turn off the CRTC since it will turn off the entire display
2356  *
2357  * |----------------------------------------------- |
2358  * |bottom pipe|curr pipe  |              |         |
2359  * |Surface    |Surface    | Blender      |  CRCT   |
2360  * |visibility |visibility | Configuration|         |
2361  * |------------------------------------------------|
2362  * |   off     |    off    | CURRENT_PIPE | blank   |
2363  * |   off     |    on     | CURRENT_PIPE | unblank |
2364  * |   on      |    off    | OTHER_PIPE   | unblank |
2365  * |   on      |    on     | BLENDING     | unblank |
2366  * -------------------------------------------------|
2367  *
2368  ******************************************************************************/
2369 static void program_surface_visibility(const struct dc *dc,
2370                 struct pipe_ctx *pipe_ctx)
2371 {
2372         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2373         bool blank_target = false;
2374
2375         if (pipe_ctx->bottom_pipe) {
2376
2377                 /* For now we are supporting only two pipes */
2378                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2379
2380                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2381                         if (pipe_ctx->plane_state->visible)
2382                                 blender_mode = BLND_MODE_BLENDING;
2383                         else
2384                                 blender_mode = BLND_MODE_OTHER_PIPE;
2385
2386                 } else if (!pipe_ctx->plane_state->visible)
2387                         blank_target = true;
2388
2389         } else if (!pipe_ctx->plane_state->visible)
2390                 blank_target = true;
2391
2392         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2393         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2394
2395 }
2396
2397 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2398 {
2399         int i = 0;
2400         struct xfm_grph_csc_adjustment adjust;
2401         memset(&adjust, 0, sizeof(adjust));
2402         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2403
2404
2405         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2406                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2407
2408                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2409                         adjust.temperature_matrix[i] =
2410                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2411         }
2412
2413         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2414 }
2415 static void update_plane_addr(const struct dc *dc,
2416                 struct pipe_ctx *pipe_ctx)
2417 {
2418         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2419
2420         if (plane_state == NULL)
2421                 return;
2422
2423         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2424                         pipe_ctx->plane_res.mi,
2425                         &plane_state->address,
2426                         plane_state->flip_immediate);
2427
2428         plane_state->status.requested_address = plane_state->address;
2429 }
2430
2431 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2432 {
2433         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2434
2435         if (plane_state == NULL)
2436                 return;
2437
2438         plane_state->status.is_flip_pending =
2439                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2440                                         pipe_ctx->plane_res.mi);
2441
2442         if (plane_state->status.is_flip_pending && !plane_state->visible)
2443                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2444
2445         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2446         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2447                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2448                 plane_state->status.is_right_eye =\
2449                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2450         }
2451 }
2452
2453 void dce110_power_down(struct dc *dc)
2454 {
2455         power_down_all_hw_blocks(dc);
2456         disable_vga_and_power_gate_all_controllers(dc);
2457 }
2458
2459 static bool wait_for_reset_trigger_to_occur(
2460         struct dc_context *dc_ctx,
2461         struct timing_generator *tg)
2462 {
2463         struct dc_context *ctx = dc_ctx;
2464         bool rc = false;
2465
2466         /* To avoid endless loop we wait at most
2467          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2468         const uint32_t frames_to_wait_on_triggered_reset = 10;
2469         uint32_t i;
2470
2471         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2472
2473                 if (!tg->funcs->is_counter_moving(tg)) {
2474                         DC_ERROR("TG counter is not moving!\n");
2475                         break;
2476                 }
2477
2478                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2479                         rc = true;
2480                         /* usually occurs at i=1 */
2481                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2482                                         i);
2483                         break;
2484                 }
2485
2486                 /* Wait for one frame. */
2487                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2488                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2489         }
2490
2491         if (false == rc)
2492                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2493
2494         return rc;
2495 }
2496
2497 /* Enable timing synchronization for a group of Timing Generators. */
2498 static void dce110_enable_timing_synchronization(
2499                 struct dc *dc,
2500                 int group_index,
2501                 int group_size,
2502                 struct pipe_ctx *grouped_pipes[])
2503 {
2504         struct dc_context *dc_ctx = dc->ctx;
2505         struct dcp_gsl_params gsl_params = { 0 };
2506         int i;
2507         DC_LOGGER_INIT();
2508
2509         DC_SYNC_INFO("GSL: Setting-up...\n");
2510
2511         /* Designate a single TG in the group as a master.
2512          * Since HW doesn't care which one, we always assign
2513          * the 1st one in the group. */
2514         gsl_params.gsl_group = 0;
2515         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2516
2517         for (i = 0; i < group_size; i++)
2518                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2519                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2520
2521         /* Reset slave controllers on master VSync */
2522         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2523
2524         for (i = 1 /* skip the master */; i < group_size; i++)
2525                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2526                                 grouped_pipes[i]->stream_res.tg,
2527                                 gsl_params.gsl_group);
2528
2529         for (i = 1 /* skip the master */; i < group_size; i++) {
2530                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2531                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2532                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2533                                 grouped_pipes[i]->stream_res.tg);
2534         }
2535
2536         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2537          * is that the sync'ed displays will not drift out of sync over time*/
2538         DC_SYNC_INFO("GSL: Restoring register states.\n");
2539         for (i = 0; i < group_size; i++)
2540                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2541
2542         DC_SYNC_INFO("GSL: Set-up complete.\n");
2543 }
2544
2545 static void dce110_enable_per_frame_crtc_position_reset(
2546                 struct dc *dc,
2547                 int group_size,
2548                 struct pipe_ctx *grouped_pipes[])
2549 {
2550         struct dc_context *dc_ctx = dc->ctx;
2551         struct dcp_gsl_params gsl_params = { 0 };
2552         int i;
2553         DC_LOGGER_INIT();
2554
2555         gsl_params.gsl_group = 0;
2556         gsl_params.gsl_master = 0;
2557
2558         for (i = 0; i < group_size; i++)
2559                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2560                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2561
2562         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2563
2564         for (i = 1; i < group_size; i++)
2565                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2566                                 grouped_pipes[i]->stream_res.tg,
2567                                 gsl_params.gsl_master,
2568                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2569
2570         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2571         for (i = 1; i < group_size; i++)
2572                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2573
2574         for (i = 0; i < group_size; i++)
2575                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2576
2577 }
2578
2579 static void init_pipes(struct dc *dc, struct dc_state *context)
2580 {
2581         // Do nothing
2582 }
2583
2584 static void init_hw(struct dc *dc)
2585 {
2586         int i;
2587         struct dc_bios *bp;
2588         struct transform *xfm;
2589         struct abm *abm;
2590         struct dmcu *dmcu;
2591         struct dce_hwseq *hws = dc->hwseq;
2592         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2593
2594         bp = dc->ctx->dc_bios;
2595         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2596                 xfm = dc->res_pool->transforms[i];
2597                 xfm->funcs->transform_reset(xfm);
2598
2599                 hws->funcs.enable_display_power_gating(
2600                                 dc, i, bp,
2601                                 PIPE_GATING_CONTROL_INIT);
2602                 hws->funcs.enable_display_power_gating(
2603                                 dc, i, bp,
2604                                 PIPE_GATING_CONTROL_DISABLE);
2605                 hws->funcs.enable_display_pipe_clock_gating(
2606                         dc->ctx,
2607                         true);
2608         }
2609
2610         dce_clock_gating_power_up(dc->hwseq, false);
2611         /***************************************/
2612
2613         for (i = 0; i < dc->link_count; i++) {
2614                 /****************************************/
2615                 /* Power up AND update implementation according to the
2616                  * required signal (which may be different from the
2617                  * default signal on connector). */
2618                 struct dc_link *link = dc->links[i];
2619
2620                 link->link_enc->funcs->hw_init(link->link_enc);
2621         }
2622
2623         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2624                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2625
2626                 tg->funcs->disable_vga(tg);
2627
2628                 /* Blank controller using driver code instead of
2629                  * command table. */
2630                 tg->funcs->set_blank(tg, true);
2631                 hwss_wait_for_blank_complete(tg);
2632         }
2633
2634         for (i = 0; i < dc->res_pool->audio_count; i++) {
2635                 struct audio *audio = dc->res_pool->audios[i];
2636                 audio->funcs->hw_init(audio);
2637         }
2638
2639         for (i = 0; i < dc->link_count; i++) {
2640                 struct dc_link *link = dc->links[i];
2641
2642                 if (link->panel_cntl)
2643                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2644         }
2645
2646         abm = dc->res_pool->abm;
2647         if (abm != NULL)
2648                 abm->funcs->abm_init(abm, backlight);
2649
2650         dmcu = dc->res_pool->dmcu;
2651         if (dmcu != NULL && abm != NULL)
2652                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2653
2654         if (dc->fbc_compressor)
2655                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2656
2657 }
2658
2659
2660 void dce110_prepare_bandwidth(
2661                 struct dc *dc,
2662                 struct dc_state *context)
2663 {
2664         struct clk_mgr *dccg = dc->clk_mgr;
2665
2666         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2667         if (dccg)
2668                 dccg->funcs->update_clocks(
2669                                 dccg,
2670                                 context,
2671                                 false);
2672 }
2673
2674 void dce110_optimize_bandwidth(
2675                 struct dc *dc,
2676                 struct dc_state *context)
2677 {
2678         struct clk_mgr *dccg = dc->clk_mgr;
2679
2680         dce110_set_displaymarks(dc, context);
2681
2682         if (dccg)
2683                 dccg->funcs->update_clocks(
2684                                 dccg,
2685                                 context,
2686                                 true);
2687 }
2688
2689 static void dce110_program_front_end_for_pipe(
2690                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2691 {
2692         struct mem_input *mi = pipe_ctx->plane_res.mi;
2693         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2694         struct xfm_grph_csc_adjustment adjust;
2695         struct out_csc_color_matrix tbl_entry;
2696         unsigned int i;
2697         struct dce_hwseq *hws = dc->hwseq;
2698
2699         memset(&tbl_entry, 0, sizeof(tbl_entry));
2700
2701         memset(&adjust, 0, sizeof(adjust));
2702         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2703
2704         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2705
2706         set_default_colors(pipe_ctx);
2707         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2708                         == true) {
2709                 tbl_entry.color_space =
2710                         pipe_ctx->stream->output_color_space;
2711
2712                 for (i = 0; i < 12; i++)
2713                         tbl_entry.regval[i] =
2714                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2715
2716                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2717                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2718         }
2719
2720         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2721                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2722
2723                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2724                         adjust.temperature_matrix[i] =
2725                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2726         }
2727
2728         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2729
2730         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
2731
2732         program_scaler(dc, pipe_ctx);
2733
2734         mi->funcs->mem_input_program_surface_config(
2735                         mi,
2736                         plane_state->format,
2737                         &plane_state->tiling_info,
2738                         &plane_state->plane_size,
2739                         plane_state->rotation,
2740                         NULL,
2741                         false);
2742         if (mi->funcs->set_blank)
2743                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2744
2745         if (dc->config.gpu_vm_support)
2746                 mi->funcs->mem_input_program_pte_vm(
2747                                 pipe_ctx->plane_res.mi,
2748                                 plane_state->format,
2749                                 &plane_state->tiling_info,
2750                                 plane_state->rotation);
2751
2752         /* Moved programming gamma from dc to hwss */
2753         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2754                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2755                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2756                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2757
2758         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2759                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2760
2761         DC_LOG_SURFACE(
2762                         "Pipe:%d %p: addr hi:0x%x, "
2763                         "addr low:0x%x, "
2764                         "src: %d, %d, %d,"
2765                         " %d; dst: %d, %d, %d, %d;"
2766                         "clip: %d, %d, %d, %d\n",
2767                         pipe_ctx->pipe_idx,
2768                         (void *) pipe_ctx->plane_state,
2769                         pipe_ctx->plane_state->address.grph.addr.high_part,
2770                         pipe_ctx->plane_state->address.grph.addr.low_part,
2771                         pipe_ctx->plane_state->src_rect.x,
2772                         pipe_ctx->plane_state->src_rect.y,
2773                         pipe_ctx->plane_state->src_rect.width,
2774                         pipe_ctx->plane_state->src_rect.height,
2775                         pipe_ctx->plane_state->dst_rect.x,
2776                         pipe_ctx->plane_state->dst_rect.y,
2777                         pipe_ctx->plane_state->dst_rect.width,
2778                         pipe_ctx->plane_state->dst_rect.height,
2779                         pipe_ctx->plane_state->clip_rect.x,
2780                         pipe_ctx->plane_state->clip_rect.y,
2781                         pipe_ctx->plane_state->clip_rect.width,
2782                         pipe_ctx->plane_state->clip_rect.height);
2783
2784         DC_LOG_SURFACE(
2785                         "Pipe %d: width, height, x, y\n"
2786                         "viewport:%d, %d, %d, %d\n"
2787                         "recout:  %d, %d, %d, %d\n",
2788                         pipe_ctx->pipe_idx,
2789                         pipe_ctx->plane_res.scl_data.viewport.width,
2790                         pipe_ctx->plane_res.scl_data.viewport.height,
2791                         pipe_ctx->plane_res.scl_data.viewport.x,
2792                         pipe_ctx->plane_res.scl_data.viewport.y,
2793                         pipe_ctx->plane_res.scl_data.recout.width,
2794                         pipe_ctx->plane_res.scl_data.recout.height,
2795                         pipe_ctx->plane_res.scl_data.recout.x,
2796                         pipe_ctx->plane_res.scl_data.recout.y);
2797 }
2798
2799 static void dce110_apply_ctx_for_surface(
2800                 struct dc *dc,
2801                 const struct dc_stream_state *stream,
2802                 int num_planes,
2803                 struct dc_state *context)
2804 {
2805         int i;
2806
2807         if (num_planes == 0)
2808                 return;
2809
2810         if (dc->fbc_compressor)
2811                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2812
2813         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2814                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2815
2816                 if (pipe_ctx->stream != stream)
2817                         continue;
2818
2819                 /* Need to allocate mem before program front end for Fiji */
2820                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2821                                 pipe_ctx->plane_res.mi,
2822                                 pipe_ctx->stream->timing.h_total,
2823                                 pipe_ctx->stream->timing.v_total,
2824                                 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2825                                 context->stream_count);
2826
2827                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2828
2829                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2830
2831                 program_surface_visibility(dc, pipe_ctx);
2832
2833         }
2834
2835         if (dc->fbc_compressor)
2836                 enable_fbc(dc, context);
2837 }
2838
2839 static void dce110_post_unlock_program_front_end(
2840                 struct dc *dc,
2841                 struct dc_state *context)
2842 {
2843 }
2844
2845 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2846 {
2847         struct dce_hwseq *hws = dc->hwseq;
2848         int fe_idx = pipe_ctx->plane_res.mi ?
2849                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2850
2851         /* Do not power down fe when stream is active on dce*/
2852         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2853                 return;
2854
2855         hws->funcs.enable_display_power_gating(
2856                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2857
2858         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2859                                 dc->res_pool->transforms[fe_idx]);
2860 }
2861
2862 static void dce110_wait_for_mpcc_disconnect(
2863                 struct dc *dc,
2864                 struct resource_pool *res_pool,
2865                 struct pipe_ctx *pipe_ctx)
2866 {
2867         /* do nothing*/
2868 }
2869
2870 static void program_output_csc(struct dc *dc,
2871                 struct pipe_ctx *pipe_ctx,
2872                 enum dc_color_space colorspace,
2873                 uint16_t *matrix,
2874                 int opp_id)
2875 {
2876         int i;
2877         struct out_csc_color_matrix tbl_entry;
2878
2879         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2880                 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2881
2882                 for (i = 0; i < 12; i++)
2883                         tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2884
2885                 tbl_entry.color_space = color_space;
2886
2887                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2888                                 pipe_ctx->plane_res.xfm, &tbl_entry);
2889         }
2890 }
2891
2892 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2893 {
2894         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2895         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2896         struct mem_input *mi = pipe_ctx->plane_res.mi;
2897         struct dc_cursor_mi_param param = {
2898                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2899                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2900                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2901                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2902                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2903                 .rotation = pipe_ctx->plane_state->rotation,
2904                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2905         };
2906
2907         /**
2908          * If the cursor's source viewport is clipped then we need to
2909          * translate the cursor to appear in the correct position on
2910          * the screen.
2911          *
2912          * This translation isn't affected by scaling so it needs to be
2913          * done *after* we adjust the position for the scale factor.
2914          *
2915          * This is only done by opt-in for now since there are still
2916          * some usecases like tiled display that might enable the
2917          * cursor on both streams while expecting dc to clip it.
2918          */
2919         if (pos_cpy.translate_by_source) {
2920                 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2921                 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2922         }
2923
2924         if (pipe_ctx->plane_state->address.type
2925                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2926                 pos_cpy.enable = false;
2927
2928         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2929                 pos_cpy.enable = false;
2930
2931         if (ipp->funcs->ipp_cursor_set_position)
2932                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2933         if (mi->funcs->set_cursor_position)
2934                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2935 }
2936
2937 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2938 {
2939         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2940
2941         if (pipe_ctx->plane_res.ipp &&
2942             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2943                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2944                                 pipe_ctx->plane_res.ipp, attributes);
2945
2946         if (pipe_ctx->plane_res.mi &&
2947             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2948                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2949                                 pipe_ctx->plane_res.mi, attributes);
2950
2951         if (pipe_ctx->plane_res.xfm &&
2952             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2953                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2954                                 pipe_ctx->plane_res.xfm, attributes);
2955 }
2956
2957 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
2958                 uint32_t backlight_pwm_u16_16,
2959                 uint32_t frame_ramp)
2960 {
2961         struct dc_link *link = pipe_ctx->stream->link;
2962         struct dc  *dc = link->ctx->dc;
2963         struct abm *abm = pipe_ctx->stream_res.abm;
2964         struct panel_cntl *panel_cntl = link->panel_cntl;
2965         struct dmcu *dmcu = dc->res_pool->dmcu;
2966         bool fw_set_brightness = true;
2967         /* DMCU -1 for all controller id values,
2968          * therefore +1 here
2969          */
2970         uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
2971
2972         if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
2973                 return false;
2974
2975         if (dmcu)
2976                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2977
2978         if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
2979                 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
2980         else
2981                 abm->funcs->set_backlight_level_pwm(
2982                                 abm,
2983                                 backlight_pwm_u16_16,
2984                                 frame_ramp,
2985                                 controller_id,
2986                                 link->panel_cntl->inst);
2987
2988         return true;
2989 }
2990
2991 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
2992 {
2993         struct abm *abm = pipe_ctx->stream_res.abm;
2994         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2995
2996         if (abm)
2997                 abm->funcs->set_abm_immediate_disable(abm,
2998                                 pipe_ctx->stream->link->panel_cntl->inst);
2999
3000         if (panel_cntl)
3001                 panel_cntl->funcs->store_backlight_level(panel_cntl);
3002 }
3003
3004 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
3005 {
3006         struct abm *abm = pipe_ctx->stream_res.abm;
3007         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3008         uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
3009
3010         if (abm && panel_cntl)
3011                 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
3012 }
3013
3014 void dce110_enable_lvds_link_output(struct dc_link *link,
3015                 const struct link_resource *link_res,
3016                 enum clock_source_id clock_source,
3017                 uint32_t pixel_clock)
3018 {
3019         link->link_enc->funcs->enable_lvds_output(
3020                         link->link_enc,
3021                         clock_source,
3022                         pixel_clock);
3023         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3024 }
3025
3026 void dce110_enable_tmds_link_output(struct dc_link *link,
3027                 const struct link_resource *link_res,
3028                 enum signal_type signal,
3029                 enum clock_source_id clock_source,
3030                 enum dc_color_depth color_depth,
3031                 uint32_t pixel_clock)
3032 {
3033         link->link_enc->funcs->enable_tmds_output(
3034                         link->link_enc,
3035                         clock_source,
3036                         color_depth,
3037                         signal,
3038                         pixel_clock);
3039         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3040 }
3041
3042 void dce110_enable_dp_link_output(
3043                 struct dc_link *link,
3044                 const struct link_resource *link_res,
3045                 enum signal_type signal,
3046                 enum clock_source_id clock_source,
3047                 const struct dc_link_settings *link_settings)
3048 {
3049         struct dc  *dc = link->ctx->dc;
3050         struct dmcu *dmcu = dc->res_pool->dmcu;
3051         struct pipe_ctx *pipes =
3052                         link->dc->current_state->res_ctx.pipe_ctx;
3053         struct clock_source *dp_cs =
3054                         link->dc->res_pool->dp_clock_source;
3055         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3056         unsigned int i;
3057
3058         /*
3059          * Add the logic to extract BOTH power up and power down sequences
3060          * from enable/disable link output and only call edp panel control
3061          * in enable_link_dp and disable_link_dp once.
3062          */
3063         if (link->connector_signal == SIGNAL_TYPE_EDP) {
3064                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
3065         }
3066
3067         /* If the current pixel clock source is not DTO(happens after
3068          * switching from HDMI passive dongle to DP on the same connector),
3069          * switch the pixel clock source to DTO.
3070          */
3071
3072         for (i = 0; i < MAX_PIPES; i++) {
3073                 if (pipes[i].stream != NULL &&
3074                                 pipes[i].stream->link == link) {
3075                         if (pipes[i].clock_source != NULL &&
3076                                         pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
3077                                 pipes[i].clock_source = dp_cs;
3078                                 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
3079                                                 pipes[i].stream->timing.pix_clk_100hz;
3080                                 pipes[i].clock_source->funcs->program_pix_clk(
3081                                                 pipes[i].clock_source,
3082                                                 &pipes[i].stream_res.pix_clk_params,
3083                                                 dc->link_srv->dp_get_encoding_format(link_settings),
3084                                                 &pipes[i].pll_settings);
3085                         }
3086                 }
3087         }
3088
3089         if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
3090                 if (dc->clk_mgr->funcs->notify_link_rate_change)
3091                         dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
3092         }
3093
3094         if (dmcu != NULL && dmcu->funcs->lock_phy)
3095                 dmcu->funcs->lock_phy(dmcu);
3096
3097         if (link_hwss->ext.enable_dp_link_output)
3098                 link_hwss->ext.enable_dp_link_output(link, link_res, signal,
3099                                 clock_source, link_settings);
3100
3101         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3102
3103         if (dmcu != NULL && dmcu->funcs->unlock_phy)
3104                 dmcu->funcs->unlock_phy(dmcu);
3105
3106         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);
3107 }
3108
3109 void dce110_disable_link_output(struct dc_link *link,
3110                 const struct link_resource *link_res,
3111                 enum signal_type signal)
3112 {
3113         struct dc *dc = link->ctx->dc;
3114         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3115         struct dmcu *dmcu = dc->res_pool->dmcu;
3116
3117         if (signal == SIGNAL_TYPE_EDP &&
3118                         link->dc->hwss.edp_backlight_control &&
3119                         !link->skip_implict_edp_power_control)
3120                 link->dc->hwss.edp_backlight_control(link, false);
3121         else if (dmcu != NULL && dmcu->funcs->lock_phy)
3122                 dmcu->funcs->lock_phy(dmcu);
3123
3124         link_hwss->disable_link_output(link, link_res, signal);
3125         link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
3126         /*
3127          * Add the logic to extract BOTH power up and power down sequences
3128          * from enable/disable link output and only call edp panel control
3129          * in enable_link_dp and disable_link_dp once.
3130          */
3131         if (dmcu != NULL && dmcu->funcs->lock_phy)
3132                 dmcu->funcs->unlock_phy(dmcu);
3133         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
3134 }
3135
3136 static const struct hw_sequencer_funcs dce110_funcs = {
3137         .program_gamut_remap = program_gamut_remap,
3138         .program_output_csc = program_output_csc,
3139         .init_hw = init_hw,
3140         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3141         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
3142         .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
3143         .update_plane_addr = update_plane_addr,
3144         .update_pending_status = dce110_update_pending_status,
3145         .enable_accelerated_mode = dce110_enable_accelerated_mode,
3146         .enable_timing_synchronization = dce110_enable_timing_synchronization,
3147         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
3148         .update_info_frame = dce110_update_info_frame,
3149         .enable_stream = dce110_enable_stream,
3150         .disable_stream = dce110_disable_stream,
3151         .unblank_stream = dce110_unblank_stream,
3152         .blank_stream = dce110_blank_stream,
3153         .enable_audio_stream = dce110_enable_audio_stream,
3154         .disable_audio_stream = dce110_disable_audio_stream,
3155         .disable_plane = dce110_power_down_fe,
3156         .pipe_control_lock = dce_pipe_control_lock,
3157         .interdependent_update_lock = NULL,
3158         .cursor_lock = dce_pipe_control_lock,
3159         .prepare_bandwidth = dce110_prepare_bandwidth,
3160         .optimize_bandwidth = dce110_optimize_bandwidth,
3161         .set_drr = set_drr,
3162         .get_position = get_position,
3163         .set_static_screen_control = set_static_screen_control,
3164         .setup_stereo = NULL,
3165         .set_avmute = dce110_set_avmute,
3166         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3167         .edp_backlight_control = dce110_edp_backlight_control,
3168         .edp_power_control = dce110_edp_power_control,
3169         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3170         .set_cursor_position = dce110_set_cursor_position,
3171         .set_cursor_attribute = dce110_set_cursor_attribute,
3172         .set_backlight_level = dce110_set_backlight_level,
3173         .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
3174         .set_pipe = dce110_set_pipe,
3175         .enable_lvds_link_output = dce110_enable_lvds_link_output,
3176         .enable_tmds_link_output = dce110_enable_tmds_link_output,
3177         .enable_dp_link_output = dce110_enable_dp_link_output,
3178         .disable_link_output = dce110_disable_link_output,
3179 };
3180
3181 static const struct hwseq_private_funcs dce110_private_funcs = {
3182         .init_pipes = init_pipes,
3183         .update_plane_addr = update_plane_addr,
3184         .set_input_transfer_func = dce110_set_input_transfer_func,
3185         .set_output_transfer_func = dce110_set_output_transfer_func,
3186         .power_down = dce110_power_down,
3187         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3188         .enable_display_power_gating = dce110_enable_display_power_gating,
3189         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3190         .enable_stream_timing = dce110_enable_stream_timing,
3191         .disable_stream_gating = NULL,
3192         .enable_stream_gating = NULL,
3193         .edp_backlight_control = dce110_edp_backlight_control,
3194 };
3195
3196 void dce110_hw_sequencer_construct(struct dc *dc)
3197 {
3198         dc->hwss = dce110_funcs;
3199         dc->hwseq->funcs = dce110_private_funcs;
3200 }
3201