2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
28 #include "amdgpu_uvd.h"
31 #include "uvd/uvd_4_2_d.h"
32 #include "uvd/uvd_4_2_sh_mask.h"
34 #include "oss/oss_2_0_d.h"
35 #include "oss/oss_2_0_sh_mask.h"
37 #include "bif/bif_4_1_d.h"
39 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
40 static void uvd_v4_2_init_cg(struct amdgpu_device *adev);
41 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
42 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
43 static int uvd_v4_2_start(struct amdgpu_device *adev);
44 static void uvd_v4_2_stop(struct amdgpu_device *adev);
47 * uvd_v4_2_ring_get_rptr - get read pointer
49 * @ring: amdgpu_ring pointer
51 * Returns the current hardware read pointer
53 static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
55 struct amdgpu_device *adev = ring->adev;
57 return RREG32(mmUVD_RBC_RB_RPTR);
61 * uvd_v4_2_ring_get_wptr - get write pointer
63 * @ring: amdgpu_ring pointer
65 * Returns the current hardware write pointer
67 static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
69 struct amdgpu_device *adev = ring->adev;
71 return RREG32(mmUVD_RBC_RB_WPTR);
75 * uvd_v4_2_ring_set_wptr - set write pointer
77 * @ring: amdgpu_ring pointer
79 * Commits the write pointer to the hardware
81 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
83 struct amdgpu_device *adev = ring->adev;
85 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
88 static int uvd_v4_2_early_init(void *handle)
90 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
92 uvd_v4_2_set_ring_funcs(adev);
93 uvd_v4_2_set_irq_funcs(adev);
98 static int uvd_v4_2_sw_init(void *handle)
100 struct amdgpu_ring *ring;
101 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
105 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
109 r = amdgpu_uvd_sw_init(adev);
113 r = amdgpu_uvd_resume(adev);
117 ring = &adev->uvd.ring;
118 sprintf(ring->name, "uvd");
119 r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
120 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
125 static int uvd_v4_2_sw_fini(void *handle)
128 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
130 r = amdgpu_uvd_suspend(adev);
134 r = amdgpu_uvd_sw_fini(adev);
142 * uvd_v4_2_hw_init - start and test UVD block
144 * @adev: amdgpu_device pointer
146 * Initialize the hardware, boot up the VCPU and do some testing
148 static int uvd_v4_2_hw_init(void *handle)
150 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
151 struct amdgpu_ring *ring = &adev->uvd.ring;
155 /* raise clocks while booting up the VCPU */
156 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
158 r = uvd_v4_2_start(adev);
163 r = amdgpu_ring_test_ring(ring);
169 r = amdgpu_ring_alloc(ring, 10);
171 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
175 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
176 amdgpu_ring_write(ring, tmp);
177 amdgpu_ring_write(ring, 0xFFFFF);
179 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
180 amdgpu_ring_write(ring, tmp);
181 amdgpu_ring_write(ring, 0xFFFFF);
183 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
184 amdgpu_ring_write(ring, tmp);
185 amdgpu_ring_write(ring, 0xFFFFF);
187 /* Clear timeout status bits */
188 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
189 amdgpu_ring_write(ring, 0x8);
191 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
192 amdgpu_ring_write(ring, 3);
194 amdgpu_ring_commit(ring);
197 /* lower clocks again */
198 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
201 DRM_INFO("UVD initialized successfully.\n");
207 * uvd_v4_2_hw_fini - stop the hardware block
209 * @adev: amdgpu_device pointer
211 * Stop the UVD block, mark ring as not ready any more
213 static int uvd_v4_2_hw_fini(void *handle)
215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
216 struct amdgpu_ring *ring = &adev->uvd.ring;
224 static int uvd_v4_2_suspend(void *handle)
227 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
229 r = uvd_v4_2_hw_fini(adev);
233 r = amdgpu_uvd_suspend(adev);
240 static int uvd_v4_2_resume(void *handle)
243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
245 r = amdgpu_uvd_resume(adev);
249 r = uvd_v4_2_hw_init(adev);
257 * uvd_v4_2_start - start UVD block
259 * @adev: amdgpu_device pointer
261 * Setup and start the UVD block
263 static int uvd_v4_2_start(struct amdgpu_device *adev)
265 struct amdgpu_ring *ring = &adev->uvd.ring;
269 /* disable byte swapping */
270 u32 lmi_swap_cntl = 0;
271 u32 mp_swap_cntl = 0;
273 uvd_v4_2_mc_resume(adev);
275 /* disable clock gating */
276 WREG32(mmUVD_CGC_GATE, 0);
278 /* disable interupt */
279 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
281 /* Stall UMC and register bus before resetting VCPU */
282 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
285 /* put LMI, VCPU, RBC etc... into reset */
286 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
287 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
288 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
289 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
290 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
293 /* take UVD block out of reset */
294 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
297 /* initialize UVD memory controller */
298 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
299 (1 << 21) | (1 << 9) | (1 << 20));
302 /* swap (8 in 32) RB and IB */
306 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
307 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
309 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
310 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
311 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
312 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
313 WREG32(mmUVD_MPC_SET_ALU, 0);
314 WREG32(mmUVD_MPC_SET_MUX, 0x88);
316 /* take all subblocks out of reset, except VCPU */
317 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
320 /* enable VCPU clock */
321 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
324 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
326 /* boot up the VCPU */
327 WREG32(mmUVD_SOFT_RESET, 0);
330 for (i = 0; i < 10; ++i) {
332 for (j = 0; j < 100; ++j) {
333 status = RREG32(mmUVD_STATUS);
342 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
343 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
344 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
346 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
352 DRM_ERROR("UVD not responding, giving up!!!\n");
356 /* enable interupt */
357 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
359 /* force RBC into idle state */
360 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
362 /* Set the write pointer delay */
363 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
365 /* programm the 4GB memory segment for rptr and ring buffer */
366 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
367 (0x7 << 16) | (0x1 << 31));
369 /* Initialize the ring buffer's read and write pointers */
370 WREG32(mmUVD_RBC_RB_RPTR, 0x0);
372 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
373 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
375 /* set the ring address */
376 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
378 /* Set ring buffer size */
379 rb_bufsz = order_base_2(ring->ring_size);
380 rb_bufsz = (0x1 << 8) | rb_bufsz;
381 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
387 * uvd_v4_2_stop - stop UVD block
389 * @adev: amdgpu_device pointer
393 static void uvd_v4_2_stop(struct amdgpu_device *adev)
395 /* force RBC into idle state */
396 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
398 /* Stall UMC and register bus before resetting VCPU */
399 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
402 /* put VCPU into reset */
403 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
406 /* disable VCPU clock */
407 WREG32(mmUVD_VCPU_CNTL, 0x0);
409 /* Unstall UMC and register bus */
410 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
414 * uvd_v4_2_ring_emit_fence - emit an fence & trap command
416 * @ring: amdgpu_ring pointer
417 * @fence: fence to emit
419 * Write a fence and a trap command to the ring.
421 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
424 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
426 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
427 amdgpu_ring_write(ring, seq);
428 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
429 amdgpu_ring_write(ring, addr & 0xffffffff);
430 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
431 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
432 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
433 amdgpu_ring_write(ring, 0);
435 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
436 amdgpu_ring_write(ring, 0);
437 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
438 amdgpu_ring_write(ring, 0);
439 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
440 amdgpu_ring_write(ring, 2);
444 * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush
446 * @ring: amdgpu_ring pointer
448 * Emits an hdp flush.
450 static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
452 amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
453 amdgpu_ring_write(ring, 0);
457 * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate
459 * @ring: amdgpu_ring pointer
461 * Emits an hdp invalidate.
463 static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
465 amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
466 amdgpu_ring_write(ring, 1);
470 * uvd_v4_2_ring_test_ring - register write test
472 * @ring: amdgpu_ring pointer
474 * Test if we can successfully write to the context register
476 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
478 struct amdgpu_device *adev = ring->adev;
483 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
484 r = amdgpu_ring_alloc(ring, 3);
486 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
490 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
491 amdgpu_ring_write(ring, 0xDEADBEEF);
492 amdgpu_ring_commit(ring);
493 for (i = 0; i < adev->usec_timeout; i++) {
494 tmp = RREG32(mmUVD_CONTEXT_ID);
495 if (tmp == 0xDEADBEEF)
500 if (i < adev->usec_timeout) {
501 DRM_INFO("ring test on %d succeeded in %d usecs\n",
504 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
512 * uvd_v4_2_ring_emit_ib - execute indirect buffer
514 * @ring: amdgpu_ring pointer
515 * @ib: indirect buffer to execute
517 * Write ring commands to execute the indirect buffer
519 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
520 struct amdgpu_ib *ib,
521 unsigned vm_id, bool ctx_switch)
523 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
524 amdgpu_ring_write(ring, ib->gpu_addr);
525 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
526 amdgpu_ring_write(ring, ib->length_dw);
530 * uvd_v4_2_mc_resume - memory controller programming
532 * @adev: amdgpu_device pointer
534 * Let the UVD memory controller know it's offsets
536 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
541 /* programm the VCPU memory controller bits 0-27 */
542 addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
543 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
544 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
545 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
548 size = AMDGPU_UVD_HEAP_SIZE >> 3;
549 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
550 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
553 size = (AMDGPU_UVD_STACK_SIZE +
554 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
555 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
556 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
559 addr = (adev->uvd.gpu_addr >> 28) & 0xF;
560 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
563 addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
564 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
566 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
567 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
568 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
570 uvd_v4_2_init_cg(adev);
573 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
578 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
579 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
581 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
583 orig = data = RREG32(mmUVD_CGC_CTRL);
584 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
586 WREG32(mmUVD_CGC_CTRL, data);
588 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
590 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
592 orig = data = RREG32(mmUVD_CGC_CTRL);
593 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
595 WREG32(mmUVD_CGC_CTRL, data);
599 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
604 tmp = RREG32(mmUVD_CGC_CTRL);
605 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
606 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
607 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
608 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
612 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
613 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
614 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
620 WREG32(mmUVD_CGC_CTRL, tmp);
621 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
624 static void uvd_v4_2_init_cg(struct amdgpu_device *adev)
629 uvd_v4_2_set_dcm(adev, false);
631 u32 tmp = RREG32(mmUVD_CGC_CTRL);
632 tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
633 WREG32(mmUVD_CGC_CTRL, tmp);
637 static bool uvd_v4_2_is_idle(void *handle)
639 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
641 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
644 static int uvd_v4_2_wait_for_idle(void *handle)
647 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
649 for (i = 0; i < adev->usec_timeout; i++) {
650 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
656 static int uvd_v4_2_soft_reset(void *handle)
658 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
662 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
663 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
666 return uvd_v4_2_start(adev);
669 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
670 struct amdgpu_irq_src *source,
672 enum amdgpu_interrupt_state state)
678 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
679 struct amdgpu_irq_src *source,
680 struct amdgpu_iv_entry *entry)
682 DRM_DEBUG("IH: UVD TRAP\n");
683 amdgpu_fence_process(&adev->uvd.ring);
687 static int uvd_v4_2_set_clockgating_state(void *handle,
688 enum amd_clockgating_state state)
691 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
693 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
696 if (state == AMD_CG_STATE_GATE)
699 uvd_v4_2_enable_mgcg(adev, gate);
704 static int uvd_v4_2_set_powergating_state(void *handle,
705 enum amd_powergating_state state)
707 /* This doesn't actually powergate the UVD block.
708 * That's done in the dpm code via the SMC. This
709 * just re-inits the block as necessary. The actual
710 * gating still happens in the dpm code. We should
711 * revisit this when there is a cleaner line between
712 * the smc and the hw blocks
714 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
716 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
719 if (state == AMD_PG_STATE_GATE) {
723 return uvd_v4_2_start(adev);
727 const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
729 .early_init = uvd_v4_2_early_init,
731 .sw_init = uvd_v4_2_sw_init,
732 .sw_fini = uvd_v4_2_sw_fini,
733 .hw_init = uvd_v4_2_hw_init,
734 .hw_fini = uvd_v4_2_hw_fini,
735 .suspend = uvd_v4_2_suspend,
736 .resume = uvd_v4_2_resume,
737 .is_idle = uvd_v4_2_is_idle,
738 .wait_for_idle = uvd_v4_2_wait_for_idle,
739 .soft_reset = uvd_v4_2_soft_reset,
740 .set_clockgating_state = uvd_v4_2_set_clockgating_state,
741 .set_powergating_state = uvd_v4_2_set_powergating_state,
744 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
745 .get_rptr = uvd_v4_2_ring_get_rptr,
746 .get_wptr = uvd_v4_2_ring_get_wptr,
747 .set_wptr = uvd_v4_2_ring_set_wptr,
748 .parse_cs = amdgpu_uvd_ring_parse_cs,
749 .emit_ib = uvd_v4_2_ring_emit_ib,
750 .emit_fence = uvd_v4_2_ring_emit_fence,
751 .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush,
752 .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate,
753 .test_ring = uvd_v4_2_ring_test_ring,
754 .test_ib = amdgpu_uvd_ring_test_ib,
755 .insert_nop = amdgpu_ring_insert_nop,
756 .pad_ib = amdgpu_ring_generic_pad_ib,
757 .begin_use = amdgpu_uvd_ring_begin_use,
758 .end_use = amdgpu_uvd_ring_end_use,
761 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
763 adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;
766 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
767 .set = uvd_v4_2_set_interrupt_state,
768 .process = uvd_v4_2_process_interrupt,
771 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
773 adev->uvd.irq.num_types = 1;
774 adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;