drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic_helper.h>
  41 #include <drm/drm_dp_helper.h>
  42 #include <drm/drm_crtc_helper.h>
  43 #include <drm/drm_plane_helper.h>
  44 #include <drm/drm_rect.h>
  45 #include <linux/dma_remapping.h>
  46
  47 /* Primary plane formats supported by all gen */
  48 #define COMMON_PRIMARY_FORMATS \
  49         DRM_FORMAT_C8, \
  50         DRM_FORMAT_RGB565, \
  51         DRM_FORMAT_XRGB8888, \
  52         DRM_FORMAT_ARGB8888
  53
  54 /* Primary plane formats for gen <= 3 */
  55 static const uint32_t intel_primary_formats_gen2[] = {
  56         COMMON_PRIMARY_FORMATS,
  57         DRM_FORMAT_XRGB1555,
  58         DRM_FORMAT_ARGB1555,
  59 };
  60
  61 /* Primary plane formats for gen >= 4 */
  62 static const uint32_t intel_primary_formats_gen4[] = {
  63         COMMON_PRIMARY_FORMATS, \
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_ARGB2101010,
  68         DRM_FORMAT_XBGR2101010,
  69         DRM_FORMAT_ABGR2101010,
  70 };
  71
  72 /* Cursor formats */
  73 static const uint32_t intel_cursor_formats[] = {
  74         DRM_FORMAT_ARGB8888,
  75 };
  76
  77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  78
  79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  80                                 struct intel_crtc_state *pipe_config);
  81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  82                                    struct intel_crtc_state *pipe_config);
  83
  84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  85                           int x, int y, struct drm_framebuffer *old_fb);
  86 static int intel_framebuffer_init(struct drm_device *dev,
  87                                   struct intel_framebuffer *ifb,
  88                                   struct drm_mode_fb_cmd2 *mode_cmd,
  89                                   struct drm_i915_gem_object *obj);
  90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  93                                          struct intel_link_m_n *m_n,
  94                                          struct intel_link_m_n *m2_n2);
  95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  98 static void vlv_prepare_pll(struct intel_crtc *crtc,
  99                             const struct intel_crtc_state *pipe_config);
 100 static void chv_prepare_pll(struct intel_crtc *crtc,
 101                             const struct intel_crtc_state *pipe_config);
 102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 104
 105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 106 {
 107         if (!connector->mst_port)
 108                 return connector->encoder;
 109         else
 110                 return &connector->mst_port->mst_encoders[pipe]->base;
 111 }
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4860000, .max = 6700000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static void vlv_clock(int refclk, intel_clock_t *clock)
 402 {
 403         clock->m = clock->m1 * clock->m2;
 404         clock->p = clock->p1 * clock->p2;
 405         if (WARN_ON(clock->n == 0 || clock->p == 0))
 406                 return;
 407         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 408         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 409 }
 410
 411 /**
 412  * Returns whether any output on the specified pipe is of the specified type
 413  */
 414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 415 {
 416         struct drm_device *dev = crtc->base.dev;
 417         struct intel_encoder *encoder;
 418
 419         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 420                 if (encoder->type == type)
 421                         return true;
 422
 423         return false;
 424 }
 425
 426 /**
 427  * Returns whether any output on the specified pipe will have the specified
 428  * type after a staged modeset is complete, i.e., the same as
 429  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 430  * encoder->crtc.
 431  */
 432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 433 {
 434         struct drm_device *dev = crtc->base.dev;
 435         struct intel_encoder *encoder;
 436
 437         for_each_intel_encoder(dev, encoder)
 438                 if (encoder->new_crtc == crtc && encoder->type == type)
 439                         return true;
 440
 441         return false;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->base.dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev)) {
 452                         if (refclk == 100000)
 453                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 454                         else
 455                                 limit = &intel_limits_ironlake_dual_lvds;
 456                 } else {
 457                         if (refclk == 100000)
 458                                 limit = &intel_limits_ironlake_single_lvds_100m;
 459                         else
 460                                 limit = &intel_limits_ironlake_single_lvds;
 461                 }
 462         } else
 463                 limit = &intel_limits_ironlake_dac;
 464
 465         return limit;
 466 }
 467
 468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 469 {
 470         struct drm_device *dev = crtc->base.dev;
 471         const intel_limit_t *limit;
 472
 473         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 474                 if (intel_is_dual_link_lvds(dev))
 475                         limit = &intel_limits_g4x_dual_channel_lvds;
 476                 else
 477                         limit = &intel_limits_g4x_single_channel_lvds;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 479                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 480                 limit = &intel_limits_g4x_hdmi;
 481         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 482                 limit = &intel_limits_g4x_sdvo;
 483         } else /* The option is for other outputs */
 484                 limit = &intel_limits_i9xx_sdvo;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 490 {
 491         struct drm_device *dev = crtc->base.dev;
 492         const intel_limit_t *limit;
 493
 494         if (HAS_PCH_SPLIT(dev))
 495                 limit = intel_ironlake_limit(crtc, refclk);
 496         else if (IS_G4X(dev)) {
 497                 limit = intel_g4x_limit(crtc);
 498         } else if (IS_PINEVIEW(dev)) {
 499                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 500                         limit = &intel_limits_pineview_lvds;
 501                 else
 502                         limit = &intel_limits_pineview_sdvo;
 503         } else if (IS_CHERRYVIEW(dev)) {
 504                 limit = &intel_limits_chv;
 505         } else if (IS_VALLEYVIEW(dev)) {
 506                 limit = &intel_limits_vlv;
 507         } else if (!IS_GEN2(dev)) {
 508                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 509                         limit = &intel_limits_i9xx_lvds;
 510                 else
 511                         limit = &intel_limits_i9xx_sdvo;
 512         } else {
 513                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 514                         limit = &intel_limits_i8xx_lvds;
 515                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 516                         limit = &intel_limits_i8xx_dvo;
 517                 else
 518                         limit = &intel_limits_i8xx_dac;
 519         }
 520         return limit;
 521 }
 522
 523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 524 static void pineview_clock(int refclk, intel_clock_t *clock)
 525 {
 526         clock->m = clock->m2 + 2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return;
 530         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 531         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 532 }
 533
 534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 535 {
 536         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 537 }
 538
 539 static void i9xx_clock(int refclk, intel_clock_t *clock)
 540 {
 541         clock->m = i9xx_dpll_compute_m(clock);
 542         clock->p = clock->p1 * clock->p2;
 543         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 544                 return;
 545         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 546         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 547 }
 548
 549 static void chv_clock(int refclk, intel_clock_t *clock)
 550 {
 551         clock->m = clock->m1 * clock->m2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return;
 555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 556                         clock->n << 22);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558 }
 559
 560 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 561 /**
 562  * Returns whether the given set of divisors are valid for a given refclk with
 563  * the given connectors.
 564  */
 565
 566 static bool intel_PLL_is_valid(struct drm_device *dev,
 567                                const intel_limit_t *limit,
 568                                const intel_clock_t *clock)
 569 {
 570         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 571                 INTELPllInvalid("n out of range\n");
 572         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 573                 INTELPllInvalid("p1 out of range\n");
 574         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 575                 INTELPllInvalid("m2 out of range\n");
 576         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 577                 INTELPllInvalid("m1 out of range\n");
 578
 579         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 580                 if (clock->m1 <= clock->m2)
 581                         INTELPllInvalid("m1 <= m2\n");
 582
 583         if (!IS_VALLEYVIEW(dev)) {
 584                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 585                         INTELPllInvalid("p out of range\n");
 586                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 587                         INTELPllInvalid("m out of range\n");
 588         }
 589
 590         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 591                 INTELPllInvalid("vco out of range\n");
 592         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 593          * connector, etc., rather than just a single range.
 594          */
 595         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 596                 INTELPllInvalid("dot out of range\n");
 597
 598         return true;
 599 }
 600
 601 static bool
 602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 603                     int target, int refclk, intel_clock_t *match_clock,
 604                     intel_clock_t *best_clock)
 605 {
 606         struct drm_device *dev = crtc->base.dev;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 611                 /*
 612                  * For LVDS just rely on its current settings for dual-channel.
 613                  * We haven't figured out how to reliably set up different
 614                  * single/dual channel state, if we even can.
 615                  */
 616                 if (intel_is_dual_link_lvds(dev))
 617                         clock.p2 = limit->p2.p2_fast;
 618                 else
 619                         clock.p2 = limit->p2.p2_slow;
 620         } else {
 621                 if (target < limit->p2.dot_limit)
 622                         clock.p2 = limit->p2.p2_slow;
 623                 else
 624                         clock.p2 = limit->p2.p2_fast;
 625         }
 626
 627         memset(best_clock, 0, sizeof(*best_clock));
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_clock(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(dev, limit,
 643                                                                 &clock))
 644                                                 continue;
 645                                         if (match_clock &&
 646                                             clock.p != match_clock->p)
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err) {
 651                                                 *best_clock = clock;
 652                                                 err = this_err;
 653                                         }
 654                                 }
 655                         }
 656                 }
 657         }
 658
 659         return (err != target);
 660 }
 661
 662 static bool
 663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 664                    int target, int refclk, intel_clock_t *match_clock,
 665                    intel_clock_t *best_clock)
 666 {
 667         struct drm_device *dev = crtc->base.dev;
 668         intel_clock_t clock;
 669         int err = target;
 670
 671         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 672                 /*
 673                  * For LVDS just rely on its current settings for dual-channel.
 674                  * We haven't figured out how to reliably set up different
 675                  * single/dual channel state, if we even can.
 676                  */
 677                 if (intel_is_dual_link_lvds(dev))
 678                         clock.p2 = limit->p2.p2_fast;
 679                 else
 680                         clock.p2 = limit->p2.p2_slow;
 681         } else {
 682                 if (target < limit->p2.dot_limit)
 683                         clock.p2 = limit->p2.p2_slow;
 684                 else
 685                         clock.p2 = limit->p2.p2_fast;
 686         }
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 691              clock.m1++) {
 692                 for (clock.m2 = limit->m2.min;
 693                      clock.m2 <= limit->m2.max; clock.m2++) {
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         pineview_clock(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 static bool
 722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 723                    int target, int refclk, intel_clock_t *match_clock,
 724                    intel_clock_t *best_clock)
 725 {
 726         struct drm_device *dev = crtc->base.dev;
 727         intel_clock_t clock;
 728         int max_n;
 729         bool found;
 730         /* approximately equals target * 0.00585 */
 731         int err_most = (target >> 8) + (target >> 9);
 732         found = false;
 733
 734         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 735                 if (intel_is_dual_link_lvds(dev))
 736                         clock.p2 = limit->p2.p2_fast;
 737                 else
 738                         clock.p2 = limit->p2.p2_slow;
 739         } else {
 740                 if (target < limit->p2.dot_limit)
 741                         clock.p2 = limit->p2.p2_slow;
 742                 else
 743                         clock.p2 = limit->p2.p2_fast;
 744         }
 745
 746         memset(best_clock, 0, sizeof(*best_clock));
 747         max_n = limit->n.max;
 748         /* based on hardware requirement, prefer smaller n to precision */
 749         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 750                 /* based on hardware requirement, prefere larger m1,m2 */
 751                 for (clock.m1 = limit->m1.max;
 752                      clock.m1 >= limit->m1.min; clock.m1--) {
 753                         for (clock.m2 = limit->m2.max;
 754                              clock.m2 >= limit->m2.min; clock.m2--) {
 755                                 for (clock.p1 = limit->p1.max;
 756                                      clock.p1 >= limit->p1.min; clock.p1--) {
 757                                         int this_err;
 758
 759                                         i9xx_clock(refclk, &clock);
 760                                         if (!intel_PLL_is_valid(dev, limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 static bool
 779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 780                    int target, int refclk, intel_clock_t *match_clock,
 781                    intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->base.dev;
 784         intel_clock_t clock;
 785         unsigned int bestppm = 1000000;
 786         /* min update 19.2 MHz */
 787         int max_n = min(limit->n.max, refclk / 19200);
 788         bool found = false;
 789
 790         target *= 5; /* fast clock */
 791
 792         memset(best_clock, 0, sizeof(*best_clock));
 793
 794         /* based on hardware requirement, prefer smaller n to precision */
 795         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 796                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 797                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 798                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799                                 clock.p = clock.p1 * clock.p2;
 800                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 801                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 802                                         unsigned int ppm, diff;
 803
 804                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 805                                                                      refclk * clock.m1);
 806
 807                                         vlv_clock(refclk, &clock);
 808
 809                                         if (!intel_PLL_is_valid(dev, limit,
 810                                                                 &clock))
 811                                                 continue;
 812
 813                                         diff = abs(clock.dot - target);
 814                                         ppm = div_u64(1000000ULL * diff, target);
 815
 816                                         if (ppm < 100 && clock.p > best_clock->p) {
 817                                                 bestppm = 0;
 818                                                 *best_clock = clock;
 819                                                 found = true;
 820                                         }
 821
 822                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 823                                                 bestppm = ppm;
 824                                                 *best_clock = clock;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831
 832         return found;
 833 }
 834
 835 static bool
 836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 837                    int target, int refclk, intel_clock_t *match_clock,
 838                    intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->base.dev;
 841         intel_clock_t clock;
 842         uint64_t m2;
 843         int found = false;
 844
 845         memset(best_clock, 0, sizeof(*best_clock));
 846
 847         /*
 848          * Based on hardware doc, the n always set to 1, and m1 always
 849          * set to 2.  If requires to support 200Mhz refclk, we need to
 850          * revisit this because n may not 1 anymore.
 851          */
 852         clock.n = 1, clock.m1 = 2;
 853         target *= 5;    /* fast clock */
 854
 855         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 856                 for (clock.p2 = limit->p2.p2_fast;
 857                                 clock.p2 >= limit->p2.p2_slow;
 858                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 859
 860                         clock.p = clock.p1 * clock.p2;
 861
 862                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 863                                         clock.n) << 22, refclk * clock.m1);
 864
 865                         if (m2 > INT_MAX/clock.m1)
 866                                 continue;
 867
 868                         clock.m2 = m2;
 869
 870                         chv_clock(refclk, &clock);
 871
 872                         if (!intel_PLL_is_valid(dev, limit, &clock))
 873                                 continue;
 874
 875                         /* based on hardware requirement, prefer bigger p
 876                          */
 877                         if (clock.p > best_clock->p) {
 878                                 *best_clock = clock;
 879                                 found = true;
 880                         }
 881                 }
 882         }
 883
 884         return found;
 885 }
 886
 887 bool intel_crtc_active(struct drm_crtc *crtc)
 888 {
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         /* Be paranoid as we can arrive here with only partial
 892          * state retrieved from the hardware during setup.
 893          *
 894          * We can ditch the adjusted_mode.crtc_clock check as soon
 895          * as Haswell has gained clock readout/fastboot support.
 896          *
 897          * We can ditch the crtc->primary->fb check as soon as we can
 898          * properly reconstruct framebuffers.
 899          */
 900         return intel_crtc->active && crtc->primary->fb &&
 901                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 902 }
 903
 904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 905                                              enum pipe pipe)
 906 {
 907         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 909
 910         return intel_crtc->config->cpu_transcoder;
 911 }
 912
 913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         u32 reg = PIPEDSL(pipe);
 917         u32 line1, line2;
 918         u32 line_mask;
 919
 920         if (IS_GEN2(dev))
 921                 line_mask = DSL_LINEMASK_GEN2;
 922         else
 923                 line_mask = DSL_LINEMASK_GEN3;
 924
 925         line1 = I915_READ(reg) & line_mask;
 926         mdelay(5);
 927         line2 = I915_READ(reg) & line_mask;
 928
 929         return line1 == line2;
 930 }
 931
 932 /*
 933  * intel_wait_for_pipe_off - wait for pipe to turn off
 934  * @crtc: crtc whose pipe to wait for
 935  *
 936  * After disabling a pipe, we can't wait for vblank in the usual way,
 937  * spinning on the vblank interrupt status bit, since we won't actually
 938  * see an interrupt when the pipe is disabled.
 939  *
 940  * On Gen4 and above:
 941  *   wait for the pipe register state bit to turn off
 942  *
 943  * Otherwise:
 944  *   wait for the display line value to settle (it usually
 945  *   ends up stopping at the start of the next frame).
 946  *
 947  */
 948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 949 {
 950         struct drm_device *dev = crtc->base.dev;
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 953         enum pipe pipe = crtc->pipe;
 954
 955         if (INTEL_INFO(dev)->gen >= 4) {
 956                 int reg = PIPECONF(cpu_transcoder);
 957
 958                 /* Wait for the Pipe State to go off */
 959                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 960                              100))
 961                         WARN(1, "pipe_off wait timed out\n");
 962         } else {
 963                 /* Wait for the display line to settle */
 964                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 965                         WARN(1, "pipe_off wait timed out\n");
 966         }
 967 }
 968
 969 /*
 970  * ibx_digital_port_connected - is the specified port connected?
 971  * @dev_priv: i915 private structure
 972  * @port: the port to test
 973  *
 974  * Returns true if @port is connected, false otherwise.
 975  */
 976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 977                                 struct intel_digital_port *port)
 978 {
 979         u32 bit;
 980
 981         if (HAS_PCH_IBX(dev_priv->dev)) {
 982                 switch (port->port) {
 983                 case PORT_B:
 984                         bit = SDE_PORTB_HOTPLUG;
 985                         break;
 986                 case PORT_C:
 987                         bit = SDE_PORTC_HOTPLUG;
 988                         break;
 989                 case PORT_D:
 990                         bit = SDE_PORTD_HOTPLUG;
 991                         break;
 992                 default:
 993                         return true;
 994                 }
 995         } else {
 996                 switch (port->port) {
 997                 case PORT_B:
 998                         bit = SDE_PORTB_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_C:
1001                         bit = SDE_PORTC_HOTPLUG_CPT;
1002                         break;
1003                 case PORT_D:
1004                         bit = SDE_PORTD_HOTPLUG_CPT;
1005                         break;
1006                 default:
1007                         return true;
1008                 }
1009         }
1010
1011         return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016         return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021                 enum pipe pipe, bool state)
1022 {
1023         int reg;
1024         u32 val;
1025         bool cur_state;
1026
1027         reg = DPLL(pipe);
1028         val = I915_READ(reg);
1029         cur_state = !!(val & DPLL_VCO_ENABLE);
1030         I915_STATE_WARN(cur_state != state,
1031              "PLL state assertion failure (expected %s, current %s)\n",
1032              state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038         u32 val;
1039         bool cur_state;
1040
1041         mutex_lock(&dev_priv->dpio_lock);
1042         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043         mutex_unlock(&dev_priv->dpio_lock);
1044
1045         cur_state = val & DSI_PLL_VCO_EN;
1046         I915_STATE_WARN(cur_state != state,
1047              "DSI PLL state assertion failure (expected %s, current %s)\n",
1048              state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058         if (crtc->config->shared_dpll < 0)
1059                 return NULL;
1060
1061         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066                         struct intel_shared_dpll *pll,
1067                         bool state)
1068 {
1069         bool cur_state;
1070         struct intel_dpll_hw_state hw_state;
1071
1072         if (WARN (!pll,
1073                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1074                 return;
1075
1076         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077         I915_STATE_WARN(cur_state != state,
1078              "%s assertion failure (expected %s, current %s)\n",
1079              pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083                           enum pipe pipe, bool state)
1084 {
1085         int reg;
1086         u32 val;
1087         bool cur_state;
1088         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089                                                                       pipe);
1090
1091         if (HAS_DDI(dev_priv->dev)) {
1092                 /* DDI does not have a specific FDI_TX register */
1093                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094                 val = I915_READ(reg);
1095                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096         } else {
1097                 reg = FDI_TX_CTL(pipe);
1098                 val = I915_READ(reg);
1099                 cur_state = !!(val & FDI_TX_ENABLE);
1100         }
1101         I915_STATE_WARN(cur_state != state,
1102              "FDI TX state assertion failure (expected %s, current %s)\n",
1103              state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109                           enum pipe pipe, bool state)
1110 {
1111         int reg;
1112         u32 val;
1113         bool cur_state;
1114
1115         reg = FDI_RX_CTL(pipe);
1116         val = I915_READ(reg);
1117         cur_state = !!(val & FDI_RX_ENABLE);
1118         I915_STATE_WARN(cur_state != state,
1119              "FDI RX state assertion failure (expected %s, current %s)\n",
1120              state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126                                       enum pipe pipe)
1127 {
1128         int reg;
1129         u32 val;
1130
1131         /* ILK FDI PLL is always enabled */
1132         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133                 return;
1134
1135         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136         if (HAS_DDI(dev_priv->dev))
1137                 return;
1138
1139         reg = FDI_TX_CTL(pipe);
1140         val = I915_READ(reg);
1141         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145                        enum pipe pipe, bool state)
1146 {
1147         int reg;
1148         u32 val;
1149         bool cur_state;
1150
1151         reg = FDI_RX_CTL(pipe);
1152         val = I915_READ(reg);
1153         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154         I915_STATE_WARN(cur_state != state,
1155              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156              state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160                            enum pipe pipe)
1161 {
1162         struct drm_device *dev = dev_priv->dev;
1163         int pp_reg;
1164         u32 val;
1165         enum pipe panel_pipe = PIPE_A;
1166         bool locked = true;
1167
1168         if (WARN_ON(HAS_DDI(dev)))
1169                 return;
1170
1171         if (HAS_PCH_SPLIT(dev)) {
1172                 u32 port_sel;
1173
1174                 pp_reg = PCH_PP_CONTROL;
1175                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179                         panel_pipe = PIPE_B;
1180                 /* XXX: else fix for eDP */
1181         } else if (IS_VALLEYVIEW(dev)) {
1182                 /* presumably write lock depends on pipe, not port select */
1183                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184                 panel_pipe = pipe;
1185         } else {
1186                 pp_reg = PP_CONTROL;
1187                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188                         panel_pipe = PIPE_B;
1189         }
1190
1191         val = I915_READ(pp_reg);
1192         if (!(val & PANEL_POWER_ON) ||
1193             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194                 locked = false;
1195
1196         I915_STATE_WARN(panel_pipe == pipe && locked,
1197              "panel assertion failure, pipe %c regs locked\n",
1198              pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202                           enum pipe pipe, bool state)
1203 {
1204         struct drm_device *dev = dev_priv->dev;
1205         bool cur_state;
1206
1207         if (IS_845G(dev) || IS_I865G(dev))
1208                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209         else
1210                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212         I915_STATE_WARN(cur_state != state,
1213              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214              pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220                  enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226                                                                       pipe);
1227
1228         /* if we need the pipe quirk it must be always on */
1229         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231                 state = true;
1232
1233         if (!intel_display_power_is_enabled(dev_priv,
1234                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235                 cur_state = false;
1236         } else {
1237                 reg = PIPECONF(cpu_transcoder);
1238                 val = I915_READ(reg);
1239                 cur_state = !!(val & PIPECONF_ENABLE);
1240         }
1241
1242         I915_STATE_WARN(cur_state != state,
1243              "pipe %c assertion failure (expected %s, current %s)\n",
1244              pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248                          enum plane plane, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = DSPCNTR(plane);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257         I915_STATE_WARN(cur_state != state,
1258              "plane %c assertion failure (expected %s, current %s)\n",
1259              plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266                                    enum pipe pipe)
1267 {
1268         struct drm_device *dev = dev_priv->dev;
1269         int reg, i;
1270         u32 val;
1271         int cur_pipe;
1272
1273         /* Primary planes are fixed to pipes on gen4+ */
1274         if (INTEL_INFO(dev)->gen >= 4) {
1275                 reg = DSPCNTR(pipe);
1276                 val = I915_READ(reg);
1277                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278                      "plane %c assertion failure, should be disabled but not\n",
1279                      plane_name(pipe));
1280                 return;
1281         }
1282
1283         /* Need to check both planes against the pipe */
1284         for_each_pipe(dev_priv, i) {
1285                 reg = DSPCNTR(i);
1286                 val = I915_READ(reg);
1287                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288                         DISPPLANE_SEL_PIPE_SHIFT;
1289                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(i), pipe_name(pipe));
1292         }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296                                     enum pipe pipe)
1297 {
1298         struct drm_device *dev = dev_priv->dev;
1299         int reg, sprite;
1300         u32 val;
1301
1302         if (INTEL_INFO(dev)->gen >= 9) {
1303                 for_each_sprite(pipe, sprite) {
1304                         val = I915_READ(PLANE_CTL(pipe, sprite));
1305                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307                              sprite, pipe_name(pipe));
1308                 }
1309         } else if (IS_VALLEYVIEW(dev)) {
1310                 for_each_sprite(pipe, sprite) {
1311                         reg = SPCNTR(pipe, sprite);
1312                         val = I915_READ(reg);
1313                         I915_STATE_WARN(val & SP_ENABLE,
1314                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315                              sprite_name(pipe, sprite), pipe_name(pipe));
1316                 }
1317         } else if (INTEL_INFO(dev)->gen >= 7) {
1318                 reg = SPRCTL(pipe);
1319                 val = I915_READ(reg);
1320                 I915_STATE_WARN(val & SPRITE_ENABLE,
1321                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322                      plane_name(pipe), pipe_name(pipe));
1323         } else if (INTEL_INFO(dev)->gen >= 5) {
1324                 reg = DVSCNTR(pipe);
1325                 val = I915_READ(reg);
1326                 I915_STATE_WARN(val & DVS_ENABLE,
1327                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328                      plane_name(pipe), pipe_name(pipe));
1329         }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335                 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340         u32 val;
1341         bool enabled;
1342
1343         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345         val = I915_READ(PCH_DREF_CONTROL);
1346         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347                             DREF_SUPERSPREAD_SOURCE_MASK));
1348         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352                                            enum pipe pipe)
1353 {
1354         int reg;
1355         u32 val;
1356         bool enabled;
1357
1358         reg = PCH_TRANSCONF(pipe);
1359         val = I915_READ(reg);
1360         enabled = !!(val & TRANS_ENABLE);
1361         I915_STATE_WARN(enabled,
1362              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363              pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367                             enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369         if ((val & DP_PORT_EN) == 0)
1370                 return false;
1371
1372         if (HAS_PCH_CPT(dev_priv->dev)) {
1373                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv->dev)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv->dev)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, int reg, u32 port_sel)
1439 {
1440         u32 val = I915_READ(reg);
1441         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443              reg, pipe_name(pipe));
1444
1445         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446              && (val & DP_PIPEB_SELECT),
1447              "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451                                      enum pipe pipe, int reg)
1452 {
1453         u32 val = I915_READ(reg);
1454         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456              reg, pipe_name(pipe));
1457
1458         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459              && (val & SDVO_PIPE_B_SELECT),
1460              "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464                                       enum pipe pipe)
1465 {
1466         int reg;
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         reg = PCH_ADPA;
1474         val = I915_READ(reg);
1475         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476              "PCH VGA enabled on transcoder %c, should be disabled\n",
1477              pipe_name(pipe));
1478
1479         reg = PCH_LVDS;
1480         val = I915_READ(reg);
1481         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483              pipe_name(pipe));
1484
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494         if (!IS_VALLEYVIEW(dev))
1495                 return;
1496
1497         /*
1498          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499          * CHV x1 PHY (DP/HDMI D)
1500          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501          */
1502         if (IS_CHERRYVIEW(dev)) {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505         } else {
1506                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507         }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511                            const struct intel_crtc_state *pipe_config)
1512 {
1513         struct drm_device *dev = crtc->base.dev;
1514         struct drm_i915_private *dev_priv = dev->dev_private;
1515         int reg = DPLL(crtc->pipe);
1516         u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518         assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520         /* No really, not for ILK+ */
1521         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523         /* PLL is protected by panel, make sure we can write it */
1524         if (IS_MOBILE(dev_priv->dev))
1525                 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527         I915_WRITE(reg, dpll);
1528         POSTING_READ(reg);
1529         udelay(150);
1530
1531         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535         POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537         /* We do this three times for luck */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544         I915_WRITE(reg, dpll);
1545         POSTING_READ(reg);
1546         udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550                            const struct intel_crtc_state *pipe_config)
1551 {
1552         struct drm_device *dev = crtc->base.dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         int pipe = crtc->pipe;
1555         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556         u32 tmp;
1557
1558         assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562         mutex_lock(&dev_priv->dpio_lock);
1563
1564         /* Enable back the 10bit clock to display controller */
1565         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566         tmp |= DPIO_DCLKP_EN;
1567         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569         /*
1570          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571          */
1572         udelay(1);
1573
1574         /* Enable PLL */
1575         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577         /* Check PLL is locked */
1578         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581         /* not sure when this should be written */
1582         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583         POSTING_READ(DPLL_MD(pipe));
1584
1585         mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590         struct intel_crtc *crtc;
1591         int count = 0;
1592
1593         for_each_intel_crtc(dev, crtc)
1594                 count += crtc->active &&
1595                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597         return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         int reg = DPLL(crtc->pipe);
1605         u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* No really, not for ILK+ */
1610         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612         /* PLL is protected by panel, make sure we can write it */
1613         if (IS_MOBILE(dev) && !IS_I830(dev))
1614                 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616         /* Enable DVO 2x clock on both PLLs if necessary */
1617         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618                 /*
1619                  * It appears to be important that we don't enable this
1620                  * for the current pipe before otherwise configuring the
1621                  * PLL. No idea how this should be handled if multiple
1622                  * DVO outputs are enabled simultaneosly.
1623                  */
1624                 dpll |= DPLL_DVO_2X_MODE;
1625                 I915_WRITE(DPLL(!crtc->pipe),
1626                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627         }
1628
1629         /* Wait for the clocks to stabilize. */
1630         POSTING_READ(reg);
1631         udelay(150);
1632
1633         if (INTEL_INFO(dev)->gen >= 4) {
1634                 I915_WRITE(DPLL_MD(crtc->pipe),
1635                            crtc->config->dpll_hw_state.dpll_md);
1636         } else {
1637                 /* The pixel multiplier can only be updated once the
1638                  * DPLL is enabled and the clocks are stable.
1639                  *
1640                  * So write it again.
1641                  */
1642                 I915_WRITE(reg, dpll);
1643         }
1644
1645         /* We do this three times for luck */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652         I915_WRITE(reg, dpll);
1653         POSTING_READ(reg);
1654         udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658  * i9xx_disable_pll - disable a PLL
1659  * @dev_priv: i915 private structure
1660  * @pipe: pipe PLL to disable
1661  *
1662  * Disable the PLL for @pipe, making sure the pipe is off first.
1663  *
1664  * Note!  This is for pre-ILK only.
1665  */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668         struct drm_device *dev = crtc->base.dev;
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670         enum pipe pipe = crtc->pipe;
1671
1672         /* Disable DVO 2x clock on both PLLs if necessary */
1673         if (IS_I830(dev) &&
1674             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675             intel_num_dvo_pipes(dev) == 1) {
1676                 I915_WRITE(DPLL(PIPE_B),
1677                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678                 I915_WRITE(DPLL(PIPE_A),
1679                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680         }
1681
1682         /* Don't disable pipe or pipe PLLs if needed */
1683         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685                 return;
1686
1687         /* Make sure the pipe isn't still relying on us */
1688         assert_pipe_disabled(dev_priv, pipe);
1689
1690         I915_WRITE(DPLL(pipe), 0);
1691         POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696         u32 val = 0;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         /*
1702          * Leave integrated clock source and reference clock enabled for pipe B.
1703          * The latter is needed for VGA hotplug / manual detection.
1704          */
1705         if (pipe == PIPE_B)
1706                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707         I915_WRITE(DPLL(pipe), val);
1708         POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715         u32 val;
1716
1717         /* Make sure the pipe isn't still relying on us */
1718         assert_pipe_disabled(dev_priv, pipe);
1719
1720         /* Set PLL en = 0 */
1721         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722         if (pipe != PIPE_A)
1723                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726
1727         mutex_lock(&dev_priv->dpio_lock);
1728
1729         /* Disable 10bit clock to display controller */
1730         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731         val &= ~DPIO_DCLKP_EN;
1732         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734         /* disable left/right clock distribution */
1735         if (pipe != PIPE_B) {
1736                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739         } else {
1740                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743         }
1744
1745         mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749                 struct intel_digital_port *dport)
1750 {
1751         u32 port_mask;
1752         int dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 break;
1763         case PORT_D:
1764                 port_mask = DPLL_PORTD_READY_MASK;
1765                 dpll_reg = DPIO_PHY_STATUS;
1766                 break;
1767         default:
1768                 BUG();
1769         }
1770
1771         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773                      port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778         struct drm_device *dev = crtc->base.dev;
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782         if (WARN_ON(pll == NULL))
1783                 return;
1784
1785         WARN_ON(!pll->config.crtc_mask);
1786         if (pll->active == 0) {
1787                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788                 WARN_ON(pll->on);
1789                 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791                 pll->mode_set(dev_priv, pll);
1792         }
1793 }
1794
1795 /**
1796  * intel_enable_shared_dpll - enable PCH PLL
1797  * @dev_priv: i915 private structure
1798  * @pipe: pipe PLL to enable
1799  *
1800  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801  * drives the transcoder clock.
1802  */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805         struct drm_device *dev = crtc->base.dev;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809         if (WARN_ON(pll == NULL))
1810                 return;
1811
1812         if (WARN_ON(pll->config.crtc_mask == 0))
1813                 return;
1814
1815         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816                       pll->name, pll->active, pll->on,
1817                       crtc->base.base.id);
1818
1819         if (pll->active++) {
1820                 WARN_ON(!pll->on);
1821                 assert_shared_dpll_enabled(dev_priv, pll);
1822                 return;
1823         }
1824         WARN_ON(pll->on);
1825
1826         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829         pll->enable(dev_priv, pll);
1830         pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835         struct drm_device *dev = crtc->base.dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839         /* PCH only available on ILK+ */
1840         BUG_ON(INTEL_INFO(dev)->gen < 5);
1841         if (WARN_ON(pll == NULL))
1842                return;
1843
1844         if (WARN_ON(pll->config.crtc_mask == 0))
1845                 return;
1846
1847         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848                       pll->name, pll->active, pll->on,
1849                       crtc->base.base.id);
1850
1851         if (WARN_ON(pll->active == 0)) {
1852                 assert_shared_dpll_disabled(dev_priv, pll);
1853                 return;
1854         }
1855
1856         assert_shared_dpll_enabled(dev_priv, pll);
1857         WARN_ON(!pll->on);
1858         if (--pll->active)
1859                 return;
1860
1861         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862         pll->disable(dev_priv, pll);
1863         pll->on = false;
1864
1865         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869                                            enum pipe pipe)
1870 {
1871         struct drm_device *dev = dev_priv->dev;
1872         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874         uint32_t reg, val, pipeconf_val;
1875
1876         /* PCH only available on ILK+ */
1877         BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879         /* Make sure PCH DPLL is enabled */
1880         assert_shared_dpll_enabled(dev_priv,
1881                                    intel_crtc_to_shared_dpll(intel_crtc));
1882
1883         /* FDI must be feeding us bits for PCH ports */
1884         assert_fdi_tx_enabled(dev_priv, pipe);
1885         assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887         if (HAS_PCH_CPT(dev)) {
1888                 /* Workaround: Set the timing override bit before enabling the
1889                  * pch transcoder. */
1890                 reg = TRANS_CHICKEN2(pipe);
1891                 val = I915_READ(reg);
1892                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893                 I915_WRITE(reg, val);
1894         }
1895
1896         reg = PCH_TRANSCONF(pipe);
1897         val = I915_READ(reg);
1898         pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900         if (HAS_PCH_IBX(dev_priv->dev)) {
1901                 /*
1902                  * make the BPC in transcoder be consistent with
1903                  * that in pipeconf reg.
1904                  */
1905                 val &= ~PIPECONF_BPC_MASK;
1906                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907         }
1908
1909         val &= ~TRANS_INTERLACE_MASK;
1910         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911                 if (HAS_PCH_IBX(dev_priv->dev) &&
1912                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913                         val |= TRANS_LEGACY_INTERLACED_ILK;
1914                 else
1915                         val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(reg, val | TRANS_ENABLE);
1920         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                       enum transcoder cpu_transcoder)
1926 {
1927         u32 val, pipeconf_val;
1928
1929         /* PCH only available on ILK+ */
1930         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932         /* FDI must be feeding us bits for PCH ports */
1933         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936         /* Workaround: set timing override bit. */
1937         val = I915_READ(_TRANSA_CHICKEN2);
1938         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939         I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941         val = TRANS_ENABLE;
1942         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945             PIPECONF_INTERLACED_ILK)
1946                 val |= TRANS_INTERLACED;
1947         else
1948                 val |= TRANS_PROGRESSIVE;
1949
1950         I915_WRITE(LPT_TRANSCONF, val);
1951         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952                 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956                                             enum pipe pipe)
1957 {
1958         struct drm_device *dev = dev_priv->dev;
1959         uint32_t reg, val;
1960
1961         /* FDI relies on the transcoder */
1962         assert_fdi_tx_disabled(dev_priv, pipe);
1963         assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965         /* Ports must be off as well */
1966         assert_pch_ports_disabled(dev_priv, pipe);
1967
1968         reg = PCH_TRANSCONF(pipe);
1969         val = I915_READ(reg);
1970         val &= ~TRANS_ENABLE;
1971         I915_WRITE(reg, val);
1972         /* wait for PCH transcoder off, transcoder state */
1973         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976         if (!HAS_PCH_IBX(dev)) {
1977                 /* Workaround: Clear the timing override chicken bit again. */
1978                 reg = TRANS_CHICKEN2(pipe);
1979                 val = I915_READ(reg);
1980                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981                 I915_WRITE(reg, val);
1982         }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987         u32 val;
1988
1989         val = I915_READ(LPT_TRANSCONF);
1990         val &= ~TRANS_ENABLE;
1991         I915_WRITE(LPT_TRANSCONF, val);
1992         /* wait for PCH transcoder off, transcoder state */
1993         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994                 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996         /* Workaround: clear timing override bit. */
1997         val = I915_READ(_TRANSA_CHICKEN2);
1998         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999         I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003  * intel_enable_pipe - enable a pipe, asserting requirements
2004  * @crtc: crtc responsible for the pipe
2005  *
2006  * Enable @crtc's pipe, making sure that various hardware specific requirements
2007  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008  */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_device *dev = crtc->base.dev;
2012         struct drm_i915_private *dev_priv = dev->dev_private;
2013         enum pipe pipe = crtc->pipe;
2014         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015                                                                       pipe);
2016         enum pipe pch_transcoder;
2017         int reg;
2018         u32 val;
2019
2020         assert_planes_disabled(dev_priv, pipe);
2021         assert_cursor_disabled(dev_priv, pipe);
2022         assert_sprites_disabled(dev_priv, pipe);
2023
2024         if (HAS_PCH_LPT(dev_priv->dev))
2025                 pch_transcoder = TRANSCODER_A;
2026         else
2027                 pch_transcoder = pipe;
2028
2029         /*
2030          * A pipe without a PLL won't actually be able to drive bits from
2031          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2032          * need the check.
2033          */
2034         if (!HAS_PCH_SPLIT(dev_priv->dev))
2035                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036                         assert_dsi_pll_enabled(dev_priv);
2037                 else
2038                         assert_pll_enabled(dev_priv, pipe);
2039         else {
2040                 if (crtc->config->has_pch_encoder) {
2041                         /* if driving the PCH, we need FDI enabled */
2042                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043                         assert_fdi_tx_pll_enabled(dev_priv,
2044                                                   (enum pipe) cpu_transcoder);
2045                 }
2046                 /* FIXME: assert CPU port conditions for SNB+ */
2047         }
2048
2049         reg = PIPECONF(cpu_transcoder);
2050         val = I915_READ(reg);
2051         if (val & PIPECONF_ENABLE) {
2052                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054                 return;
2055         }
2056
2057         I915_WRITE(reg, val | PIPECONF_ENABLE);
2058         POSTING_READ(reg);
2059 }
2060
2061 /**
2062  * intel_disable_pipe - disable a pipe, asserting requirements
2063  * @crtc: crtc whose pipes is to be disabled
2064  *
2065  * Disable the pipe of @crtc, making sure that various hardware
2066  * specific requirements are met, if applicable, e.g. plane
2067  * disabled, panel fitter off, etc.
2068  *
2069  * Will wait until the pipe has shut down before returning.
2070  */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075         enum pipe pipe = crtc->pipe;
2076         int reg;
2077         u32 val;
2078
2079         /*
2080          * Make sure planes won't keep trying to pump pixels to us,
2081          * or we might hang the display.
2082          */
2083         assert_planes_disabled(dev_priv, pipe);
2084         assert_cursor_disabled(dev_priv, pipe);
2085         assert_sprites_disabled(dev_priv, pipe);
2086
2087         reg = PIPECONF(cpu_transcoder);
2088         val = I915_READ(reg);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 return;
2091
2092         /*
2093          * Double wide has implications for planes
2094          * so best keep it disabled when not needed.
2095          */
2096         if (crtc->config->double_wide)
2097                 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099         /* Don't disable pipe or pipe PLLs if needed */
2100         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102                 val &= ~PIPECONF_ENABLE;
2103
2104         I915_WRITE(reg, val);
2105         if ((val & PIPECONF_ENABLE) == 0)
2106                 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110  * Plane regs are double buffered, going from enabled->disabled needs a
2111  * trigger in order to latch.  The display address reg provides this.
2112  */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114                                enum plane plane)
2115 {
2116         struct drm_device *dev = dev_priv->dev;
2117         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119         I915_WRITE(reg, I915_READ(reg));
2120         POSTING_READ(reg);
2121 }
2122
2123 /**
2124  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125  * @plane:  plane to be enabled
2126  * @crtc: crtc for the plane
2127  *
2128  * Enable @plane on @crtc, making sure that the pipe is running first.
2129  */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131                                           struct drm_crtc *crtc)
2132 {
2133         struct drm_device *dev = plane->dev;
2134         struct drm_i915_private *dev_priv = dev->dev_private;
2135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140         if (intel_crtc->primary_enabled)
2141                 return;
2142
2143         intel_crtc->primary_enabled = true;
2144
2145         dev_priv->display.update_primary_plane(crtc, plane->fb,
2146                                                crtc->x, crtc->y);
2147
2148         /*
2149          * BDW signals flip done immediately if the plane
2150          * is disabled, even if the plane enable is already
2151          * armed to occur at the next vblank :(
2152          */
2153         if (IS_BROADWELL(dev))
2154                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158  * intel_disable_primary_hw_plane - disable the primary hardware plane
2159  * @plane: plane to be disabled
2160  * @crtc: crtc for the plane
2161  *
2162  * Disable @plane on @crtc, making sure that the pipe is running first.
2163  */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165                                            struct drm_crtc *crtc)
2166 {
2167         struct drm_device *dev = plane->dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171         if (WARN_ON(!intel_crtc->active))
2172                 return;
2173
2174         if (!intel_crtc->primary_enabled)
2175                 return;
2176
2177         intel_crtc->primary_enabled = false;
2178
2179         dev_priv->display.update_primary_plane(crtc, plane->fb,
2180                                                crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187                 return true;
2188 #endif
2189         return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height,
2194                       uint32_t pixel_format,
2195                       uint64_t fb_format_modifier)
2196 {
2197         int tile_height;
2198
2199         tile_height = fb_format_modifier == I915_FORMAT_MOD_X_TILED ?
2200                 (IS_GEN2(dev) ? 16 : 8) : 1;
2201
2202         return ALIGN(height, tile_height);
2203 }
2204
2205 int
2206 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2207                            struct drm_framebuffer *fb,
2208                            struct intel_engine_cs *pipelined)
2209 {
2210         struct drm_device *dev = fb->dev;
2211         struct drm_i915_private *dev_priv = dev->dev_private;
2212         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2213         u32 alignment;
2214         int ret;
2215
2216         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2217
2218         switch (fb->modifier[0]) {
2219         case DRM_FORMAT_MOD_NONE:
2220                 if (INTEL_INFO(dev)->gen >= 9)
2221                         alignment = 256 * 1024;
2222                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2223                         alignment = 128 * 1024;
2224                 else if (INTEL_INFO(dev)->gen >= 4)
2225                         alignment = 4 * 1024;
2226                 else
2227                         alignment = 64 * 1024;
2228                 break;
2229         case I915_FORMAT_MOD_X_TILED:
2230                 if (INTEL_INFO(dev)->gen >= 9)
2231                         alignment = 256 * 1024;
2232                 else {
2233                         /* pin() will align the object as required by fence */
2234                         alignment = 0;
2235                 }
2236                 break;
2237         case I915_FORMAT_MOD_Y_TILED:
2238                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2239                 return -EINVAL;
2240         default:
2241                 MISSING_CASE(fb->modifier[0]);
2242                 return -EINVAL;
2243         }
2244
2245         /* Note that the w/a also requires 64 PTE of padding following the
2246          * bo. We currently fill all unused PTE with the shadow page and so
2247          * we should always have valid PTE following the scanout preventing
2248          * the VT-d warning.
2249          */
2250         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2251                 alignment = 256 * 1024;
2252
2253         /*
2254          * Global gtt pte registers are special registers which actually forward
2255          * writes to a chunk of system memory. Which means that there is no risk
2256          * that the register values disappear as soon as we call
2257          * intel_runtime_pm_put(), so it is correct to wrap only the
2258          * pin/unpin/fence and not more.
2259          */
2260         intel_runtime_pm_get(dev_priv);
2261
2262         dev_priv->mm.interruptible = false;
2263         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2264         if (ret)
2265                 goto err_interruptible;
2266
2267         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2268          * fence, whereas 965+ only requires a fence if using
2269          * framebuffer compression.  For simplicity, we always install
2270          * a fence as the cost is not that onerous.
2271          */
2272         ret = i915_gem_object_get_fence(obj);
2273         if (ret)
2274                 goto err_unpin;
2275
2276         i915_gem_object_pin_fence(obj);
2277
2278         dev_priv->mm.interruptible = true;
2279         intel_runtime_pm_put(dev_priv);
2280         return 0;
2281
2282 err_unpin:
2283         i915_gem_object_unpin_from_display_plane(obj);
2284 err_interruptible:
2285         dev_priv->mm.interruptible = true;
2286         intel_runtime_pm_put(dev_priv);
2287         return ret;
2288 }
2289
2290 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2291 {
2292         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2293
2294         i915_gem_object_unpin_fence(obj);
2295         i915_gem_object_unpin_from_display_plane(obj);
2296 }
2297
2298 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2299  * is assumed to be a power-of-two. */
2300 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2301                                              unsigned int tiling_mode,
2302                                              unsigned int cpp,
2303                                              unsigned int pitch)
2304 {
2305         if (tiling_mode != I915_TILING_NONE) {
2306                 unsigned int tile_rows, tiles;
2307
2308                 tile_rows = *y / 8;
2309                 *y %= 8;
2310
2311                 tiles = *x / (512/cpp);
2312                 *x %= 512/cpp;
2313
2314                 return tile_rows * pitch * 8 + tiles * 4096;
2315         } else {
2316                 unsigned int offset;
2317
2318                 offset = *y * pitch + *x * cpp;
2319                 *y = 0;
2320                 *x = (offset & 4095) / cpp;
2321                 return offset & -4096;
2322         }
2323 }
2324
2325 static int i9xx_format_to_fourcc(int format)
2326 {
2327         switch (format) {
2328         case DISPPLANE_8BPP:
2329                 return DRM_FORMAT_C8;
2330         case DISPPLANE_BGRX555:
2331                 return DRM_FORMAT_XRGB1555;
2332         case DISPPLANE_BGRX565:
2333                 return DRM_FORMAT_RGB565;
2334         default:
2335         case DISPPLANE_BGRX888:
2336                 return DRM_FORMAT_XRGB8888;
2337         case DISPPLANE_RGBX888:
2338                 return DRM_FORMAT_XBGR8888;
2339         case DISPPLANE_BGRX101010:
2340                 return DRM_FORMAT_XRGB2101010;
2341         case DISPPLANE_RGBX101010:
2342                 return DRM_FORMAT_XBGR2101010;
2343         }
2344 }
2345
2346 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2347 {
2348         switch (format) {
2349         case PLANE_CTL_FORMAT_RGB_565:
2350                 return DRM_FORMAT_RGB565;
2351         default:
2352         case PLANE_CTL_FORMAT_XRGB_8888:
2353                 if (rgb_order) {
2354                         if (alpha)
2355                                 return DRM_FORMAT_ABGR8888;
2356                         else
2357                                 return DRM_FORMAT_XBGR8888;
2358                 } else {
2359                         if (alpha)
2360                                 return DRM_FORMAT_ARGB8888;
2361                         else
2362                                 return DRM_FORMAT_XRGB8888;
2363                 }
2364         case PLANE_CTL_FORMAT_XRGB_2101010:
2365                 if (rgb_order)
2366                         return DRM_FORMAT_XBGR2101010;
2367                 else
2368                         return DRM_FORMAT_XRGB2101010;
2369         }
2370 }
2371
2372 static bool
2373 intel_alloc_plane_obj(struct intel_crtc *crtc,
2374                       struct intel_initial_plane_config *plane_config)
2375 {
2376         struct drm_device *dev = crtc->base.dev;
2377         struct drm_i915_gem_object *obj = NULL;
2378         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2379         struct drm_framebuffer *fb = &plane_config->fb->base;
2380         u32 base = plane_config->base;
2381
2382         if (plane_config->size == 0)
2383                 return false;
2384
2385         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2386                                                              plane_config->size);
2387         if (!obj)
2388                 return false;
2389
2390         obj->tiling_mode = plane_config->tiling;
2391         if (obj->tiling_mode == I915_TILING_X)
2392                 obj->stride = fb->pitches[0];
2393
2394         mode_cmd.pixel_format = fb->pixel_format;
2395         mode_cmd.width = fb->width;
2396         mode_cmd.height = fb->height;
2397         mode_cmd.pitches[0] = fb->pitches[0];
2398         mode_cmd.modifier[0] = fb->modifier[0];
2399         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2400
2401         mutex_lock(&dev->struct_mutex);
2402
2403         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2404                                    &mode_cmd, obj)) {
2405                 DRM_DEBUG_KMS("intel fb init failed\n");
2406                 goto out_unref_obj;
2407         }
2408
2409         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2410         mutex_unlock(&dev->struct_mutex);
2411
2412         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2413         return true;
2414
2415 out_unref_obj:
2416         drm_gem_object_unreference(&obj->base);
2417         mutex_unlock(&dev->struct_mutex);
2418         return false;
2419 }
2420
2421 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2422 static void
2423 update_state_fb(struct drm_plane *plane)
2424 {
2425         if (plane->fb == plane->state->fb)
2426                 return;
2427
2428         if (plane->state->fb)
2429                 drm_framebuffer_unreference(plane->state->fb);
2430         plane->state->fb = plane->fb;
2431         if (plane->state->fb)
2432                 drm_framebuffer_reference(plane->state->fb);
2433 }
2434
2435 static void
2436 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2437                      struct intel_initial_plane_config *plane_config)
2438 {
2439         struct drm_device *dev = intel_crtc->base.dev;
2440         struct drm_i915_private *dev_priv = dev->dev_private;
2441         struct drm_crtc *c;
2442         struct intel_crtc *i;
2443         struct drm_i915_gem_object *obj;
2444
2445         if (!plane_config->fb)
2446                 return;
2447
2448         if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2449                 struct drm_plane *primary = intel_crtc->base.primary;
2450
2451                 primary->fb = &plane_config->fb->base;
2452                 primary->state->crtc = &intel_crtc->base;
2453                 update_state_fb(primary);
2454
2455                 return;
2456         }
2457
2458         kfree(plane_config->fb);
2459
2460         /*
2461          * Failed to alloc the obj, check to see if we should share
2462          * an fb with another CRTC instead
2463          */
2464         for_each_crtc(dev, c) {
2465                 i = to_intel_crtc(c);
2466
2467                 if (c == &intel_crtc->base)
2468                         continue;
2469
2470                 if (!i->active)
2471                         continue;
2472
2473                 obj = intel_fb_obj(c->primary->fb);
2474                 if (obj == NULL)
2475                         continue;
2476
2477                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2478                         struct drm_plane *primary = intel_crtc->base.primary;
2479
2480                         if (obj->tiling_mode != I915_TILING_NONE)
2481                                 dev_priv->preserve_bios_swizzle = true;
2482
2483                         drm_framebuffer_reference(c->primary->fb);
2484                         primary->fb = c->primary->fb;
2485                         primary->state->crtc = &intel_crtc->base;
2486                         update_state_fb(intel_crtc->base.primary);
2487                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2488                         break;
2489                 }
2490         }
2491
2492 }
2493
2494 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2495                                       struct drm_framebuffer *fb,
2496                                       int x, int y)
2497 {
2498         struct drm_device *dev = crtc->dev;
2499         struct drm_i915_private *dev_priv = dev->dev_private;
2500         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2501         struct drm_i915_gem_object *obj;
2502         int plane = intel_crtc->plane;
2503         unsigned long linear_offset;
2504         u32 dspcntr;
2505         u32 reg = DSPCNTR(plane);
2506         int pixel_size;
2507
2508         if (!intel_crtc->primary_enabled) {
2509                 I915_WRITE(reg, 0);
2510                 if (INTEL_INFO(dev)->gen >= 4)
2511                         I915_WRITE(DSPSURF(plane), 0);
2512                 else
2513                         I915_WRITE(DSPADDR(plane), 0);
2514                 POSTING_READ(reg);
2515                 return;
2516         }
2517
2518         obj = intel_fb_obj(fb);
2519         if (WARN_ON(obj == NULL))
2520                 return;
2521
2522         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2523
2524         dspcntr = DISPPLANE_GAMMA_ENABLE;
2525
2526         dspcntr |= DISPLAY_PLANE_ENABLE;
2527
2528         if (INTEL_INFO(dev)->gen < 4) {
2529                 if (intel_crtc->pipe == PIPE_B)
2530                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2531
2532                 /* pipesrc and dspsize control the size that is scaled from,
2533                  * which should always be the user's requested size.
2534                  */
2535                 I915_WRITE(DSPSIZE(plane),
2536                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2537                            (intel_crtc->config->pipe_src_w - 1));
2538                 I915_WRITE(DSPPOS(plane), 0);
2539         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2540                 I915_WRITE(PRIMSIZE(plane),
2541                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2542                            (intel_crtc->config->pipe_src_w - 1));
2543                 I915_WRITE(PRIMPOS(plane), 0);
2544                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2545         }
2546
2547         switch (fb->pixel_format) {
2548         case DRM_FORMAT_C8:
2549                 dspcntr |= DISPPLANE_8BPP;
2550                 break;
2551         case DRM_FORMAT_XRGB1555:
2552         case DRM_FORMAT_ARGB1555:
2553                 dspcntr |= DISPPLANE_BGRX555;
2554                 break;
2555         case DRM_FORMAT_RGB565:
2556                 dspcntr |= DISPPLANE_BGRX565;
2557                 break;
2558         case DRM_FORMAT_XRGB8888:
2559         case DRM_FORMAT_ARGB8888:
2560                 dspcntr |= DISPPLANE_BGRX888;
2561                 break;
2562         case DRM_FORMAT_XBGR8888:
2563         case DRM_FORMAT_ABGR8888:
2564                 dspcntr |= DISPPLANE_RGBX888;
2565                 break;
2566         case DRM_FORMAT_XRGB2101010:
2567         case DRM_FORMAT_ARGB2101010:
2568                 dspcntr |= DISPPLANE_BGRX101010;
2569                 break;
2570         case DRM_FORMAT_XBGR2101010:
2571         case DRM_FORMAT_ABGR2101010:
2572                 dspcntr |= DISPPLANE_RGBX101010;
2573                 break;
2574         default:
2575                 BUG();
2576         }
2577
2578         if (INTEL_INFO(dev)->gen >= 4 &&
2579             obj->tiling_mode != I915_TILING_NONE)
2580                 dspcntr |= DISPPLANE_TILED;
2581
2582         if (IS_G4X(dev))
2583                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2584
2585         linear_offset = y * fb->pitches[0] + x * pixel_size;
2586
2587         if (INTEL_INFO(dev)->gen >= 4) {
2588                 intel_crtc->dspaddr_offset =
2589                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2590                                                        pixel_size,
2591                                                        fb->pitches[0]);
2592                 linear_offset -= intel_crtc->dspaddr_offset;
2593         } else {
2594                 intel_crtc->dspaddr_offset = linear_offset;
2595         }
2596
2597         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2598                 dspcntr |= DISPPLANE_ROTATE_180;
2599
2600                 x += (intel_crtc->config->pipe_src_w - 1);
2601                 y += (intel_crtc->config->pipe_src_h - 1);
2602
2603                 /* Finding the last pixel of the last line of the display
2604                 data and adding to linear_offset*/
2605                 linear_offset +=
2606                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2607                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2608         }
2609
2610         I915_WRITE(reg, dspcntr);
2611
2612         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2613                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2614                       fb->pitches[0]);
2615         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2616         if (INTEL_INFO(dev)->gen >= 4) {
2617                 I915_WRITE(DSPSURF(plane),
2618                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2619                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2620                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2621         } else
2622                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2623         POSTING_READ(reg);
2624 }
2625
2626 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2627                                           struct drm_framebuffer *fb,
2628                                           int x, int y)
2629 {
2630         struct drm_device *dev = crtc->dev;
2631         struct drm_i915_private *dev_priv = dev->dev_private;
2632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2633         struct drm_i915_gem_object *obj;
2634         int plane = intel_crtc->plane;
2635         unsigned long linear_offset;
2636         u32 dspcntr;
2637         u32 reg = DSPCNTR(plane);
2638         int pixel_size;
2639
2640         if (!intel_crtc->primary_enabled) {
2641                 I915_WRITE(reg, 0);
2642                 I915_WRITE(DSPSURF(plane), 0);
2643                 POSTING_READ(reg);
2644                 return;
2645         }
2646
2647         obj = intel_fb_obj(fb);
2648         if (WARN_ON(obj == NULL))
2649                 return;
2650
2651         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2652
2653         dspcntr = DISPPLANE_GAMMA_ENABLE;
2654
2655         dspcntr |= DISPLAY_PLANE_ENABLE;
2656
2657         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2658                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2659
2660         switch (fb->pixel_format) {
2661         case DRM_FORMAT_C8:
2662                 dspcntr |= DISPPLANE_8BPP;
2663                 break;
2664         case DRM_FORMAT_RGB565:
2665                 dspcntr |= DISPPLANE_BGRX565;
2666                 break;
2667         case DRM_FORMAT_XRGB8888:
2668         case DRM_FORMAT_ARGB8888:
2669                 dspcntr |= DISPPLANE_BGRX888;
2670                 break;
2671         case DRM_FORMAT_XBGR8888:
2672         case DRM_FORMAT_ABGR8888:
2673                 dspcntr |= DISPPLANE_RGBX888;
2674                 break;
2675         case DRM_FORMAT_XRGB2101010:
2676         case DRM_FORMAT_ARGB2101010:
2677                 dspcntr |= DISPPLANE_BGRX101010;
2678                 break;
2679         case DRM_FORMAT_XBGR2101010:
2680         case DRM_FORMAT_ABGR2101010:
2681                 dspcntr |= DISPPLANE_RGBX101010;
2682                 break;
2683         default:
2684                 BUG();
2685         }
2686
2687         if (obj->tiling_mode != I915_TILING_NONE)
2688                 dspcntr |= DISPPLANE_TILED;
2689
2690         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2691                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2692
2693         linear_offset = y * fb->pitches[0] + x * pixel_size;
2694         intel_crtc->dspaddr_offset =
2695                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2696                                                pixel_size,
2697                                                fb->pitches[0]);
2698         linear_offset -= intel_crtc->dspaddr_offset;
2699         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2700                 dspcntr |= DISPPLANE_ROTATE_180;
2701
2702                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2703                         x += (intel_crtc->config->pipe_src_w - 1);
2704                         y += (intel_crtc->config->pipe_src_h - 1);
2705
2706                         /* Finding the last pixel of the last line of the display
2707                         data and adding to linear_offset*/
2708                         linear_offset +=
2709                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2710                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2711                 }
2712         }
2713
2714         I915_WRITE(reg, dspcntr);
2715
2716         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2717                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2718                       fb->pitches[0]);
2719         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2720         I915_WRITE(DSPSURF(plane),
2721                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2722         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2723                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2724         } else {
2725                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2726                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2727         }
2728         POSTING_READ(reg);
2729 }
2730
2731 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2732                                          struct drm_framebuffer *fb,
2733                                          int x, int y)
2734 {
2735         struct drm_device *dev = crtc->dev;
2736         struct drm_i915_private *dev_priv = dev->dev_private;
2737         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2738         struct intel_framebuffer *intel_fb;
2739         struct drm_i915_gem_object *obj;
2740         int pipe = intel_crtc->pipe;
2741         u32 plane_ctl, stride;
2742
2743         if (!intel_crtc->primary_enabled) {
2744                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2745                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2746                 POSTING_READ(PLANE_CTL(pipe, 0));
2747                 return;
2748         }
2749
2750         plane_ctl = PLANE_CTL_ENABLE |
2751                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2752                     PLANE_CTL_PIPE_CSC_ENABLE;
2753
2754         switch (fb->pixel_format) {
2755         case DRM_FORMAT_RGB565:
2756                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2757                 break;
2758         case DRM_FORMAT_XRGB8888:
2759                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2760                 break;
2761         case DRM_FORMAT_XBGR8888:
2762                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2763                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2764                 break;
2765         case DRM_FORMAT_XRGB2101010:
2766                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2767                 break;
2768         case DRM_FORMAT_XBGR2101010:
2769                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2770                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2771                 break;
2772         default:
2773                 BUG();
2774         }
2775
2776         intel_fb = to_intel_framebuffer(fb);
2777         obj = intel_fb->obj;
2778
2779         /*
2780          * The stride is either expressed as a multiple of 64 bytes chunks for
2781          * linear buffers or in number of tiles for tiled buffers.
2782          */
2783         switch (fb->modifier[0]) {
2784         case DRM_FORMAT_MOD_NONE:
2785                 stride = fb->pitches[0] >> 6;
2786                 break;
2787         case I915_FORMAT_MOD_X_TILED:
2788                 plane_ctl |= PLANE_CTL_TILED_X;
2789                 stride = fb->pitches[0] >> 9;
2790                 break;
2791         default:
2792                 BUG();
2793         }
2794
2795         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2796         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2797                 plane_ctl |= PLANE_CTL_ROTATE_180;
2798
2799         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2800
2801         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2802                       i915_gem_obj_ggtt_offset(obj),
2803                       x, y, fb->width, fb->height,
2804                       fb->pitches[0]);
2805
2806         I915_WRITE(PLANE_POS(pipe, 0), 0);
2807         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2808         I915_WRITE(PLANE_SIZE(pipe, 0),
2809                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2810                    (intel_crtc->config->pipe_src_w - 1));
2811         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2812         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2813
2814         POSTING_READ(PLANE_SURF(pipe, 0));
2815 }
2816
2817 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2818 static int
2819 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2820                            int x, int y, enum mode_set_atomic state)
2821 {
2822         struct drm_device *dev = crtc->dev;
2823         struct drm_i915_private *dev_priv = dev->dev_private;
2824
2825         if (dev_priv->display.disable_fbc)
2826                 dev_priv->display.disable_fbc(dev);
2827
2828         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2829
2830         return 0;
2831 }
2832
2833 static void intel_complete_page_flips(struct drm_device *dev)
2834 {
2835         struct drm_crtc *crtc;
2836
2837         for_each_crtc(dev, crtc) {
2838                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839                 enum plane plane = intel_crtc->plane;
2840
2841                 intel_prepare_page_flip(dev, plane);
2842                 intel_finish_page_flip_plane(dev, plane);
2843         }
2844 }
2845
2846 static void intel_update_primary_planes(struct drm_device *dev)
2847 {
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         struct drm_crtc *crtc;
2850
2851         for_each_crtc(dev, crtc) {
2852                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2853
2854                 drm_modeset_lock(&crtc->mutex, NULL);
2855                 /*
2856                  * FIXME: Once we have proper support for primary planes (and
2857                  * disabling them without disabling the entire crtc) allow again
2858                  * a NULL crtc->primary->fb.
2859                  */
2860                 if (intel_crtc->active && crtc->primary->fb)
2861                         dev_priv->display.update_primary_plane(crtc,
2862                                                                crtc->primary->fb,
2863                                                                crtc->x,
2864                                                                crtc->y);
2865                 drm_modeset_unlock(&crtc->mutex);
2866         }
2867 }
2868
2869 void intel_prepare_reset(struct drm_device *dev)
2870 {
2871         struct drm_i915_private *dev_priv = to_i915(dev);
2872         struct intel_crtc *crtc;
2873
2874         /* no reset support for gen2 */
2875         if (IS_GEN2(dev))
2876                 return;
2877
2878         /* reset doesn't touch the display */
2879         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2880                 return;
2881
2882         drm_modeset_lock_all(dev);
2883
2884         /*
2885          * Disabling the crtcs gracefully seems nicer. Also the
2886          * g33 docs say we should at least disable all the planes.
2887          */
2888         for_each_intel_crtc(dev, crtc) {
2889                 if (crtc->active)
2890                         dev_priv->display.crtc_disable(&crtc->base);
2891         }
2892 }
2893
2894 void intel_finish_reset(struct drm_device *dev)
2895 {
2896         struct drm_i915_private *dev_priv = to_i915(dev);
2897
2898         /*
2899          * Flips in the rings will be nuked by the reset,
2900          * so complete all pending flips so that user space
2901          * will get its events and not get stuck.
2902          */
2903         intel_complete_page_flips(dev);
2904
2905         /* no reset support for gen2 */
2906         if (IS_GEN2(dev))
2907                 return;
2908
2909         /* reset doesn't touch the display */
2910         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2911                 /*
2912                  * Flips in the rings have been nuked by the reset,
2913                  * so update the base address of all primary
2914                  * planes to the the last fb to make sure we're
2915                  * showing the correct fb after a reset.
2916                  */
2917                 intel_update_primary_planes(dev);
2918                 return;
2919         }
2920
2921         /*
2922          * The display has been reset as well,
2923          * so need a full re-initialization.
2924          */
2925         intel_runtime_pm_disable_interrupts(dev_priv);
2926         intel_runtime_pm_enable_interrupts(dev_priv);
2927
2928         intel_modeset_init_hw(dev);
2929
2930         spin_lock_irq(&dev_priv->irq_lock);
2931         if (dev_priv->display.hpd_irq_setup)
2932                 dev_priv->display.hpd_irq_setup(dev);
2933         spin_unlock_irq(&dev_priv->irq_lock);
2934
2935         intel_modeset_setup_hw_state(dev, true);
2936
2937         intel_hpd_init(dev_priv);
2938
2939         drm_modeset_unlock_all(dev);
2940 }
2941
2942 static int
2943 intel_finish_fb(struct drm_framebuffer *old_fb)
2944 {
2945         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2946         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2947         bool was_interruptible = dev_priv->mm.interruptible;
2948         int ret;
2949
2950         /* Big Hammer, we also need to ensure that any pending
2951          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2952          * current scanout is retired before unpinning the old
2953          * framebuffer.
2954          *
2955          * This should only fail upon a hung GPU, in which case we
2956          * can safely continue.
2957          */
2958         dev_priv->mm.interruptible = false;
2959         ret = i915_gem_object_finish_gpu(obj);
2960         dev_priv->mm.interruptible = was_interruptible;
2961
2962         return ret;
2963 }
2964
2965 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2966 {
2967         struct drm_device *dev = crtc->dev;
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2970         bool pending;
2971
2972         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2973             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2974                 return false;
2975
2976         spin_lock_irq(&dev->event_lock);
2977         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2978         spin_unlock_irq(&dev->event_lock);
2979
2980         return pending;
2981 }
2982
2983 static void intel_update_pipe_size(struct intel_crtc *crtc)
2984 {
2985         struct drm_device *dev = crtc->base.dev;
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         const struct drm_display_mode *adjusted_mode;
2988
2989         if (!i915.fastboot)
2990                 return;
2991
2992         /*
2993          * Update pipe size and adjust fitter if needed: the reason for this is
2994          * that in compute_mode_changes we check the native mode (not the pfit
2995          * mode) to see if we can flip rather than do a full mode set. In the
2996          * fastboot case, we'll flip, but if we don't update the pipesrc and
2997          * pfit state, we'll end up with a big fb scanned out into the wrong
2998          * sized surface.
2999          *
3000          * To fix this properly, we need to hoist the checks up into
3001          * compute_mode_changes (or above), check the actual pfit state and
3002          * whether the platform allows pfit disable with pipe active, and only
3003          * then update the pipesrc and pfit state, even on the flip path.
3004          */
3005
3006         adjusted_mode = &crtc->config->base.adjusted_mode;
3007
3008         I915_WRITE(PIPESRC(crtc->pipe),
3009                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3010                    (adjusted_mode->crtc_vdisplay - 1));
3011         if (!crtc->config->pch_pfit.enabled &&
3012             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3013              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3014                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3015                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3016                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3017         }
3018         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3019         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3020 }
3021
3022 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3023 {
3024         struct drm_device *dev = crtc->dev;
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3027         int pipe = intel_crtc->pipe;
3028         u32 reg, temp;
3029
3030         /* enable normal train */
3031         reg = FDI_TX_CTL(pipe);
3032         temp = I915_READ(reg);
3033         if (IS_IVYBRIDGE(dev)) {
3034                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3035                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3036         } else {
3037                 temp &= ~FDI_LINK_TRAIN_NONE;
3038                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3039         }
3040         I915_WRITE(reg, temp);
3041
3042         reg = FDI_RX_CTL(pipe);
3043         temp = I915_READ(reg);
3044         if (HAS_PCH_CPT(dev)) {
3045                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3046                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3047         } else {
3048                 temp &= ~FDI_LINK_TRAIN_NONE;
3049                 temp |= FDI_LINK_TRAIN_NONE;
3050         }
3051         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3052
3053         /* wait one idle pattern time */
3054         POSTING_READ(reg);
3055         udelay(1000);
3056
3057         /* IVB wants error correction enabled */
3058         if (IS_IVYBRIDGE(dev))
3059                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3060                            FDI_FE_ERRC_ENABLE);
3061 }
3062
3063 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3064 {
3065         return crtc->base.enabled && crtc->active &&
3066                 crtc->config->has_pch_encoder;
3067 }
3068
3069 static void ivb_modeset_global_resources(struct drm_device *dev)
3070 {
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072         struct intel_crtc *pipe_B_crtc =
3073                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3074         struct intel_crtc *pipe_C_crtc =
3075                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3076         uint32_t temp;
3077
3078         /*
3079          * When everything is off disable fdi C so that we could enable fdi B
3080          * with all lanes. Note that we don't care about enabled pipes without
3081          * an enabled pch encoder.
3082          */
3083         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3084             !pipe_has_enabled_pch(pipe_C_crtc)) {
3085                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3086                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3087
3088                 temp = I915_READ(SOUTH_CHICKEN1);
3089                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3090                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3091                 I915_WRITE(SOUTH_CHICKEN1, temp);
3092         }
3093 }
3094
3095 /* The FDI link training functions for ILK/Ibexpeak. */
3096 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3097 {
3098         struct drm_device *dev = crtc->dev;
3099         struct drm_i915_private *dev_priv = dev->dev_private;
3100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101         int pipe = intel_crtc->pipe;
3102         u32 reg, temp, tries;
3103
3104         /* FDI needs bits from pipe first */
3105         assert_pipe_enabled(dev_priv, pipe);
3106
3107         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3108            for train result */
3109         reg = FDI_RX_IMR(pipe);
3110         temp = I915_READ(reg);
3111         temp &= ~FDI_RX_SYMBOL_LOCK;
3112         temp &= ~FDI_RX_BIT_LOCK;
3113         I915_WRITE(reg, temp);
3114         I915_READ(reg);
3115         udelay(150);
3116
3117         /* enable CPU FDI TX and PCH FDI RX */
3118         reg = FDI_TX_CTL(pipe);
3119         temp = I915_READ(reg);
3120         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3121         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3122         temp &= ~FDI_LINK_TRAIN_NONE;
3123         temp |= FDI_LINK_TRAIN_PATTERN_1;
3124         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3125
3126         reg = FDI_RX_CTL(pipe);
3127         temp = I915_READ(reg);
3128         temp &= ~FDI_LINK_TRAIN_NONE;
3129         temp |= FDI_LINK_TRAIN_PATTERN_1;
3130         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3131
3132         POSTING_READ(reg);
3133         udelay(150);
3134
3135         /* Ironlake workaround, enable clock pointer after FDI enable*/
3136         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3137         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3138                    FDI_RX_PHASE_SYNC_POINTER_EN);
3139
3140         reg = FDI_RX_IIR(pipe);
3141         for (tries = 0; tries < 5; tries++) {
3142                 temp = I915_READ(reg);
3143                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3144
3145                 if ((temp & FDI_RX_BIT_LOCK)) {
3146                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3147                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3148                         break;
3149                 }
3150         }
3151         if (tries == 5)
3152                 DRM_ERROR("FDI train 1 fail!\n");
3153
3154         /* Train 2 */
3155         reg = FDI_TX_CTL(pipe);
3156         temp = I915_READ(reg);
3157         temp &= ~FDI_LINK_TRAIN_NONE;
3158         temp |= FDI_LINK_TRAIN_PATTERN_2;
3159         I915_WRITE(reg, temp);
3160
3161         reg = FDI_RX_CTL(pipe);
3162         temp = I915_READ(reg);
3163         temp &= ~FDI_LINK_TRAIN_NONE;
3164         temp |= FDI_LINK_TRAIN_PATTERN_2;
3165         I915_WRITE(reg, temp);
3166
3167         POSTING_READ(reg);
3168         udelay(150);
3169
3170         reg = FDI_RX_IIR(pipe);
3171         for (tries = 0; tries < 5; tries++) {
3172                 temp = I915_READ(reg);
3173                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3174
3175                 if (temp & FDI_RX_SYMBOL_LOCK) {
3176                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3177                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3178                         break;
3179                 }
3180         }
3181         if (tries == 5)
3182                 DRM_ERROR("FDI train 2 fail!\n");
3183
3184         DRM_DEBUG_KMS("FDI train done\n");
3185
3186 }
3187
3188 static const int snb_b_fdi_train_param[] = {
3189         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3190         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3191         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3192         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3193 };
3194
3195 /* The FDI link training functions for SNB/Cougarpoint. */
3196 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3197 {
3198         struct drm_device *dev = crtc->dev;
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201         int pipe = intel_crtc->pipe;
3202         u32 reg, temp, i, retry;
3203
3204         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3205            for train result */
3206         reg = FDI_RX_IMR(pipe);
3207         temp = I915_READ(reg);
3208         temp &= ~FDI_RX_SYMBOL_LOCK;
3209         temp &= ~FDI_RX_BIT_LOCK;
3210         I915_WRITE(reg, temp);
3211
3212         POSTING_READ(reg);
3213         udelay(150);
3214
3215         /* enable CPU FDI TX and PCH FDI RX */
3216         reg = FDI_TX_CTL(pipe);
3217         temp = I915_READ(reg);
3218         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3219         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3220         temp &= ~FDI_LINK_TRAIN_NONE;
3221         temp |= FDI_LINK_TRAIN_PATTERN_1;
3222         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3223         /* SNB-B */
3224         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3225         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3226
3227         I915_WRITE(FDI_RX_MISC(pipe),
3228                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3229
3230         reg = FDI_RX_CTL(pipe);
3231         temp = I915_READ(reg);
3232         if (HAS_PCH_CPT(dev)) {
3233                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3234                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3235         } else {
3236                 temp &= ~FDI_LINK_TRAIN_NONE;
3237                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3238         }
3239         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3240
3241         POSTING_READ(reg);
3242         udelay(150);
3243
3244         for (i = 0; i < 4; i++) {
3245                 reg = FDI_TX_CTL(pipe);
3246                 temp = I915_READ(reg);
3247                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3248                 temp |= snb_b_fdi_train_param[i];
3249                 I915_WRITE(reg, temp);
3250
3251                 POSTING_READ(reg);
3252                 udelay(500);
3253
3254                 for (retry = 0; retry < 5; retry++) {
3255                         reg = FDI_RX_IIR(pipe);
3256                         temp = I915_READ(reg);
3257                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3258                         if (temp & FDI_RX_BIT_LOCK) {
3259                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3260                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3261                                 break;
3262                         }
3263                         udelay(50);
3264                 }
3265                 if (retry < 5)
3266                         break;
3267         }
3268         if (i == 4)
3269                 DRM_ERROR("FDI train 1 fail!\n");
3270
3271         /* Train 2 */
3272         reg = FDI_TX_CTL(pipe);
3273         temp = I915_READ(reg);
3274         temp &= ~FDI_LINK_TRAIN_NONE;
3275         temp |= FDI_LINK_TRAIN_PATTERN_2;
3276         if (IS_GEN6(dev)) {
3277                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3278                 /* SNB-B */
3279                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3280         }
3281         I915_WRITE(reg, temp);
3282
3283         reg = FDI_RX_CTL(pipe);
3284         temp = I915_READ(reg);
3285         if (HAS_PCH_CPT(dev)) {
3286                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3287                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3288         } else {
3289                 temp &= ~FDI_LINK_TRAIN_NONE;
3290                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3291         }
3292         I915_WRITE(reg, temp);
3293
3294         POSTING_READ(reg);
3295         udelay(150);
3296
3297         for (i = 0; i < 4; i++) {
3298                 reg = FDI_TX_CTL(pipe);
3299                 temp = I915_READ(reg);
3300                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3301                 temp |= snb_b_fdi_train_param[i];
3302                 I915_WRITE(reg, temp);
3303
3304                 POSTING_READ(reg);
3305                 udelay(500);
3306
3307                 for (retry = 0; retry < 5; retry++) {
3308                         reg = FDI_RX_IIR(pipe);
3309                         temp = I915_READ(reg);
3310                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3311                         if (temp & FDI_RX_SYMBOL_LOCK) {
3312                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3313                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3314                                 break;
3315                         }
3316                         udelay(50);
3317                 }
3318                 if (retry < 5)
3319                         break;
3320         }
3321         if (i == 4)
3322                 DRM_ERROR("FDI train 2 fail!\n");
3323
3324         DRM_DEBUG_KMS("FDI train done.\n");
3325 }
3326
3327 /* Manual link training for Ivy Bridge A0 parts */
3328 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3329 {
3330         struct drm_device *dev = crtc->dev;
3331         struct drm_i915_private *dev_priv = dev->dev_private;
3332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333         int pipe = intel_crtc->pipe;
3334         u32 reg, temp, i, j;
3335
3336         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3337            for train result */
3338         reg = FDI_RX_IMR(pipe);
3339         temp = I915_READ(reg);
3340         temp &= ~FDI_RX_SYMBOL_LOCK;
3341         temp &= ~FDI_RX_BIT_LOCK;
3342         I915_WRITE(reg, temp);
3343
3344         POSTING_READ(reg);
3345         udelay(150);
3346
3347         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3348                       I915_READ(FDI_RX_IIR(pipe)));
3349
3350         /* Try each vswing and preemphasis setting twice before moving on */
3351         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3352                 /* disable first in case we need to retry */
3353                 reg = FDI_TX_CTL(pipe);
3354                 temp = I915_READ(reg);
3355                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3356                 temp &= ~FDI_TX_ENABLE;
3357                 I915_WRITE(reg, temp);
3358
3359                 reg = FDI_RX_CTL(pipe);
3360                 temp = I915_READ(reg);
3361                 temp &= ~FDI_LINK_TRAIN_AUTO;
3362                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3363                 temp &= ~FDI_RX_ENABLE;
3364                 I915_WRITE(reg, temp);
3365
3366                 /* enable CPU FDI TX and PCH FDI RX */
3367                 reg = FDI_TX_CTL(pipe);
3368                 temp = I915_READ(reg);
3369                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3370                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3371                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3372                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3373                 temp |= snb_b_fdi_train_param[j/2];
3374                 temp |= FDI_COMPOSITE_SYNC;
3375                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3376
3377                 I915_WRITE(FDI_RX_MISC(pipe),
3378                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3379
3380                 reg = FDI_RX_CTL(pipe);
3381                 temp = I915_READ(reg);
3382                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3383                 temp |= FDI_COMPOSITE_SYNC;
3384                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3385
3386                 POSTING_READ(reg);
3387                 udelay(1); /* should be 0.5us */
3388
3389                 for (i = 0; i < 4; i++) {
3390                         reg = FDI_RX_IIR(pipe);
3391                         temp = I915_READ(reg);
3392                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3393
3394                         if (temp & FDI_RX_BIT_LOCK ||
3395                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3396                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3397                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3398                                               i);
3399                                 break;
3400                         }
3401                         udelay(1); /* should be 0.5us */
3402                 }
3403                 if (i == 4) {
3404                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3405                         continue;
3406                 }
3407
3408                 /* Train 2 */
3409                 reg = FDI_TX_CTL(pipe);
3410                 temp = I915_READ(reg);
3411                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3413                 I915_WRITE(reg, temp);
3414
3415                 reg = FDI_RX_CTL(pipe);
3416                 temp = I915_READ(reg);
3417                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3418                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3419                 I915_WRITE(reg, temp);
3420
3421                 POSTING_READ(reg);
3422                 udelay(2); /* should be 1.5us */
3423
3424                 for (i = 0; i < 4; i++) {
3425                         reg = FDI_RX_IIR(pipe);
3426                         temp = I915_READ(reg);
3427                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3428
3429                         if (temp & FDI_RX_SYMBOL_LOCK ||
3430                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3431                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3432                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3433                                               i);
3434                                 goto train_done;
3435                         }
3436                         udelay(2); /* should be 1.5us */
3437                 }
3438                 if (i == 4)
3439                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3440         }
3441
3442 train_done:
3443         DRM_DEBUG_KMS("FDI train done.\n");
3444 }
3445
3446 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3447 {
3448         struct drm_device *dev = intel_crtc->base.dev;
3449         struct drm_i915_private *dev_priv = dev->dev_private;
3450         int pipe = intel_crtc->pipe;
3451         u32 reg, temp;
3452
3453
3454         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3455         reg = FDI_RX_CTL(pipe);
3456         temp = I915_READ(reg);
3457         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3458         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3459         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3460         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3461
3462         POSTING_READ(reg);
3463         udelay(200);
3464
3465         /* Switch from Rawclk to PCDclk */
3466         temp = I915_READ(reg);
3467         I915_WRITE(reg, temp | FDI_PCDCLK);
3468
3469         POSTING_READ(reg);
3470         udelay(200);
3471
3472         /* Enable CPU FDI TX PLL, always on for Ironlake */
3473         reg = FDI_TX_CTL(pipe);
3474         temp = I915_READ(reg);
3475         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3476                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3477
3478                 POSTING_READ(reg);
3479                 udelay(100);
3480         }
3481 }
3482
3483 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3484 {
3485         struct drm_device *dev = intel_crtc->base.dev;
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         int pipe = intel_crtc->pipe;
3488         u32 reg, temp;
3489
3490         /* Switch from PCDclk to Rawclk */
3491         reg = FDI_RX_CTL(pipe);
3492         temp = I915_READ(reg);
3493         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3494
3495         /* Disable CPU FDI TX PLL */
3496         reg = FDI_TX_CTL(pipe);
3497         temp = I915_READ(reg);
3498         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3499
3500         POSTING_READ(reg);
3501         udelay(100);
3502
3503         reg = FDI_RX_CTL(pipe);
3504         temp = I915_READ(reg);
3505         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3506
3507         /* Wait for the clocks to turn off. */
3508         POSTING_READ(reg);
3509         udelay(100);
3510 }
3511
3512 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3513 {
3514         struct drm_device *dev = crtc->dev;
3515         struct drm_i915_private *dev_priv = dev->dev_private;
3516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517         int pipe = intel_crtc->pipe;
3518         u32 reg, temp;
3519
3520         /* disable CPU FDI tx and PCH FDI rx */
3521         reg = FDI_TX_CTL(pipe);
3522         temp = I915_READ(reg);
3523         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3524         POSTING_READ(reg);
3525
3526         reg = FDI_RX_CTL(pipe);
3527         temp = I915_READ(reg);
3528         temp &= ~(0x7 << 16);
3529         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3530         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3531
3532         POSTING_READ(reg);
3533         udelay(100);
3534
3535         /* Ironlake workaround, disable clock pointer after downing FDI */
3536         if (HAS_PCH_IBX(dev))
3537                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3538
3539         /* still set train pattern 1 */
3540         reg = FDI_TX_CTL(pipe);
3541         temp = I915_READ(reg);
3542         temp &= ~FDI_LINK_TRAIN_NONE;
3543         temp |= FDI_LINK_TRAIN_PATTERN_1;
3544         I915_WRITE(reg, temp);
3545
3546         reg = FDI_RX_CTL(pipe);
3547         temp = I915_READ(reg);
3548         if (HAS_PCH_CPT(dev)) {
3549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3550                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3551         } else {
3552                 temp &= ~FDI_LINK_TRAIN_NONE;
3553                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3554         }
3555         /* BPC in FDI rx is consistent with that in PIPECONF */
3556         temp &= ~(0x07 << 16);
3557         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3558         I915_WRITE(reg, temp);
3559
3560         POSTING_READ(reg);
3561         udelay(100);
3562 }
3563
3564 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3565 {
3566         struct intel_crtc *crtc;
3567
3568         /* Note that we don't need to be called with mode_config.lock here
3569          * as our list of CRTC objects is static for the lifetime of the
3570          * device and so cannot disappear as we iterate. Similarly, we can
3571          * happily treat the predicates as racy, atomic checks as userspace
3572          * cannot claim and pin a new fb without at least acquring the
3573          * struct_mutex and so serialising with us.
3574          */
3575         for_each_intel_crtc(dev, crtc) {
3576                 if (atomic_read(&crtc->unpin_work_count) == 0)
3577                         continue;
3578
3579                 if (crtc->unpin_work)
3580                         intel_wait_for_vblank(dev, crtc->pipe);
3581
3582                 return true;
3583         }
3584
3585         return false;
3586 }
3587
3588 static void page_flip_completed(struct intel_crtc *intel_crtc)
3589 {
3590         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3591         struct intel_unpin_work *work = intel_crtc->unpin_work;
3592
3593         /* ensure that the unpin work is consistent wrt ->pending. */
3594         smp_rmb();
3595         intel_crtc->unpin_work = NULL;
3596
3597         if (work->event)
3598                 drm_send_vblank_event(intel_crtc->base.dev,
3599                                       intel_crtc->pipe,
3600                                       work->event);
3601
3602         drm_crtc_vblank_put(&intel_crtc->base);
3603
3604         wake_up_all(&dev_priv->pending_flip_queue);
3605         queue_work(dev_priv->wq, &work->work);
3606
3607         trace_i915_flip_complete(intel_crtc->plane,
3608                                  work->pending_flip_obj);
3609 }
3610
3611 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3612 {
3613         struct drm_device *dev = crtc->dev;
3614         struct drm_i915_private *dev_priv = dev->dev_private;
3615
3616         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3617         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3618                                        !intel_crtc_has_pending_flip(crtc),
3619                                        60*HZ) == 0)) {
3620                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621
3622                 spin_lock_irq(&dev->event_lock);
3623                 if (intel_crtc->unpin_work) {
3624                         WARN_ONCE(1, "Removing stuck page flip\n");
3625                         page_flip_completed(intel_crtc);
3626                 }
3627                 spin_unlock_irq(&dev->event_lock);
3628         }
3629
3630         if (crtc->primary->fb) {
3631                 mutex_lock(&dev->struct_mutex);
3632                 intel_finish_fb(crtc->primary->fb);
3633                 mutex_unlock(&dev->struct_mutex);
3634         }
3635 }
3636
3637 /* Program iCLKIP clock to the desired frequency */
3638 static void lpt_program_iclkip(struct drm_crtc *crtc)
3639 {
3640         struct drm_device *dev = crtc->dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3643         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3644         u32 temp;
3645
3646         mutex_lock(&dev_priv->dpio_lock);
3647
3648         /* It is necessary to ungate the pixclk gate prior to programming
3649          * the divisors, and gate it back when it is done.
3650          */
3651         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3652
3653         /* Disable SSCCTL */
3654         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3655                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3656                                 SBI_SSCCTL_DISABLE,
3657                         SBI_ICLK);
3658
3659         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3660         if (clock == 20000) {
3661                 auxdiv = 1;
3662                 divsel = 0x41;
3663                 phaseinc = 0x20;
3664         } else {
3665                 /* The iCLK virtual clock root frequency is in MHz,
3666                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3667                  * divisors, it is necessary to divide one by another, so we
3668                  * convert the virtual clock precision to KHz here for higher
3669                  * precision.
3670                  */
3671                 u32 iclk_virtual_root_freq = 172800 * 1000;
3672                 u32 iclk_pi_range = 64;
3673                 u32 desired_divisor, msb_divisor_value, pi_value;
3674
3675                 desired_divisor = (iclk_virtual_root_freq / clock);
3676                 msb_divisor_value = desired_divisor / iclk_pi_range;
3677                 pi_value = desired_divisor % iclk_pi_range;
3678
3679                 auxdiv = 0;
3680                 divsel = msb_divisor_value - 2;
3681                 phaseinc = pi_value;
3682         }
3683
3684         /* This should not happen with any sane values */
3685         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3686                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3687         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3688                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3689
3690         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3691                         clock,
3692                         auxdiv,
3693                         divsel,
3694                         phasedir,
3695                         phaseinc);
3696
3697         /* Program SSCDIVINTPHASE6 */
3698         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3699         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3700         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3701         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3702         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3703         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3704         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3705         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3706
3707         /* Program SSCAUXDIV */
3708         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3709         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3710         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3711         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3712
3713         /* Enable modulator and associated divider */
3714         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3715         temp &= ~SBI_SSCCTL_DISABLE;
3716         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3717
3718         /* Wait for initialization time */
3719         udelay(24);
3720
3721         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3722
3723         mutex_unlock(&dev_priv->dpio_lock);
3724 }
3725
3726 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3727                                                 enum pipe pch_transcoder)
3728 {
3729         struct drm_device *dev = crtc->base.dev;
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3732
3733         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3734                    I915_READ(HTOTAL(cpu_transcoder)));
3735         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3736                    I915_READ(HBLANK(cpu_transcoder)));
3737         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3738                    I915_READ(HSYNC(cpu_transcoder)));
3739
3740         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3741                    I915_READ(VTOTAL(cpu_transcoder)));
3742         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3743                    I915_READ(VBLANK(cpu_transcoder)));
3744         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3745                    I915_READ(VSYNC(cpu_transcoder)));
3746         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3747                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3748 }
3749
3750 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3751 {
3752         struct drm_i915_private *dev_priv = dev->dev_private;
3753         uint32_t temp;
3754
3755         temp = I915_READ(SOUTH_CHICKEN1);
3756         if (temp & FDI_BC_BIFURCATION_SELECT)
3757                 return;
3758
3759         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3760         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3761
3762         temp |= FDI_BC_BIFURCATION_SELECT;
3763         DRM_DEBUG_KMS("enabling fdi C rx\n");
3764         I915_WRITE(SOUTH_CHICKEN1, temp);
3765         POSTING_READ(SOUTH_CHICKEN1);
3766 }
3767
3768 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3769 {
3770         struct drm_device *dev = intel_crtc->base.dev;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772
3773         switch (intel_crtc->pipe) {
3774         case PIPE_A:
3775                 break;
3776         case PIPE_B:
3777                 if (intel_crtc->config->fdi_lanes > 2)
3778                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3779                 else
3780                         cpt_enable_fdi_bc_bifurcation(dev);
3781
3782                 break;
3783         case PIPE_C:
3784                 cpt_enable_fdi_bc_bifurcation(dev);
3785
3786                 break;
3787         default:
3788                 BUG();
3789         }
3790 }
3791
3792 /*
3793  * Enable PCH resources required for PCH ports:
3794  *   - PCH PLLs
3795  *   - FDI training & RX/TX
3796  *   - update transcoder timings
3797  *   - DP transcoding bits
3798  *   - transcoder
3799  */
3800 static void ironlake_pch_enable(struct drm_crtc *crtc)
3801 {
3802         struct drm_device *dev = crtc->dev;
3803         struct drm_i915_private *dev_priv = dev->dev_private;
3804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3805         int pipe = intel_crtc->pipe;
3806         u32 reg, temp;
3807
3808         assert_pch_transcoder_disabled(dev_priv, pipe);
3809
3810         if (IS_IVYBRIDGE(dev))
3811                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3812
3813         /* Write the TU size bits before fdi link training, so that error
3814          * detection works. */
3815         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3816                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3817
3818         /* For PCH output, training FDI link */
3819         dev_priv->display.fdi_link_train(crtc);
3820
3821         /* We need to program the right clock selection before writing the pixel
3822          * mutliplier into the DPLL. */
3823         if (HAS_PCH_CPT(dev)) {
3824                 u32 sel;
3825
3826                 temp = I915_READ(PCH_DPLL_SEL);
3827                 temp |= TRANS_DPLL_ENABLE(pipe);
3828                 sel = TRANS_DPLLB_SEL(pipe);
3829                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3830                         temp |= sel;
3831                 else
3832                         temp &= ~sel;
3833                 I915_WRITE(PCH_DPLL_SEL, temp);
3834         }
3835
3836         /* XXX: pch pll's can be enabled any time before we enable the PCH
3837          * transcoder, and we actually should do this to not upset any PCH
3838          * transcoder that already use the clock when we share it.
3839          *
3840          * Note that enable_shared_dpll tries to do the right thing, but
3841          * get_shared_dpll unconditionally resets the pll - we need that to have
3842          * the right LVDS enable sequence. */
3843         intel_enable_shared_dpll(intel_crtc);
3844
3845         /* set transcoder timing, panel must allow it */
3846         assert_panel_unlocked(dev_priv, pipe);
3847         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3848
3849         intel_fdi_normal_train(crtc);
3850
3851         /* For PCH DP, enable TRANS_DP_CTL */
3852         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3853                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3854                 reg = TRANS_DP_CTL(pipe);
3855                 temp = I915_READ(reg);
3856                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3857                           TRANS_DP_SYNC_MASK |
3858                           TRANS_DP_BPC_MASK);
3859                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3860                          TRANS_DP_ENH_FRAMING);
3861                 temp |= bpc << 9; /* same format but at 11:9 */
3862
3863                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3864                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3865                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3866                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3867
3868                 switch (intel_trans_dp_port_sel(crtc)) {
3869                 case PCH_DP_B:
3870                         temp |= TRANS_DP_PORT_SEL_B;
3871                         break;
3872                 case PCH_DP_C:
3873                         temp |= TRANS_DP_PORT_SEL_C;
3874                         break;
3875                 case PCH_DP_D:
3876                         temp |= TRANS_DP_PORT_SEL_D;
3877                         break;
3878                 default:
3879                         BUG();
3880                 }
3881
3882                 I915_WRITE(reg, temp);
3883         }
3884
3885         ironlake_enable_pch_transcoder(dev_priv, pipe);
3886 }
3887
3888 static void lpt_pch_enable(struct drm_crtc *crtc)
3889 {
3890         struct drm_device *dev = crtc->dev;
3891         struct drm_i915_private *dev_priv = dev->dev_private;
3892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3894
3895         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3896
3897         lpt_program_iclkip(crtc);
3898
3899         /* Set transcoder timing. */
3900         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3901
3902         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3903 }
3904
3905 void intel_put_shared_dpll(struct intel_crtc *crtc)
3906 {
3907         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3908
3909         if (pll == NULL)
3910                 return;
3911
3912         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3913                 WARN(1, "bad %s crtc mask\n", pll->name);
3914                 return;
3915         }
3916
3917         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3918         if (pll->config.crtc_mask == 0) {
3919                 WARN_ON(pll->on);
3920                 WARN_ON(pll->active);
3921         }
3922
3923         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3924 }
3925
3926 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3927                                                 struct intel_crtc_state *crtc_state)
3928 {
3929         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3930         struct intel_shared_dpll *pll;
3931         enum intel_dpll_id i;
3932
3933         if (HAS_PCH_IBX(dev_priv->dev)) {
3934                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3935                 i = (enum intel_dpll_id) crtc->pipe;
3936                 pll = &dev_priv->shared_dplls[i];
3937
3938                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3939                               crtc->base.base.id, pll->name);
3940
3941                 WARN_ON(pll->new_config->crtc_mask);
3942
3943                 goto found;
3944         }
3945
3946         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3947                 pll = &dev_priv->shared_dplls[i];
3948
3949                 /* Only want to check enabled timings first */
3950                 if (pll->new_config->crtc_mask == 0)
3951                         continue;
3952
3953                 if (memcmp(&crtc_state->dpll_hw_state,
3954                            &pll->new_config->hw_state,
3955                            sizeof(pll->new_config->hw_state)) == 0) {
3956                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3957                                       crtc->base.base.id, pll->name,
3958                                       pll->new_config->crtc_mask,
3959                                       pll->active);
3960                         goto found;
3961                 }
3962         }
3963
3964         /* Ok no matching timings, maybe there's a free one? */
3965         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3966                 pll = &dev_priv->shared_dplls[i];
3967                 if (pll->new_config->crtc_mask == 0) {
3968                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3969                                       crtc->base.base.id, pll->name);
3970                         goto found;
3971                 }
3972         }
3973
3974         return NULL;
3975
3976 found:
3977         if (pll->new_config->crtc_mask == 0)
3978                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3979
3980         crtc_state->shared_dpll = i;
3981         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3982                          pipe_name(crtc->pipe));
3983
3984         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3985
3986         return pll;
3987 }
3988
3989 /**
3990  * intel_shared_dpll_start_config - start a new PLL staged config
3991  * @dev_priv: DRM device
3992  * @clear_pipes: mask of pipes that will have their PLLs freed
3993  *
3994  * Starts a new PLL staged config, copying the current config but
3995  * releasing the references of pipes specified in clear_pipes.
3996  */
3997 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3998                                           unsigned clear_pipes)
3999 {
4000         struct intel_shared_dpll *pll;
4001         enum intel_dpll_id i;
4002
4003         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4004                 pll = &dev_priv->shared_dplls[i];
4005
4006                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4007                                           GFP_KERNEL);
4008                 if (!pll->new_config)
4009                         goto cleanup;
4010
4011                 pll->new_config->crtc_mask &= ~clear_pipes;
4012         }
4013
4014         return 0;
4015
4016 cleanup:
4017         while (--i >= 0) {
4018                 pll = &dev_priv->shared_dplls[i];
4019                 kfree(pll->new_config);
4020                 pll->new_config = NULL;
4021         }
4022
4023         return -ENOMEM;
4024 }
4025
4026 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4027 {
4028         struct intel_shared_dpll *pll;
4029         enum intel_dpll_id i;
4030
4031         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4032                 pll = &dev_priv->shared_dplls[i];
4033
4034                 WARN_ON(pll->new_config == &pll->config);
4035
4036                 pll->config = *pll->new_config;
4037                 kfree(pll->new_config);
4038                 pll->new_config = NULL;
4039         }
4040 }
4041
4042 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4043 {
4044         struct intel_shared_dpll *pll;
4045         enum intel_dpll_id i;
4046
4047         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4048                 pll = &dev_priv->shared_dplls[i];
4049
4050                 WARN_ON(pll->new_config == &pll->config);
4051
4052                 kfree(pll->new_config);
4053                 pll->new_config = NULL;
4054         }
4055 }
4056
4057 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4058 {
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         int dslreg = PIPEDSL(pipe);
4061         u32 temp;
4062
4063         temp = I915_READ(dslreg);
4064         udelay(500);
4065         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4066                 if (wait_for(I915_READ(dslreg) != temp, 5))
4067                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4068         }
4069 }
4070
4071 static void skylake_pfit_enable(struct intel_crtc *crtc)
4072 {
4073         struct drm_device *dev = crtc->base.dev;
4074         struct drm_i915_private *dev_priv = dev->dev_private;
4075         int pipe = crtc->pipe;
4076
4077         if (crtc->config->pch_pfit.enabled) {
4078                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4079                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4080                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4081         }
4082 }
4083
4084 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4085 {
4086         struct drm_device *dev = crtc->base.dev;
4087         struct drm_i915_private *dev_priv = dev->dev_private;
4088         int pipe = crtc->pipe;
4089
4090         if (crtc->config->pch_pfit.enabled) {
4091                 /* Force use of hard-coded filter coefficients
4092                  * as some pre-programmed values are broken,
4093                  * e.g. x201.
4094                  */
4095                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4096                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4097                                                  PF_PIPE_SEL_IVB(pipe));
4098                 else
4099                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4100                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4101                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4102         }
4103 }
4104
4105 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4106 {
4107         struct drm_device *dev = crtc->dev;
4108         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4109         struct drm_plane *plane;
4110         struct intel_plane *intel_plane;
4111
4112         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4113                 intel_plane = to_intel_plane(plane);
4114                 if (intel_plane->pipe == pipe)
4115                         intel_plane_restore(&intel_plane->base);
4116         }
4117 }
4118
4119 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4120 {
4121         struct drm_device *dev = crtc->dev;
4122         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4123         struct drm_plane *plane;
4124         struct intel_plane *intel_plane;
4125
4126         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4127                 intel_plane = to_intel_plane(plane);
4128                 if (intel_plane->pipe == pipe)
4129                         plane->funcs->disable_plane(plane);
4130         }
4131 }
4132
4133 void hsw_enable_ips(struct intel_crtc *crtc)
4134 {
4135         struct drm_device *dev = crtc->base.dev;
4136         struct drm_i915_private *dev_priv = dev->dev_private;
4137
4138         if (!crtc->config->ips_enabled)
4139                 return;
4140
4141         /* We can only enable IPS after we enable a plane and wait for a vblank */
4142         intel_wait_for_vblank(dev, crtc->pipe);
4143
4144         assert_plane_enabled(dev_priv, crtc->plane);
4145         if (IS_BROADWELL(dev)) {
4146                 mutex_lock(&dev_priv->rps.hw_lock);
4147                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4148                 mutex_unlock(&dev_priv->rps.hw_lock);
4149                 /* Quoting Art Runyan: "its not safe to expect any particular
4150                  * value in IPS_CTL bit 31 after enabling IPS through the
4151                  * mailbox." Moreover, the mailbox may return a bogus state,
4152                  * so we need to just enable it and continue on.
4153                  */
4154         } else {
4155                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4156                 /* The bit only becomes 1 in the next vblank, so this wait here
4157                  * is essentially intel_wait_for_vblank. If we don't have this
4158                  * and don't wait for vblanks until the end of crtc_enable, then
4159                  * the HW state readout code will complain that the expected
4160                  * IPS_CTL value is not the one we read. */
4161                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4162                         DRM_ERROR("Timed out waiting for IPS enable\n");
4163         }
4164 }
4165
4166 void hsw_disable_ips(struct intel_crtc *crtc)
4167 {
4168         struct drm_device *dev = crtc->base.dev;
4169         struct drm_i915_private *dev_priv = dev->dev_private;
4170
4171         if (!crtc->config->ips_enabled)
4172                 return;
4173
4174         assert_plane_enabled(dev_priv, crtc->plane);
4175         if (IS_BROADWELL(dev)) {
4176                 mutex_lock(&dev_priv->rps.hw_lock);
4177                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4178                 mutex_unlock(&dev_priv->rps.hw_lock);
4179                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4180                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4181                         DRM_ERROR("Timed out waiting for IPS disable\n");
4182         } else {
4183                 I915_WRITE(IPS_CTL, 0);
4184                 POSTING_READ(IPS_CTL);
4185         }
4186
4187         /* We need to wait for a vblank before we can disable the plane. */
4188         intel_wait_for_vblank(dev, crtc->pipe);
4189 }
4190
4191 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4192 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4193 {
4194         struct drm_device *dev = crtc->dev;
4195         struct drm_i915_private *dev_priv = dev->dev_private;
4196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197         enum pipe pipe = intel_crtc->pipe;
4198         int palreg = PALETTE(pipe);
4199         int i;
4200         bool reenable_ips = false;
4201
4202         /* The clocks have to be on to load the palette. */
4203         if (!crtc->enabled || !intel_crtc->active)
4204                 return;
4205
4206         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4207                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4208                         assert_dsi_pll_enabled(dev_priv);
4209                 else
4210                         assert_pll_enabled(dev_priv, pipe);
4211         }
4212
4213         /* use legacy palette for Ironlake */
4214         if (!HAS_GMCH_DISPLAY(dev))
4215                 palreg = LGC_PALETTE(pipe);
4216
4217         /* Workaround : Do not read or write the pipe palette/gamma data while
4218          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4219          */
4220         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4221             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4222              GAMMA_MODE_MODE_SPLIT)) {
4223                 hsw_disable_ips(intel_crtc);
4224                 reenable_ips = true;
4225         }
4226
4227         for (i = 0; i < 256; i++) {
4228                 I915_WRITE(palreg + 4 * i,
4229                            (intel_crtc->lut_r[i] << 16) |
4230                            (intel_crtc->lut_g[i] << 8) |
4231                            intel_crtc->lut_b[i]);
4232         }
4233
4234         if (reenable_ips)
4235                 hsw_enable_ips(intel_crtc);
4236 }
4237
4238 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4239 {
4240         if (!enable && intel_crtc->overlay) {
4241                 struct drm_device *dev = intel_crtc->base.dev;
4242                 struct drm_i915_private *dev_priv = dev->dev_private;
4243
4244                 mutex_lock(&dev->struct_mutex);
4245                 dev_priv->mm.interruptible = false;
4246                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4247                 dev_priv->mm.interruptible = true;
4248                 mutex_unlock(&dev->struct_mutex);
4249         }
4250
4251         /* Let userspace switch the overlay on again. In most cases userspace
4252          * has to recompute where to put it anyway.
4253          */
4254 }
4255
4256 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4257 {
4258         struct drm_device *dev = crtc->dev;
4259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4260         int pipe = intel_crtc->pipe;
4261
4262         intel_enable_primary_hw_plane(crtc->primary, crtc);
4263         intel_enable_sprite_planes(crtc);
4264         intel_crtc_update_cursor(crtc, true);
4265         intel_crtc_dpms_overlay(intel_crtc, true);
4266
4267         hsw_enable_ips(intel_crtc);
4268
4269         mutex_lock(&dev->struct_mutex);
4270         intel_fbc_update(dev);
4271         mutex_unlock(&dev->struct_mutex);
4272
4273         /*
4274          * FIXME: Once we grow proper nuclear flip support out of this we need
4275          * to compute the mask of flip planes precisely. For the time being
4276          * consider this a flip from a NULL plane.
4277          */
4278         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4279 }
4280
4281 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4282 {
4283         struct drm_device *dev = crtc->dev;
4284         struct drm_i915_private *dev_priv = dev->dev_private;
4285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286         int pipe = intel_crtc->pipe;
4287
4288         intel_crtc_wait_for_pending_flips(crtc);
4289
4290         if (dev_priv->fbc.crtc == intel_crtc)
4291                 intel_fbc_disable(dev);
4292
4293         hsw_disable_ips(intel_crtc);
4294
4295         intel_crtc_dpms_overlay(intel_crtc, false);
4296         intel_crtc_update_cursor(crtc, false);
4297         intel_disable_sprite_planes(crtc);
4298         intel_disable_primary_hw_plane(crtc->primary, crtc);
4299
4300         /*
4301          * FIXME: Once we grow proper nuclear flip support out of this we need
4302          * to compute the mask of flip planes precisely. For the time being
4303          * consider this a flip to a NULL plane.
4304          */
4305         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4306 }
4307
4308 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4309 {
4310         struct drm_device *dev = crtc->dev;
4311         struct drm_i915_private *dev_priv = dev->dev_private;
4312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4313         struct intel_encoder *encoder;
4314         int pipe = intel_crtc->pipe;
4315
4316         WARN_ON(!crtc->enabled);
4317
4318         if (intel_crtc->active)
4319                 return;
4320
4321         if (intel_crtc->config->has_pch_encoder)
4322                 intel_prepare_shared_dpll(intel_crtc);
4323
4324         if (intel_crtc->config->has_dp_encoder)
4325                 intel_dp_set_m_n(intel_crtc);
4326
4327         intel_set_pipe_timings(intel_crtc);
4328
4329         if (intel_crtc->config->has_pch_encoder) {
4330                 intel_cpu_transcoder_set_m_n(intel_crtc,
4331                                      &intel_crtc->config->fdi_m_n, NULL);
4332         }
4333
4334         ironlake_set_pipeconf(crtc);
4335
4336         intel_crtc->active = true;
4337
4338         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4339         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4340
4341         for_each_encoder_on_crtc(dev, crtc, encoder)
4342                 if (encoder->pre_enable)
4343                         encoder->pre_enable(encoder);
4344
4345         if (intel_crtc->config->has_pch_encoder) {
4346                 /* Note: FDI PLL enabling _must_ be done before we enable the
4347                  * cpu pipes, hence this is separate from all the other fdi/pch
4348                  * enabling. */
4349                 ironlake_fdi_pll_enable(intel_crtc);
4350         } else {
4351                 assert_fdi_tx_disabled(dev_priv, pipe);
4352                 assert_fdi_rx_disabled(dev_priv, pipe);
4353         }
4354
4355         ironlake_pfit_enable(intel_crtc);
4356
4357         /*
4358          * On ILK+ LUT must be loaded before the pipe is running but with
4359          * clocks enabled
4360          */
4361         intel_crtc_load_lut(crtc);
4362
4363         intel_update_watermarks(crtc);
4364         intel_enable_pipe(intel_crtc);
4365
4366         if (intel_crtc->config->has_pch_encoder)
4367                 ironlake_pch_enable(crtc);
4368
4369         assert_vblank_disabled(crtc);
4370         drm_crtc_vblank_on(crtc);
4371
4372         for_each_encoder_on_crtc(dev, crtc, encoder)
4373                 encoder->enable(encoder);
4374
4375         if (HAS_PCH_CPT(dev))
4376                 cpt_verify_modeset(dev, intel_crtc->pipe);
4377
4378         intel_crtc_enable_planes(crtc);
4379 }
4380
4381 /* IPS only exists on ULT machines and is tied to pipe A. */
4382 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4383 {
4384         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4385 }
4386
4387 /*
4388  * This implements the workaround described in the "notes" section of the mode
4389  * set sequence documentation. When going from no pipes or single pipe to
4390  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4391  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4392  */
4393 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4394 {
4395         struct drm_device *dev = crtc->base.dev;
4396         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4397
4398         /* We want to get the other_active_crtc only if there's only 1 other
4399          * active crtc. */
4400         for_each_intel_crtc(dev, crtc_it) {
4401                 if (!crtc_it->active || crtc_it == crtc)
4402                         continue;
4403
4404                 if (other_active_crtc)
4405                         return;
4406
4407                 other_active_crtc = crtc_it;
4408         }
4409         if (!other_active_crtc)
4410                 return;
4411
4412         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4413         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4414 }
4415
4416 static void haswell_crtc_enable(struct drm_crtc *crtc)
4417 {
4418         struct drm_device *dev = crtc->dev;
4419         struct drm_i915_private *dev_priv = dev->dev_private;
4420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4421         struct intel_encoder *encoder;
4422         int pipe = intel_crtc->pipe;
4423
4424         WARN_ON(!crtc->enabled);
4425
4426         if (intel_crtc->active)
4427                 return;
4428
4429         if (intel_crtc_to_shared_dpll(intel_crtc))
4430                 intel_enable_shared_dpll(intel_crtc);
4431
4432         if (intel_crtc->config->has_dp_encoder)
4433                 intel_dp_set_m_n(intel_crtc);
4434
4435         intel_set_pipe_timings(intel_crtc);
4436
4437         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4438                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4439                            intel_crtc->config->pixel_multiplier - 1);
4440         }
4441
4442         if (intel_crtc->config->has_pch_encoder) {
4443                 intel_cpu_transcoder_set_m_n(intel_crtc,
4444                                      &intel_crtc->config->fdi_m_n, NULL);
4445         }
4446
4447         haswell_set_pipeconf(crtc);
4448
4449         intel_set_pipe_csc(crtc);
4450
4451         intel_crtc->active = true;
4452
4453         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4454         for_each_encoder_on_crtc(dev, crtc, encoder)
4455                 if (encoder->pre_enable)
4456                         encoder->pre_enable(encoder);
4457
4458         if (intel_crtc->config->has_pch_encoder) {
4459                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4460                                                       true);
4461                 dev_priv->display.fdi_link_train(crtc);
4462         }
4463
4464         intel_ddi_enable_pipe_clock(intel_crtc);
4465
4466         if (IS_SKYLAKE(dev))
4467                 skylake_pfit_enable(intel_crtc);
4468         else
4469                 ironlake_pfit_enable(intel_crtc);
4470
4471         /*
4472          * On ILK+ LUT must be loaded before the pipe is running but with
4473          * clocks enabled
4474          */
4475         intel_crtc_load_lut(crtc);
4476
4477         intel_ddi_set_pipe_settings(crtc);
4478         intel_ddi_enable_transcoder_func(crtc);
4479
4480         intel_update_watermarks(crtc);
4481         intel_enable_pipe(intel_crtc);
4482
4483         if (intel_crtc->config->has_pch_encoder)
4484                 lpt_pch_enable(crtc);
4485
4486         if (intel_crtc->config->dp_encoder_is_mst)
4487                 intel_ddi_set_vc_payload_alloc(crtc, true);
4488
4489         assert_vblank_disabled(crtc);
4490         drm_crtc_vblank_on(crtc);
4491
4492         for_each_encoder_on_crtc(dev, crtc, encoder) {
4493                 encoder->enable(encoder);
4494                 intel_opregion_notify_encoder(encoder, true);
4495         }
4496
4497         /* If we change the relative order between pipe/planes enabling, we need
4498          * to change the workaround. */
4499         haswell_mode_set_planes_workaround(intel_crtc);
4500         intel_crtc_enable_planes(crtc);
4501 }
4502
4503 static void skylake_pfit_disable(struct intel_crtc *crtc)
4504 {
4505         struct drm_device *dev = crtc->base.dev;
4506         struct drm_i915_private *dev_priv = dev->dev_private;
4507         int pipe = crtc->pipe;
4508
4509         /* To avoid upsetting the power well on haswell only disable the pfit if
4510          * it's in use. The hw state code will make sure we get this right. */
4511         if (crtc->config->pch_pfit.enabled) {
4512                 I915_WRITE(PS_CTL(pipe), 0);
4513                 I915_WRITE(PS_WIN_POS(pipe), 0);
4514                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4515         }
4516 }
4517
4518 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4519 {
4520         struct drm_device *dev = crtc->base.dev;
4521         struct drm_i915_private *dev_priv = dev->dev_private;
4522         int pipe = crtc->pipe;
4523
4524         /* To avoid upsetting the power well on haswell only disable the pfit if
4525          * it's in use. The hw state code will make sure we get this right. */
4526         if (crtc->config->pch_pfit.enabled) {
4527                 I915_WRITE(PF_CTL(pipe), 0);
4528                 I915_WRITE(PF_WIN_POS(pipe), 0);
4529                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4530         }
4531 }
4532
4533 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4534 {
4535         struct drm_device *dev = crtc->dev;
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538         struct intel_encoder *encoder;
4539         int pipe = intel_crtc->pipe;
4540         u32 reg, temp;
4541
4542         if (!intel_crtc->active)
4543                 return;
4544
4545         intel_crtc_disable_planes(crtc);
4546
4547         for_each_encoder_on_crtc(dev, crtc, encoder)
4548                 encoder->disable(encoder);
4549
4550         drm_crtc_vblank_off(crtc);
4551         assert_vblank_disabled(crtc);
4552
4553         if (intel_crtc->config->has_pch_encoder)
4554                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4555
4556         intel_disable_pipe(intel_crtc);
4557
4558         ironlake_pfit_disable(intel_crtc);
4559
4560         for_each_encoder_on_crtc(dev, crtc, encoder)
4561                 if (encoder->post_disable)
4562                         encoder->post_disable(encoder);
4563
4564         if (intel_crtc->config->has_pch_encoder) {
4565                 ironlake_fdi_disable(crtc);
4566
4567                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4568
4569                 if (HAS_PCH_CPT(dev)) {
4570                         /* disable TRANS_DP_CTL */
4571                         reg = TRANS_DP_CTL(pipe);
4572                         temp = I915_READ(reg);
4573                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4574                                   TRANS_DP_PORT_SEL_MASK);
4575                         temp |= TRANS_DP_PORT_SEL_NONE;
4576                         I915_WRITE(reg, temp);
4577
4578                         /* disable DPLL_SEL */
4579                         temp = I915_READ(PCH_DPLL_SEL);
4580                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4581                         I915_WRITE(PCH_DPLL_SEL, temp);
4582                 }
4583
4584                 /* disable PCH DPLL */
4585                 intel_disable_shared_dpll(intel_crtc);
4586
4587                 ironlake_fdi_pll_disable(intel_crtc);
4588         }
4589
4590         intel_crtc->active = false;
4591         intel_update_watermarks(crtc);
4592
4593         mutex_lock(&dev->struct_mutex);
4594         intel_fbc_update(dev);
4595         mutex_unlock(&dev->struct_mutex);
4596 }
4597
4598 static void haswell_crtc_disable(struct drm_crtc *crtc)
4599 {
4600         struct drm_device *dev = crtc->dev;
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4603         struct intel_encoder *encoder;
4604         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4605
4606         if (!intel_crtc->active)
4607                 return;
4608
4609         intel_crtc_disable_planes(crtc);
4610
4611         for_each_encoder_on_crtc(dev, crtc, encoder) {
4612                 intel_opregion_notify_encoder(encoder, false);
4613                 encoder->disable(encoder);
4614         }
4615
4616         drm_crtc_vblank_off(crtc);
4617         assert_vblank_disabled(crtc);
4618
4619         if (intel_crtc->config->has_pch_encoder)
4620                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4621                                                       false);
4622         intel_disable_pipe(intel_crtc);
4623
4624         if (intel_crtc->config->dp_encoder_is_mst)
4625                 intel_ddi_set_vc_payload_alloc(crtc, false);
4626
4627         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4628
4629         if (IS_SKYLAKE(dev))
4630                 skylake_pfit_disable(intel_crtc);
4631         else
4632                 ironlake_pfit_disable(intel_crtc);
4633
4634         intel_ddi_disable_pipe_clock(intel_crtc);
4635
4636         if (intel_crtc->config->has_pch_encoder) {
4637                 lpt_disable_pch_transcoder(dev_priv);
4638                 intel_ddi_fdi_disable(crtc);
4639         }
4640
4641         for_each_encoder_on_crtc(dev, crtc, encoder)
4642                 if (encoder->post_disable)
4643                         encoder->post_disable(encoder);
4644
4645         intel_crtc->active = false;
4646         intel_update_watermarks(crtc);
4647
4648         mutex_lock(&dev->struct_mutex);
4649         intel_fbc_update(dev);
4650         mutex_unlock(&dev->struct_mutex);
4651
4652         if (intel_crtc_to_shared_dpll(intel_crtc))
4653                 intel_disable_shared_dpll(intel_crtc);
4654 }
4655
4656 static void ironlake_crtc_off(struct drm_crtc *crtc)
4657 {
4658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4659         intel_put_shared_dpll(intel_crtc);
4660 }
4661
4662
4663 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4664 {
4665         struct drm_device *dev = crtc->base.dev;
4666         struct drm_i915_private *dev_priv = dev->dev_private;
4667         struct intel_crtc_state *pipe_config = crtc->config;
4668
4669         if (!pipe_config->gmch_pfit.control)
4670                 return;
4671
4672         /*
4673          * The panel fitter should only be adjusted whilst the pipe is disabled,
4674          * according to register description and PRM.
4675          */
4676         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4677         assert_pipe_disabled(dev_priv, crtc->pipe);
4678
4679         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4680         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4681
4682         /* Border color in case we don't scale up to the full screen. Black by
4683          * default, change to something else for debugging. */
4684         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4685 }
4686
4687 static enum intel_display_power_domain port_to_power_domain(enum port port)
4688 {
4689         switch (port) {
4690         case PORT_A:
4691                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4692         case PORT_B:
4693                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4694         case PORT_C:
4695                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4696         case PORT_D:
4697                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4698         default:
4699                 WARN_ON_ONCE(1);
4700                 return POWER_DOMAIN_PORT_OTHER;
4701         }
4702 }
4703
4704 #define for_each_power_domain(domain, mask)                             \
4705         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4706                 if ((1 << (domain)) & (mask))
4707
4708 enum intel_display_power_domain
4709 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4710 {
4711         struct drm_device *dev = intel_encoder->base.dev;
4712         struct intel_digital_port *intel_dig_port;
4713
4714         switch (intel_encoder->type) {
4715         case INTEL_OUTPUT_UNKNOWN:
4716                 /* Only DDI platforms should ever use this output type */
4717                 WARN_ON_ONCE(!HAS_DDI(dev));
4718         case INTEL_OUTPUT_DISPLAYPORT:
4719         case INTEL_OUTPUT_HDMI:
4720         case INTEL_OUTPUT_EDP:
4721                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4722                 return port_to_power_domain(intel_dig_port->port);
4723         case INTEL_OUTPUT_DP_MST:
4724                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4725                 return port_to_power_domain(intel_dig_port->port);
4726         case INTEL_OUTPUT_ANALOG:
4727                 return POWER_DOMAIN_PORT_CRT;
4728         case INTEL_OUTPUT_DSI:
4729                 return POWER_DOMAIN_PORT_DSI;
4730         default:
4731                 return POWER_DOMAIN_PORT_OTHER;
4732         }
4733 }
4734
4735 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4736 {
4737         struct drm_device *dev = crtc->dev;
4738         struct intel_encoder *intel_encoder;
4739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740         enum pipe pipe = intel_crtc->pipe;
4741         unsigned long mask;
4742         enum transcoder transcoder;
4743
4744         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4745
4746         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4747         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4748         if (intel_crtc->config->pch_pfit.enabled ||
4749             intel_crtc->config->pch_pfit.force_thru)
4750                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4751
4752         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4753                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4754
4755         return mask;
4756 }
4757
4758 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4759 {
4760         struct drm_i915_private *dev_priv = dev->dev_private;
4761         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4762         struct intel_crtc *crtc;
4763
4764         /*
4765          * First get all needed power domains, then put all unneeded, to avoid
4766          * any unnecessary toggling of the power wells.
4767          */
4768         for_each_intel_crtc(dev, crtc) {
4769                 enum intel_display_power_domain domain;
4770
4771                 if (!crtc->base.enabled)
4772                         continue;
4773
4774                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4775
4776                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4777                         intel_display_power_get(dev_priv, domain);
4778         }
4779
4780         if (dev_priv->display.modeset_global_resources)
4781                 dev_priv->display.modeset_global_resources(dev);
4782
4783         for_each_intel_crtc(dev, crtc) {
4784                 enum intel_display_power_domain domain;
4785
4786                 for_each_power_domain(domain, crtc->enabled_power_domains)
4787                         intel_display_power_put(dev_priv, domain);
4788
4789                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4790         }
4791
4792         intel_display_set_init_power(dev_priv, false);
4793 }
4794
4795 /* returns HPLL frequency in kHz */
4796 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4797 {
4798         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4799
4800         /* Obtain SKU information */
4801         mutex_lock(&dev_priv->dpio_lock);
4802         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4803                 CCK_FUSE_HPLL_FREQ_MASK;
4804         mutex_unlock(&dev_priv->dpio_lock);
4805
4806         return vco_freq[hpll_freq] * 1000;
4807 }
4808
4809 static void vlv_update_cdclk(struct drm_device *dev)
4810 {
4811         struct drm_i915_private *dev_priv = dev->dev_private;
4812
4813         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4814         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4815                          dev_priv->vlv_cdclk_freq);
4816
4817         /*
4818          * Program the gmbus_freq based on the cdclk frequency.
4819          * BSpec erroneously claims we should aim for 4MHz, but
4820          * in fact 1MHz is the correct frequency.
4821          */
4822         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4823 }
4824
4825 /* Adjust CDclk dividers to allow high res or save power if possible */
4826 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4827 {
4828         struct drm_i915_private *dev_priv = dev->dev_private;
4829         u32 val, cmd;
4830
4831         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4832
4833         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4834                 cmd = 2;
4835         else if (cdclk == 266667)
4836                 cmd = 1;
4837         else
4838                 cmd = 0;
4839
4840         mutex_lock(&dev_priv->rps.hw_lock);
4841         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4842         val &= ~DSPFREQGUAR_MASK;
4843         val |= (cmd << DSPFREQGUAR_SHIFT);
4844         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4845         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4846                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4847                      50)) {
4848                 DRM_ERROR("timed out waiting for CDclk change\n");
4849         }
4850         mutex_unlock(&dev_priv->rps.hw_lock);
4851
4852         if (cdclk == 400000) {
4853                 u32 divider;
4854
4855                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4856
4857                 mutex_lock(&dev_priv->dpio_lock);
4858                 /* adjust cdclk divider */
4859                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4860                 val &= ~DISPLAY_FREQUENCY_VALUES;
4861                 val |= divider;
4862                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4863
4864                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4865                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4866                              50))
4867                         DRM_ERROR("timed out waiting for CDclk change\n");
4868                 mutex_unlock(&dev_priv->dpio_lock);
4869         }
4870
4871         mutex_lock(&dev_priv->dpio_lock);
4872         /* adjust self-refresh exit latency value */
4873         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4874         val &= ~0x7f;
4875
4876         /*
4877          * For high bandwidth configs, we set a higher latency in the bunit
4878          * so that the core display fetch happens in time to avoid underruns.
4879          */
4880         if (cdclk == 400000)
4881                 val |= 4500 / 250; /* 4.5 usec */
4882         else
4883                 val |= 3000 / 250; /* 3.0 usec */
4884         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4885         mutex_unlock(&dev_priv->dpio_lock);
4886
4887         vlv_update_cdclk(dev);
4888 }
4889
4890 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4891 {
4892         struct drm_i915_private *dev_priv = dev->dev_private;
4893         u32 val, cmd;
4894
4895         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4896
4897         switch (cdclk) {
4898         case 400000:
4899                 cmd = 3;
4900                 break;
4901         case 333333:
4902         case 320000:
4903                 cmd = 2;
4904                 break;
4905         case 266667:
4906                 cmd = 1;
4907                 break;
4908         case 200000:
4909                 cmd = 0;
4910                 break;
4911         default:
4912                 MISSING_CASE(cdclk);
4913                 return;
4914         }
4915
4916         mutex_lock(&dev_priv->rps.hw_lock);
4917         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4918         val &= ~DSPFREQGUAR_MASK_CHV;
4919         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4920         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4921         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4922                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4923                      50)) {
4924                 DRM_ERROR("timed out waiting for CDclk change\n");
4925         }
4926         mutex_unlock(&dev_priv->rps.hw_lock);
4927
4928         vlv_update_cdclk(dev);
4929 }
4930
4931 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4932                                  int max_pixclk)
4933 {
4934         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4935
4936         /* FIXME: Punit isn't quite ready yet */
4937         if (IS_CHERRYVIEW(dev_priv->dev))
4938                 return 400000;
4939
4940         /*
4941          * Really only a few cases to deal with, as only 4 CDclks are supported:
4942          *   200MHz
4943          *   267MHz
4944          *   320/333MHz (depends on HPLL freq)
4945          *   400MHz
4946          * So we check to see whether we're above 90% of the lower bin and
4947          * adjust if needed.
4948          *
4949          * We seem to get an unstable or solid color picture at 200MHz.
4950          * Not sure what's wrong. For now use 200MHz only when all pipes
4951          * are off.
4952          */
4953         if (max_pixclk > freq_320*9/10)
4954                 return 400000;
4955         else if (max_pixclk > 266667*9/10)
4956                 return freq_320;
4957         else if (max_pixclk > 0)
4958                 return 266667;
4959         else
4960                 return 200000;
4961 }
4962
4963 /* compute the max pixel clock for new configuration */
4964 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4965 {
4966         struct drm_device *dev = dev_priv->dev;
4967         struct intel_crtc *intel_crtc;
4968         int max_pixclk = 0;
4969
4970         for_each_intel_crtc(dev, intel_crtc) {
4971                 if (intel_crtc->new_enabled)
4972                         max_pixclk = max(max_pixclk,
4973                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4974         }
4975
4976         return max_pixclk;
4977 }
4978
4979 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4980                                             unsigned *prepare_pipes)
4981 {
4982         struct drm_i915_private *dev_priv = dev->dev_private;
4983         struct intel_crtc *intel_crtc;
4984         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4985
4986         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4987             dev_priv->vlv_cdclk_freq)
4988                 return;
4989
4990         /* disable/enable all currently active pipes while we change cdclk */
4991         for_each_intel_crtc(dev, intel_crtc)
4992                 if (intel_crtc->base.enabled)
4993                         *prepare_pipes |= (1 << intel_crtc->pipe);
4994 }
4995
4996 static void valleyview_modeset_global_resources(struct drm_device *dev)
4997 {
4998         struct drm_i915_private *dev_priv = dev->dev_private;
4999         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5000         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5001
5002         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5003                 /*
5004                  * FIXME: We can end up here with all power domains off, yet
5005                  * with a CDCLK frequency other than the minimum. To account
5006                  * for this take the PIPE-A power domain, which covers the HW
5007                  * blocks needed for the following programming. This can be
5008                  * removed once it's guaranteed that we get here either with
5009                  * the minimum CDCLK set, or the required power domains
5010                  * enabled.
5011                  */
5012                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5013
5014                 if (IS_CHERRYVIEW(dev))
5015                         cherryview_set_cdclk(dev, req_cdclk);
5016                 else
5017                         valleyview_set_cdclk(dev, req_cdclk);
5018
5019                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5020         }
5021 }
5022
5023 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5024 {
5025         struct drm_device *dev = crtc->dev;
5026         struct drm_i915_private *dev_priv = to_i915(dev);
5027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028         struct intel_encoder *encoder;
5029         int pipe = intel_crtc->pipe;
5030         bool is_dsi;
5031
5032         WARN_ON(!crtc->enabled);
5033
5034         if (intel_crtc->active)
5035                 return;
5036
5037         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5038
5039         if (!is_dsi) {
5040                 if (IS_CHERRYVIEW(dev))
5041                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5042                 else
5043                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5044         }
5045
5046         if (intel_crtc->config->has_dp_encoder)
5047                 intel_dp_set_m_n(intel_crtc);
5048
5049         intel_set_pipe_timings(intel_crtc);
5050
5051         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5052                 struct drm_i915_private *dev_priv = dev->dev_private;
5053
5054                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5055                 I915_WRITE(CHV_CANVAS(pipe), 0);
5056         }
5057
5058         i9xx_set_pipeconf(intel_crtc);
5059
5060         intel_crtc->active = true;
5061
5062         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5063
5064         for_each_encoder_on_crtc(dev, crtc, encoder)
5065                 if (encoder->pre_pll_enable)
5066                         encoder->pre_pll_enable(encoder);
5067
5068         if (!is_dsi) {
5069                 if (IS_CHERRYVIEW(dev))
5070                         chv_enable_pll(intel_crtc, intel_crtc->config);
5071                 else
5072                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5073         }
5074
5075         for_each_encoder_on_crtc(dev, crtc, encoder)
5076                 if (encoder->pre_enable)
5077                         encoder->pre_enable(encoder);
5078
5079         i9xx_pfit_enable(intel_crtc);
5080
5081         intel_crtc_load_lut(crtc);
5082
5083         intel_update_watermarks(crtc);
5084         intel_enable_pipe(intel_crtc);
5085
5086         assert_vblank_disabled(crtc);
5087         drm_crtc_vblank_on(crtc);
5088
5089         for_each_encoder_on_crtc(dev, crtc, encoder)
5090                 encoder->enable(encoder);
5091
5092         intel_crtc_enable_planes(crtc);
5093
5094         /* Underruns don't raise interrupts, so check manually. */
5095         i9xx_check_fifo_underruns(dev_priv);
5096 }
5097
5098 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5099 {
5100         struct drm_device *dev = crtc->base.dev;
5101         struct drm_i915_private *dev_priv = dev->dev_private;
5102
5103         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5104         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5105 }
5106
5107 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5108 {
5109         struct drm_device *dev = crtc->dev;
5110         struct drm_i915_private *dev_priv = to_i915(dev);
5111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5112         struct intel_encoder *encoder;
5113         int pipe = intel_crtc->pipe;
5114
5115         WARN_ON(!crtc->enabled);
5116
5117         if (intel_crtc->active)
5118                 return;
5119
5120         i9xx_set_pll_dividers(intel_crtc);
5121
5122         if (intel_crtc->config->has_dp_encoder)
5123                 intel_dp_set_m_n(intel_crtc);
5124
5125         intel_set_pipe_timings(intel_crtc);
5126
5127         i9xx_set_pipeconf(intel_crtc);
5128
5129         intel_crtc->active = true;
5130
5131         if (!IS_GEN2(dev))
5132                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5133
5134         for_each_encoder_on_crtc(dev, crtc, encoder)
5135                 if (encoder->pre_enable)
5136                         encoder->pre_enable(encoder);
5137
5138         i9xx_enable_pll(intel_crtc);
5139
5140         i9xx_pfit_enable(intel_crtc);
5141
5142         intel_crtc_load_lut(crtc);
5143
5144         intel_update_watermarks(crtc);
5145         intel_enable_pipe(intel_crtc);
5146
5147         assert_vblank_disabled(crtc);
5148         drm_crtc_vblank_on(crtc);
5149
5150         for_each_encoder_on_crtc(dev, crtc, encoder)
5151                 encoder->enable(encoder);
5152
5153         intel_crtc_enable_planes(crtc);
5154
5155         /*
5156          * Gen2 reports pipe underruns whenever all planes are disabled.
5157          * So don't enable underrun reporting before at least some planes
5158          * are enabled.
5159          * FIXME: Need to fix the logic to work when we turn off all planes
5160          * but leave the pipe running.
5161          */
5162         if (IS_GEN2(dev))
5163                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5164
5165         /* Underruns don't raise interrupts, so check manually. */
5166         i9xx_check_fifo_underruns(dev_priv);
5167 }
5168
5169 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5170 {
5171         struct drm_device *dev = crtc->base.dev;
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173
5174         if (!crtc->config->gmch_pfit.control)
5175                 return;
5176
5177         assert_pipe_disabled(dev_priv, crtc->pipe);
5178
5179         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5180                          I915_READ(PFIT_CONTROL));
5181         I915_WRITE(PFIT_CONTROL, 0);
5182 }
5183
5184 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5185 {
5186         struct drm_device *dev = crtc->dev;
5187         struct drm_i915_private *dev_priv = dev->dev_private;
5188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5189         struct intel_encoder *encoder;
5190         int pipe = intel_crtc->pipe;
5191
5192         if (!intel_crtc->active)
5193                 return;
5194
5195         /*
5196          * Gen2 reports pipe underruns whenever all planes are disabled.
5197          * So diasble underrun reporting before all the planes get disabled.
5198          * FIXME: Need to fix the logic to work when we turn off all planes
5199          * but leave the pipe running.
5200          */
5201         if (IS_GEN2(dev))
5202                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5203
5204         /*
5205          * Vblank time updates from the shadow to live plane control register
5206          * are blocked if the memory self-refresh mode is active at that
5207          * moment. So to make sure the plane gets truly disabled, disable
5208          * first the self-refresh mode. The self-refresh enable bit in turn
5209          * will be checked/applied by the HW only at the next frame start
5210          * event which is after the vblank start event, so we need to have a
5211          * wait-for-vblank between disabling the plane and the pipe.
5212          */
5213         intel_set_memory_cxsr(dev_priv, false);
5214         intel_crtc_disable_planes(crtc);
5215
5216         /*
5217          * On gen2 planes are double buffered but the pipe isn't, so we must
5218          * wait for planes to fully turn off before disabling the pipe.
5219          * We also need to wait on all gmch platforms because of the
5220          * self-refresh mode constraint explained above.
5221          */
5222         intel_wait_for_vblank(dev, pipe);
5223
5224         for_each_encoder_on_crtc(dev, crtc, encoder)
5225                 encoder->disable(encoder);
5226
5227         drm_crtc_vblank_off(crtc);
5228         assert_vblank_disabled(crtc);
5229
5230         intel_disable_pipe(intel_crtc);
5231
5232         i9xx_pfit_disable(intel_crtc);
5233
5234         for_each_encoder_on_crtc(dev, crtc, encoder)
5235                 if (encoder->post_disable)
5236                         encoder->post_disable(encoder);
5237
5238         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5239                 if (IS_CHERRYVIEW(dev))
5240                         chv_disable_pll(dev_priv, pipe);
5241                 else if (IS_VALLEYVIEW(dev))
5242                         vlv_disable_pll(dev_priv, pipe);
5243                 else
5244                         i9xx_disable_pll(intel_crtc);
5245         }
5246
5247         if (!IS_GEN2(dev))
5248                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5249
5250         intel_crtc->active = false;
5251         intel_update_watermarks(crtc);
5252
5253         mutex_lock(&dev->struct_mutex);
5254         intel_fbc_update(dev);
5255         mutex_unlock(&dev->struct_mutex);
5256 }
5257
5258 static void i9xx_crtc_off(struct drm_crtc *crtc)
5259 {
5260 }
5261
5262 /* Master function to enable/disable CRTC and corresponding power wells */
5263 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5264 {
5265         struct drm_device *dev = crtc->dev;
5266         struct drm_i915_private *dev_priv = dev->dev_private;
5267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268         enum intel_display_power_domain domain;
5269         unsigned long domains;
5270
5271         if (enable) {
5272                 if (!intel_crtc->active) {
5273                         domains = get_crtc_power_domains(crtc);
5274                         for_each_power_domain(domain, domains)
5275                                 intel_display_power_get(dev_priv, domain);
5276                         intel_crtc->enabled_power_domains = domains;
5277
5278                         dev_priv->display.crtc_enable(crtc);
5279                 }
5280         } else {
5281                 if (intel_crtc->active) {
5282                         dev_priv->display.crtc_disable(crtc);
5283
5284                         domains = intel_crtc->enabled_power_domains;
5285                         for_each_power_domain(domain, domains)
5286                                 intel_display_power_put(dev_priv, domain);
5287                         intel_crtc->enabled_power_domains = 0;
5288                 }
5289         }
5290 }
5291
5292 /**
5293  * Sets the power management mode of the pipe and plane.
5294  */
5295 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5296 {
5297         struct drm_device *dev = crtc->dev;
5298         struct intel_encoder *intel_encoder;
5299         bool enable = false;
5300
5301         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5302                 enable |= intel_encoder->connectors_active;
5303
5304         intel_crtc_control(crtc, enable);
5305 }
5306
5307 static void intel_crtc_disable(struct drm_crtc *crtc)
5308 {
5309         struct drm_device *dev = crtc->dev;
5310         struct drm_connector *connector;
5311         struct drm_i915_private *dev_priv = dev->dev_private;
5312
5313         /* crtc should still be enabled when we disable it. */
5314         WARN_ON(!crtc->enabled);
5315
5316         dev_priv->display.crtc_disable(crtc);
5317         dev_priv->display.off(crtc);
5318
5319         crtc->primary->funcs->disable_plane(crtc->primary);
5320
5321         /* Update computed state. */
5322         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5323                 if (!connector->encoder || !connector->encoder->crtc)
5324                         continue;
5325
5326                 if (connector->encoder->crtc != crtc)
5327                         continue;
5328
5329                 connector->dpms = DRM_MODE_DPMS_OFF;
5330                 to_intel_encoder(connector->encoder)->connectors_active = false;
5331         }
5332 }
5333
5334 void intel_encoder_destroy(struct drm_encoder *encoder)
5335 {
5336         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5337
5338         drm_encoder_cleanup(encoder);
5339         kfree(intel_encoder);
5340 }
5341
5342 /* Simple dpms helper for encoders with just one connector, no cloning and only
5343  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5344  * state of the entire output pipe. */
5345 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5346 {
5347         if (mode == DRM_MODE_DPMS_ON) {
5348                 encoder->connectors_active = true;
5349
5350                 intel_crtc_update_dpms(encoder->base.crtc);
5351         } else {
5352                 encoder->connectors_active = false;
5353
5354                 intel_crtc_update_dpms(encoder->base.crtc);
5355         }
5356 }
5357
5358 /* Cross check the actual hw state with our own modeset state tracking (and it's
5359  * internal consistency). */
5360 static void intel_connector_check_state(struct intel_connector *connector)
5361 {
5362         if (connector->get_hw_state(connector)) {
5363                 struct intel_encoder *encoder = connector->encoder;
5364                 struct drm_crtc *crtc;
5365                 bool encoder_enabled;
5366                 enum pipe pipe;
5367
5368                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5369                               connector->base.base.id,
5370                               connector->base.name);
5371
5372                 /* there is no real hw state for MST connectors */
5373                 if (connector->mst_port)
5374                         return;
5375
5376                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5377                      "wrong connector dpms state\n");
5378                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5379                      "active connector not linked to encoder\n");
5380
5381                 if (encoder) {
5382                         I915_STATE_WARN(!encoder->connectors_active,
5383                              "encoder->connectors_active not set\n");
5384
5385                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5386                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5387                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5388                                 return;
5389
5390                         crtc = encoder->base.crtc;
5391
5392                         I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5393                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5394                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5395                              "encoder active on the wrong pipe\n");
5396                 }
5397         }
5398 }
5399
5400 /* Even simpler default implementation, if there's really no special case to
5401  * consider. */
5402 void intel_connector_dpms(struct drm_connector *connector, int mode)
5403 {
5404         /* All the simple cases only support two dpms states. */
5405         if (mode != DRM_MODE_DPMS_ON)
5406                 mode = DRM_MODE_DPMS_OFF;
5407
5408         if (mode == connector->dpms)
5409                 return;
5410
5411         connector->dpms = mode;
5412
5413         /* Only need to change hw state when actually enabled */
5414         if (connector->encoder)
5415                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5416
5417         intel_modeset_check_state(connector->dev);
5418 }
5419
5420 /* Simple connector->get_hw_state implementation for encoders that support only
5421  * one connector and no cloning and hence the encoder state determines the state
5422  * of the connector. */
5423 bool intel_connector_get_hw_state(struct intel_connector *connector)
5424 {
5425         enum pipe pipe = 0;
5426         struct intel_encoder *encoder = connector->encoder;
5427
5428         return encoder->get_hw_state(encoder, &pipe);
5429 }
5430
5431 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5432                                      struct intel_crtc_state *pipe_config)
5433 {
5434         struct drm_i915_private *dev_priv = dev->dev_private;
5435         struct intel_crtc *pipe_B_crtc =
5436                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5437
5438         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5439                       pipe_name(pipe), pipe_config->fdi_lanes);
5440         if (pipe_config->fdi_lanes > 4) {
5441                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5442                               pipe_name(pipe), pipe_config->fdi_lanes);
5443                 return false;
5444         }
5445
5446         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5447                 if (pipe_config->fdi_lanes > 2) {
5448                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5449                                       pipe_config->fdi_lanes);
5450                         return false;
5451                 } else {
5452                         return true;
5453                 }
5454         }
5455
5456         if (INTEL_INFO(dev)->num_pipes == 2)
5457                 return true;
5458
5459         /* Ivybridge 3 pipe is really complicated */
5460         switch (pipe) {
5461         case PIPE_A:
5462                 return true;
5463         case PIPE_B:
5464                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5465                     pipe_config->fdi_lanes > 2) {
5466                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5467                                       pipe_name(pipe), pipe_config->fdi_lanes);
5468                         return false;
5469                 }
5470                 return true;
5471         case PIPE_C:
5472                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5473                     pipe_B_crtc->config->fdi_lanes <= 2) {
5474                         if (pipe_config->fdi_lanes > 2) {
5475                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5476                                               pipe_name(pipe), pipe_config->fdi_lanes);
5477                                 return false;
5478                         }
5479                 } else {
5480                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5481                         return false;
5482                 }
5483                 return true;
5484         default:
5485                 BUG();
5486         }
5487 }
5488
5489 #define RETRY 1
5490 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5491                                        struct intel_crtc_state *pipe_config)
5492 {
5493         struct drm_device *dev = intel_crtc->base.dev;
5494         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5495         int lane, link_bw, fdi_dotclock;
5496         bool setup_ok, needs_recompute = false;
5497
5498 retry:
5499         /* FDI is a binary signal running at ~2.7GHz, encoding
5500          * each output octet as 10 bits. The actual frequency
5501          * is stored as a divider into a 100MHz clock, and the
5502          * mode pixel clock is stored in units of 1KHz.
5503          * Hence the bw of each lane in terms of the mode signal
5504          * is:
5505          */
5506         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5507
5508         fdi_dotclock = adjusted_mode->crtc_clock;
5509
5510         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5511                                            pipe_config->pipe_bpp);
5512
5513         pipe_config->fdi_lanes = lane;
5514
5515         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5516                                link_bw, &pipe_config->fdi_m_n);
5517
5518         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5519                                             intel_crtc->pipe, pipe_config);
5520         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5521                 pipe_config->pipe_bpp -= 2*3;
5522                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5523                               pipe_config->pipe_bpp);
5524                 needs_recompute = true;
5525                 pipe_config->bw_constrained = true;
5526
5527                 goto retry;
5528         }
5529
5530         if (needs_recompute)
5531                 return RETRY;
5532
5533         return setup_ok ? 0 : -EINVAL;
5534 }
5535
5536 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5537                                    struct intel_crtc_state *pipe_config)
5538 {
5539         pipe_config->ips_enabled = i915.enable_ips &&
5540                                    hsw_crtc_supports_ips(crtc) &&
5541                                    pipe_config->pipe_bpp <= 24;
5542 }
5543
5544 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5545                                      struct intel_crtc_state *pipe_config)
5546 {
5547         struct drm_device *dev = crtc->base.dev;
5548         struct drm_i915_private *dev_priv = dev->dev_private;
5549         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5550
5551         /* FIXME should check pixel clock limits on all platforms */
5552         if (INTEL_INFO(dev)->gen < 4) {
5553                 int clock_limit =
5554                         dev_priv->display.get_display_clock_speed(dev);
5555
5556                 /*
5557                  * Enable pixel doubling when the dot clock
5558                  * is > 90% of the (display) core speed.
5559                  *
5560                  * GDG double wide on either pipe,
5561                  * otherwise pipe A only.
5562                  */
5563                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5564                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5565                         clock_limit *= 2;
5566                         pipe_config->double_wide = true;
5567                 }
5568
5569                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5570                         return -EINVAL;
5571         }
5572
5573         /*
5574          * Pipe horizontal size must be even in:
5575          * - DVO ganged mode
5576          * - LVDS dual channel mode
5577          * - Double wide pipe
5578          */
5579         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5580              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5581                 pipe_config->pipe_src_w &= ~1;
5582
5583         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5584          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5585          */
5586         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5587                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5588                 return -EINVAL;
5589
5590         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5591                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5592         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5593                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5594                  * for lvds. */
5595                 pipe_config->pipe_bpp = 8*3;
5596         }
5597
5598         if (HAS_IPS(dev))
5599                 hsw_compute_ips_config(crtc, pipe_config);
5600
5601         if (pipe_config->has_pch_encoder)
5602                 return ironlake_fdi_compute_config(crtc, pipe_config);
5603
5604         return 0;
5605 }
5606
5607 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5608 {
5609         struct drm_i915_private *dev_priv = dev->dev_private;
5610         u32 val;
5611         int divider;
5612
5613         /* FIXME: Punit isn't quite ready yet */
5614         if (IS_CHERRYVIEW(dev))
5615                 return 400000;
5616
5617         if (dev_priv->hpll_freq == 0)
5618                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5619
5620         mutex_lock(&dev_priv->dpio_lock);
5621         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5622         mutex_unlock(&dev_priv->dpio_lock);
5623
5624         divider = val & DISPLAY_FREQUENCY_VALUES;
5625
5626         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5627              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5628              "cdclk change in progress\n");
5629
5630         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5631 }
5632
5633 static int i945_get_display_clock_speed(struct drm_device *dev)
5634 {
5635         return 400000;
5636 }
5637
5638 static int i915_get_display_clock_speed(struct drm_device *dev)
5639 {
5640         return 333000;
5641 }
5642
5643 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5644 {
5645         return 200000;
5646 }
5647
5648 static int pnv_get_display_clock_speed(struct drm_device *dev)
5649 {
5650         u16 gcfgc = 0;
5651
5652         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5653
5654         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5655         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5656                 return 267000;
5657         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5658                 return 333000;
5659         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5660                 return 444000;
5661         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5662                 return 200000;
5663         default:
5664                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5665         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5666                 return 133000;
5667         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5668                 return 167000;
5669         }
5670 }
5671
5672 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5673 {
5674         u16 gcfgc = 0;
5675
5676         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5677
5678         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5679                 return 133000;
5680         else {
5681                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5682                 case GC_DISPLAY_CLOCK_333_MHZ:
5683                         return 333000;
5684                 default:
5685                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5686                         return 190000;
5687                 }
5688         }
5689 }
5690
5691 static int i865_get_display_clock_speed(struct drm_device *dev)
5692 {
5693         return 266000;
5694 }
5695
5696 static int i855_get_display_clock_speed(struct drm_device *dev)
5697 {
5698         u16 hpllcc = 0;
5699         /* Assume that the hardware is in the high speed state.  This
5700          * should be the default.
5701          */
5702         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5703         case GC_CLOCK_133_200:
5704         case GC_CLOCK_100_200:
5705                 return 200000;
5706         case GC_CLOCK_166_250:
5707                 return 250000;
5708         case GC_CLOCK_100_133:
5709                 return 133000;
5710         }
5711
5712         /* Shouldn't happen */
5713         return 0;
5714 }
5715
5716 static int i830_get_display_clock_speed(struct drm_device *dev)
5717 {
5718         return 133000;
5719 }
5720
5721 static void
5722 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5723 {
5724         while (*num > DATA_LINK_M_N_MASK ||
5725                *den > DATA_LINK_M_N_MASK) {
5726                 *num >>= 1;
5727                 *den >>= 1;
5728         }
5729 }
5730
5731 static void compute_m_n(unsigned int m, unsigned int n,
5732                         uint32_t *ret_m, uint32_t *ret_n)
5733 {
5734         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5735         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5736         intel_reduce_m_n_ratio(ret_m, ret_n);
5737 }
5738
5739 void
5740 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5741                        int pixel_clock, int link_clock,
5742                        struct intel_link_m_n *m_n)
5743 {
5744         m_n->tu = 64;
5745
5746         compute_m_n(bits_per_pixel * pixel_clock,
5747                     link_clock * nlanes * 8,
5748                     &m_n->gmch_m, &m_n->gmch_n);
5749
5750         compute_m_n(pixel_clock, link_clock,
5751                     &m_n->link_m, &m_n->link_n);
5752 }
5753
5754 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5755 {
5756         if (i915.panel_use_ssc >= 0)
5757                 return i915.panel_use_ssc != 0;
5758         return dev_priv->vbt.lvds_use_ssc
5759                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5760 }
5761
5762 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5763 {
5764         struct drm_device *dev = crtc->base.dev;
5765         struct drm_i915_private *dev_priv = dev->dev_private;
5766         int refclk;
5767
5768         if (IS_VALLEYVIEW(dev)) {
5769                 refclk = 100000;
5770         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5771             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5772                 refclk = dev_priv->vbt.lvds_ssc_freq;
5773                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5774         } else if (!IS_GEN2(dev)) {
5775                 refclk = 96000;
5776         } else {
5777                 refclk = 48000;
5778         }
5779
5780         return refclk;
5781 }
5782
5783 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5784 {
5785         return (1 << dpll->n) << 16 | dpll->m2;
5786 }
5787
5788 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5789 {
5790         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5791 }
5792
5793 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5794                                      struct intel_crtc_state *crtc_state,
5795                                      intel_clock_t *reduced_clock)
5796 {
5797         struct drm_device *dev = crtc->base.dev;
5798         u32 fp, fp2 = 0;
5799
5800         if (IS_PINEVIEW(dev)) {
5801                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5802                 if (reduced_clock)
5803                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5804         } else {
5805                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5806                 if (reduced_clock)
5807                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5808         }
5809
5810         crtc_state->dpll_hw_state.fp0 = fp;
5811
5812         crtc->lowfreq_avail = false;
5813         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5814             reduced_clock && i915.powersave) {
5815                 crtc_state->dpll_hw_state.fp1 = fp2;
5816                 crtc->lowfreq_avail = true;
5817         } else {
5818                 crtc_state->dpll_hw_state.fp1 = fp;
5819         }
5820 }
5821
5822 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5823                 pipe)
5824 {
5825         u32 reg_val;
5826
5827         /*
5828          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5829          * and set it to a reasonable value instead.
5830          */
5831         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5832         reg_val &= 0xffffff00;
5833         reg_val |= 0x00000030;
5834         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5835
5836         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5837         reg_val &= 0x8cffffff;
5838         reg_val = 0x8c000000;
5839         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5840
5841         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5842         reg_val &= 0xffffff00;
5843         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5844
5845         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5846         reg_val &= 0x00ffffff;
5847         reg_val |= 0xb0000000;
5848         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5849 }
5850
5851 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5852                                          struct intel_link_m_n *m_n)
5853 {
5854         struct drm_device *dev = crtc->base.dev;
5855         struct drm_i915_private *dev_priv = dev->dev_private;
5856         int pipe = crtc->pipe;
5857
5858         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5859         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5860         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5861         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5862 }
5863
5864 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5865                                          struct intel_link_m_n *m_n,
5866                                          struct intel_link_m_n *m2_n2)
5867 {
5868         struct drm_device *dev = crtc->base.dev;
5869         struct drm_i915_private *dev_priv = dev->dev_private;
5870         int pipe = crtc->pipe;
5871         enum transcoder transcoder = crtc->config->cpu_transcoder;
5872
5873         if (INTEL_INFO(dev)->gen >= 5) {
5874                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5875                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5876                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5877                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5878                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5879                  * for gen < 8) and if DRRS is supported (to make sure the
5880                  * registers are not unnecessarily accessed).
5881                  */
5882                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5883                         crtc->config->has_drrs) {
5884                         I915_WRITE(PIPE_DATA_M2(transcoder),
5885                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5886                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5887                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5888                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5889                 }
5890         } else {
5891                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5892                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5893                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5894                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5895         }
5896 }
5897
5898 void intel_dp_set_m_n(struct intel_crtc *crtc)
5899 {
5900         if (crtc->config->has_pch_encoder)
5901                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5902         else
5903                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5904                                                    &crtc->config->dp_m2_n2);
5905 }
5906
5907 static void vlv_update_pll(struct intel_crtc *crtc,
5908                            struct intel_crtc_state *pipe_config)
5909 {
5910         u32 dpll, dpll_md;
5911
5912         /*
5913          * Enable DPIO clock input. We should never disable the reference
5914          * clock for pipe B, since VGA hotplug / manual detection depends
5915          * on it.
5916          */
5917         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5918                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5919         /* We should never disable this, set it here for state tracking */
5920         if (crtc->pipe == PIPE_B)
5921                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5922         dpll |= DPLL_VCO_ENABLE;
5923         pipe_config->dpll_hw_state.dpll = dpll;
5924
5925         dpll_md = (pipe_config->pixel_multiplier - 1)
5926                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5927         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5928 }
5929
5930 static void vlv_prepare_pll(struct intel_crtc *crtc,
5931                             const struct intel_crtc_state *pipe_config)
5932 {
5933         struct drm_device *dev = crtc->base.dev;
5934         struct drm_i915_private *dev_priv = dev->dev_private;
5935         int pipe = crtc->pipe;
5936         u32 mdiv;
5937         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5938         u32 coreclk, reg_val;
5939
5940         mutex_lock(&dev_priv->dpio_lock);
5941
5942         bestn = pipe_config->dpll.n;
5943         bestm1 = pipe_config->dpll.m1;
5944         bestm2 = pipe_config->dpll.m2;
5945         bestp1 = pipe_config->dpll.p1;
5946         bestp2 = pipe_config->dpll.p2;
5947
5948         /* See eDP HDMI DPIO driver vbios notes doc */
5949
5950         /* PLL B needs special handling */
5951         if (pipe == PIPE_B)
5952                 vlv_pllb_recal_opamp(dev_priv, pipe);
5953
5954         /* Set up Tx target for periodic Rcomp update */
5955         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5956
5957         /* Disable target IRef on PLL */
5958         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5959         reg_val &= 0x00ffffff;
5960         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5961
5962         /* Disable fast lock */
5963         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5964
5965         /* Set idtafcrecal before PLL is enabled */
5966         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5967         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5968         mdiv |= ((bestn << DPIO_N_SHIFT));
5969         mdiv |= (1 << DPIO_K_SHIFT);
5970
5971         /*
5972          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5973          * but we don't support that).
5974          * Note: don't use the DAC post divider as it seems unstable.
5975          */
5976         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5977         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5978
5979         mdiv |= DPIO_ENABLE_CALIBRATION;
5980         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5981
5982         /* Set HBR and RBR LPF coefficients */
5983         if (pipe_config->port_clock == 162000 ||
5984             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5985             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5986                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5987                                  0x009f0003);
5988         else
5989                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5990                                  0x00d0000f);
5991
5992         if (pipe_config->has_dp_encoder) {
5993                 /* Use SSC source */
5994                 if (pipe == PIPE_A)
5995                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5996                                          0x0df40000);
5997                 else
5998                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5999                                          0x0df70000);
6000         } else { /* HDMI or VGA */
6001                 /* Use bend source */
6002                 if (pipe == PIPE_A)
6003                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6004                                          0x0df70000);
6005                 else
6006                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6007                                          0x0df40000);
6008         }
6009
6010         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6011         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6012         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6013             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6014                 coreclk |= 0x01000000;
6015         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6016
6017         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6018         mutex_unlock(&dev_priv->dpio_lock);
6019 }
6020
6021 static void chv_update_pll(struct intel_crtc *crtc,
6022                            struct intel_crtc_state *pipe_config)
6023 {
6024         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6025                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6026                 DPLL_VCO_ENABLE;
6027         if (crtc->pipe != PIPE_A)
6028                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6029
6030         pipe_config->dpll_hw_state.dpll_md =
6031                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6032 }
6033
6034 static void chv_prepare_pll(struct intel_crtc *crtc,
6035                             const struct intel_crtc_state *pipe_config)
6036 {
6037         struct drm_device *dev = crtc->base.dev;
6038         struct drm_i915_private *dev_priv = dev->dev_private;
6039         int pipe = crtc->pipe;
6040         int dpll_reg = DPLL(crtc->pipe);
6041         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6042         u32 loopfilter, intcoeff;
6043         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6044         int refclk;
6045
6046         bestn = pipe_config->dpll.n;
6047         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6048         bestm1 = pipe_config->dpll.m1;
6049         bestm2 = pipe_config->dpll.m2 >> 22;
6050         bestp1 = pipe_config->dpll.p1;
6051         bestp2 = pipe_config->dpll.p2;
6052
6053         /*
6054          * Enable Refclk and SSC
6055          */
6056         I915_WRITE(dpll_reg,
6057                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6058
6059         mutex_lock(&dev_priv->dpio_lock);
6060
6061         /* p1 and p2 divider */
6062         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6063                         5 << DPIO_CHV_S1_DIV_SHIFT |
6064                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6065                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6066                         1 << DPIO_CHV_K_DIV_SHIFT);
6067
6068         /* Feedback post-divider - m2 */
6069         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6070
6071         /* Feedback refclk divider - n and m1 */
6072         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6073                         DPIO_CHV_M1_DIV_BY_2 |
6074                         1 << DPIO_CHV_N_DIV_SHIFT);
6075
6076         /* M2 fraction division */
6077         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6078
6079         /* M2 fraction division enable */
6080         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6081                        DPIO_CHV_FRAC_DIV_EN |
6082                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6083
6084         /* Loop filter */
6085         refclk = i9xx_get_refclk(crtc, 0);
6086         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6087                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6088         if (refclk == 100000)
6089                 intcoeff = 11;
6090         else if (refclk == 38400)
6091                 intcoeff = 10;
6092         else
6093                 intcoeff = 9;
6094         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6095         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6096
6097         /* AFC Recal */
6098         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6099                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6100                         DPIO_AFC_RECAL);
6101
6102         mutex_unlock(&dev_priv->dpio_lock);
6103 }
6104
6105 /**
6106  * vlv_force_pll_on - forcibly enable just the PLL
6107  * @dev_priv: i915 private structure
6108  * @pipe: pipe PLL to enable
6109  * @dpll: PLL configuration
6110  *
6111  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6112  * in cases where we need the PLL enabled even when @pipe is not going to
6113  * be enabled.
6114  */
6115 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6116                       const struct dpll *dpll)
6117 {
6118         struct intel_crtc *crtc =
6119                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6120         struct intel_crtc_state pipe_config = {
6121                 .pixel_multiplier = 1,
6122                 .dpll = *dpll,
6123         };
6124
6125         if (IS_CHERRYVIEW(dev)) {
6126                 chv_update_pll(crtc, &pipe_config);
6127                 chv_prepare_pll(crtc, &pipe_config);
6128                 chv_enable_pll(crtc, &pipe_config);
6129         } else {
6130                 vlv_update_pll(crtc, &pipe_config);
6131                 vlv_prepare_pll(crtc, &pipe_config);
6132                 vlv_enable_pll(crtc, &pipe_config);
6133         }
6134 }
6135
6136 /**
6137  * vlv_force_pll_off - forcibly disable just the PLL
6138  * @dev_priv: i915 private structure
6139  * @pipe: pipe PLL to disable
6140  *
6141  * Disable the PLL for @pipe. To be used in cases where we need
6142  * the PLL enabled even when @pipe is not going to be enabled.
6143  */
6144 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6145 {
6146         if (IS_CHERRYVIEW(dev))
6147                 chv_disable_pll(to_i915(dev), pipe);
6148         else
6149                 vlv_disable_pll(to_i915(dev), pipe);
6150 }
6151
6152 static void i9xx_update_pll(struct intel_crtc *crtc,
6153                             struct intel_crtc_state *crtc_state,
6154                             intel_clock_t *reduced_clock,
6155                             int num_connectors)
6156 {
6157         struct drm_device *dev = crtc->base.dev;
6158         struct drm_i915_private *dev_priv = dev->dev_private;
6159         u32 dpll;
6160         bool is_sdvo;
6161         struct dpll *clock = &crtc_state->dpll;
6162
6163         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6164
6165         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6166                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6167
6168         dpll = DPLL_VGA_MODE_DIS;
6169
6170         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6171                 dpll |= DPLLB_MODE_LVDS;
6172         else
6173                 dpll |= DPLLB_MODE_DAC_SERIAL;
6174
6175         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6176                 dpll |= (crtc_state->pixel_multiplier - 1)
6177                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6178         }
6179
6180         if (is_sdvo)
6181                 dpll |= DPLL_SDVO_HIGH_SPEED;
6182
6183         if (crtc_state->has_dp_encoder)
6184                 dpll |= DPLL_SDVO_HIGH_SPEED;
6185
6186         /* compute bitmask from p1 value */
6187         if (IS_PINEVIEW(dev))
6188                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6189         else {
6190                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6191                 if (IS_G4X(dev) && reduced_clock)
6192                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6193         }
6194         switch (clock->p2) {
6195         case 5:
6196                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6197                 break;
6198         case 7:
6199                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6200                 break;
6201         case 10:
6202                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6203                 break;
6204         case 14:
6205                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6206                 break;
6207         }
6208         if (INTEL_INFO(dev)->gen >= 4)
6209                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6210
6211         if (crtc_state->sdvo_tv_clock)
6212                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6213         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6214                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6215                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6216         else
6217                 dpll |= PLL_REF_INPUT_DREFCLK;
6218
6219         dpll |= DPLL_VCO_ENABLE;
6220         crtc_state->dpll_hw_state.dpll = dpll;
6221
6222         if (INTEL_INFO(dev)->gen >= 4) {
6223                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6224                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6225                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6226         }
6227 }
6228
6229 static void i8xx_update_pll(struct intel_crtc *crtc,
6230                             struct intel_crtc_state *crtc_state,
6231                             intel_clock_t *reduced_clock,
6232                             int num_connectors)
6233 {
6234         struct drm_device *dev = crtc->base.dev;
6235         struct drm_i915_private *dev_priv = dev->dev_private;
6236         u32 dpll;
6237         struct dpll *clock = &crtc_state->dpll;
6238
6239         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6240
6241         dpll = DPLL_VGA_MODE_DIS;
6242
6243         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6244                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6245         } else {
6246                 if (clock->p1 == 2)
6247                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6248                 else
6249                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6250                 if (clock->p2 == 4)
6251                         dpll |= PLL_P2_DIVIDE_BY_4;
6252         }
6253
6254         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6255                 dpll |= DPLL_DVO_2X_MODE;
6256
6257         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6258                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6259                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6260         else
6261                 dpll |= PLL_REF_INPUT_DREFCLK;
6262
6263         dpll |= DPLL_VCO_ENABLE;
6264         crtc_state->dpll_hw_state.dpll = dpll;
6265 }
6266
6267 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6268 {
6269         struct drm_device *dev = intel_crtc->base.dev;
6270         struct drm_i915_private *dev_priv = dev->dev_private;
6271         enum pipe pipe = intel_crtc->pipe;
6272         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6273         struct drm_display_mode *adjusted_mode =
6274                 &intel_crtc->config->base.adjusted_mode;
6275         uint32_t crtc_vtotal, crtc_vblank_end;
6276         int vsyncshift = 0;
6277
6278         /* We need to be careful not to changed the adjusted mode, for otherwise
6279          * the hw state checker will get angry at the mismatch. */
6280         crtc_vtotal = adjusted_mode->crtc_vtotal;
6281         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6282
6283         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6284                 /* the chip adds 2 halflines automatically */
6285                 crtc_vtotal -= 1;
6286                 crtc_vblank_end -= 1;
6287
6288                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6289                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6290                 else
6291                         vsyncshift = adjusted_mode->crtc_hsync_start -
6292                                 adjusted_mode->crtc_htotal / 2;
6293                 if (vsyncshift < 0)
6294                         vsyncshift += adjusted_mode->crtc_htotal;
6295         }
6296
6297         if (INTEL_INFO(dev)->gen > 3)
6298                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6299
6300         I915_WRITE(HTOTAL(cpu_transcoder),
6301                    (adjusted_mode->crtc_hdisplay - 1) |
6302                    ((adjusted_mode->crtc_htotal - 1) << 16));
6303         I915_WRITE(HBLANK(cpu_transcoder),
6304                    (adjusted_mode->crtc_hblank_start - 1) |
6305                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6306         I915_WRITE(HSYNC(cpu_transcoder),
6307                    (adjusted_mode->crtc_hsync_start - 1) |
6308                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6309
6310         I915_WRITE(VTOTAL(cpu_transcoder),
6311                    (adjusted_mode->crtc_vdisplay - 1) |
6312                    ((crtc_vtotal - 1) << 16));
6313         I915_WRITE(VBLANK(cpu_transcoder),
6314                    (adjusted_mode->crtc_vblank_start - 1) |
6315                    ((crtc_vblank_end - 1) << 16));
6316         I915_WRITE(VSYNC(cpu_transcoder),
6317                    (adjusted_mode->crtc_vsync_start - 1) |
6318                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6319
6320         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6321          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6322          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6323          * bits. */
6324         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6325             (pipe == PIPE_B || pipe == PIPE_C))
6326                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6327
6328         /* pipesrc controls the size that is scaled from, which should
6329          * always be the user's requested size.
6330          */
6331         I915_WRITE(PIPESRC(pipe),
6332                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6333                    (intel_crtc->config->pipe_src_h - 1));
6334 }
6335
6336 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6337                                    struct intel_crtc_state *pipe_config)
6338 {
6339         struct drm_device *dev = crtc->base.dev;
6340         struct drm_i915_private *dev_priv = dev->dev_private;
6341         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6342         uint32_t tmp;
6343
6344         tmp = I915_READ(HTOTAL(cpu_transcoder));
6345         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6346         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6347         tmp = I915_READ(HBLANK(cpu_transcoder));
6348         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6349         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6350         tmp = I915_READ(HSYNC(cpu_transcoder));
6351         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6352         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6353
6354         tmp = I915_READ(VTOTAL(cpu_transcoder));
6355         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6356         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6357         tmp = I915_READ(VBLANK(cpu_transcoder));
6358         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6359         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6360         tmp = I915_READ(VSYNC(cpu_transcoder));
6361         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6362         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6363
6364         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6365                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6366                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6367                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6368         }
6369
6370         tmp = I915_READ(PIPESRC(crtc->pipe));
6371         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6372         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6373
6374         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6375         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6376 }
6377
6378 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6379                                  struct intel_crtc_state *pipe_config)
6380 {
6381         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6382         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6383         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6384         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6385
6386         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6387         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6388         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6389         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6390
6391         mode->flags = pipe_config->base.adjusted_mode.flags;
6392
6393         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6394         mode->flags |= pipe_config->base.adjusted_mode.flags;
6395 }
6396
6397 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6398 {
6399         struct drm_device *dev = intel_crtc->base.dev;
6400         struct drm_i915_private *dev_priv = dev->dev_private;
6401         uint32_t pipeconf;
6402
6403         pipeconf = 0;
6404
6405         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6406             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6407                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6408
6409         if (intel_crtc->config->double_wide)
6410                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6411
6412         /* only g4x and later have fancy bpc/dither controls */
6413         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6414                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6415                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6416                         pipeconf |= PIPECONF_DITHER_EN |
6417                                     PIPECONF_DITHER_TYPE_SP;
6418
6419                 switch (intel_crtc->config->pipe_bpp) {
6420                 case 18:
6421                         pipeconf |= PIPECONF_6BPC;
6422                         break;
6423                 case 24:
6424                         pipeconf |= PIPECONF_8BPC;
6425                         break;
6426                 case 30:
6427                         pipeconf |= PIPECONF_10BPC;
6428                         break;
6429                 default:
6430                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6431                         BUG();
6432                 }
6433         }
6434
6435         if (HAS_PIPE_CXSR(dev)) {
6436                 if (intel_crtc->lowfreq_avail) {
6437                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6438                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6439                 } else {
6440                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6441                 }
6442         }
6443
6444         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6445                 if (INTEL_INFO(dev)->gen < 4 ||
6446                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6447                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6448                 else
6449                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6450         } else
6451                 pipeconf |= PIPECONF_PROGRESSIVE;
6452
6453         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6454                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6455
6456         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6457         POSTING_READ(PIPECONF(intel_crtc->pipe));
6458 }
6459
6460 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6461                                    struct intel_crtc_state *crtc_state)
6462 {
6463         struct drm_device *dev = crtc->base.dev;
6464         struct drm_i915_private *dev_priv = dev->dev_private;
6465         int refclk, num_connectors = 0;
6466         intel_clock_t clock, reduced_clock;
6467         bool ok, has_reduced_clock = false;
6468         bool is_lvds = false, is_dsi = false;
6469         struct intel_encoder *encoder;
6470         const intel_limit_t *limit;
6471
6472         for_each_intel_encoder(dev, encoder) {
6473                 if (encoder->new_crtc != crtc)
6474                         continue;
6475
6476                 switch (encoder->type) {
6477                 case INTEL_OUTPUT_LVDS:
6478                         is_lvds = true;
6479                         break;
6480                 case INTEL_OUTPUT_DSI:
6481                         is_dsi = true;
6482                         break;
6483                 default:
6484                         break;
6485                 }
6486
6487                 num_connectors++;
6488         }
6489
6490         if (is_dsi)
6491                 return 0;
6492
6493         if (!crtc_state->clock_set) {
6494                 refclk = i9xx_get_refclk(crtc, num_connectors);
6495
6496                 /*
6497                  * Returns a set of divisors for the desired target clock with
6498                  * the given refclk, or FALSE.  The returned values represent
6499                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6500                  * 2) / p1 / p2.
6501                  */
6502                 limit = intel_limit(crtc, refclk);
6503                 ok = dev_priv->display.find_dpll(limit, crtc,
6504                                                  crtc_state->port_clock,
6505                                                  refclk, NULL, &clock);
6506                 if (!ok) {
6507                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6508                         return -EINVAL;
6509                 }
6510
6511                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6512                         /*
6513                          * Ensure we match the reduced clock's P to the target
6514                          * clock.  If the clocks don't match, we can't switch
6515                          * the display clock by using the FP0/FP1. In such case
6516                          * we will disable the LVDS downclock feature.
6517                          */
6518                         has_reduced_clock =
6519                                 dev_priv->display.find_dpll(limit, crtc,
6520                                                             dev_priv->lvds_downclock,
6521                                                             refclk, &clock,
6522                                                             &reduced_clock);
6523                 }
6524                 /* Compat-code for transition, will disappear. */
6525                 crtc_state->dpll.n = clock.n;
6526                 crtc_state->dpll.m1 = clock.m1;
6527                 crtc_state->dpll.m2 = clock.m2;
6528                 crtc_state->dpll.p1 = clock.p1;
6529                 crtc_state->dpll.p2 = clock.p2;
6530         }
6531
6532         if (IS_GEN2(dev)) {
6533                 i8xx_update_pll(crtc, crtc_state,
6534                                 has_reduced_clock ? &reduced_clock : NULL,
6535                                 num_connectors);
6536         } else if (IS_CHERRYVIEW(dev)) {
6537                 chv_update_pll(crtc, crtc_state);
6538         } else if (IS_VALLEYVIEW(dev)) {
6539                 vlv_update_pll(crtc, crtc_state);
6540         } else {
6541                 i9xx_update_pll(crtc, crtc_state,
6542                                 has_reduced_clock ? &reduced_clock : NULL,
6543                                 num_connectors);
6544         }
6545
6546         return 0;
6547 }
6548
6549 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6550                                  struct intel_crtc_state *pipe_config)
6551 {
6552         struct drm_device *dev = crtc->base.dev;
6553         struct drm_i915_private *dev_priv = dev->dev_private;
6554         uint32_t tmp;
6555
6556         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6557                 return;
6558
6559         tmp = I915_READ(PFIT_CONTROL);
6560         if (!(tmp & PFIT_ENABLE))
6561                 return;
6562
6563         /* Check whether the pfit is attached to our pipe. */
6564         if (INTEL_INFO(dev)->gen < 4) {
6565                 if (crtc->pipe != PIPE_B)
6566                         return;
6567         } else {
6568                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6569                         return;
6570         }
6571
6572         pipe_config->gmch_pfit.control = tmp;
6573         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6574         if (INTEL_INFO(dev)->gen < 5)
6575                 pipe_config->gmch_pfit.lvds_border_bits =
6576                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6577 }
6578
6579 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6580                                struct intel_crtc_state *pipe_config)
6581 {
6582         struct drm_device *dev = crtc->base.dev;
6583         struct drm_i915_private *dev_priv = dev->dev_private;
6584         int pipe = pipe_config->cpu_transcoder;
6585         intel_clock_t clock;
6586         u32 mdiv;
6587         int refclk = 100000;
6588
6589         /* In case of MIPI DPLL will not even be used */
6590         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6591                 return;
6592
6593         mutex_lock(&dev_priv->dpio_lock);
6594         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6595         mutex_unlock(&dev_priv->dpio_lock);
6596
6597         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6598         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6599         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6600         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6601         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6602
6603         vlv_clock(refclk, &clock);
6604
6605         /* clock.dot is the fast clock */
6606         pipe_config->port_clock = clock.dot / 5;
6607 }
6608
6609 static void
6610 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6611                               struct intel_initial_plane_config *plane_config)
6612 {
6613         struct drm_device *dev = crtc->base.dev;
6614         struct drm_i915_private *dev_priv = dev->dev_private;
6615         u32 val, base, offset;
6616         int pipe = crtc->pipe, plane = crtc->plane;
6617         int fourcc, pixel_format;
6618         int aligned_height;
6619         struct drm_framebuffer *fb;
6620         struct intel_framebuffer *intel_fb;
6621
6622         val = I915_READ(DSPCNTR(plane));
6623         if (!(val & DISPLAY_PLANE_ENABLE))
6624                 return;
6625
6626         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6627         if (!intel_fb) {
6628                 DRM_DEBUG_KMS("failed to alloc fb\n");
6629                 return;
6630         }
6631
6632         fb = &intel_fb->base;
6633
6634         if (INTEL_INFO(dev)->gen >= 4) {
6635                 if (val & DISPPLANE_TILED) {
6636                         plane_config->tiling = I915_TILING_X;
6637                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6638                 }
6639         }
6640
6641         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6642         fourcc = i9xx_format_to_fourcc(pixel_format);
6643         fb->pixel_format = fourcc;
6644         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6645
6646         if (INTEL_INFO(dev)->gen >= 4) {
6647                 if (plane_config->tiling)
6648                         offset = I915_READ(DSPTILEOFF(plane));
6649                 else
6650                         offset = I915_READ(DSPLINOFF(plane));
6651                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6652         } else {
6653                 base = I915_READ(DSPADDR(plane));
6654         }
6655         plane_config->base = base;
6656
6657         val = I915_READ(PIPESRC(pipe));
6658         fb->width = ((val >> 16) & 0xfff) + 1;
6659         fb->height = ((val >> 0) & 0xfff) + 1;
6660
6661         val = I915_READ(DSPSTRIDE(pipe));
6662         fb->pitches[0] = val & 0xffffffc0;
6663
6664         aligned_height = intel_fb_align_height(dev, fb->height,
6665                                                fb->pixel_format,
6666                                                fb->modifier[0]);
6667
6668         plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6669
6670         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6671                       pipe_name(pipe), plane, fb->width, fb->height,
6672                       fb->bits_per_pixel, base, fb->pitches[0],
6673                       plane_config->size);
6674
6675         plane_config->fb = intel_fb;
6676 }
6677
6678 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6679                                struct intel_crtc_state *pipe_config)
6680 {
6681         struct drm_device *dev = crtc->base.dev;
6682         struct drm_i915_private *dev_priv = dev->dev_private;
6683         int pipe = pipe_config->cpu_transcoder;
6684         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6685         intel_clock_t clock;
6686         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6687         int refclk = 100000;
6688
6689         mutex_lock(&dev_priv->dpio_lock);
6690         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6691         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6692         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6693         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6694         mutex_unlock(&dev_priv->dpio_lock);
6695
6696         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6697         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6698         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6699         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6700         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6701
6702         chv_clock(refclk, &clock);
6703
6704         /* clock.dot is the fast clock */
6705         pipe_config->port_clock = clock.dot / 5;
6706 }
6707
6708 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6709                                  struct intel_crtc_state *pipe_config)
6710 {
6711         struct drm_device *dev = crtc->base.dev;
6712         struct drm_i915_private *dev_priv = dev->dev_private;
6713         uint32_t tmp;
6714
6715         if (!intel_display_power_is_enabled(dev_priv,
6716                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6717                 return false;
6718
6719         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6720         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6721
6722         tmp = I915_READ(PIPECONF(crtc->pipe));
6723         if (!(tmp & PIPECONF_ENABLE))
6724                 return false;
6725
6726         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6727                 switch (tmp & PIPECONF_BPC_MASK) {
6728                 case PIPECONF_6BPC:
6729                         pipe_config->pipe_bpp = 18;
6730                         break;
6731                 case PIPECONF_8BPC:
6732                         pipe_config->pipe_bpp = 24;
6733                         break;
6734                 case PIPECONF_10BPC:
6735                         pipe_config->pipe_bpp = 30;
6736                         break;
6737                 default:
6738                         break;
6739                 }
6740         }
6741
6742         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6743                 pipe_config->limited_color_range = true;
6744
6745         if (INTEL_INFO(dev)->gen < 4)
6746                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6747
6748         intel_get_pipe_timings(crtc, pipe_config);
6749
6750         i9xx_get_pfit_config(crtc, pipe_config);
6751
6752         if (INTEL_INFO(dev)->gen >= 4) {
6753                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6754                 pipe_config->pixel_multiplier =
6755                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6756                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6757                 pipe_config->dpll_hw_state.dpll_md = tmp;
6758         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6759                 tmp = I915_READ(DPLL(crtc->pipe));
6760                 pipe_config->pixel_multiplier =
6761                         ((tmp & SDVO_MULTIPLIER_MASK)
6762                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6763         } else {
6764                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6765                  * port and will be fixed up in the encoder->get_config
6766                  * function. */
6767                 pipe_config->pixel_multiplier = 1;
6768         }
6769         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6770         if (!IS_VALLEYVIEW(dev)) {
6771                 /*
6772                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6773                  * on 830. Filter it out here so that we don't
6774                  * report errors due to that.
6775                  */
6776                 if (IS_I830(dev))
6777                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6778
6779                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6780                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6781         } else {
6782                 /* Mask out read-only status bits. */
6783                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6784                                                      DPLL_PORTC_READY_MASK |
6785                                                      DPLL_PORTB_READY_MASK);
6786         }
6787
6788         if (IS_CHERRYVIEW(dev))
6789                 chv_crtc_clock_get(crtc, pipe_config);
6790         else if (IS_VALLEYVIEW(dev))
6791                 vlv_crtc_clock_get(crtc, pipe_config);
6792         else
6793                 i9xx_crtc_clock_get(crtc, pipe_config);
6794
6795         return true;
6796 }
6797
6798 static void ironlake_init_pch_refclk(struct drm_device *dev)
6799 {
6800         struct drm_i915_private *dev_priv = dev->dev_private;
6801         struct intel_encoder *encoder;
6802         u32 val, final;
6803         bool has_lvds = false;
6804         bool has_cpu_edp = false;
6805         bool has_panel = false;
6806         bool has_ck505 = false;
6807         bool can_ssc = false;
6808
6809         /* We need to take the global config into account */
6810         for_each_intel_encoder(dev, encoder) {
6811                 switch (encoder->type) {
6812                 case INTEL_OUTPUT_LVDS:
6813                         has_panel = true;
6814                         has_lvds = true;
6815                         break;
6816                 case INTEL_OUTPUT_EDP:
6817                         has_panel = true;
6818                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6819                                 has_cpu_edp = true;
6820                         break;
6821                 default:
6822                         break;
6823                 }
6824         }
6825
6826         if (HAS_PCH_IBX(dev)) {
6827                 has_ck505 = dev_priv->vbt.display_clock_mode;
6828                 can_ssc = has_ck505;
6829         } else {
6830                 has_ck505 = false;
6831                 can_ssc = true;
6832         }
6833
6834         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6835                       has_panel, has_lvds, has_ck505);
6836
6837         /* Ironlake: try to setup display ref clock before DPLL
6838          * enabling. This is only under driver's control after
6839          * PCH B stepping, previous chipset stepping should be
6840          * ignoring this setting.
6841          */
6842         val = I915_READ(PCH_DREF_CONTROL);
6843
6844         /* As we must carefully and slowly disable/enable each source in turn,
6845          * compute the final state we want first and check if we need to
6846          * make any changes at all.
6847          */
6848         final = val;
6849         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6850         if (has_ck505)
6851                 final |= DREF_NONSPREAD_CK505_ENABLE;
6852         else
6853                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6854
6855         final &= ~DREF_SSC_SOURCE_MASK;
6856         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6857         final &= ~DREF_SSC1_ENABLE;
6858
6859         if (has_panel) {
6860                 final |= DREF_SSC_SOURCE_ENABLE;
6861
6862                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6863                         final |= DREF_SSC1_ENABLE;
6864
6865                 if (has_cpu_edp) {
6866                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6867                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6868                         else
6869                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6870                 } else
6871                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6872         } else {
6873                 final |= DREF_SSC_SOURCE_DISABLE;
6874                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6875         }
6876
6877         if (final == val)
6878                 return;
6879
6880         /* Always enable nonspread source */
6881         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6882
6883         if (has_ck505)
6884                 val |= DREF_NONSPREAD_CK505_ENABLE;
6885         else
6886                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6887
6888         if (has_panel) {
6889                 val &= ~DREF_SSC_SOURCE_MASK;
6890                 val |= DREF_SSC_SOURCE_ENABLE;
6891
6892                 /* SSC must be turned on before enabling the CPU output  */
6893                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6894                         DRM_DEBUG_KMS("Using SSC on panel\n");
6895                         val |= DREF_SSC1_ENABLE;
6896                 } else
6897                         val &= ~DREF_SSC1_ENABLE;
6898
6899                 /* Get SSC going before enabling the outputs */
6900                 I915_WRITE(PCH_DREF_CONTROL, val);
6901                 POSTING_READ(PCH_DREF_CONTROL);
6902                 udelay(200);
6903
6904                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6905
6906                 /* Enable CPU source on CPU attached eDP */
6907                 if (has_cpu_edp) {
6908                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6909                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6910                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6911                         } else
6912                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6913                 } else
6914                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6915
6916                 I915_WRITE(PCH_DREF_CONTROL, val);
6917                 POSTING_READ(PCH_DREF_CONTROL);
6918                 udelay(200);
6919         } else {
6920                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6921
6922                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6923
6924                 /* Turn off CPU output */
6925                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6926
6927                 I915_WRITE(PCH_DREF_CONTROL, val);
6928                 POSTING_READ(PCH_DREF_CONTROL);
6929                 udelay(200);
6930
6931                 /* Turn off the SSC source */
6932                 val &= ~DREF_SSC_SOURCE_MASK;
6933                 val |= DREF_SSC_SOURCE_DISABLE;
6934
6935                 /* Turn off SSC1 */
6936                 val &= ~DREF_SSC1_ENABLE;
6937
6938                 I915_WRITE(PCH_DREF_CONTROL, val);
6939                 POSTING_READ(PCH_DREF_CONTROL);
6940                 udelay(200);
6941         }
6942
6943         BUG_ON(val != final);
6944 }
6945
6946 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6947 {
6948         uint32_t tmp;
6949
6950         tmp = I915_READ(SOUTH_CHICKEN2);
6951         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6952         I915_WRITE(SOUTH_CHICKEN2, tmp);
6953
6954         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6955                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6956                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6957
6958         tmp = I915_READ(SOUTH_CHICKEN2);
6959         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6960         I915_WRITE(SOUTH_CHICKEN2, tmp);
6961
6962         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6963                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6964                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6965 }
6966
6967 /* WaMPhyProgramming:hsw */
6968 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6969 {
6970         uint32_t tmp;
6971
6972         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6973         tmp &= ~(0xFF << 24);
6974         tmp |= (0x12 << 24);
6975         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6976
6977         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6978         tmp |= (1 << 11);
6979         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6980
6981         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6982         tmp |= (1 << 11);
6983         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6984
6985         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6986         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6987         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6988
6989         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6990         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6991         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6992
6993         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6994         tmp &= ~(7 << 13);
6995         tmp |= (5 << 13);
6996         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6997
6998         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6999         tmp &= ~(7 << 13);
7000         tmp |= (5 << 13);
7001         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7002
7003         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7004         tmp &= ~0xFF;
7005         tmp |= 0x1C;
7006         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7007
7008         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7009         tmp &= ~0xFF;
7010         tmp |= 0x1C;
7011         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7012
7013         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7014         tmp &= ~(0xFF << 16);
7015         tmp |= (0x1C << 16);
7016         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7017
7018         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7019         tmp &= ~(0xFF << 16);
7020         tmp |= (0x1C << 16);
7021         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7022
7023         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7024         tmp |= (1 << 27);
7025         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7026
7027         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7028         tmp |= (1 << 27);
7029         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7030
7031         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7032         tmp &= ~(0xF << 28);
7033         tmp |= (4 << 28);
7034         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7035
7036         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7037         tmp &= ~(0xF << 28);
7038         tmp |= (4 << 28);
7039         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7040 }
7041
7042 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7043  * Programming" based on the parameters passed:
7044  * - Sequence to enable CLKOUT_DP
7045  * - Sequence to enable CLKOUT_DP without spread
7046  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7047  */
7048 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7049                                  bool with_fdi)
7050 {
7051         struct drm_i915_private *dev_priv = dev->dev_private;
7052         uint32_t reg, tmp;
7053
7054         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7055                 with_spread = true;
7056         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7057                  with_fdi, "LP PCH doesn't have FDI\n"))
7058                 with_fdi = false;
7059
7060         mutex_lock(&dev_priv->dpio_lock);
7061
7062         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7063         tmp &= ~SBI_SSCCTL_DISABLE;
7064         tmp |= SBI_SSCCTL_PATHALT;
7065         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7066
7067         udelay(24);
7068
7069         if (with_spread) {
7070                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7071                 tmp &= ~SBI_SSCCTL_PATHALT;
7072                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7073
7074                 if (with_fdi) {
7075                         lpt_reset_fdi_mphy(dev_priv);
7076                         lpt_program_fdi_mphy(dev_priv);
7077                 }
7078         }
7079
7080         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7081                SBI_GEN0 : SBI_DBUFF0;
7082         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7083         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7084         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7085
7086         mutex_unlock(&dev_priv->dpio_lock);
7087 }
7088
7089 /* Sequence to disable CLKOUT_DP */
7090 static void lpt_disable_clkout_dp(struct drm_device *dev)
7091 {
7092         struct drm_i915_private *dev_priv = dev->dev_private;
7093         uint32_t reg, tmp;
7094
7095         mutex_lock(&dev_priv->dpio_lock);
7096
7097         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7098                SBI_GEN0 : SBI_DBUFF0;
7099         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7100         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7101         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7102
7103         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7104         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7105                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7106                         tmp |= SBI_SSCCTL_PATHALT;
7107                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7108                         udelay(32);
7109                 }
7110                 tmp |= SBI_SSCCTL_DISABLE;
7111                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7112         }
7113
7114         mutex_unlock(&dev_priv->dpio_lock);
7115 }
7116
7117 static void lpt_init_pch_refclk(struct drm_device *dev)
7118 {
7119         struct intel_encoder *encoder;
7120         bool has_vga = false;
7121
7122         for_each_intel_encoder(dev, encoder) {
7123                 switch (encoder->type) {
7124                 case INTEL_OUTPUT_ANALOG:
7125                         has_vga = true;
7126                         break;
7127                 default:
7128                         break;
7129                 }
7130         }
7131
7132         if (has_vga)
7133                 lpt_enable_clkout_dp(dev, true, true);
7134         else
7135                 lpt_disable_clkout_dp(dev);
7136 }
7137
7138 /*
7139  * Initialize reference clocks when the driver loads
7140  */
7141 void intel_init_pch_refclk(struct drm_device *dev)
7142 {
7143         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7144                 ironlake_init_pch_refclk(dev);
7145         else if (HAS_PCH_LPT(dev))
7146                 lpt_init_pch_refclk(dev);
7147 }
7148
7149 static int ironlake_get_refclk(struct drm_crtc *crtc)
7150 {
7151         struct drm_device *dev = crtc->dev;
7152         struct drm_i915_private *dev_priv = dev->dev_private;
7153         struct intel_encoder *encoder;
7154         int num_connectors = 0;
7155         bool is_lvds = false;
7156
7157         for_each_intel_encoder(dev, encoder) {
7158                 if (encoder->new_crtc != to_intel_crtc(crtc))
7159                         continue;
7160
7161                 switch (encoder->type) {
7162                 case INTEL_OUTPUT_LVDS:
7163                         is_lvds = true;
7164                         break;
7165                 default:
7166                         break;
7167                 }
7168                 num_connectors++;
7169         }
7170
7171         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7172                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7173                               dev_priv->vbt.lvds_ssc_freq);
7174                 return dev_priv->vbt.lvds_ssc_freq;
7175         }
7176
7177         return 120000;
7178 }
7179
7180 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7181 {
7182         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7184         int pipe = intel_crtc->pipe;
7185         uint32_t val;
7186
7187         val = 0;
7188
7189         switch (intel_crtc->config->pipe_bpp) {
7190         case 18:
7191                 val |= PIPECONF_6BPC;
7192                 break;
7193         case 24:
7194                 val |= PIPECONF_8BPC;
7195                 break;
7196         case 30:
7197                 val |= PIPECONF_10BPC;
7198                 break;
7199         case 36:
7200                 val |= PIPECONF_12BPC;
7201                 break;
7202         default:
7203                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7204                 BUG();
7205         }
7206
7207         if (intel_crtc->config->dither)
7208                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7209
7210         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7211                 val |= PIPECONF_INTERLACED_ILK;
7212         else
7213                 val |= PIPECONF_PROGRESSIVE;
7214
7215         if (intel_crtc->config->limited_color_range)
7216                 val |= PIPECONF_COLOR_RANGE_SELECT;
7217
7218         I915_WRITE(PIPECONF(pipe), val);
7219         POSTING_READ(PIPECONF(pipe));
7220 }
7221
7222 /*
7223  * Set up the pipe CSC unit.
7224  *
7225  * Currently only full range RGB to limited range RGB conversion
7226  * is supported, but eventually this should handle various
7227  * RGB<->YCbCr scenarios as well.
7228  */
7229 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7230 {
7231         struct drm_device *dev = crtc->dev;
7232         struct drm_i915_private *dev_priv = dev->dev_private;
7233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7234         int pipe = intel_crtc->pipe;
7235         uint16_t coeff = 0x7800; /* 1.0 */
7236
7237         /*
7238          * TODO: Check what kind of values actually come out of the pipe
7239          * with these coeff/postoff values and adjust to get the best
7240          * accuracy. Perhaps we even need to take the bpc value into
7241          * consideration.
7242          */
7243
7244         if (intel_crtc->config->limited_color_range)
7245                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7246
7247         /*
7248          * GY/GU and RY/RU should be the other way around according
7249          * to BSpec, but reality doesn't agree. Just set them up in
7250          * a way that results in the correct picture.
7251          */
7252         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7253         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7254
7255         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7256         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7257
7258         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7259         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7260
7261         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7262         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7263         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7264
7265         if (INTEL_INFO(dev)->gen > 6) {
7266                 uint16_t postoff = 0;
7267
7268                 if (intel_crtc->config->limited_color_range)
7269                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7270
7271                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7272                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7273                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7274
7275                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7276         } else {
7277                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7278
7279                 if (intel_crtc->config->limited_color_range)
7280                         mode |= CSC_BLACK_SCREEN_OFFSET;
7281
7282                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7283         }
7284 }
7285
7286 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7287 {
7288         struct drm_device *dev = crtc->dev;
7289         struct drm_i915_private *dev_priv = dev->dev_private;
7290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291         enum pipe pipe = intel_crtc->pipe;
7292         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7293         uint32_t val;
7294
7295         val = 0;
7296
7297         if (IS_HASWELL(dev) && intel_crtc->config->dither)
7298                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7299
7300         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7301                 val |= PIPECONF_INTERLACED_ILK;
7302         else
7303                 val |= PIPECONF_PROGRESSIVE;
7304
7305         I915_WRITE(PIPECONF(cpu_transcoder), val);
7306         POSTING_READ(PIPECONF(cpu_transcoder));
7307
7308         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7309         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7310
7311         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7312                 val = 0;
7313
7314                 switch (intel_crtc->config->pipe_bpp) {
7315                 case 18:
7316                         val |= PIPEMISC_DITHER_6_BPC;
7317                         break;
7318                 case 24:
7319                         val |= PIPEMISC_DITHER_8_BPC;
7320                         break;
7321                 case 30:
7322                         val |= PIPEMISC_DITHER_10_BPC;
7323                         break;
7324                 case 36:
7325                         val |= PIPEMISC_DITHER_12_BPC;
7326                         break;
7327                 default:
7328                         /* Case prevented by pipe_config_set_bpp. */
7329                         BUG();
7330                 }
7331
7332                 if (intel_crtc->config->dither)
7333                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7334
7335                 I915_WRITE(PIPEMISC(pipe), val);
7336         }
7337 }
7338
7339 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7340                                     struct intel_crtc_state *crtc_state,
7341                                     intel_clock_t *clock,
7342                                     bool *has_reduced_clock,
7343                                     intel_clock_t *reduced_clock)
7344 {
7345         struct drm_device *dev = crtc->dev;
7346         struct drm_i915_private *dev_priv = dev->dev_private;
7347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7348         int refclk;
7349         const intel_limit_t *limit;
7350         bool ret, is_lvds = false;
7351
7352         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7353
7354         refclk = ironlake_get_refclk(crtc);
7355
7356         /*
7357          * Returns a set of divisors for the desired target clock with the given
7358          * refclk, or FALSE.  The returned values represent the clock equation:
7359          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7360          */
7361         limit = intel_limit(intel_crtc, refclk);
7362         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7363                                           crtc_state->port_clock,
7364                                           refclk, NULL, clock);
7365         if (!ret)
7366                 return false;
7367
7368         if (is_lvds && dev_priv->lvds_downclock_avail) {
7369                 /*
7370                  * Ensure we match the reduced clock's P to the target clock.
7371                  * If the clocks don't match, we can't switch the display clock
7372                  * by using the FP0/FP1. In such case we will disable the LVDS
7373                  * downclock feature.
7374                 */
7375                 *has_reduced_clock =
7376                         dev_priv->display.find_dpll(limit, intel_crtc,
7377                                                     dev_priv->lvds_downclock,
7378                                                     refclk, clock,
7379                                                     reduced_clock);
7380         }
7381
7382         return true;
7383 }
7384
7385 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7386 {
7387         /*
7388          * Account for spread spectrum to avoid
7389          * oversubscribing the link. Max center spread
7390          * is 2.5%; use 5% for safety's sake.
7391          */
7392         u32 bps = target_clock * bpp * 21 / 20;
7393         return DIV_ROUND_UP(bps, link_bw * 8);
7394 }
7395
7396 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7397 {
7398         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7399 }
7400
7401 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7402                                       struct intel_crtc_state *crtc_state,
7403                                       u32 *fp,
7404                                       intel_clock_t *reduced_clock, u32 *fp2)
7405 {
7406         struct drm_crtc *crtc = &intel_crtc->base;
7407         struct drm_device *dev = crtc->dev;
7408         struct drm_i915_private *dev_priv = dev->dev_private;
7409         struct intel_encoder *intel_encoder;
7410         uint32_t dpll;
7411         int factor, num_connectors = 0;
7412         bool is_lvds = false, is_sdvo = false;
7413
7414         for_each_intel_encoder(dev, intel_encoder) {
7415                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7416                         continue;
7417
7418                 switch (intel_encoder->type) {
7419                 case INTEL_OUTPUT_LVDS:
7420                         is_lvds = true;
7421                         break;
7422                 case INTEL_OUTPUT_SDVO:
7423                 case INTEL_OUTPUT_HDMI:
7424                         is_sdvo = true;
7425                         break;
7426                 default:
7427                         break;
7428                 }
7429
7430                 num_connectors++;
7431         }
7432
7433         /* Enable autotuning of the PLL clock (if permissible) */
7434         factor = 21;
7435         if (is_lvds) {
7436                 if ((intel_panel_use_ssc(dev_priv) &&
7437                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7438                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7439                         factor = 25;
7440         } else if (crtc_state->sdvo_tv_clock)
7441                 factor = 20;
7442
7443         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7444                 *fp |= FP_CB_TUNE;
7445
7446         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7447                 *fp2 |= FP_CB_TUNE;
7448
7449         dpll = 0;
7450
7451         if (is_lvds)
7452                 dpll |= DPLLB_MODE_LVDS;
7453         else
7454                 dpll |= DPLLB_MODE_DAC_SERIAL;
7455
7456         dpll |= (crtc_state->pixel_multiplier - 1)
7457                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7458
7459         if (is_sdvo)
7460                 dpll |= DPLL_SDVO_HIGH_SPEED;
7461         if (crtc_state->has_dp_encoder)
7462                 dpll |= DPLL_SDVO_HIGH_SPEED;
7463
7464         /* compute bitmask from p1 value */
7465         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7466         /* also FPA1 */
7467         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7468
7469         switch (crtc_state->dpll.p2) {
7470         case 5:
7471                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7472                 break;
7473         case 7:
7474                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7475                 break;
7476         case 10:
7477                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7478                 break;
7479         case 14:
7480                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7481                 break;
7482         }
7483
7484         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7485                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7486         else
7487                 dpll |= PLL_REF_INPUT_DREFCLK;
7488
7489         return dpll | DPLL_VCO_ENABLE;
7490 }
7491
7492 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7493                                        struct intel_crtc_state *crtc_state)
7494 {
7495         struct drm_device *dev = crtc->base.dev;
7496         intel_clock_t clock, reduced_clock;
7497         u32 dpll = 0, fp = 0, fp2 = 0;
7498         bool ok, has_reduced_clock = false;
7499         bool is_lvds = false;
7500         struct intel_shared_dpll *pll;
7501
7502         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7503
7504         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7505              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7506
7507         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7508                                      &has_reduced_clock, &reduced_clock);
7509         if (!ok && !crtc_state->clock_set) {
7510                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7511                 return -EINVAL;
7512         }
7513         /* Compat-code for transition, will disappear. */
7514         if (!crtc_state->clock_set) {
7515                 crtc_state->dpll.n = clock.n;
7516                 crtc_state->dpll.m1 = clock.m1;
7517                 crtc_state->dpll.m2 = clock.m2;
7518                 crtc_state->dpll.p1 = clock.p1;
7519                 crtc_state->dpll.p2 = clock.p2;
7520         }
7521
7522         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7523         if (crtc_state->has_pch_encoder) {
7524                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7525                 if (has_reduced_clock)
7526                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7527
7528                 dpll = ironlake_compute_dpll(crtc, crtc_state,
7529                                              &fp, &reduced_clock,
7530                                              has_reduced_clock ? &fp2 : NULL);
7531
7532                 crtc_state->dpll_hw_state.dpll = dpll;
7533                 crtc_state->dpll_hw_state.fp0 = fp;
7534                 if (has_reduced_clock)
7535                         crtc_state->dpll_hw_state.fp1 = fp2;
7536                 else
7537                         crtc_state->dpll_hw_state.fp1 = fp;
7538
7539                 pll = intel_get_shared_dpll(crtc, crtc_state);
7540                 if (pll == NULL) {
7541                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7542                                          pipe_name(crtc->pipe));
7543                         return -EINVAL;
7544                 }
7545         }
7546
7547         if (is_lvds && has_reduced_clock && i915.powersave)
7548                 crtc->lowfreq_avail = true;
7549         else
7550                 crtc->lowfreq_avail = false;
7551
7552         return 0;
7553 }
7554
7555 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7556                                          struct intel_link_m_n *m_n)
7557 {
7558         struct drm_device *dev = crtc->base.dev;
7559         struct drm_i915_private *dev_priv = dev->dev_private;
7560         enum pipe pipe = crtc->pipe;
7561
7562         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7563         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7564         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7565                 & ~TU_SIZE_MASK;
7566         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7567         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7568                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7569 }
7570
7571 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7572                                          enum transcoder transcoder,
7573                                          struct intel_link_m_n *m_n,
7574                                          struct intel_link_m_n *m2_n2)
7575 {
7576         struct drm_device *dev = crtc->base.dev;
7577         struct drm_i915_private *dev_priv = dev->dev_private;
7578         enum pipe pipe = crtc->pipe;
7579
7580         if (INTEL_INFO(dev)->gen >= 5) {
7581                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7582                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7583                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7584                         & ~TU_SIZE_MASK;
7585                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7586                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7587                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7588                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7589                  * gen < 8) and if DRRS is supported (to make sure the
7590                  * registers are not unnecessarily read).
7591                  */
7592                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7593                         crtc->config->has_drrs) {
7594                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7595                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7596                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7597                                         & ~TU_SIZE_MASK;
7598                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7599                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7600                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7601                 }
7602         } else {
7603                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7604                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7605                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7606                         & ~TU_SIZE_MASK;
7607                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7608                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7609                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7610         }
7611 }
7612
7613 void intel_dp_get_m_n(struct intel_crtc *crtc,
7614                       struct intel_crtc_state *pipe_config)
7615 {
7616         if (pipe_config->has_pch_encoder)
7617                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7618         else
7619                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7620                                              &pipe_config->dp_m_n,
7621                                              &pipe_config->dp_m2_n2);
7622 }
7623
7624 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7625                                         struct intel_crtc_state *pipe_config)
7626 {
7627         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7628                                      &pipe_config->fdi_m_n, NULL);
7629 }
7630
7631 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7632                                     struct intel_crtc_state *pipe_config)
7633 {
7634         struct drm_device *dev = crtc->base.dev;
7635         struct drm_i915_private *dev_priv = dev->dev_private;
7636         uint32_t tmp;
7637
7638         tmp = I915_READ(PS_CTL(crtc->pipe));
7639
7640         if (tmp & PS_ENABLE) {
7641                 pipe_config->pch_pfit.enabled = true;
7642                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7643                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7644         }
7645 }
7646
7647 static void
7648 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7649                                  struct intel_initial_plane_config *plane_config)
7650 {
7651         struct drm_device *dev = crtc->base.dev;
7652         struct drm_i915_private *dev_priv = dev->dev_private;
7653         u32 val, base, offset, stride_mult;
7654         int pipe = crtc->pipe;
7655         int fourcc, pixel_format;
7656         int aligned_height;
7657         struct drm_framebuffer *fb;
7658         struct intel_framebuffer *intel_fb;
7659
7660         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7661         if (!intel_fb) {
7662                 DRM_DEBUG_KMS("failed to alloc fb\n");
7663                 return;
7664         }
7665
7666         fb = &intel_fb->base;
7667
7668         val = I915_READ(PLANE_CTL(pipe, 0));
7669         if (!(val & PLANE_CTL_ENABLE))
7670                 goto error;
7671
7672         if (val & PLANE_CTL_TILED_MASK) {
7673                 plane_config->tiling = I915_TILING_X;
7674                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7675         }
7676
7677         pixel_format = val & PLANE_CTL_FORMAT_MASK;
7678         fourcc = skl_format_to_fourcc(pixel_format,
7679                                       val & PLANE_CTL_ORDER_RGBX,
7680                                       val & PLANE_CTL_ALPHA_MASK);
7681         fb->pixel_format = fourcc;
7682         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7683
7684         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7685         plane_config->base = base;
7686
7687         offset = I915_READ(PLANE_OFFSET(pipe, 0));
7688
7689         val = I915_READ(PLANE_SIZE(pipe, 0));
7690         fb->height = ((val >> 16) & 0xfff) + 1;
7691         fb->width = ((val >> 0) & 0x1fff) + 1;
7692
7693         val = I915_READ(PLANE_STRIDE(pipe, 0));
7694         switch (plane_config->tiling) {
7695         case I915_TILING_NONE:
7696                 stride_mult = 64;
7697                 break;
7698         case I915_TILING_X:
7699                 stride_mult = 512;
7700                 break;
7701         default:
7702                 MISSING_CASE(plane_config->tiling);
7703                 goto error;
7704         }
7705         fb->pitches[0] = (val & 0x3ff) * stride_mult;
7706
7707         aligned_height = intel_fb_align_height(dev, fb->height,
7708                                                fb->pixel_format,
7709                                                fb->modifier[0]);
7710
7711         plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7712
7713         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7714                       pipe_name(pipe), fb->width, fb->height,
7715                       fb->bits_per_pixel, base, fb->pitches[0],
7716                       plane_config->size);
7717
7718         plane_config->fb = intel_fb;
7719         return;
7720
7721 error:
7722         kfree(fb);
7723 }
7724
7725 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7726                                      struct intel_crtc_state *pipe_config)
7727 {
7728         struct drm_device *dev = crtc->base.dev;
7729         struct drm_i915_private *dev_priv = dev->dev_private;
7730         uint32_t tmp;
7731
7732         tmp = I915_READ(PF_CTL(crtc->pipe));
7733
7734         if (tmp & PF_ENABLE) {
7735                 pipe_config->pch_pfit.enabled = true;
7736                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7737                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7738
7739                 /* We currently do not free assignements of panel fitters on
7740                  * ivb/hsw (since we don't use the higher upscaling modes which
7741                  * differentiates them) so just WARN about this case for now. */
7742                 if (IS_GEN7(dev)) {
7743                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7744                                 PF_PIPE_SEL_IVB(crtc->pipe));
7745                 }
7746         }
7747 }
7748
7749 static void
7750 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7751                                   struct intel_initial_plane_config *plane_config)
7752 {
7753         struct drm_device *dev = crtc->base.dev;
7754         struct drm_i915_private *dev_priv = dev->dev_private;
7755         u32 val, base, offset;
7756         int pipe = crtc->pipe;
7757         int fourcc, pixel_format;
7758         int aligned_height;
7759         struct drm_framebuffer *fb;
7760         struct intel_framebuffer *intel_fb;
7761
7762         val = I915_READ(DSPCNTR(pipe));
7763         if (!(val & DISPLAY_PLANE_ENABLE))
7764                 return;
7765
7766         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7767         if (!intel_fb) {
7768                 DRM_DEBUG_KMS("failed to alloc fb\n");
7769                 return;
7770         }
7771
7772         fb = &intel_fb->base;
7773
7774         if (INTEL_INFO(dev)->gen >= 4) {
7775                 if (val & DISPPLANE_TILED) {
7776                         plane_config->tiling = I915_TILING_X;
7777                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7778                 }
7779         }
7780
7781         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7782         fourcc = i9xx_format_to_fourcc(pixel_format);
7783         fb->pixel_format = fourcc;
7784         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7785
7786         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7787         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7788                 offset = I915_READ(DSPOFFSET(pipe));
7789         } else {
7790                 if (plane_config->tiling)
7791                         offset = I915_READ(DSPTILEOFF(pipe));
7792                 else
7793                         offset = I915_READ(DSPLINOFF(pipe));
7794         }
7795         plane_config->base = base;
7796
7797         val = I915_READ(PIPESRC(pipe));
7798         fb->width = ((val >> 16) & 0xfff) + 1;
7799         fb->height = ((val >> 0) & 0xfff) + 1;
7800
7801         val = I915_READ(DSPSTRIDE(pipe));
7802         fb->pitches[0] = val & 0xffffffc0;
7803
7804         aligned_height = intel_fb_align_height(dev, fb->height,
7805                                                fb->pixel_format,
7806                                                fb->modifier[0]);
7807
7808         plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7809
7810         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7811                       pipe_name(pipe), fb->width, fb->height,
7812                       fb->bits_per_pixel, base, fb->pitches[0],
7813                       plane_config->size);
7814
7815         plane_config->fb = intel_fb;
7816 }
7817
7818 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7819                                      struct intel_crtc_state *pipe_config)
7820 {
7821         struct drm_device *dev = crtc->base.dev;
7822         struct drm_i915_private *dev_priv = dev->dev_private;
7823         uint32_t tmp;
7824
7825         if (!intel_display_power_is_enabled(dev_priv,
7826                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7827                 return false;
7828
7829         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7830         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7831
7832         tmp = I915_READ(PIPECONF(crtc->pipe));
7833         if (!(tmp & PIPECONF_ENABLE))
7834                 return false;
7835
7836         switch (tmp & PIPECONF_BPC_MASK) {
7837         case PIPECONF_6BPC:
7838                 pipe_config->pipe_bpp = 18;
7839                 break;
7840         case PIPECONF_8BPC:
7841                 pipe_config->pipe_bpp = 24;
7842                 break;
7843         case PIPECONF_10BPC:
7844                 pipe_config->pipe_bpp = 30;
7845                 break;
7846         case PIPECONF_12BPC:
7847                 pipe_config->pipe_bpp = 36;
7848                 break;
7849         default:
7850                 break;
7851         }
7852
7853         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7854                 pipe_config->limited_color_range = true;
7855
7856         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7857                 struct intel_shared_dpll *pll;
7858
7859                 pipe_config->has_pch_encoder = true;
7860
7861                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7862                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7863                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7864
7865                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7866
7867                 if (HAS_PCH_IBX(dev_priv->dev)) {
7868                         pipe_config->shared_dpll =
7869                                 (enum intel_dpll_id) crtc->pipe;
7870                 } else {
7871                         tmp = I915_READ(PCH_DPLL_SEL);
7872                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7873                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7874                         else
7875                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7876                 }
7877
7878                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7879
7880                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7881                                            &pipe_config->dpll_hw_state));
7882
7883                 tmp = pipe_config->dpll_hw_state.dpll;
7884                 pipe_config->pixel_multiplier =
7885                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7886                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7887
7888                 ironlake_pch_clock_get(crtc, pipe_config);
7889         } else {
7890                 pipe_config->pixel_multiplier = 1;
7891         }
7892
7893         intel_get_pipe_timings(crtc, pipe_config);
7894
7895         ironlake_get_pfit_config(crtc, pipe_config);
7896
7897         return true;
7898 }
7899
7900 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7901 {
7902         struct drm_device *dev = dev_priv->dev;
7903         struct intel_crtc *crtc;
7904
7905         for_each_intel_crtc(dev, crtc)
7906                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7907                      pipe_name(crtc->pipe));
7908
7909         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7910         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7911         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7912         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7913         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7914         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7915              "CPU PWM1 enabled\n");
7916         if (IS_HASWELL(dev))
7917                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7918                      "CPU PWM2 enabled\n");
7919         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7920              "PCH PWM1 enabled\n");
7921         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7922              "Utility pin enabled\n");
7923         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7924
7925         /*
7926          * In theory we can still leave IRQs enabled, as long as only the HPD
7927          * interrupts remain enabled. We used to check for that, but since it's
7928          * gen-specific and since we only disable LCPLL after we fully disable
7929          * the interrupts, the check below should be enough.
7930          */
7931         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7932 }
7933
7934 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7935 {
7936         struct drm_device *dev = dev_priv->dev;
7937
7938         if (IS_HASWELL(dev))
7939                 return I915_READ(D_COMP_HSW);
7940         else
7941                 return I915_READ(D_COMP_BDW);
7942 }
7943
7944 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7945 {
7946         struct drm_device *dev = dev_priv->dev;
7947
7948         if (IS_HASWELL(dev)) {
7949                 mutex_lock(&dev_priv->rps.hw_lock);
7950                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7951                                             val))
7952                         DRM_ERROR("Failed to write to D_COMP\n");
7953                 mutex_unlock(&dev_priv->rps.hw_lock);
7954         } else {
7955                 I915_WRITE(D_COMP_BDW, val);
7956                 POSTING_READ(D_COMP_BDW);
7957         }
7958 }
7959
7960 /*
7961  * This function implements pieces of two sequences from BSpec:
7962  * - Sequence for display software to disable LCPLL
7963  * - Sequence for display software to allow package C8+
7964  * The steps implemented here are just the steps that actually touch the LCPLL
7965  * register. Callers should take care of disabling all the display engine
7966  * functions, doing the mode unset, fixing interrupts, etc.
7967  */
7968 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7969                               bool switch_to_fclk, bool allow_power_down)
7970 {
7971         uint32_t val;
7972
7973         assert_can_disable_lcpll(dev_priv);
7974
7975         val = I915_READ(LCPLL_CTL);
7976
7977         if (switch_to_fclk) {
7978                 val |= LCPLL_CD_SOURCE_FCLK;
7979                 I915_WRITE(LCPLL_CTL, val);
7980
7981                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7982                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7983                         DRM_ERROR("Switching to FCLK failed\n");
7984
7985                 val = I915_READ(LCPLL_CTL);
7986         }
7987
7988         val |= LCPLL_PLL_DISABLE;
7989         I915_WRITE(LCPLL_CTL, val);
7990         POSTING_READ(LCPLL_CTL);
7991
7992         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7993                 DRM_ERROR("LCPLL still locked\n");
7994
7995         val = hsw_read_dcomp(dev_priv);
7996         val |= D_COMP_COMP_DISABLE;
7997         hsw_write_dcomp(dev_priv, val);
7998         ndelay(100);
7999
8000         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8001                      1))
8002                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8003
8004         if (allow_power_down) {
8005                 val = I915_READ(LCPLL_CTL);
8006                 val |= LCPLL_POWER_DOWN_ALLOW;
8007                 I915_WRITE(LCPLL_CTL, val);
8008                 POSTING_READ(LCPLL_CTL);
8009         }
8010 }
8011
8012 /*
8013  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8014  * source.
8015  */
8016 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8017 {
8018         uint32_t val;
8019
8020         val = I915_READ(LCPLL_CTL);
8021
8022         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8023                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8024                 return;
8025
8026         /*
8027          * Make sure we're not on PC8 state before disabling PC8, otherwise
8028          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8029          */
8030         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8031
8032         if (val & LCPLL_POWER_DOWN_ALLOW) {
8033                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8034                 I915_WRITE(LCPLL_CTL, val);
8035                 POSTING_READ(LCPLL_CTL);
8036         }
8037
8038         val = hsw_read_dcomp(dev_priv);
8039         val |= D_COMP_COMP_FORCE;
8040         val &= ~D_COMP_COMP_DISABLE;
8041         hsw_write_dcomp(dev_priv, val);
8042
8043         val = I915_READ(LCPLL_CTL);
8044         val &= ~LCPLL_PLL_DISABLE;
8045         I915_WRITE(LCPLL_CTL, val);
8046
8047         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8048                 DRM_ERROR("LCPLL not locked yet\n");
8049
8050         if (val & LCPLL_CD_SOURCE_FCLK) {
8051                 val = I915_READ(LCPLL_CTL);
8052                 val &= ~LCPLL_CD_SOURCE_FCLK;
8053                 I915_WRITE(LCPLL_CTL, val);
8054
8055                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8056                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8057                         DRM_ERROR("Switching back to LCPLL failed\n");
8058         }
8059
8060         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8061 }
8062
8063 /*
8064  * Package states C8 and deeper are really deep PC states that can only be
8065  * reached when all the devices on the system allow it, so even if the graphics
8066  * device allows PC8+, it doesn't mean the system will actually get to these
8067  * states. Our driver only allows PC8+ when going into runtime PM.
8068  *
8069  * The requirements for PC8+ are that all the outputs are disabled, the power
8070  * well is disabled and most interrupts are disabled, and these are also
8071  * requirements for runtime PM. When these conditions are met, we manually do
8072  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8073  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8074  * hang the machine.
8075  *
8076  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8077  * the state of some registers, so when we come back from PC8+ we need to
8078  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8079  * need to take care of the registers kept by RC6. Notice that this happens even
8080  * if we don't put the device in PCI D3 state (which is what currently happens
8081  * because of the runtime PM support).
8082  *
8083  * For more, read "Display Sequences for Package C8" on the hardware
8084  * documentation.
8085  */
8086 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8087 {
8088         struct drm_device *dev = dev_priv->dev;
8089         uint32_t val;
8090
8091         DRM_DEBUG_KMS("Enabling package C8+\n");
8092
8093         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8094                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8095                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8096                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8097         }
8098
8099         lpt_disable_clkout_dp(dev);
8100         hsw_disable_lcpll(dev_priv, true, true);
8101 }
8102
8103 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8104 {
8105         struct drm_device *dev = dev_priv->dev;
8106         uint32_t val;
8107
8108         DRM_DEBUG_KMS("Disabling package C8+\n");
8109
8110         hsw_restore_lcpll(dev_priv);
8111         lpt_init_pch_refclk(dev);
8112
8113         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8114                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8115                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8116                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8117         }
8118
8119         intel_prepare_ddi(dev);
8120 }
8121
8122 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8123                                       struct intel_crtc_state *crtc_state)
8124 {
8125         if (!intel_ddi_pll_select(crtc, crtc_state))
8126                 return -EINVAL;
8127
8128         crtc->lowfreq_avail = false;
8129
8130         return 0;
8131 }
8132
8133 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8134                                 enum port port,
8135                                 struct intel_crtc_state *pipe_config)
8136 {
8137         u32 temp, dpll_ctl1;
8138
8139         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8140         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8141
8142         switch (pipe_config->ddi_pll_sel) {
8143         case SKL_DPLL0:
8144                 /*
8145                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8146                  * of the shared DPLL framework and thus needs to be read out
8147                  * separately
8148                  */
8149                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8150                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8151                 break;
8152         case SKL_DPLL1:
8153                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8154                 break;
8155         case SKL_DPLL2:
8156                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8157                 break;
8158         case SKL_DPLL3:
8159                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8160                 break;
8161         }
8162 }
8163
8164 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8165                                 enum port port,
8166                                 struct intel_crtc_state *pipe_config)
8167 {
8168         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8169
8170         switch (pipe_config->ddi_pll_sel) {
8171         case PORT_CLK_SEL_WRPLL1:
8172                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8173                 break;
8174         case PORT_CLK_SEL_WRPLL2:
8175                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8176                 break;
8177         }
8178 }
8179
8180 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8181                                        struct intel_crtc_state *pipe_config)
8182 {
8183         struct drm_device *dev = crtc->base.dev;
8184         struct drm_i915_private *dev_priv = dev->dev_private;
8185         struct intel_shared_dpll *pll;
8186         enum port port;
8187         uint32_t tmp;
8188
8189         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8190
8191         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8192
8193         if (IS_SKYLAKE(dev))
8194                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8195         else
8196                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8197
8198         if (pipe_config->shared_dpll >= 0) {
8199                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8200
8201                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8202                                            &pipe_config->dpll_hw_state));
8203         }
8204
8205         /*
8206          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8207          * DDI E. So just check whether this pipe is wired to DDI E and whether
8208          * the PCH transcoder is on.
8209          */
8210         if (INTEL_INFO(dev)->gen < 9 &&
8211             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8212                 pipe_config->has_pch_encoder = true;
8213
8214                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8215                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8216                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8217
8218                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8219         }
8220 }
8221
8222 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8223                                     struct intel_crtc_state *pipe_config)
8224 {
8225         struct drm_device *dev = crtc->base.dev;
8226         struct drm_i915_private *dev_priv = dev->dev_private;
8227         enum intel_display_power_domain pfit_domain;
8228         uint32_t tmp;
8229
8230         if (!intel_display_power_is_enabled(dev_priv,
8231                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8232                 return false;
8233
8234         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8235         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8236
8237         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8238         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8239                 enum pipe trans_edp_pipe;
8240                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8241                 default:
8242                         WARN(1, "unknown pipe linked to edp transcoder\n");
8243                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8244                 case TRANS_DDI_EDP_INPUT_A_ON:
8245                         trans_edp_pipe = PIPE_A;
8246                         break;
8247                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8248                         trans_edp_pipe = PIPE_B;
8249                         break;
8250                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8251                         trans_edp_pipe = PIPE_C;
8252                         break;
8253                 }
8254
8255                 if (trans_edp_pipe == crtc->pipe)
8256                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8257         }
8258
8259         if (!intel_display_power_is_enabled(dev_priv,
8260                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8261                 return false;
8262
8263         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8264         if (!(tmp & PIPECONF_ENABLE))
8265                 return false;
8266
8267         haswell_get_ddi_port_state(crtc, pipe_config);
8268
8269         intel_get_pipe_timings(crtc, pipe_config);
8270
8271         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8272         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8273                 if (IS_SKYLAKE(dev))
8274                         skylake_get_pfit_config(crtc, pipe_config);
8275                 else
8276                         ironlake_get_pfit_config(crtc, pipe_config);
8277         }
8278
8279         if (IS_HASWELL(dev))
8280                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8281                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8282
8283         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8284                 pipe_config->pixel_multiplier =
8285                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8286         } else {
8287                 pipe_config->pixel_multiplier = 1;
8288         }
8289
8290         return true;
8291 }
8292
8293 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8294 {
8295         struct drm_device *dev = crtc->dev;
8296         struct drm_i915_private *dev_priv = dev->dev_private;
8297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8298         uint32_t cntl = 0, size = 0;
8299
8300         if (base) {
8301                 unsigned int width = intel_crtc->cursor_width;
8302                 unsigned int height = intel_crtc->cursor_height;
8303                 unsigned int stride = roundup_pow_of_two(width) * 4;
8304
8305                 switch (stride) {
8306                 default:
8307                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8308                                   width, stride);
8309                         stride = 256;
8310                         /* fallthrough */
8311                 case 256:
8312                 case 512:
8313                 case 1024:
8314                 case 2048:
8315                         break;
8316                 }
8317
8318                 cntl |= CURSOR_ENABLE |
8319                         CURSOR_GAMMA_ENABLE |
8320                         CURSOR_FORMAT_ARGB |
8321                         CURSOR_STRIDE(stride);
8322
8323                 size = (height << 12) | width;
8324         }
8325
8326         if (intel_crtc->cursor_cntl != 0 &&
8327             (intel_crtc->cursor_base != base ||
8328              intel_crtc->cursor_size != size ||
8329              intel_crtc->cursor_cntl != cntl)) {
8330                 /* On these chipsets we can only modify the base/size/stride
8331                  * whilst the cursor is disabled.
8332                  */
8333                 I915_WRITE(_CURACNTR, 0);
8334                 POSTING_READ(_CURACNTR);
8335                 intel_crtc->cursor_cntl = 0;
8336         }
8337
8338         if (intel_crtc->cursor_base != base) {
8339                 I915_WRITE(_CURABASE, base);
8340                 intel_crtc->cursor_base = base;
8341         }
8342
8343         if (intel_crtc->cursor_size != size) {
8344                 I915_WRITE(CURSIZE, size);
8345                 intel_crtc->cursor_size = size;
8346         }
8347
8348         if (intel_crtc->cursor_cntl != cntl) {
8349                 I915_WRITE(_CURACNTR, cntl);
8350                 POSTING_READ(_CURACNTR);
8351                 intel_crtc->cursor_cntl = cntl;
8352         }
8353 }
8354
8355 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8356 {
8357         struct drm_device *dev = crtc->dev;
8358         struct drm_i915_private *dev_priv = dev->dev_private;
8359         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8360         int pipe = intel_crtc->pipe;
8361         uint32_t cntl;
8362
8363         cntl = 0;
8364         if (base) {
8365                 cntl = MCURSOR_GAMMA_ENABLE;
8366                 switch (intel_crtc->cursor_width) {
8367                         case 64:
8368                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8369                                 break;
8370                         case 128:
8371                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8372                                 break;
8373                         case 256:
8374                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8375                                 break;
8376                         default:
8377                                 MISSING_CASE(intel_crtc->cursor_width);
8378                                 return;
8379                 }
8380                 cntl |= pipe << 28; /* Connect to correct pipe */
8381
8382                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8383                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8384         }
8385
8386         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8387                 cntl |= CURSOR_ROTATE_180;
8388
8389         if (intel_crtc->cursor_cntl != cntl) {
8390                 I915_WRITE(CURCNTR(pipe), cntl);
8391                 POSTING_READ(CURCNTR(pipe));
8392                 intel_crtc->cursor_cntl = cntl;
8393         }
8394
8395         /* and commit changes on next vblank */
8396         I915_WRITE(CURBASE(pipe), base);
8397         POSTING_READ(CURBASE(pipe));
8398
8399         intel_crtc->cursor_base = base;
8400 }
8401
8402 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8403 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8404                                      bool on)
8405 {
8406         struct drm_device *dev = crtc->dev;
8407         struct drm_i915_private *dev_priv = dev->dev_private;
8408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8409         int pipe = intel_crtc->pipe;
8410         int x = crtc->cursor_x;
8411         int y = crtc->cursor_y;
8412         u32 base = 0, pos = 0;
8413
8414         if (on)
8415                 base = intel_crtc->cursor_addr;
8416
8417         if (x >= intel_crtc->config->pipe_src_w)
8418                 base = 0;
8419
8420         if (y >= intel_crtc->config->pipe_src_h)
8421                 base = 0;
8422
8423         if (x < 0) {
8424                 if (x + intel_crtc->cursor_width <= 0)
8425                         base = 0;
8426
8427                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8428                 x = -x;
8429         }
8430         pos |= x << CURSOR_X_SHIFT;
8431
8432         if (y < 0) {
8433                 if (y + intel_crtc->cursor_height <= 0)
8434                         base = 0;
8435
8436                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8437                 y = -y;
8438         }
8439         pos |= y << CURSOR_Y_SHIFT;
8440
8441         if (base == 0 && intel_crtc->cursor_base == 0)
8442                 return;
8443
8444         I915_WRITE(CURPOS(pipe), pos);
8445
8446         /* ILK+ do this automagically */
8447         if (HAS_GMCH_DISPLAY(dev) &&
8448             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8449                 base += (intel_crtc->cursor_height *
8450                         intel_crtc->cursor_width - 1) * 4;
8451         }
8452
8453         if (IS_845G(dev) || IS_I865G(dev))
8454                 i845_update_cursor(crtc, base);
8455         else
8456                 i9xx_update_cursor(crtc, base);
8457 }
8458
8459 static bool cursor_size_ok(struct drm_device *dev,
8460                            uint32_t width, uint32_t height)
8461 {
8462         if (width == 0 || height == 0)
8463                 return false;
8464
8465         /*
8466          * 845g/865g are special in that they are only limited by
8467          * the width of their cursors, the height is arbitrary up to
8468          * the precision of the register. Everything else requires
8469          * square cursors, limited to a few power-of-two sizes.
8470          */
8471         if (IS_845G(dev) || IS_I865G(dev)) {
8472                 if ((width & 63) != 0)
8473                         return false;
8474
8475                 if (width > (IS_845G(dev) ? 64 : 512))
8476                         return false;
8477
8478                 if (height > 1023)
8479                         return false;
8480         } else {
8481                 switch (width | height) {
8482                 case 256:
8483                 case 128:
8484                         if (IS_GEN2(dev))
8485                                 return false;
8486                 case 64:
8487                         break;
8488                 default:
8489                         return false;
8490                 }
8491         }
8492
8493         return true;
8494 }
8495
8496 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8497                                  u16 *blue, uint32_t start, uint32_t size)
8498 {
8499         int end = (start + size > 256) ? 256 : start + size, i;
8500         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8501
8502         for (i = start; i < end; i++) {
8503                 intel_crtc->lut_r[i] = red[i] >> 8;
8504                 intel_crtc->lut_g[i] = green[i] >> 8;
8505                 intel_crtc->lut_b[i] = blue[i] >> 8;
8506         }
8507
8508         intel_crtc_load_lut(crtc);
8509 }
8510
8511 /* VESA 640x480x72Hz mode to set on the pipe */
8512 static struct drm_display_mode load_detect_mode = {
8513         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8514                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8515 };
8516
8517 struct drm_framebuffer *
8518 __intel_framebuffer_create(struct drm_device *dev,
8519                            struct drm_mode_fb_cmd2 *mode_cmd,
8520                            struct drm_i915_gem_object *obj)
8521 {
8522         struct intel_framebuffer *intel_fb;
8523         int ret;
8524
8525         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8526         if (!intel_fb) {
8527                 drm_gem_object_unreference(&obj->base);
8528                 return ERR_PTR(-ENOMEM);
8529         }
8530
8531         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8532         if (ret)
8533                 goto err;
8534
8535         return &intel_fb->base;
8536 err:
8537         drm_gem_object_unreference(&obj->base);
8538         kfree(intel_fb);
8539
8540         return ERR_PTR(ret);
8541 }
8542
8543 static struct drm_framebuffer *
8544 intel_framebuffer_create(struct drm_device *dev,
8545                          struct drm_mode_fb_cmd2 *mode_cmd,
8546                          struct drm_i915_gem_object *obj)
8547 {
8548         struct drm_framebuffer *fb;
8549         int ret;
8550
8551         ret = i915_mutex_lock_interruptible(dev);
8552         if (ret)
8553                 return ERR_PTR(ret);
8554         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8555         mutex_unlock(&dev->struct_mutex);
8556
8557         return fb;
8558 }
8559
8560 static u32
8561 intel_framebuffer_pitch_for_width(int width, int bpp)
8562 {
8563         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8564         return ALIGN(pitch, 64);
8565 }
8566
8567 static u32
8568 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8569 {
8570         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8571         return PAGE_ALIGN(pitch * mode->vdisplay);
8572 }
8573
8574 static struct drm_framebuffer *
8575 intel_framebuffer_create_for_mode(struct drm_device *dev,
8576                                   struct drm_display_mode *mode,
8577                                   int depth, int bpp)
8578 {
8579         struct drm_i915_gem_object *obj;
8580         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8581
8582         obj = i915_gem_alloc_object(dev,
8583                                     intel_framebuffer_size_for_mode(mode, bpp));
8584         if (obj == NULL)
8585                 return ERR_PTR(-ENOMEM);
8586
8587         mode_cmd.width = mode->hdisplay;
8588         mode_cmd.height = mode->vdisplay;
8589         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8590                                                                 bpp);
8591         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8592
8593         return intel_framebuffer_create(dev, &mode_cmd, obj);
8594 }
8595
8596 static struct drm_framebuffer *
8597 mode_fits_in_fbdev(struct drm_device *dev,
8598                    struct drm_display_mode *mode)
8599 {
8600 #ifdef CONFIG_DRM_I915_FBDEV
8601         struct drm_i915_private *dev_priv = dev->dev_private;
8602         struct drm_i915_gem_object *obj;
8603         struct drm_framebuffer *fb;
8604
8605         if (!dev_priv->fbdev)
8606                 return NULL;
8607
8608         if (!dev_priv->fbdev->fb)
8609                 return NULL;
8610
8611         obj = dev_priv->fbdev->fb->obj;
8612         BUG_ON(!obj);
8613
8614         fb = &dev_priv->fbdev->fb->base;
8615         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8616                                                                fb->bits_per_pixel))
8617                 return NULL;
8618
8619         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8620                 return NULL;
8621
8622         return fb;
8623 #else
8624         return NULL;
8625 #endif
8626 }
8627
8628 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8629                                 struct drm_display_mode *mode,
8630                                 struct intel_load_detect_pipe *old,
8631                                 struct drm_modeset_acquire_ctx *ctx)
8632 {
8633         struct intel_crtc *intel_crtc;
8634         struct intel_encoder *intel_encoder =
8635                 intel_attached_encoder(connector);
8636         struct drm_crtc *possible_crtc;
8637         struct drm_encoder *encoder = &intel_encoder->base;
8638         struct drm_crtc *crtc = NULL;
8639         struct drm_device *dev = encoder->dev;
8640         struct drm_framebuffer *fb;
8641         struct drm_mode_config *config = &dev->mode_config;
8642         int ret, i = -1;
8643
8644         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8645                       connector->base.id, connector->name,
8646                       encoder->base.id, encoder->name);
8647
8648 retry:
8649         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8650         if (ret)
8651                 goto fail_unlock;
8652
8653         /*
8654          * Algorithm gets a little messy:
8655          *
8656          *   - if the connector already has an assigned crtc, use it (but make
8657          *     sure it's on first)
8658          *
8659          *   - try to find the first unused crtc that can drive this connector,
8660          *     and use that if we find one
8661          */
8662
8663         /* See if we already have a CRTC for this connector */
8664         if (encoder->crtc) {
8665                 crtc = encoder->crtc;
8666
8667                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8668                 if (ret)
8669                         goto fail_unlock;
8670                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8671                 if (ret)
8672                         goto fail_unlock;
8673
8674                 old->dpms_mode = connector->dpms;
8675                 old->load_detect_temp = false;
8676
8677                 /* Make sure the crtc and connector are running */
8678                 if (connector->dpms != DRM_MODE_DPMS_ON)
8679                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8680
8681                 return true;
8682         }
8683
8684         /* Find an unused one (if possible) */
8685         for_each_crtc(dev, possible_crtc) {
8686                 i++;
8687                 if (!(encoder->possible_crtcs & (1 << i)))
8688                         continue;
8689                 if (possible_crtc->enabled)
8690                         continue;
8691                 /* This can occur when applying the pipe A quirk on resume. */
8692                 if (to_intel_crtc(possible_crtc)->new_enabled)
8693                         continue;
8694
8695                 crtc = possible_crtc;
8696                 break;
8697         }
8698
8699         /*
8700          * If we didn't find an unused CRTC, don't use any.
8701          */
8702         if (!crtc) {
8703                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8704                 goto fail_unlock;
8705         }
8706
8707         ret = drm_modeset_lock(&crtc->mutex, ctx);
8708         if (ret)
8709                 goto fail_unlock;
8710         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8711         if (ret)
8712                 goto fail_unlock;
8713         intel_encoder->new_crtc = to_intel_crtc(crtc);
8714         to_intel_connector(connector)->new_encoder = intel_encoder;
8715
8716         intel_crtc = to_intel_crtc(crtc);
8717         intel_crtc->new_enabled = true;
8718         intel_crtc->new_config = intel_crtc->config;
8719         old->dpms_mode = connector->dpms;
8720         old->load_detect_temp = true;
8721         old->release_fb = NULL;
8722
8723         if (!mode)
8724                 mode = &load_detect_mode;
8725
8726         /* We need a framebuffer large enough to accommodate all accesses
8727          * that the plane may generate whilst we perform load detection.
8728          * We can not rely on the fbcon either being present (we get called
8729          * during its initialisation to detect all boot displays, or it may
8730          * not even exist) or that it is large enough to satisfy the
8731          * requested mode.
8732          */
8733         fb = mode_fits_in_fbdev(dev, mode);
8734         if (fb == NULL) {
8735                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8736                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8737                 old->release_fb = fb;
8738         } else
8739                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8740         if (IS_ERR(fb)) {
8741                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8742                 goto fail;
8743         }
8744
8745         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8746                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8747                 if (old->release_fb)
8748                         old->release_fb->funcs->destroy(old->release_fb);
8749                 goto fail;
8750         }
8751
8752         /* let the connector get through one full cycle before testing */
8753         intel_wait_for_vblank(dev, intel_crtc->pipe);
8754         return true;
8755
8756  fail:
8757         intel_crtc->new_enabled = crtc->enabled;
8758         if (intel_crtc->new_enabled)
8759                 intel_crtc->new_config = intel_crtc->config;
8760         else
8761                 intel_crtc->new_config = NULL;
8762 fail_unlock:
8763         if (ret == -EDEADLK) {
8764                 drm_modeset_backoff(ctx);
8765                 goto retry;
8766         }
8767
8768         return false;
8769 }
8770
8771 void intel_release_load_detect_pipe(struct drm_connector *connector,
8772                                     struct intel_load_detect_pipe *old)
8773 {
8774         struct intel_encoder *intel_encoder =
8775                 intel_attached_encoder(connector);
8776         struct drm_encoder *encoder = &intel_encoder->base;
8777         struct drm_crtc *crtc = encoder->crtc;
8778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8779
8780         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8781                       connector->base.id, connector->name,
8782                       encoder->base.id, encoder->name);
8783
8784         if (old->load_detect_temp) {
8785                 to_intel_connector(connector)->new_encoder = NULL;
8786                 intel_encoder->new_crtc = NULL;
8787                 intel_crtc->new_enabled = false;
8788                 intel_crtc->new_config = NULL;
8789                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8790
8791                 if (old->release_fb) {
8792                         drm_framebuffer_unregister_private(old->release_fb);
8793                         drm_framebuffer_unreference(old->release_fb);
8794                 }
8795
8796                 return;
8797         }
8798
8799         /* Switch crtc and encoder back off if necessary */
8800         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8801                 connector->funcs->dpms(connector, old->dpms_mode);
8802 }
8803
8804 static int i9xx_pll_refclk(struct drm_device *dev,
8805                            const struct intel_crtc_state *pipe_config)
8806 {
8807         struct drm_i915_private *dev_priv = dev->dev_private;
8808         u32 dpll = pipe_config->dpll_hw_state.dpll;
8809
8810         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8811                 return dev_priv->vbt.lvds_ssc_freq;
8812         else if (HAS_PCH_SPLIT(dev))
8813                 return 120000;
8814         else if (!IS_GEN2(dev))
8815                 return 96000;
8816         else
8817                 return 48000;
8818 }
8819
8820 /* Returns the clock of the currently programmed mode of the given pipe. */
8821 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8822                                 struct intel_crtc_state *pipe_config)
8823 {
8824         struct drm_device *dev = crtc->base.dev;
8825         struct drm_i915_private *dev_priv = dev->dev_private;
8826         int pipe = pipe_config->cpu_transcoder;
8827         u32 dpll = pipe_config->dpll_hw_state.dpll;
8828         u32 fp;
8829         intel_clock_t clock;
8830         int refclk = i9xx_pll_refclk(dev, pipe_config);
8831
8832         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8833                 fp = pipe_config->dpll_hw_state.fp0;
8834         else
8835                 fp = pipe_config->dpll_hw_state.fp1;
8836
8837         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8838         if (IS_PINEVIEW(dev)) {
8839                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8840                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8841         } else {
8842                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8843                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8844         }
8845
8846         if (!IS_GEN2(dev)) {
8847                 if (IS_PINEVIEW(dev))
8848                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8849                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8850                 else
8851                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8852                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8853
8854                 switch (dpll & DPLL_MODE_MASK) {
8855                 case DPLLB_MODE_DAC_SERIAL:
8856                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8857                                 5 : 10;
8858                         break;
8859                 case DPLLB_MODE_LVDS:
8860                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8861                                 7 : 14;
8862                         break;
8863                 default:
8864                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8865                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8866                         return;
8867                 }
8868
8869                 if (IS_PINEVIEW(dev))
8870                         pineview_clock(refclk, &clock);
8871                 else
8872                         i9xx_clock(refclk, &clock);
8873         } else {
8874                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8875                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8876
8877                 if (is_lvds) {
8878                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8879                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8880
8881                         if (lvds & LVDS_CLKB_POWER_UP)
8882                                 clock.p2 = 7;
8883                         else
8884                                 clock.p2 = 14;
8885                 } else {
8886                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8887                                 clock.p1 = 2;
8888                         else {
8889                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8890                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8891                         }
8892                         if (dpll & PLL_P2_DIVIDE_BY_4)
8893                                 clock.p2 = 4;
8894                         else
8895                                 clock.p2 = 2;
8896                 }
8897
8898                 i9xx_clock(refclk, &clock);
8899         }
8900
8901         /*
8902          * This value includes pixel_multiplier. We will use
8903          * port_clock to compute adjusted_mode.crtc_clock in the
8904          * encoder's get_config() function.
8905          */
8906         pipe_config->port_clock = clock.dot;
8907 }
8908
8909 int intel_dotclock_calculate(int link_freq,
8910                              const struct intel_link_m_n *m_n)
8911 {
8912         /*
8913          * The calculation for the data clock is:
8914          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8915          * But we want to avoid losing precison if possible, so:
8916          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8917          *
8918          * and the link clock is simpler:
8919          * link_clock = (m * link_clock) / n
8920          */
8921
8922         if (!m_n->link_n)
8923                 return 0;
8924
8925         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8926 }
8927
8928 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8929                                    struct intel_crtc_state *pipe_config)
8930 {
8931         struct drm_device *dev = crtc->base.dev;
8932
8933         /* read out port_clock from the DPLL */
8934         i9xx_crtc_clock_get(crtc, pipe_config);
8935
8936         /*
8937          * This value does not include pixel_multiplier.
8938          * We will check that port_clock and adjusted_mode.crtc_clock
8939          * agree once we know their relationship in the encoder's
8940          * get_config() function.
8941          */
8942         pipe_config->base.adjusted_mode.crtc_clock =
8943                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8944                                          &pipe_config->fdi_m_n);
8945 }
8946
8947 /** Returns the currently programmed mode of the given pipe. */
8948 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8949                                              struct drm_crtc *crtc)
8950 {
8951         struct drm_i915_private *dev_priv = dev->dev_private;
8952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8953         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8954         struct drm_display_mode *mode;
8955         struct intel_crtc_state pipe_config;
8956         int htot = I915_READ(HTOTAL(cpu_transcoder));
8957         int hsync = I915_READ(HSYNC(cpu_transcoder));
8958         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8959         int vsync = I915_READ(VSYNC(cpu_transcoder));
8960         enum pipe pipe = intel_crtc->pipe;
8961
8962         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8963         if (!mode)
8964                 return NULL;
8965
8966         /*
8967          * Construct a pipe_config sufficient for getting the clock info
8968          * back out of crtc_clock_get.
8969          *
8970          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8971          * to use a real value here instead.
8972          */
8973         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8974         pipe_config.pixel_multiplier = 1;
8975         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8976         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8977         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8978         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8979
8980         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8981         mode->hdisplay = (htot & 0xffff) + 1;
8982         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8983         mode->hsync_start = (hsync & 0xffff) + 1;
8984         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8985         mode->vdisplay = (vtot & 0xffff) + 1;
8986         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8987         mode->vsync_start = (vsync & 0xffff) + 1;
8988         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8989
8990         drm_mode_set_name(mode);
8991
8992         return mode;
8993 }
8994
8995 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8996 {
8997         struct drm_device *dev = crtc->dev;
8998         struct drm_i915_private *dev_priv = dev->dev_private;
8999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9000
9001         if (!HAS_GMCH_DISPLAY(dev))
9002                 return;
9003
9004         if (!dev_priv->lvds_downclock_avail)
9005                 return;
9006
9007         /*
9008          * Since this is called by a timer, we should never get here in
9009          * the manual case.
9010          */
9011         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9012                 int pipe = intel_crtc->pipe;
9013                 int dpll_reg = DPLL(pipe);
9014                 int dpll;
9015
9016                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9017
9018                 assert_panel_unlocked(dev_priv, pipe);
9019
9020                 dpll = I915_READ(dpll_reg);
9021                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9022                 I915_WRITE(dpll_reg, dpll);
9023                 intel_wait_for_vblank(dev, pipe);
9024                 dpll = I915_READ(dpll_reg);
9025                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9026                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9027         }
9028
9029 }
9030
9031 void intel_mark_busy(struct drm_device *dev)
9032 {
9033         struct drm_i915_private *dev_priv = dev->dev_private;
9034
9035         if (dev_priv->mm.busy)
9036                 return;
9037
9038         intel_runtime_pm_get(dev_priv);
9039         i915_update_gfx_val(dev_priv);
9040         dev_priv->mm.busy = true;
9041 }
9042
9043 void intel_mark_idle(struct drm_device *dev)
9044 {
9045         struct drm_i915_private *dev_priv = dev->dev_private;
9046         struct drm_crtc *crtc;
9047
9048         if (!dev_priv->mm.busy)
9049                 return;
9050
9051         dev_priv->mm.busy = false;
9052
9053         if (!i915.powersave)
9054                 goto out;
9055
9056         for_each_crtc(dev, crtc) {
9057                 if (!crtc->primary->fb)
9058                         continue;
9059
9060                 intel_decrease_pllclock(crtc);
9061         }
9062
9063         if (INTEL_INFO(dev)->gen >= 6)
9064                 gen6_rps_idle(dev->dev_private);
9065
9066 out:
9067         intel_runtime_pm_put(dev_priv);
9068 }
9069
9070 static void intel_crtc_set_state(struct intel_crtc *crtc,
9071                                  struct intel_crtc_state *crtc_state)
9072 {
9073         kfree(crtc->config);
9074         crtc->config = crtc_state;
9075         crtc->base.state = &crtc_state->base;
9076 }
9077
9078 static void intel_crtc_destroy(struct drm_crtc *crtc)
9079 {
9080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9081         struct drm_device *dev = crtc->dev;
9082         struct intel_unpin_work *work;
9083
9084         spin_lock_irq(&dev->event_lock);
9085         work = intel_crtc->unpin_work;
9086         intel_crtc->unpin_work = NULL;
9087         spin_unlock_irq(&dev->event_lock);
9088
9089         if (work) {
9090                 cancel_work_sync(&work->work);
9091                 kfree(work);
9092         }
9093
9094         intel_crtc_set_state(intel_crtc, NULL);
9095         drm_crtc_cleanup(crtc);
9096
9097         kfree(intel_crtc);
9098 }
9099
9100 static void intel_unpin_work_fn(struct work_struct *__work)
9101 {
9102         struct intel_unpin_work *work =
9103                 container_of(__work, struct intel_unpin_work, work);
9104         struct drm_device *dev = work->crtc->dev;
9105         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9106
9107         mutex_lock(&dev->struct_mutex);
9108         intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9109         drm_gem_object_unreference(&work->pending_flip_obj->base);
9110         drm_framebuffer_unreference(work->old_fb);
9111
9112         intel_fbc_update(dev);
9113
9114         if (work->flip_queued_req)
9115                 i915_gem_request_assign(&work->flip_queued_req, NULL);
9116         mutex_unlock(&dev->struct_mutex);
9117
9118         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9119
9120         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9121         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9122
9123         kfree(work);
9124 }
9125
9126 static void do_intel_finish_page_flip(struct drm_device *dev,
9127                                       struct drm_crtc *crtc)
9128 {
9129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9130         struct intel_unpin_work *work;
9131         unsigned long flags;
9132
9133         /* Ignore early vblank irqs */
9134         if (intel_crtc == NULL)
9135                 return;
9136
9137         /*
9138          * This is called both by irq handlers and the reset code (to complete
9139          * lost pageflips) so needs the full irqsave spinlocks.
9140          */
9141         spin_lock_irqsave(&dev->event_lock, flags);
9142         work = intel_crtc->unpin_work;
9143
9144         /* Ensure we don't miss a work->pending update ... */
9145         smp_rmb();
9146
9147         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9148                 spin_unlock_irqrestore(&dev->event_lock, flags);
9149                 return;
9150         }
9151
9152         page_flip_completed(intel_crtc);
9153
9154         spin_unlock_irqrestore(&dev->event_lock, flags);
9155 }
9156
9157 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9158 {
9159         struct drm_i915_private *dev_priv = dev->dev_private;
9160         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9161
9162         do_intel_finish_page_flip(dev, crtc);
9163 }
9164
9165 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9166 {
9167         struct drm_i915_private *dev_priv = dev->dev_private;
9168         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9169
9170         do_intel_finish_page_flip(dev, crtc);
9171 }
9172
9173 /* Is 'a' after or equal to 'b'? */
9174 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9175 {
9176         return !((a - b) & 0x80000000);
9177 }
9178
9179 static bool page_flip_finished(struct intel_crtc *crtc)
9180 {
9181         struct drm_device *dev = crtc->base.dev;
9182         struct drm_i915_private *dev_priv = dev->dev_private;
9183
9184         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9185             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9186                 return true;
9187
9188         /*
9189          * The relevant registers doen't exist on pre-ctg.
9190          * As the flip done interrupt doesn't trigger for mmio
9191          * flips on gmch platforms, a flip count check isn't
9192          * really needed there. But since ctg has the registers,
9193          * include it in the check anyway.
9194          */
9195         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9196                 return true;
9197
9198         /*
9199          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9200          * used the same base address. In that case the mmio flip might
9201          * have completed, but the CS hasn't even executed the flip yet.
9202          *
9203          * A flip count check isn't enough as the CS might have updated
9204          * the base address just after start of vblank, but before we
9205          * managed to process the interrupt. This means we'd complete the
9206          * CS flip too soon.
9207          *
9208          * Combining both checks should get us a good enough result. It may
9209          * still happen that the CS flip has been executed, but has not
9210          * yet actually completed. But in case the base address is the same
9211          * anyway, we don't really care.
9212          */
9213         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9214                 crtc->unpin_work->gtt_offset &&
9215                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9216                                     crtc->unpin_work->flip_count);
9217 }
9218
9219 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9220 {
9221         struct drm_i915_private *dev_priv = dev->dev_private;
9222         struct intel_crtc *intel_crtc =
9223                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9224         unsigned long flags;
9225
9226
9227         /*
9228          * This is called both by irq handlers and the reset code (to complete
9229          * lost pageflips) so needs the full irqsave spinlocks.
9230          *
9231          * NB: An MMIO update of the plane base pointer will also
9232          * generate a page-flip completion irq, i.e. every modeset
9233          * is also accompanied by a spurious intel_prepare_page_flip().
9234          */
9235         spin_lock_irqsave(&dev->event_lock, flags);
9236         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9237                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9238         spin_unlock_irqrestore(&dev->event_lock, flags);
9239 }
9240
9241 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9242 {
9243         /* Ensure that the work item is consistent when activating it ... */
9244         smp_wmb();
9245         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9246         /* and that it is marked active as soon as the irq could fire. */
9247         smp_wmb();
9248 }
9249
9250 static int intel_gen2_queue_flip(struct drm_device *dev,
9251                                  struct drm_crtc *crtc,
9252                                  struct drm_framebuffer *fb,
9253                                  struct drm_i915_gem_object *obj,
9254                                  struct intel_engine_cs *ring,
9255                                  uint32_t flags)
9256 {
9257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9258         u32 flip_mask;
9259         int ret;
9260
9261         ret = intel_ring_begin(ring, 6);
9262         if (ret)
9263                 return ret;
9264
9265         /* Can't queue multiple flips, so wait for the previous
9266          * one to finish before executing the next.
9267          */
9268         if (intel_crtc->plane)
9269                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9270         else
9271                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9272         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9273         intel_ring_emit(ring, MI_NOOP);
9274         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9275                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9276         intel_ring_emit(ring, fb->pitches[0]);
9277         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9278         intel_ring_emit(ring, 0); /* aux display base address, unused */
9279
9280         intel_mark_page_flip_active(intel_crtc);
9281         __intel_ring_advance(ring);
9282         return 0;
9283 }
9284
9285 static int intel_gen3_queue_flip(struct drm_device *dev,
9286                                  struct drm_crtc *crtc,
9287                                  struct drm_framebuffer *fb,
9288                                  struct drm_i915_gem_object *obj,
9289                                  struct intel_engine_cs *ring,
9290                                  uint32_t flags)
9291 {
9292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9293         u32 flip_mask;
9294         int ret;
9295
9296         ret = intel_ring_begin(ring, 6);
9297         if (ret)
9298                 return ret;
9299
9300         if (intel_crtc->plane)
9301                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9302         else
9303                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9304         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9305         intel_ring_emit(ring, MI_NOOP);
9306         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9307                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9308         intel_ring_emit(ring, fb->pitches[0]);
9309         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9310         intel_ring_emit(ring, MI_NOOP);
9311
9312         intel_mark_page_flip_active(intel_crtc);
9313         __intel_ring_advance(ring);
9314         return 0;
9315 }
9316
9317 static int intel_gen4_queue_flip(struct drm_device *dev,
9318                                  struct drm_crtc *crtc,
9319                                  struct drm_framebuffer *fb,
9320                                  struct drm_i915_gem_object *obj,
9321                                  struct intel_engine_cs *ring,
9322                                  uint32_t flags)
9323 {
9324         struct drm_i915_private *dev_priv = dev->dev_private;
9325         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9326         uint32_t pf, pipesrc;
9327         int ret;
9328
9329         ret = intel_ring_begin(ring, 4);
9330         if (ret)
9331                 return ret;
9332
9333         /* i965+ uses the linear or tiled offsets from the
9334          * Display Registers (which do not change across a page-flip)
9335          * so we need only reprogram the base address.
9336          */
9337         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9338                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9339         intel_ring_emit(ring, fb->pitches[0]);
9340         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9341                         obj->tiling_mode);
9342
9343         /* XXX Enabling the panel-fitter across page-flip is so far
9344          * untested on non-native modes, so ignore it for now.
9345          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9346          */
9347         pf = 0;
9348         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9349         intel_ring_emit(ring, pf | pipesrc);
9350
9351         intel_mark_page_flip_active(intel_crtc);
9352         __intel_ring_advance(ring);
9353         return 0;
9354 }
9355
9356 static int intel_gen6_queue_flip(struct drm_device *dev,
9357                                  struct drm_crtc *crtc,
9358                                  struct drm_framebuffer *fb,
9359                                  struct drm_i915_gem_object *obj,
9360                                  struct intel_engine_cs *ring,
9361                                  uint32_t flags)
9362 {
9363         struct drm_i915_private *dev_priv = dev->dev_private;
9364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9365         uint32_t pf, pipesrc;
9366         int ret;
9367
9368         ret = intel_ring_begin(ring, 4);
9369         if (ret)
9370                 return ret;
9371
9372         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9373                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9374         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9375         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9376
9377         /* Contrary to the suggestions in the documentation,
9378          * "Enable Panel Fitter" does not seem to be required when page
9379          * flipping with a non-native mode, and worse causes a normal
9380          * modeset to fail.
9381          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9382          */
9383         pf = 0;
9384         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9385         intel_ring_emit(ring, pf | pipesrc);
9386
9387         intel_mark_page_flip_active(intel_crtc);
9388         __intel_ring_advance(ring);
9389         return 0;
9390 }
9391
9392 static int intel_gen7_queue_flip(struct drm_device *dev,
9393                                  struct drm_crtc *crtc,
9394                                  struct drm_framebuffer *fb,
9395                                  struct drm_i915_gem_object *obj,
9396                                  struct intel_engine_cs *ring,
9397                                  uint32_t flags)
9398 {
9399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9400         uint32_t plane_bit = 0;
9401         int len, ret;
9402
9403         switch (intel_crtc->plane) {
9404         case PLANE_A:
9405                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9406                 break;
9407         case PLANE_B:
9408                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9409                 break;
9410         case PLANE_C:
9411                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9412                 break;
9413         default:
9414                 WARN_ONCE(1, "unknown plane in flip command\n");
9415                 return -ENODEV;
9416         }
9417
9418         len = 4;
9419         if (ring->id == RCS) {
9420                 len += 6;
9421                 /*
9422                  * On Gen 8, SRM is now taking an extra dword to accommodate
9423                  * 48bits addresses, and we need a NOOP for the batch size to
9424                  * stay even.
9425                  */
9426                 if (IS_GEN8(dev))
9427                         len += 2;
9428         }
9429
9430         /*
9431          * BSpec MI_DISPLAY_FLIP for IVB:
9432          * "The full packet must be contained within the same cache line."
9433          *
9434          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9435          * cacheline, if we ever start emitting more commands before
9436          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9437          * then do the cacheline alignment, and finally emit the
9438          * MI_DISPLAY_FLIP.
9439          */
9440         ret = intel_ring_cacheline_align(ring);
9441         if (ret)
9442                 return ret;
9443
9444         ret = intel_ring_begin(ring, len);
9445         if (ret)
9446                 return ret;
9447
9448         /* Unmask the flip-done completion message. Note that the bspec says that
9449          * we should do this for both the BCS and RCS, and that we must not unmask
9450          * more than one flip event at any time (or ensure that one flip message
9451          * can be sent by waiting for flip-done prior to queueing new flips).
9452          * Experimentation says that BCS works despite DERRMR masking all
9453          * flip-done completion events and that unmasking all planes at once
9454          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9455          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9456          */
9457         if (ring->id == RCS) {
9458                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9459                 intel_ring_emit(ring, DERRMR);
9460                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9461                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9462                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9463                 if (IS_GEN8(dev))
9464                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9465                                               MI_SRM_LRM_GLOBAL_GTT);
9466                 else
9467                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9468                                               MI_SRM_LRM_GLOBAL_GTT);
9469                 intel_ring_emit(ring, DERRMR);
9470                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9471                 if (IS_GEN8(dev)) {
9472                         intel_ring_emit(ring, 0);
9473                         intel_ring_emit(ring, MI_NOOP);
9474                 }
9475         }
9476
9477         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9478         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9479         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9480         intel_ring_emit(ring, (MI_NOOP));
9481
9482         intel_mark_page_flip_active(intel_crtc);
9483         __intel_ring_advance(ring);
9484         return 0;
9485 }
9486
9487 static bool use_mmio_flip(struct intel_engine_cs *ring,
9488                           struct drm_i915_gem_object *obj)
9489 {
9490         /*
9491          * This is not being used for older platforms, because
9492          * non-availability of flip done interrupt forces us to use
9493          * CS flips. Older platforms derive flip done using some clever
9494          * tricks involving the flip_pending status bits and vblank irqs.
9495          * So using MMIO flips there would disrupt this mechanism.
9496          */
9497
9498         if (ring == NULL)
9499                 return true;
9500
9501         if (INTEL_INFO(ring->dev)->gen < 5)
9502                 return false;
9503
9504         if (i915.use_mmio_flip < 0)
9505                 return false;
9506         else if (i915.use_mmio_flip > 0)
9507                 return true;
9508         else if (i915.enable_execlists)
9509                 return true;
9510         else
9511                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9512 }
9513
9514 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9515 {
9516         struct drm_device *dev = intel_crtc->base.dev;
9517         struct drm_i915_private *dev_priv = dev->dev_private;
9518         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9519         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9520         struct drm_i915_gem_object *obj = intel_fb->obj;
9521         const enum pipe pipe = intel_crtc->pipe;
9522         u32 ctl, stride;
9523
9524         ctl = I915_READ(PLANE_CTL(pipe, 0));
9525         ctl &= ~PLANE_CTL_TILED_MASK;
9526         if (obj->tiling_mode == I915_TILING_X)
9527                 ctl |= PLANE_CTL_TILED_X;
9528
9529         /*
9530          * The stride is either expressed as a multiple of 64 bytes chunks for
9531          * linear buffers or in number of tiles for tiled buffers.
9532          */
9533         stride = fb->pitches[0] >> 6;
9534         if (obj->tiling_mode == I915_TILING_X)
9535                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9536
9537         /*
9538          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9539          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9540          */
9541         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9542         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9543
9544         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9545         POSTING_READ(PLANE_SURF(pipe, 0));
9546 }
9547
9548 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9549 {
9550         struct drm_device *dev = intel_crtc->base.dev;
9551         struct drm_i915_private *dev_priv = dev->dev_private;
9552         struct intel_framebuffer *intel_fb =
9553                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9554         struct drm_i915_gem_object *obj = intel_fb->obj;
9555         u32 dspcntr;
9556         u32 reg;
9557
9558         reg = DSPCNTR(intel_crtc->plane);
9559         dspcntr = I915_READ(reg);
9560
9561         if (obj->tiling_mode != I915_TILING_NONE)
9562                 dspcntr |= DISPPLANE_TILED;
9563         else
9564                 dspcntr &= ~DISPPLANE_TILED;
9565
9566         I915_WRITE(reg, dspcntr);
9567
9568         I915_WRITE(DSPSURF(intel_crtc->plane),
9569                    intel_crtc->unpin_work->gtt_offset);
9570         POSTING_READ(DSPSURF(intel_crtc->plane));
9571
9572 }
9573
9574 /*
9575  * XXX: This is the temporary way to update the plane registers until we get
9576  * around to using the usual plane update functions for MMIO flips
9577  */
9578 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9579 {
9580         struct drm_device *dev = intel_crtc->base.dev;
9581         bool atomic_update;
9582         u32 start_vbl_count;
9583
9584         intel_mark_page_flip_active(intel_crtc);
9585
9586         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9587
9588         if (INTEL_INFO(dev)->gen >= 9)
9589                 skl_do_mmio_flip(intel_crtc);
9590         else
9591                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9592                 ilk_do_mmio_flip(intel_crtc);
9593
9594         if (atomic_update)
9595                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9596 }
9597
9598 static void intel_mmio_flip_work_func(struct work_struct *work)
9599 {
9600         struct intel_crtc *crtc =
9601                 container_of(work, struct intel_crtc, mmio_flip.work);
9602         struct intel_mmio_flip *mmio_flip;
9603
9604         mmio_flip = &crtc->mmio_flip;
9605         if (mmio_flip->req)
9606                 WARN_ON(__i915_wait_request(mmio_flip->req,
9607                                             crtc->reset_counter,
9608                                             false, NULL, NULL) != 0);
9609
9610         intel_do_mmio_flip(crtc);
9611         if (mmio_flip->req) {
9612                 mutex_lock(&crtc->base.dev->struct_mutex);
9613                 i915_gem_request_assign(&mmio_flip->req, NULL);
9614                 mutex_unlock(&crtc->base.dev->struct_mutex);
9615         }
9616 }
9617
9618 static int intel_queue_mmio_flip(struct drm_device *dev,
9619                                  struct drm_crtc *crtc,
9620                                  struct drm_framebuffer *fb,
9621                                  struct drm_i915_gem_object *obj,
9622                                  struct intel_engine_cs *ring,
9623                                  uint32_t flags)
9624 {
9625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9626
9627         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9628                                 obj->last_write_req);
9629
9630         schedule_work(&intel_crtc->mmio_flip.work);
9631
9632         return 0;
9633 }
9634
9635 static int intel_default_queue_flip(struct drm_device *dev,
9636                                     struct drm_crtc *crtc,
9637                                     struct drm_framebuffer *fb,
9638                                     struct drm_i915_gem_object *obj,
9639                                     struct intel_engine_cs *ring,
9640                                     uint32_t flags)
9641 {
9642         return -ENODEV;
9643 }
9644
9645 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9646                                          struct drm_crtc *crtc)
9647 {
9648         struct drm_i915_private *dev_priv = dev->dev_private;
9649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9650         struct intel_unpin_work *work = intel_crtc->unpin_work;
9651         u32 addr;
9652
9653         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9654                 return true;
9655
9656         if (!work->enable_stall_check)
9657                 return false;
9658
9659         if (work->flip_ready_vblank == 0) {
9660                 if (work->flip_queued_req &&
9661                     !i915_gem_request_completed(work->flip_queued_req, true))
9662                         return false;
9663
9664                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9665         }
9666
9667         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9668                 return false;
9669
9670         /* Potential stall - if we see that the flip has happened,
9671          * assume a missed interrupt. */
9672         if (INTEL_INFO(dev)->gen >= 4)
9673                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9674         else
9675                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9676
9677         /* There is a potential issue here with a false positive after a flip
9678          * to the same address. We could address this by checking for a
9679          * non-incrementing frame counter.
9680          */
9681         return addr == work->gtt_offset;
9682 }
9683
9684 void intel_check_page_flip(struct drm_device *dev, int pipe)
9685 {
9686         struct drm_i915_private *dev_priv = dev->dev_private;
9687         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9689
9690         WARN_ON(!in_irq());
9691
9692         if (crtc == NULL)
9693                 return;
9694
9695         spin_lock(&dev->event_lock);
9696         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9697                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9698                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9699                 page_flip_completed(intel_crtc);
9700         }
9701         spin_unlock(&dev->event_lock);
9702 }
9703
9704 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9705                                 struct drm_framebuffer *fb,
9706                                 struct drm_pending_vblank_event *event,
9707                                 uint32_t page_flip_flags)
9708 {
9709         struct drm_device *dev = crtc->dev;
9710         struct drm_i915_private *dev_priv = dev->dev_private;
9711         struct drm_framebuffer *old_fb = crtc->primary->fb;
9712         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9714         struct drm_plane *primary = crtc->primary;
9715         enum pipe pipe = intel_crtc->pipe;
9716         struct intel_unpin_work *work;
9717         struct intel_engine_cs *ring;
9718         int ret;
9719
9720         /*
9721          * drm_mode_page_flip_ioctl() should already catch this, but double
9722          * check to be safe.  In the future we may enable pageflipping from
9723          * a disabled primary plane.
9724          */
9725         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9726                 return -EBUSY;
9727
9728         /* Can't change pixel format via MI display flips. */
9729         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9730                 return -EINVAL;
9731
9732         /*
9733          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9734          * Note that pitch changes could also affect these register.
9735          */
9736         if (INTEL_INFO(dev)->gen > 3 &&
9737             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9738              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9739                 return -EINVAL;
9740
9741         if (i915_terminally_wedged(&dev_priv->gpu_error))
9742                 goto out_hang;
9743
9744         work = kzalloc(sizeof(*work), GFP_KERNEL);
9745         if (work == NULL)
9746                 return -ENOMEM;
9747
9748         work->event = event;
9749         work->crtc = crtc;
9750         work->old_fb = old_fb;
9751         INIT_WORK(&work->work, intel_unpin_work_fn);
9752
9753         ret = drm_crtc_vblank_get(crtc);
9754         if (ret)
9755                 goto free_work;
9756
9757         /* We borrow the event spin lock for protecting unpin_work */
9758         spin_lock_irq(&dev->event_lock);
9759         if (intel_crtc->unpin_work) {
9760                 /* Before declaring the flip queue wedged, check if
9761                  * the hardware completed the operation behind our backs.
9762                  */
9763                 if (__intel_pageflip_stall_check(dev, crtc)) {
9764                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9765                         page_flip_completed(intel_crtc);
9766                 } else {
9767                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9768                         spin_unlock_irq(&dev->event_lock);
9769
9770                         drm_crtc_vblank_put(crtc);
9771                         kfree(work);
9772                         return -EBUSY;
9773                 }
9774         }
9775         intel_crtc->unpin_work = work;
9776         spin_unlock_irq(&dev->event_lock);
9777
9778         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9779                 flush_workqueue(dev_priv->wq);
9780
9781         ret = i915_mutex_lock_interruptible(dev);
9782         if (ret)
9783                 goto cleanup;
9784
9785         /* Reference the objects for the scheduled work. */
9786         drm_framebuffer_reference(work->old_fb);
9787         drm_gem_object_reference(&obj->base);
9788
9789         crtc->primary->fb = fb;
9790         update_state_fb(crtc->primary);
9791
9792         work->pending_flip_obj = obj;
9793
9794         atomic_inc(&intel_crtc->unpin_work_count);
9795         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9796
9797         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9798                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9799
9800         if (IS_VALLEYVIEW(dev)) {
9801                 ring = &dev_priv->ring[BCS];
9802                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9803                         /* vlv: DISPLAY_FLIP fails to change tiling */
9804                         ring = NULL;
9805         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9806                 ring = &dev_priv->ring[BCS];
9807         } else if (INTEL_INFO(dev)->gen >= 7) {
9808                 ring = i915_gem_request_get_ring(obj->last_read_req);
9809                 if (ring == NULL || ring->id != RCS)
9810                         ring = &dev_priv->ring[BCS];
9811         } else {
9812                 ring = &dev_priv->ring[RCS];
9813         }
9814
9815         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9816         if (ret)
9817                 goto cleanup_pending;
9818
9819         work->gtt_offset =
9820                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9821
9822         if (use_mmio_flip(ring, obj)) {
9823                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9824                                             page_flip_flags);
9825                 if (ret)
9826                         goto cleanup_unpin;
9827
9828                 i915_gem_request_assign(&work->flip_queued_req,
9829                                         obj->last_write_req);
9830         } else {
9831                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9832                                                    page_flip_flags);
9833                 if (ret)
9834                         goto cleanup_unpin;
9835
9836                 i915_gem_request_assign(&work->flip_queued_req,
9837                                         intel_ring_get_request(ring));
9838         }
9839
9840         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9841         work->enable_stall_check = true;
9842
9843         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9844                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9845
9846         intel_fbc_disable(dev);
9847         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9848         mutex_unlock(&dev->struct_mutex);
9849
9850         trace_i915_flip_request(intel_crtc->plane, obj);
9851
9852         return 0;
9853
9854 cleanup_unpin:
9855         intel_unpin_fb_obj(obj);
9856 cleanup_pending:
9857         atomic_dec(&intel_crtc->unpin_work_count);
9858         crtc->primary->fb = old_fb;
9859         update_state_fb(crtc->primary);
9860         drm_framebuffer_unreference(work->old_fb);
9861         drm_gem_object_unreference(&obj->base);
9862         mutex_unlock(&dev->struct_mutex);
9863
9864 cleanup:
9865         spin_lock_irq(&dev->event_lock);
9866         intel_crtc->unpin_work = NULL;
9867         spin_unlock_irq(&dev->event_lock);
9868
9869         drm_crtc_vblank_put(crtc);
9870 free_work:
9871         kfree(work);
9872
9873         if (ret == -EIO) {
9874 out_hang:
9875                 ret = intel_plane_restore(primary);
9876                 if (ret == 0 && event) {
9877                         spin_lock_irq(&dev->event_lock);
9878                         drm_send_vblank_event(dev, pipe, event);
9879                         spin_unlock_irq(&dev->event_lock);
9880                 }
9881         }
9882         return ret;
9883 }
9884
9885 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9886         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9887         .load_lut = intel_crtc_load_lut,
9888         .atomic_begin = intel_begin_crtc_commit,
9889         .atomic_flush = intel_finish_crtc_commit,
9890 };
9891
9892 /**
9893  * intel_modeset_update_staged_output_state
9894  *
9895  * Updates the staged output configuration state, e.g. after we've read out the
9896  * current hw state.
9897  */
9898 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9899 {
9900         struct intel_crtc *crtc;
9901         struct intel_encoder *encoder;
9902         struct intel_connector *connector;
9903
9904         list_for_each_entry(connector, &dev->mode_config.connector_list,
9905                             base.head) {
9906                 connector->new_encoder =
9907                         to_intel_encoder(connector->base.encoder);
9908         }
9909
9910         for_each_intel_encoder(dev, encoder) {
9911                 encoder->new_crtc =
9912                         to_intel_crtc(encoder->base.crtc);
9913         }
9914
9915         for_each_intel_crtc(dev, crtc) {
9916                 crtc->new_enabled = crtc->base.enabled;
9917
9918                 if (crtc->new_enabled)
9919                         crtc->new_config = crtc->config;
9920                 else
9921                         crtc->new_config = NULL;
9922         }
9923 }
9924
9925 /**
9926  * intel_modeset_commit_output_state
9927  *
9928  * This function copies the stage display pipe configuration to the real one.
9929  */
9930 static void intel_modeset_commit_output_state(struct drm_device *dev)
9931 {
9932         struct intel_crtc *crtc;
9933         struct intel_encoder *encoder;
9934         struct intel_connector *connector;
9935
9936         list_for_each_entry(connector, &dev->mode_config.connector_list,
9937                             base.head) {
9938                 connector->base.encoder = &connector->new_encoder->base;
9939         }
9940
9941         for_each_intel_encoder(dev, encoder) {
9942                 encoder->base.crtc = &encoder->new_crtc->base;
9943         }
9944
9945         for_each_intel_crtc(dev, crtc) {
9946                 crtc->base.enabled = crtc->new_enabled;
9947         }
9948 }
9949
9950 static void
9951 connected_sink_compute_bpp(struct intel_connector *connector,
9952                            struct intel_crtc_state *pipe_config)
9953 {
9954         int bpp = pipe_config->pipe_bpp;
9955
9956         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9957                 connector->base.base.id,
9958                 connector->base.name);
9959
9960         /* Don't use an invalid EDID bpc value */
9961         if (connector->base.display_info.bpc &&
9962             connector->base.display_info.bpc * 3 < bpp) {
9963                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9964                               bpp, connector->base.display_info.bpc*3);
9965                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9966         }
9967
9968         /* Clamp bpp to 8 on screens without EDID 1.4 */
9969         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9970                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9971                               bpp);
9972                 pipe_config->pipe_bpp = 24;
9973         }
9974 }
9975
9976 static int
9977 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9978                           struct drm_framebuffer *fb,
9979                           struct intel_crtc_state *pipe_config)
9980 {
9981         struct drm_device *dev = crtc->base.dev;
9982         struct intel_connector *connector;
9983         int bpp;
9984
9985         switch (fb->pixel_format) {
9986         case DRM_FORMAT_C8:
9987                 bpp = 8*3; /* since we go through a colormap */
9988                 break;
9989         case DRM_FORMAT_XRGB1555:
9990         case DRM_FORMAT_ARGB1555:
9991                 /* checked in intel_framebuffer_init already */
9992                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9993                         return -EINVAL;
9994         case DRM_FORMAT_RGB565:
9995                 bpp = 6*3; /* min is 18bpp */
9996                 break;
9997         case DRM_FORMAT_XBGR8888:
9998         case DRM_FORMAT_ABGR8888:
9999                 /* checked in intel_framebuffer_init already */
10000                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10001                         return -EINVAL;
10002         case DRM_FORMAT_XRGB8888:
10003         case DRM_FORMAT_ARGB8888:
10004                 bpp = 8*3;
10005                 break;
10006         case DRM_FORMAT_XRGB2101010:
10007         case DRM_FORMAT_ARGB2101010:
10008         case DRM_FORMAT_XBGR2101010:
10009         case DRM_FORMAT_ABGR2101010:
10010                 /* checked in intel_framebuffer_init already */
10011                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10012                         return -EINVAL;
10013                 bpp = 10*3;
10014                 break;
10015         /* TODO: gen4+ supports 16 bpc floating point, too. */
10016         default:
10017                 DRM_DEBUG_KMS("unsupported depth\n");
10018                 return -EINVAL;
10019         }
10020
10021         pipe_config->pipe_bpp = bpp;
10022
10023         /* Clamp display bpp to EDID value */
10024         list_for_each_entry(connector, &dev->mode_config.connector_list,
10025                             base.head) {
10026                 if (!connector->new_encoder ||
10027                     connector->new_encoder->new_crtc != crtc)
10028                         continue;
10029
10030                 connected_sink_compute_bpp(connector, pipe_config);
10031         }
10032
10033         return bpp;
10034 }
10035
10036 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10037 {
10038         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10039                         "type: 0x%x flags: 0x%x\n",
10040                 mode->crtc_clock,
10041                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10042                 mode->crtc_hsync_end, mode->crtc_htotal,
10043                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10044                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10045 }
10046
10047 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10048                                    struct intel_crtc_state *pipe_config,
10049                                    const char *context)
10050 {
10051         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10052                       context, pipe_name(crtc->pipe));
10053
10054         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10055         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10056                       pipe_config->pipe_bpp, pipe_config->dither);
10057         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10058                       pipe_config->has_pch_encoder,
10059                       pipe_config->fdi_lanes,
10060                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10061                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10062                       pipe_config->fdi_m_n.tu);
10063         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10064                       pipe_config->has_dp_encoder,
10065                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10066                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10067                       pipe_config->dp_m_n.tu);
10068
10069         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10070                       pipe_config->has_dp_encoder,
10071                       pipe_config->dp_m2_n2.gmch_m,
10072                       pipe_config->dp_m2_n2.gmch_n,
10073                       pipe_config->dp_m2_n2.link_m,
10074                       pipe_config->dp_m2_n2.link_n,
10075                       pipe_config->dp_m2_n2.tu);
10076
10077         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10078                       pipe_config->has_audio,
10079                       pipe_config->has_infoframe);
10080
10081         DRM_DEBUG_KMS("requested mode:\n");
10082         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10083         DRM_DEBUG_KMS("adjusted mode:\n");
10084         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10085         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10086         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10087         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10088                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10089         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10090                       pipe_config->gmch_pfit.control,
10091                       pipe_config->gmch_pfit.pgm_ratios,
10092                       pipe_config->gmch_pfit.lvds_border_bits);
10093         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10094                       pipe_config->pch_pfit.pos,
10095                       pipe_config->pch_pfit.size,
10096                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10097         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10098         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10099 }
10100
10101 static bool encoders_cloneable(const struct intel_encoder *a,
10102                                const struct intel_encoder *b)
10103 {
10104         /* masks could be asymmetric, so check both ways */
10105         return a == b || (a->cloneable & (1 << b->type) &&
10106                           b->cloneable & (1 << a->type));
10107 }
10108
10109 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10110                                          struct intel_encoder *encoder)
10111 {
10112         struct drm_device *dev = crtc->base.dev;
10113         struct intel_encoder *source_encoder;
10114
10115         for_each_intel_encoder(dev, source_encoder) {
10116                 if (source_encoder->new_crtc != crtc)
10117                         continue;
10118
10119                 if (!encoders_cloneable(encoder, source_encoder))
10120                         return false;
10121         }
10122
10123         return true;
10124 }
10125
10126 static bool check_encoder_cloning(struct intel_crtc *crtc)
10127 {
10128         struct drm_device *dev = crtc->base.dev;
10129         struct intel_encoder *encoder;
10130
10131         for_each_intel_encoder(dev, encoder) {
10132                 if (encoder->new_crtc != crtc)
10133                         continue;
10134
10135                 if (!check_single_encoder_cloning(crtc, encoder))
10136                         return false;
10137         }
10138
10139         return true;
10140 }
10141
10142 static bool check_digital_port_conflicts(struct drm_device *dev)
10143 {
10144         struct intel_connector *connector;
10145         unsigned int used_ports = 0;
10146
10147         /*
10148          * Walk the connector list instead of the encoder
10149          * list to detect the problem on ddi platforms
10150          * where there's just one encoder per digital port.
10151          */
10152         list_for_each_entry(connector,
10153                             &dev->mode_config.connector_list, base.head) {
10154                 struct intel_encoder *encoder = connector->new_encoder;
10155
10156                 if (!encoder)
10157                         continue;
10158
10159                 WARN_ON(!encoder->new_crtc);
10160
10161                 switch (encoder->type) {
10162                         unsigned int port_mask;
10163                 case INTEL_OUTPUT_UNKNOWN:
10164                         if (WARN_ON(!HAS_DDI(dev)))
10165                                 break;
10166                 case INTEL_OUTPUT_DISPLAYPORT:
10167                 case INTEL_OUTPUT_HDMI:
10168                 case INTEL_OUTPUT_EDP:
10169                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10170
10171                         /* the same port mustn't appear more than once */
10172                         if (used_ports & port_mask)
10173                                 return false;
10174
10175                         used_ports |= port_mask;
10176                 default:
10177                         break;
10178                 }
10179         }
10180
10181         return true;
10182 }
10183
10184 static struct intel_crtc_state *
10185 intel_modeset_pipe_config(struct drm_crtc *crtc,
10186                           struct drm_framebuffer *fb,
10187                           struct drm_display_mode *mode)
10188 {
10189         struct drm_device *dev = crtc->dev;
10190         struct intel_encoder *encoder;
10191         struct intel_crtc_state *pipe_config;
10192         int plane_bpp, ret = -EINVAL;
10193         bool retry = true;
10194
10195         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10196                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10197                 return ERR_PTR(-EINVAL);
10198         }
10199
10200         if (!check_digital_port_conflicts(dev)) {
10201                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10202                 return ERR_PTR(-EINVAL);
10203         }
10204
10205         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10206         if (!pipe_config)
10207                 return ERR_PTR(-ENOMEM);
10208
10209         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10210         drm_mode_copy(&pipe_config->base.mode, mode);
10211
10212         pipe_config->cpu_transcoder =
10213                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10214         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10215
10216         /*
10217          * Sanitize sync polarity flags based on requested ones. If neither
10218          * positive or negative polarity is requested, treat this as meaning
10219          * negative polarity.
10220          */
10221         if (!(pipe_config->base.adjusted_mode.flags &
10222               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10223                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10224
10225         if (!(pipe_config->base.adjusted_mode.flags &
10226               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10227                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10228
10229         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10230          * plane pixel format and any sink constraints into account. Returns the
10231          * source plane bpp so that dithering can be selected on mismatches
10232          * after encoders and crtc also have had their say. */
10233         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10234                                               fb, pipe_config);
10235         if (plane_bpp < 0)
10236                 goto fail;
10237
10238         /*
10239          * Determine the real pipe dimensions. Note that stereo modes can
10240          * increase the actual pipe size due to the frame doubling and
10241          * insertion of additional space for blanks between the frame. This
10242          * is stored in the crtc timings. We use the requested mode to do this
10243          * computation to clearly distinguish it from the adjusted mode, which
10244          * can be changed by the connectors in the below retry loop.
10245          */
10246         drm_crtc_get_hv_timing(&pipe_config->base.mode,
10247                                &pipe_config->pipe_src_w,
10248                                &pipe_config->pipe_src_h);
10249
10250 encoder_retry:
10251         /* Ensure the port clock defaults are reset when retrying. */
10252         pipe_config->port_clock = 0;
10253         pipe_config->pixel_multiplier = 1;
10254
10255         /* Fill in default crtc timings, allow encoders to overwrite them. */
10256         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10257                               CRTC_STEREO_DOUBLE);
10258
10259         /* Pass our mode to the connectors and the CRTC to give them a chance to
10260          * adjust it according to limitations or connector properties, and also
10261          * a chance to reject the mode entirely.
10262          */
10263         for_each_intel_encoder(dev, encoder) {
10264
10265                 if (&encoder->new_crtc->base != crtc)
10266                         continue;
10267
10268                 if (!(encoder->compute_config(encoder, pipe_config))) {
10269                         DRM_DEBUG_KMS("Encoder config failure\n");
10270                         goto fail;
10271                 }
10272         }
10273
10274         /* Set default port clock if not overwritten by the encoder. Needs to be
10275          * done afterwards in case the encoder adjusts the mode. */
10276         if (!pipe_config->port_clock)
10277                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10278                         * pipe_config->pixel_multiplier;
10279
10280         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10281         if (ret < 0) {
10282                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10283                 goto fail;
10284         }
10285
10286         if (ret == RETRY) {
10287                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10288                         ret = -EINVAL;
10289                         goto fail;
10290                 }
10291
10292                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10293                 retry = false;
10294                 goto encoder_retry;
10295         }
10296
10297         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10298         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10299                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10300
10301         return pipe_config;
10302 fail:
10303         kfree(pipe_config);
10304         return ERR_PTR(ret);
10305 }
10306
10307 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10308  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10309 static void
10310 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10311                              unsigned *prepare_pipes, unsigned *disable_pipes)
10312 {
10313         struct intel_crtc *intel_crtc;
10314         struct drm_device *dev = crtc->dev;
10315         struct intel_encoder *encoder;
10316         struct intel_connector *connector;
10317         struct drm_crtc *tmp_crtc;
10318
10319         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10320
10321         /* Check which crtcs have changed outputs connected to them, these need
10322          * to be part of the prepare_pipes mask. We don't (yet) support global
10323          * modeset across multiple crtcs, so modeset_pipes will only have one
10324          * bit set at most. */
10325         list_for_each_entry(connector, &dev->mode_config.connector_list,
10326                             base.head) {
10327                 if (connector->base.encoder == &connector->new_encoder->base)
10328                         continue;
10329
10330                 if (connector->base.encoder) {
10331                         tmp_crtc = connector->base.encoder->crtc;
10332
10333                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10334                 }
10335
10336                 if (connector->new_encoder)
10337                         *prepare_pipes |=
10338                                 1 << connector->new_encoder->new_crtc->pipe;
10339         }
10340
10341         for_each_intel_encoder(dev, encoder) {
10342                 if (encoder->base.crtc == &encoder->new_crtc->base)
10343                         continue;
10344
10345                 if (encoder->base.crtc) {
10346                         tmp_crtc = encoder->base.crtc;
10347
10348                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10349                 }
10350
10351                 if (encoder->new_crtc)
10352                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10353         }
10354
10355         /* Check for pipes that will be enabled/disabled ... */
10356         for_each_intel_crtc(dev, intel_crtc) {
10357                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10358                         continue;
10359
10360                 if (!intel_crtc->new_enabled)
10361                         *disable_pipes |= 1 << intel_crtc->pipe;
10362                 else
10363                         *prepare_pipes |= 1 << intel_crtc->pipe;
10364         }
10365
10366
10367         /* set_mode is also used to update properties on life display pipes. */
10368         intel_crtc = to_intel_crtc(crtc);
10369         if (intel_crtc->new_enabled)
10370                 *prepare_pipes |= 1 << intel_crtc->pipe;
10371
10372         /*
10373          * For simplicity do a full modeset on any pipe where the output routing
10374          * changed. We could be more clever, but that would require us to be
10375          * more careful with calling the relevant encoder->mode_set functions.
10376          */
10377         if (*prepare_pipes)
10378                 *modeset_pipes = *prepare_pipes;
10379
10380         /* ... and mask these out. */
10381         *modeset_pipes &= ~(*disable_pipes);
10382         *prepare_pipes &= ~(*disable_pipes);
10383
10384         /*
10385          * HACK: We don't (yet) fully support global modesets. intel_set_config
10386          * obies this rule, but the modeset restore mode of
10387          * intel_modeset_setup_hw_state does not.
10388          */
10389         *modeset_pipes &= 1 << intel_crtc->pipe;
10390         *prepare_pipes &= 1 << intel_crtc->pipe;
10391
10392         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10393                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10394 }
10395
10396 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10397 {
10398         struct drm_encoder *encoder;
10399         struct drm_device *dev = crtc->dev;
10400
10401         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10402                 if (encoder->crtc == crtc)
10403                         return true;
10404
10405         return false;
10406 }
10407
10408 static void
10409 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10410 {
10411         struct drm_i915_private *dev_priv = dev->dev_private;
10412         struct intel_encoder *intel_encoder;
10413         struct intel_crtc *intel_crtc;
10414         struct drm_connector *connector;
10415
10416         intel_shared_dpll_commit(dev_priv);
10417
10418         for_each_intel_encoder(dev, intel_encoder) {
10419                 if (!intel_encoder->base.crtc)
10420                         continue;
10421
10422                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10423
10424                 if (prepare_pipes & (1 << intel_crtc->pipe))
10425                         intel_encoder->connectors_active = false;
10426         }
10427
10428         intel_modeset_commit_output_state(dev);
10429
10430         /* Double check state. */
10431         for_each_intel_crtc(dev, intel_crtc) {
10432                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10433                 WARN_ON(intel_crtc->new_config &&
10434                         intel_crtc->new_config != intel_crtc->config);
10435                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10436         }
10437
10438         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10439                 if (!connector->encoder || !connector->encoder->crtc)
10440                         continue;
10441
10442                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10443
10444                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10445                         struct drm_property *dpms_property =
10446                                 dev->mode_config.dpms_property;
10447
10448                         connector->dpms = DRM_MODE_DPMS_ON;
10449                         drm_object_property_set_value(&connector->base,
10450                                                          dpms_property,
10451                                                          DRM_MODE_DPMS_ON);
10452
10453                         intel_encoder = to_intel_encoder(connector->encoder);
10454                         intel_encoder->connectors_active = true;
10455                 }
10456         }
10457
10458 }
10459
10460 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10461 {
10462         int diff;
10463
10464         if (clock1 == clock2)
10465                 return true;
10466
10467         if (!clock1 || !clock2)
10468                 return false;
10469
10470         diff = abs(clock1 - clock2);
10471
10472         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10473                 return true;
10474
10475         return false;
10476 }
10477
10478 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10479         list_for_each_entry((intel_crtc), \
10480                             &(dev)->mode_config.crtc_list, \
10481                             base.head) \
10482                 if (mask & (1 <<(intel_crtc)->pipe))
10483
10484 static bool
10485 intel_pipe_config_compare(struct drm_device *dev,
10486                           struct intel_crtc_state *current_config,
10487                           struct intel_crtc_state *pipe_config)
10488 {
10489 #define PIPE_CONF_CHECK_X(name) \
10490         if (current_config->name != pipe_config->name) { \
10491                 DRM_ERROR("mismatch in " #name " " \
10492                           "(expected 0x%08x, found 0x%08x)\n", \
10493                           current_config->name, \
10494                           pipe_config->name); \
10495                 return false; \
10496         }
10497
10498 #define PIPE_CONF_CHECK_I(name) \
10499         if (current_config->name != pipe_config->name) { \
10500                 DRM_ERROR("mismatch in " #name " " \
10501                           "(expected %i, found %i)\n", \
10502                           current_config->name, \
10503                           pipe_config->name); \
10504                 return false; \
10505         }
10506
10507 /* This is required for BDW+ where there is only one set of registers for
10508  * switching between high and low RR.
10509  * This macro can be used whenever a comparison has to be made between one
10510  * hw state and multiple sw state variables.
10511  */
10512 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10513         if ((current_config->name != pipe_config->name) && \
10514                 (current_config->alt_name != pipe_config->name)) { \
10515                         DRM_ERROR("mismatch in " #name " " \
10516                                   "(expected %i or %i, found %i)\n", \
10517                                   current_config->name, \
10518                                   current_config->alt_name, \
10519                                   pipe_config->name); \
10520                         return false; \
10521         }
10522
10523 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10524         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10525                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10526                           "(expected %i, found %i)\n", \
10527                           current_config->name & (mask), \
10528                           pipe_config->name & (mask)); \
10529                 return false; \
10530         }
10531
10532 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10533         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10534                 DRM_ERROR("mismatch in " #name " " \
10535                           "(expected %i, found %i)\n", \
10536                           current_config->name, \
10537                           pipe_config->name); \
10538                 return false; \
10539         }
10540
10541 #define PIPE_CONF_QUIRK(quirk)  \
10542         ((current_config->quirks | pipe_config->quirks) & (quirk))
10543
10544         PIPE_CONF_CHECK_I(cpu_transcoder);
10545
10546         PIPE_CONF_CHECK_I(has_pch_encoder);
10547         PIPE_CONF_CHECK_I(fdi_lanes);
10548         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10549         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10550         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10551         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10552         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10553
10554         PIPE_CONF_CHECK_I(has_dp_encoder);
10555
10556         if (INTEL_INFO(dev)->gen < 8) {
10557                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10558                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10559                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10560                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10561                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10562
10563                 if (current_config->has_drrs) {
10564                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10565                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10566                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10567                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10568                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10569                 }
10570         } else {
10571                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10572                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10573                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10574                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10575                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10576         }
10577
10578         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10579         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10580         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10581         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10582         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10583         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10584
10585         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10586         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10587         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10588         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10589         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10590         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10591
10592         PIPE_CONF_CHECK_I(pixel_multiplier);
10593         PIPE_CONF_CHECK_I(has_hdmi_sink);
10594         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10595             IS_VALLEYVIEW(dev))
10596                 PIPE_CONF_CHECK_I(limited_color_range);
10597         PIPE_CONF_CHECK_I(has_infoframe);
10598
10599         PIPE_CONF_CHECK_I(has_audio);
10600
10601         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10602                               DRM_MODE_FLAG_INTERLACE);
10603
10604         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10605                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10606                                       DRM_MODE_FLAG_PHSYNC);
10607                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10608                                       DRM_MODE_FLAG_NHSYNC);
10609                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10610                                       DRM_MODE_FLAG_PVSYNC);
10611                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10612                                       DRM_MODE_FLAG_NVSYNC);
10613         }
10614
10615         PIPE_CONF_CHECK_I(pipe_src_w);
10616         PIPE_CONF_CHECK_I(pipe_src_h);
10617
10618         /*
10619          * FIXME: BIOS likes to set up a cloned config with lvds+external
10620          * screen. Since we don't yet re-compute the pipe config when moving
10621          * just the lvds port away to another pipe the sw tracking won't match.
10622          *
10623          * Proper atomic modesets with recomputed global state will fix this.
10624          * Until then just don't check gmch state for inherited modes.
10625          */
10626         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10627                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10628                 /* pfit ratios are autocomputed by the hw on gen4+ */
10629                 if (INTEL_INFO(dev)->gen < 4)
10630                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10631                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10632         }
10633
10634         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10635         if (current_config->pch_pfit.enabled) {
10636                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10637                 PIPE_CONF_CHECK_I(pch_pfit.size);
10638         }
10639
10640         /* BDW+ don't expose a synchronous way to read the state */
10641         if (IS_HASWELL(dev))
10642                 PIPE_CONF_CHECK_I(ips_enabled);
10643
10644         PIPE_CONF_CHECK_I(double_wide);
10645
10646         PIPE_CONF_CHECK_X(ddi_pll_sel);
10647
10648         PIPE_CONF_CHECK_I(shared_dpll);
10649         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10650         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10651         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10652         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10653         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10654         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10655         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10656         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10657
10658         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10659                 PIPE_CONF_CHECK_I(pipe_bpp);
10660
10661         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10662         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10663
10664 #undef PIPE_CONF_CHECK_X
10665 #undef PIPE_CONF_CHECK_I
10666 #undef PIPE_CONF_CHECK_I_ALT
10667 #undef PIPE_CONF_CHECK_FLAGS
10668 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10669 #undef PIPE_CONF_QUIRK
10670
10671         return true;
10672 }
10673
10674 static void check_wm_state(struct drm_device *dev)
10675 {
10676         struct drm_i915_private *dev_priv = dev->dev_private;
10677         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10678         struct intel_crtc *intel_crtc;
10679         int plane;
10680
10681         if (INTEL_INFO(dev)->gen < 9)
10682                 return;
10683
10684         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10685         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10686
10687         for_each_intel_crtc(dev, intel_crtc) {
10688                 struct skl_ddb_entry *hw_entry, *sw_entry;
10689                 const enum pipe pipe = intel_crtc->pipe;
10690
10691                 if (!intel_crtc->active)
10692                         continue;
10693
10694                 /* planes */
10695                 for_each_plane(pipe, plane) {
10696                         hw_entry = &hw_ddb.plane[pipe][plane];
10697                         sw_entry = &sw_ddb->plane[pipe][plane];
10698
10699                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10700                                 continue;
10701
10702                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10703                                   "(expected (%u,%u), found (%u,%u))\n",
10704                                   pipe_name(pipe), plane + 1,
10705                                   sw_entry->start, sw_entry->end,
10706                                   hw_entry->start, hw_entry->end);
10707                 }
10708
10709                 /* cursor */
10710                 hw_entry = &hw_ddb.cursor[pipe];
10711                 sw_entry = &sw_ddb->cursor[pipe];
10712
10713                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10714                         continue;
10715
10716                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10717                           "(expected (%u,%u), found (%u,%u))\n",
10718                           pipe_name(pipe),
10719                           sw_entry->start, sw_entry->end,
10720                           hw_entry->start, hw_entry->end);
10721         }
10722 }
10723
10724 static void
10725 check_connector_state(struct drm_device *dev)
10726 {
10727         struct intel_connector *connector;
10728
10729         list_for_each_entry(connector, &dev->mode_config.connector_list,
10730                             base.head) {
10731                 /* This also checks the encoder/connector hw state with the
10732                  * ->get_hw_state callbacks. */
10733                 intel_connector_check_state(connector);
10734
10735                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10736                      "connector's staged encoder doesn't match current encoder\n");
10737         }
10738 }
10739
10740 static void
10741 check_encoder_state(struct drm_device *dev)
10742 {
10743         struct intel_encoder *encoder;
10744         struct intel_connector *connector;
10745
10746         for_each_intel_encoder(dev, encoder) {
10747                 bool enabled = false;
10748                 bool active = false;
10749                 enum pipe pipe, tracked_pipe;
10750
10751                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10752                               encoder->base.base.id,
10753                               encoder->base.name);
10754
10755                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10756                      "encoder's stage crtc doesn't match current crtc\n");
10757                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10758                      "encoder's active_connectors set, but no crtc\n");
10759
10760                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10761                                     base.head) {
10762                         if (connector->base.encoder != &encoder->base)
10763                                 continue;
10764                         enabled = true;
10765                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10766                                 active = true;
10767                 }
10768                 /*
10769                  * for MST connectors if we unplug the connector is gone
10770                  * away but the encoder is still connected to a crtc
10771                  * until a modeset happens in response to the hotplug.
10772                  */
10773                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10774                         continue;
10775
10776                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10777                      "encoder's enabled state mismatch "
10778                      "(expected %i, found %i)\n",
10779                      !!encoder->base.crtc, enabled);
10780                 I915_STATE_WARN(active && !encoder->base.crtc,
10781                      "active encoder with no crtc\n");
10782
10783                 I915_STATE_WARN(encoder->connectors_active != active,
10784                      "encoder's computed active state doesn't match tracked active state "
10785                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10786
10787                 active = encoder->get_hw_state(encoder, &pipe);
10788                 I915_STATE_WARN(active != encoder->connectors_active,
10789                      "encoder's hw state doesn't match sw tracking "
10790                      "(expected %i, found %i)\n",
10791                      encoder->connectors_active, active);
10792
10793                 if (!encoder->base.crtc)
10794                         continue;
10795
10796                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10797                 I915_STATE_WARN(active && pipe != tracked_pipe,
10798                      "active encoder's pipe doesn't match"
10799                      "(expected %i, found %i)\n",
10800                      tracked_pipe, pipe);
10801
10802         }
10803 }
10804
10805 static void
10806 check_crtc_state(struct drm_device *dev)
10807 {
10808         struct drm_i915_private *dev_priv = dev->dev_private;
10809         struct intel_crtc *crtc;
10810         struct intel_encoder *encoder;
10811         struct intel_crtc_state pipe_config;
10812
10813         for_each_intel_crtc(dev, crtc) {
10814                 bool enabled = false;
10815                 bool active = false;
10816
10817                 memset(&pipe_config, 0, sizeof(pipe_config));
10818
10819                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10820                               crtc->base.base.id);
10821
10822                 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10823                      "active crtc, but not enabled in sw tracking\n");
10824
10825                 for_each_intel_encoder(dev, encoder) {
10826                         if (encoder->base.crtc != &crtc->base)
10827                                 continue;
10828                         enabled = true;
10829                         if (encoder->connectors_active)
10830                                 active = true;
10831                 }
10832
10833                 I915_STATE_WARN(active != crtc->active,
10834                      "crtc's computed active state doesn't match tracked active state "
10835                      "(expected %i, found %i)\n", active, crtc->active);
10836                 I915_STATE_WARN(enabled != crtc->base.enabled,
10837                      "crtc's computed enabled state doesn't match tracked enabled state "
10838                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10839
10840                 active = dev_priv->display.get_pipe_config(crtc,
10841                                                            &pipe_config);
10842
10843                 /* hw state is inconsistent with the pipe quirk */
10844                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10845                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10846                         active = crtc->active;
10847
10848                 for_each_intel_encoder(dev, encoder) {
10849                         enum pipe pipe;
10850                         if (encoder->base.crtc != &crtc->base)
10851                                 continue;
10852                         if (encoder->get_hw_state(encoder, &pipe))
10853                                 encoder->get_config(encoder, &pipe_config);
10854                 }
10855
10856                 I915_STATE_WARN(crtc->active != active,
10857                      "crtc active state doesn't match with hw state "
10858                      "(expected %i, found %i)\n", crtc->active, active);
10859
10860                 if (active &&
10861                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10862                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
10863                         intel_dump_pipe_config(crtc, &pipe_config,
10864                                                "[hw state]");
10865                         intel_dump_pipe_config(crtc, crtc->config,
10866                                                "[sw state]");
10867                 }
10868         }
10869 }
10870
10871 static void
10872 check_shared_dpll_state(struct drm_device *dev)
10873 {
10874         struct drm_i915_private *dev_priv = dev->dev_private;
10875         struct intel_crtc *crtc;
10876         struct intel_dpll_hw_state dpll_hw_state;
10877         int i;
10878
10879         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10880                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10881                 int enabled_crtcs = 0, active_crtcs = 0;
10882                 bool active;
10883
10884                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10885
10886                 DRM_DEBUG_KMS("%s\n", pll->name);
10887
10888                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10889
10890                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10891                      "more active pll users than references: %i vs %i\n",
10892                      pll->active, hweight32(pll->config.crtc_mask));
10893                 I915_STATE_WARN(pll->active && !pll->on,
10894                      "pll in active use but not on in sw tracking\n");
10895                 I915_STATE_WARN(pll->on && !pll->active,
10896                      "pll in on but not on in use in sw tracking\n");
10897                 I915_STATE_WARN(pll->on != active,
10898                      "pll on state mismatch (expected %i, found %i)\n",
10899                      pll->on, active);
10900
10901                 for_each_intel_crtc(dev, crtc) {
10902                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10903                                 enabled_crtcs++;
10904                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10905                                 active_crtcs++;
10906                 }
10907                 I915_STATE_WARN(pll->active != active_crtcs,
10908                      "pll active crtcs mismatch (expected %i, found %i)\n",
10909                      pll->active, active_crtcs);
10910                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10911                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10912                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10913
10914                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10915                                        sizeof(dpll_hw_state)),
10916                      "pll hw state mismatch\n");
10917         }
10918 }
10919
10920 void
10921 intel_modeset_check_state(struct drm_device *dev)
10922 {
10923         check_wm_state(dev);
10924         check_connector_state(dev);
10925         check_encoder_state(dev);
10926         check_crtc_state(dev);
10927         check_shared_dpll_state(dev);
10928 }
10929
10930 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10931                                      int dotclock)
10932 {
10933         /*
10934          * FDI already provided one idea for the dotclock.
10935          * Yell if the encoder disagrees.
10936          */
10937         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10938              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10939              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10940 }
10941
10942 static void update_scanline_offset(struct intel_crtc *crtc)
10943 {
10944         struct drm_device *dev = crtc->base.dev;
10945
10946         /*
10947          * The scanline counter increments at the leading edge of hsync.
10948          *
10949          * On most platforms it starts counting from vtotal-1 on the
10950          * first active line. That means the scanline counter value is
10951          * always one less than what we would expect. Ie. just after
10952          * start of vblank, which also occurs at start of hsync (on the
10953          * last active line), the scanline counter will read vblank_start-1.
10954          *
10955          * On gen2 the scanline counter starts counting from 1 instead
10956          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10957          * to keep the value positive), instead of adding one.
10958          *
10959          * On HSW+ the behaviour of the scanline counter depends on the output
10960          * type. For DP ports it behaves like most other platforms, but on HDMI
10961          * there's an extra 1 line difference. So we need to add two instead of
10962          * one to the value.
10963          */
10964         if (IS_GEN2(dev)) {
10965                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10966                 int vtotal;
10967
10968                 vtotal = mode->crtc_vtotal;
10969                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10970                         vtotal /= 2;
10971
10972                 crtc->scanline_offset = vtotal - 1;
10973         } else if (HAS_DDI(dev) &&
10974                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10975                 crtc->scanline_offset = 2;
10976         } else
10977                 crtc->scanline_offset = 1;
10978 }
10979
10980 static struct intel_crtc_state *
10981 intel_modeset_compute_config(struct drm_crtc *crtc,
10982                              struct drm_display_mode *mode,
10983                              struct drm_framebuffer *fb,
10984                              unsigned *modeset_pipes,
10985                              unsigned *prepare_pipes,
10986                              unsigned *disable_pipes)
10987 {
10988         struct intel_crtc_state *pipe_config = NULL;
10989
10990         intel_modeset_affected_pipes(crtc, modeset_pipes,
10991                                      prepare_pipes, disable_pipes);
10992
10993         if ((*modeset_pipes) == 0)
10994                 goto out;
10995
10996         /*
10997          * Note this needs changes when we start tracking multiple modes
10998          * and crtcs.  At that point we'll need to compute the whole config
10999          * (i.e. one pipe_config for each crtc) rather than just the one
11000          * for this crtc.
11001          */
11002         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11003         if (IS_ERR(pipe_config)) {
11004                 goto out;
11005         }
11006         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11007                                "[modeset]");
11008
11009 out:
11010         return pipe_config;
11011 }
11012
11013 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11014                                        unsigned modeset_pipes,
11015                                        unsigned disable_pipes)
11016 {
11017         struct drm_i915_private *dev_priv = to_i915(dev);
11018         unsigned clear_pipes = modeset_pipes | disable_pipes;
11019         struct intel_crtc *intel_crtc;
11020         int ret = 0;
11021
11022         if (!dev_priv->display.crtc_compute_clock)
11023                 return 0;
11024
11025         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11026         if (ret)
11027                 goto done;
11028
11029         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11030                 struct intel_crtc_state *state = intel_crtc->new_config;
11031                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11032                                                            state);
11033                 if (ret) {
11034                         intel_shared_dpll_abort_config(dev_priv);
11035                         goto done;
11036                 }
11037         }
11038
11039 done:
11040         return ret;
11041 }
11042
11043 static int __intel_set_mode(struct drm_crtc *crtc,
11044                             struct drm_display_mode *mode,
11045                             int x, int y, struct drm_framebuffer *fb,
11046                             struct intel_crtc_state *pipe_config,
11047                             unsigned modeset_pipes,
11048                             unsigned prepare_pipes,
11049                             unsigned disable_pipes)
11050 {
11051         struct drm_device *dev = crtc->dev;
11052         struct drm_i915_private *dev_priv = dev->dev_private;
11053         struct drm_display_mode *saved_mode;
11054         struct intel_crtc *intel_crtc;
11055         int ret = 0;
11056
11057         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11058         if (!saved_mode)
11059                 return -ENOMEM;
11060
11061         *saved_mode = crtc->mode;
11062
11063         if (modeset_pipes)
11064                 to_intel_crtc(crtc)->new_config = pipe_config;
11065
11066         /*
11067          * See if the config requires any additional preparation, e.g.
11068          * to adjust global state with pipes off.  We need to do this
11069          * here so we can get the modeset_pipe updated config for the new
11070          * mode set on this crtc.  For other crtcs we need to use the
11071          * adjusted_mode bits in the crtc directly.
11072          */
11073         if (IS_VALLEYVIEW(dev)) {
11074                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11075
11076                 /* may have added more to prepare_pipes than we should */
11077                 prepare_pipes &= ~disable_pipes;
11078         }
11079
11080         ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11081         if (ret)
11082                 goto done;
11083
11084         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11085                 intel_crtc_disable(&intel_crtc->base);
11086
11087         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11088                 if (intel_crtc->base.enabled)
11089                         dev_priv->display.crtc_disable(&intel_crtc->base);
11090         }
11091
11092         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11093          * to set it here already despite that we pass it down the callchain.
11094          *
11095          * Note we'll need to fix this up when we start tracking multiple
11096          * pipes; here we assume a single modeset_pipe and only track the
11097          * single crtc and mode.
11098          */
11099         if (modeset_pipes) {
11100                 crtc->mode = *mode;
11101                 /* mode_set/enable/disable functions rely on a correct pipe
11102                  * config. */
11103                 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11104
11105                 /*
11106                  * Calculate and store various constants which
11107                  * are later needed by vblank and swap-completion
11108                  * timestamping. They are derived from true hwmode.
11109                  */
11110                 drm_calc_timestamping_constants(crtc,
11111                                                 &pipe_config->base.adjusted_mode);
11112         }
11113
11114         /* Only after disabling all output pipelines that will be changed can we
11115          * update the the output configuration. */
11116         intel_modeset_update_state(dev, prepare_pipes);
11117
11118         modeset_update_crtc_power_domains(dev);
11119
11120         /* Set up the DPLL and any encoders state that needs to adjust or depend
11121          * on the DPLL.
11122          */
11123         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11124                 struct drm_plane *primary = intel_crtc->base.primary;
11125                 int vdisplay, hdisplay;
11126
11127                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11128                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11129                                                    fb, 0, 0,
11130                                                    hdisplay, vdisplay,
11131                                                    x << 16, y << 16,
11132                                                    hdisplay << 16, vdisplay << 16);
11133         }
11134
11135         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11136         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11137                 update_scanline_offset(intel_crtc);
11138
11139                 dev_priv->display.crtc_enable(&intel_crtc->base);
11140         }
11141
11142         /* FIXME: add subpixel order */
11143 done:
11144         if (ret && crtc->enabled)
11145                 crtc->mode = *saved_mode;
11146
11147         kfree(saved_mode);
11148         return ret;
11149 }
11150
11151 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11152                                 struct drm_display_mode *mode,
11153                                 int x, int y, struct drm_framebuffer *fb,
11154                                 struct intel_crtc_state *pipe_config,
11155                                 unsigned modeset_pipes,
11156                                 unsigned prepare_pipes,
11157                                 unsigned disable_pipes)
11158 {
11159         int ret;
11160
11161         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11162                                prepare_pipes, disable_pipes);
11163
11164         if (ret == 0)
11165                 intel_modeset_check_state(crtc->dev);
11166
11167         return ret;
11168 }
11169
11170 static int intel_set_mode(struct drm_crtc *crtc,
11171                           struct drm_display_mode *mode,
11172                           int x, int y, struct drm_framebuffer *fb)
11173 {
11174         struct intel_crtc_state *pipe_config;
11175         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11176
11177         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11178                                                    &modeset_pipes,
11179                                                    &prepare_pipes,
11180                                                    &disable_pipes);
11181
11182         if (IS_ERR(pipe_config))
11183                 return PTR_ERR(pipe_config);
11184
11185         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11186                                     modeset_pipes, prepare_pipes,
11187                                     disable_pipes);
11188 }
11189
11190 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11191 {
11192         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11193 }
11194
11195 #undef for_each_intel_crtc_masked
11196
11197 static void intel_set_config_free(struct intel_set_config *config)
11198 {
11199         if (!config)
11200                 return;
11201
11202         kfree(config->save_connector_encoders);
11203         kfree(config->save_encoder_crtcs);
11204         kfree(config->save_crtc_enabled);
11205         kfree(config);
11206 }
11207
11208 static int intel_set_config_save_state(struct drm_device *dev,
11209                                        struct intel_set_config *config)
11210 {
11211         struct drm_crtc *crtc;
11212         struct drm_encoder *encoder;
11213         struct drm_connector *connector;
11214         int count;
11215
11216         config->save_crtc_enabled =
11217                 kcalloc(dev->mode_config.num_crtc,
11218                         sizeof(bool), GFP_KERNEL);
11219         if (!config->save_crtc_enabled)
11220                 return -ENOMEM;
11221
11222         config->save_encoder_crtcs =
11223                 kcalloc(dev->mode_config.num_encoder,
11224                         sizeof(struct drm_crtc *), GFP_KERNEL);
11225         if (!config->save_encoder_crtcs)
11226                 return -ENOMEM;
11227
11228         config->save_connector_encoders =
11229                 kcalloc(dev->mode_config.num_connector,
11230                         sizeof(struct drm_encoder *), GFP_KERNEL);
11231         if (!config->save_connector_encoders)
11232                 return -ENOMEM;
11233
11234         /* Copy data. Note that driver private data is not affected.
11235          * Should anything bad happen only the expected state is
11236          * restored, not the drivers personal bookkeeping.
11237          */
11238         count = 0;
11239         for_each_crtc(dev, crtc) {
11240                 config->save_crtc_enabled[count++] = crtc->enabled;
11241         }
11242
11243         count = 0;
11244         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11245                 config->save_encoder_crtcs[count++] = encoder->crtc;
11246         }
11247
11248         count = 0;
11249         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11250                 config->save_connector_encoders[count++] = connector->encoder;
11251         }
11252
11253         return 0;
11254 }
11255
11256 static void intel_set_config_restore_state(struct drm_device *dev,
11257                                            struct intel_set_config *config)
11258 {
11259         struct intel_crtc *crtc;
11260         struct intel_encoder *encoder;
11261         struct intel_connector *connector;
11262         int count;
11263
11264         count = 0;
11265         for_each_intel_crtc(dev, crtc) {
11266                 crtc->new_enabled = config->save_crtc_enabled[count++];
11267
11268                 if (crtc->new_enabled)
11269                         crtc->new_config = crtc->config;
11270                 else
11271                         crtc->new_config = NULL;
11272         }
11273
11274         count = 0;
11275         for_each_intel_encoder(dev, encoder) {
11276                 encoder->new_crtc =
11277                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11278         }
11279
11280         count = 0;
11281         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11282                 connector->new_encoder =
11283                         to_intel_encoder(config->save_connector_encoders[count++]);
11284         }
11285 }
11286
11287 static bool
11288 is_crtc_connector_off(struct drm_mode_set *set)
11289 {
11290         int i;
11291
11292         if (set->num_connectors == 0)
11293                 return false;
11294
11295         if (WARN_ON(set->connectors == NULL))
11296                 return false;
11297
11298         for (i = 0; i < set->num_connectors; i++)
11299                 if (set->connectors[i]->encoder &&
11300                     set->connectors[i]->encoder->crtc == set->crtc &&
11301                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11302                         return true;
11303
11304         return false;
11305 }
11306
11307 static void
11308 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11309                                       struct intel_set_config *config)
11310 {
11311
11312         /* We should be able to check here if the fb has the same properties
11313          * and then just flip_or_move it */
11314         if (is_crtc_connector_off(set)) {
11315                 config->mode_changed = true;
11316         } else if (set->crtc->primary->fb != set->fb) {
11317                 /*
11318                  * If we have no fb, we can only flip as long as the crtc is
11319                  * active, otherwise we need a full mode set.  The crtc may
11320                  * be active if we've only disabled the primary plane, or
11321                  * in fastboot situations.
11322                  */
11323                 if (set->crtc->primary->fb == NULL) {
11324                         struct intel_crtc *intel_crtc =
11325                                 to_intel_crtc(set->crtc);
11326
11327                         if (intel_crtc->active) {
11328                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11329                                 config->fb_changed = true;
11330                         } else {
11331                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11332                                 config->mode_changed = true;
11333                         }
11334                 } else if (set->fb == NULL) {
11335                         config->mode_changed = true;
11336                 } else if (set->fb->pixel_format !=
11337                            set->crtc->primary->fb->pixel_format) {
11338                         config->mode_changed = true;
11339                 } else {
11340                         config->fb_changed = true;
11341                 }
11342         }
11343
11344         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11345                 config->fb_changed = true;
11346
11347         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11348                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11349                 drm_mode_debug_printmodeline(&set->crtc->mode);
11350                 drm_mode_debug_printmodeline(set->mode);
11351                 config->mode_changed = true;
11352         }
11353
11354         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11355                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11356 }
11357
11358 static int
11359 intel_modeset_stage_output_state(struct drm_device *dev,
11360                                  struct drm_mode_set *set,
11361                                  struct intel_set_config *config)
11362 {
11363         struct intel_connector *connector;
11364         struct intel_encoder *encoder;
11365         struct intel_crtc *crtc;
11366         int ro;
11367
11368         /* The upper layers ensure that we either disable a crtc or have a list
11369          * of connectors. For paranoia, double-check this. */
11370         WARN_ON(!set->fb && (set->num_connectors != 0));
11371         WARN_ON(set->fb && (set->num_connectors == 0));
11372
11373         list_for_each_entry(connector, &dev->mode_config.connector_list,
11374                             base.head) {
11375                 /* Otherwise traverse passed in connector list and get encoders
11376                  * for them. */
11377                 for (ro = 0; ro < set->num_connectors; ro++) {
11378                         if (set->connectors[ro] == &connector->base) {
11379                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11380                                 break;
11381                         }
11382                 }
11383
11384                 /* If we disable the crtc, disable all its connectors. Also, if
11385                  * the connector is on the changing crtc but not on the new
11386                  * connector list, disable it. */
11387                 if ((!set->fb || ro == set->num_connectors) &&
11388                     connector->base.encoder &&
11389                     connector->base.encoder->crtc == set->crtc) {
11390                         connector->new_encoder = NULL;
11391
11392                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11393                                 connector->base.base.id,
11394                                 connector->base.name);
11395                 }
11396
11397
11398                 if (&connector->new_encoder->base != connector->base.encoder) {
11399                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11400                         config->mode_changed = true;
11401                 }
11402         }
11403         /* connector->new_encoder is now updated for all connectors. */
11404
11405         /* Update crtc of enabled connectors. */
11406         list_for_each_entry(connector, &dev->mode_config.connector_list,
11407                             base.head) {
11408                 struct drm_crtc *new_crtc;
11409
11410                 if (!connector->new_encoder)
11411                         continue;
11412
11413                 new_crtc = connector->new_encoder->base.crtc;
11414
11415                 for (ro = 0; ro < set->num_connectors; ro++) {
11416                         if (set->connectors[ro] == &connector->base)
11417                                 new_crtc = set->crtc;
11418                 }
11419
11420                 /* Make sure the new CRTC will work with the encoder */
11421                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11422                                          new_crtc)) {
11423                         return -EINVAL;
11424                 }
11425                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11426
11427                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11428                         connector->base.base.id,
11429                         connector->base.name,
11430                         new_crtc->base.id);
11431         }
11432
11433         /* Check for any encoders that needs to be disabled. */
11434         for_each_intel_encoder(dev, encoder) {
11435                 int num_connectors = 0;
11436                 list_for_each_entry(connector,
11437                                     &dev->mode_config.connector_list,
11438                                     base.head) {
11439                         if (connector->new_encoder == encoder) {
11440                                 WARN_ON(!connector->new_encoder->new_crtc);
11441                                 num_connectors++;
11442                         }
11443                 }
11444
11445                 if (num_connectors == 0)
11446                         encoder->new_crtc = NULL;
11447                 else if (num_connectors > 1)
11448                         return -EINVAL;
11449
11450                 /* Only now check for crtc changes so we don't miss encoders
11451                  * that will be disabled. */
11452                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11453                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11454                         config->mode_changed = true;
11455                 }
11456         }
11457         /* Now we've also updated encoder->new_crtc for all encoders. */
11458         list_for_each_entry(connector, &dev->mode_config.connector_list,
11459                             base.head) {
11460                 if (connector->new_encoder)
11461                         if (connector->new_encoder != connector->encoder)
11462                                 connector->encoder = connector->new_encoder;
11463         }
11464         for_each_intel_crtc(dev, crtc) {
11465                 crtc->new_enabled = false;
11466
11467                 for_each_intel_encoder(dev, encoder) {
11468                         if (encoder->new_crtc == crtc) {
11469                                 crtc->new_enabled = true;
11470                                 break;
11471                         }
11472                 }
11473
11474                 if (crtc->new_enabled != crtc->base.enabled) {
11475                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11476                                       crtc->new_enabled ? "en" : "dis");
11477                         config->mode_changed = true;
11478                 }
11479
11480                 if (crtc->new_enabled)
11481                         crtc->new_config = crtc->config;
11482                 else
11483                         crtc->new_config = NULL;
11484         }
11485
11486         return 0;
11487 }
11488
11489 static void disable_crtc_nofb(struct intel_crtc *crtc)
11490 {
11491         struct drm_device *dev = crtc->base.dev;
11492         struct intel_encoder *encoder;
11493         struct intel_connector *connector;
11494
11495         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11496                       pipe_name(crtc->pipe));
11497
11498         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11499                 if (connector->new_encoder &&
11500                     connector->new_encoder->new_crtc == crtc)
11501                         connector->new_encoder = NULL;
11502         }
11503
11504         for_each_intel_encoder(dev, encoder) {
11505                 if (encoder->new_crtc == crtc)
11506                         encoder->new_crtc = NULL;
11507         }
11508
11509         crtc->new_enabled = false;
11510         crtc->new_config = NULL;
11511 }
11512
11513 static int intel_crtc_set_config(struct drm_mode_set *set)
11514 {
11515         struct drm_device *dev;
11516         struct drm_mode_set save_set;
11517         struct intel_set_config *config;
11518         struct intel_crtc_state *pipe_config;
11519         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11520         int ret;
11521
11522         BUG_ON(!set);
11523         BUG_ON(!set->crtc);
11524         BUG_ON(!set->crtc->helper_private);
11525
11526         /* Enforce sane interface api - has been abused by the fb helper. */
11527         BUG_ON(!set->mode && set->fb);
11528         BUG_ON(set->fb && set->num_connectors == 0);
11529
11530         if (set->fb) {
11531                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11532                                 set->crtc->base.id, set->fb->base.id,
11533                                 (int)set->num_connectors, set->x, set->y);
11534         } else {
11535                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11536         }
11537
11538         dev = set->crtc->dev;
11539
11540         ret = -ENOMEM;
11541         config = kzalloc(sizeof(*config), GFP_KERNEL);
11542         if (!config)
11543                 goto out_config;
11544
11545         ret = intel_set_config_save_state(dev, config);
11546         if (ret)
11547                 goto out_config;
11548
11549         save_set.crtc = set->crtc;
11550         save_set.mode = &set->crtc->mode;
11551         save_set.x = set->crtc->x;
11552         save_set.y = set->crtc->y;
11553         save_set.fb = set->crtc->primary->fb;
11554
11555         /* Compute whether we need a full modeset, only an fb base update or no
11556          * change at all. In the future we might also check whether only the
11557          * mode changed, e.g. for LVDS where we only change the panel fitter in
11558          * such cases. */
11559         intel_set_config_compute_mode_changes(set, config);
11560
11561         ret = intel_modeset_stage_output_state(dev, set, config);
11562         if (ret)
11563                 goto fail;
11564
11565         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11566                                                    set->fb,
11567                                                    &modeset_pipes,
11568                                                    &prepare_pipes,
11569                                                    &disable_pipes);
11570         if (IS_ERR(pipe_config)) {
11571                 ret = PTR_ERR(pipe_config);
11572                 goto fail;
11573         } else if (pipe_config) {
11574                 if (pipe_config->has_audio !=
11575                     to_intel_crtc(set->crtc)->config->has_audio)
11576                         config->mode_changed = true;
11577
11578                 /*
11579                  * Note we have an issue here with infoframes: current code
11580                  * only updates them on the full mode set path per hw
11581                  * requirements.  So here we should be checking for any
11582                  * required changes and forcing a mode set.
11583                  */
11584         }
11585
11586         /* set_mode will free it in the mode_changed case */
11587         if (!config->mode_changed)
11588                 kfree(pipe_config);
11589
11590         intel_update_pipe_size(to_intel_crtc(set->crtc));
11591
11592         if (config->mode_changed) {
11593                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11594                                            set->x, set->y, set->fb, pipe_config,
11595                                            modeset_pipes, prepare_pipes,
11596                                            disable_pipes);
11597         } else if (config->fb_changed) {
11598                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11599                 struct drm_plane *primary = set->crtc->primary;
11600                 int vdisplay, hdisplay;
11601
11602                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11603                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11604                                                    0, 0, hdisplay, vdisplay,
11605                                                    set->x << 16, set->y << 16,
11606                                                    hdisplay << 16, vdisplay << 16);
11607
11608                 /*
11609                  * We need to make sure the primary plane is re-enabled if it
11610                  * has previously been turned off.
11611                  */
11612                 if (!intel_crtc->primary_enabled && ret == 0) {
11613                         WARN_ON(!intel_crtc->active);
11614                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11615                 }
11616
11617                 /*
11618                  * In the fastboot case this may be our only check of the
11619                  * state after boot.  It would be better to only do it on
11620                  * the first update, but we don't have a nice way of doing that
11621                  * (and really, set_config isn't used much for high freq page
11622                  * flipping, so increasing its cost here shouldn't be a big
11623                  * deal).
11624                  */
11625                 if (i915.fastboot && ret == 0)
11626                         intel_modeset_check_state(set->crtc->dev);
11627         }
11628
11629         if (ret) {
11630                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11631                               set->crtc->base.id, ret);
11632 fail:
11633                 intel_set_config_restore_state(dev, config);
11634
11635                 /*
11636                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11637                  * force the pipe off to avoid oopsing in the modeset code
11638                  * due to fb==NULL. This should only happen during boot since
11639                  * we don't yet reconstruct the FB from the hardware state.
11640                  */
11641                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11642                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11643
11644                 /* Try to restore the config */
11645                 if (config->mode_changed &&
11646                     intel_set_mode(save_set.crtc, save_set.mode,
11647                                    save_set.x, save_set.y, save_set.fb))
11648                         DRM_ERROR("failed to restore config after modeset failure\n");
11649         }
11650
11651 out_config:
11652         intel_set_config_free(config);
11653         return ret;
11654 }
11655
11656 static const struct drm_crtc_funcs intel_crtc_funcs = {
11657         .gamma_set = intel_crtc_gamma_set,
11658         .set_config = intel_crtc_set_config,
11659         .destroy = intel_crtc_destroy,
11660         .page_flip = intel_crtc_page_flip,
11661         .atomic_duplicate_state = intel_crtc_duplicate_state,
11662         .atomic_destroy_state = intel_crtc_destroy_state,
11663 };
11664
11665 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11666                                       struct intel_shared_dpll *pll,
11667                                       struct intel_dpll_hw_state *hw_state)
11668 {
11669         uint32_t val;
11670
11671         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11672                 return false;
11673
11674         val = I915_READ(PCH_DPLL(pll->id));
11675         hw_state->dpll = val;
11676         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11677         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11678
11679         return val & DPLL_VCO_ENABLE;
11680 }
11681
11682 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11683                                   struct intel_shared_dpll *pll)
11684 {
11685         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11686         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11687 }
11688
11689 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11690                                 struct intel_shared_dpll *pll)
11691 {
11692         /* PCH refclock must be enabled first */
11693         ibx_assert_pch_refclk_enabled(dev_priv);
11694
11695         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11696
11697         /* Wait for the clocks to stabilize. */
11698         POSTING_READ(PCH_DPLL(pll->id));
11699         udelay(150);
11700
11701         /* The pixel multiplier can only be updated once the
11702          * DPLL is enabled and the clocks are stable.
11703          *
11704          * So write it again.
11705          */
11706         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11707         POSTING_READ(PCH_DPLL(pll->id));
11708         udelay(200);
11709 }
11710
11711 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11712                                  struct intel_shared_dpll *pll)
11713 {
11714         struct drm_device *dev = dev_priv->dev;
11715         struct intel_crtc *crtc;
11716
11717         /* Make sure no transcoder isn't still depending on us. */
11718         for_each_intel_crtc(dev, crtc) {
11719                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11720                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11721         }
11722
11723         I915_WRITE(PCH_DPLL(pll->id), 0);
11724         POSTING_READ(PCH_DPLL(pll->id));
11725         udelay(200);
11726 }
11727
11728 static char *ibx_pch_dpll_names[] = {
11729         "PCH DPLL A",
11730         "PCH DPLL B",
11731 };
11732
11733 static void ibx_pch_dpll_init(struct drm_device *dev)
11734 {
11735         struct drm_i915_private *dev_priv = dev->dev_private;
11736         int i;
11737
11738         dev_priv->num_shared_dpll = 2;
11739
11740         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11741                 dev_priv->shared_dplls[i].id = i;
11742                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11743                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11744                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11745                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11746                 dev_priv->shared_dplls[i].get_hw_state =
11747                         ibx_pch_dpll_get_hw_state;
11748         }
11749 }
11750
11751 static void intel_shared_dpll_init(struct drm_device *dev)
11752 {
11753         struct drm_i915_private *dev_priv = dev->dev_private;
11754
11755         if (HAS_DDI(dev))
11756                 intel_ddi_pll_init(dev);
11757         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11758                 ibx_pch_dpll_init(dev);
11759         else
11760                 dev_priv->num_shared_dpll = 0;
11761
11762         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11763 }
11764
11765 /**
11766  * intel_prepare_plane_fb - Prepare fb for usage on plane
11767  * @plane: drm plane to prepare for
11768  * @fb: framebuffer to prepare for presentation
11769  *
11770  * Prepares a framebuffer for usage on a display plane.  Generally this
11771  * involves pinning the underlying object and updating the frontbuffer tracking
11772  * bits.  Some older platforms need special physical address handling for
11773  * cursor planes.
11774  *
11775  * Returns 0 on success, negative error code on failure.
11776  */
11777 int
11778 intel_prepare_plane_fb(struct drm_plane *plane,
11779                        struct drm_framebuffer *fb,
11780                        const struct drm_plane_state *new_state)
11781 {
11782         struct drm_device *dev = plane->dev;
11783         struct intel_plane *intel_plane = to_intel_plane(plane);
11784         enum pipe pipe = intel_plane->pipe;
11785         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11786         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11787         unsigned frontbuffer_bits = 0;
11788         int ret = 0;
11789
11790         if (!obj)
11791                 return 0;
11792
11793         switch (plane->type) {
11794         case DRM_PLANE_TYPE_PRIMARY:
11795                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11796                 break;
11797         case DRM_PLANE_TYPE_CURSOR:
11798                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11799                 break;
11800         case DRM_PLANE_TYPE_OVERLAY:
11801                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11802                 break;
11803         }
11804
11805         mutex_lock(&dev->struct_mutex);
11806
11807         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11808             INTEL_INFO(dev)->cursor_needs_physical) {
11809                 int align = IS_I830(dev) ? 16 * 1024 : 256;
11810                 ret = i915_gem_object_attach_phys(obj, align);
11811                 if (ret)
11812                         DRM_DEBUG_KMS("failed to attach phys object\n");
11813         } else {
11814                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11815         }
11816
11817         if (ret == 0)
11818                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11819
11820         mutex_unlock(&dev->struct_mutex);
11821
11822         return ret;
11823 }
11824
11825 /**
11826  * intel_cleanup_plane_fb - Cleans up an fb after plane use
11827  * @plane: drm plane to clean up for
11828  * @fb: old framebuffer that was on plane
11829  *
11830  * Cleans up a framebuffer that has just been removed from a plane.
11831  */
11832 void
11833 intel_cleanup_plane_fb(struct drm_plane *plane,
11834                        struct drm_framebuffer *fb,
11835                        const struct drm_plane_state *old_state)
11836 {
11837         struct drm_device *dev = plane->dev;
11838         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11839
11840         if (WARN_ON(!obj))
11841                 return;
11842
11843         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11844             !INTEL_INFO(dev)->cursor_needs_physical) {
11845                 mutex_lock(&dev->struct_mutex);
11846                 intel_unpin_fb_obj(obj);
11847                 mutex_unlock(&dev->struct_mutex);
11848         }
11849 }
11850
11851 static int
11852 intel_check_primary_plane(struct drm_plane *plane,
11853                           struct intel_plane_state *state)
11854 {
11855         struct drm_device *dev = plane->dev;
11856         struct drm_i915_private *dev_priv = dev->dev_private;
11857         struct drm_crtc *crtc = state->base.crtc;
11858         struct intel_crtc *intel_crtc;
11859         struct drm_framebuffer *fb = state->base.fb;
11860         struct drm_rect *dest = &state->dst;
11861         struct drm_rect *src = &state->src;
11862         const struct drm_rect *clip = &state->clip;
11863         int ret;
11864
11865         crtc = crtc ? crtc : plane->crtc;
11866         intel_crtc = to_intel_crtc(crtc);
11867
11868         ret = drm_plane_helper_check_update(plane, crtc, fb,
11869                                             src, dest, clip,
11870                                             DRM_PLANE_HELPER_NO_SCALING,
11871                                             DRM_PLANE_HELPER_NO_SCALING,
11872                                             false, true, &state->visible);
11873         if (ret)
11874                 return ret;
11875
11876         if (intel_crtc->active) {
11877                 intel_crtc->atomic.wait_for_flips = true;
11878
11879                 /*
11880                  * FBC does not work on some platforms for rotated
11881                  * planes, so disable it when rotation is not 0 and
11882                  * update it when rotation is set back to 0.
11883                  *
11884                  * FIXME: This is redundant with the fbc update done in
11885                  * the primary plane enable function except that that
11886                  * one is done too late. We eventually need to unify
11887                  * this.
11888                  */
11889                 if (intel_crtc->primary_enabled &&
11890                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11891                     dev_priv->fbc.crtc == intel_crtc &&
11892                     state->base.rotation != BIT(DRM_ROTATE_0)) {
11893                         intel_crtc->atomic.disable_fbc = true;
11894                 }
11895
11896                 if (state->visible) {
11897                         /*
11898                          * BDW signals flip done immediately if the plane
11899                          * is disabled, even if the plane enable is already
11900                          * armed to occur at the next vblank :(
11901                          */
11902                         if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11903                                 intel_crtc->atomic.wait_vblank = true;
11904                 }
11905
11906                 intel_crtc->atomic.fb_bits |=
11907                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11908
11909                 intel_crtc->atomic.update_fbc = true;
11910         }
11911
11912         return 0;
11913 }
11914
11915 static void
11916 intel_commit_primary_plane(struct drm_plane *plane,
11917                            struct intel_plane_state *state)
11918 {
11919         struct drm_crtc *crtc = state->base.crtc;
11920         struct drm_framebuffer *fb = state->base.fb;
11921         struct drm_device *dev = plane->dev;
11922         struct drm_i915_private *dev_priv = dev->dev_private;
11923         struct intel_crtc *intel_crtc;
11924         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11925         struct intel_plane *intel_plane = to_intel_plane(plane);
11926         struct drm_rect *src = &state->src;
11927
11928         crtc = crtc ? crtc : plane->crtc;
11929         intel_crtc = to_intel_crtc(crtc);
11930
11931         plane->fb = fb;
11932         crtc->x = src->x1 >> 16;
11933         crtc->y = src->y1 >> 16;
11934
11935         intel_plane->obj = obj;
11936
11937         if (intel_crtc->active) {
11938                 if (state->visible) {
11939                         /* FIXME: kill this fastboot hack */
11940                         intel_update_pipe_size(intel_crtc);
11941
11942                         intel_crtc->primary_enabled = true;
11943
11944                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11945                                         crtc->x, crtc->y);
11946                 } else {
11947                         /*
11948                          * If clipping results in a non-visible primary plane,
11949                          * we'll disable the primary plane.  Note that this is
11950                          * a bit different than what happens if userspace
11951                          * explicitly disables the plane by passing fb=0
11952                          * because plane->fb still gets set and pinned.
11953                          */
11954                         intel_disable_primary_hw_plane(plane, crtc);
11955                 }
11956         }
11957 }
11958
11959 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
11960 {
11961         struct drm_device *dev = crtc->dev;
11962         struct drm_i915_private *dev_priv = dev->dev_private;
11963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11964         struct intel_plane *intel_plane;
11965         struct drm_plane *p;
11966         unsigned fb_bits = 0;
11967
11968         /* Track fb's for any planes being disabled */
11969         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
11970                 intel_plane = to_intel_plane(p);
11971
11972                 if (intel_crtc->atomic.disabled_planes &
11973                     (1 << drm_plane_index(p))) {
11974                         switch (p->type) {
11975                         case DRM_PLANE_TYPE_PRIMARY:
11976                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
11977                                 break;
11978                         case DRM_PLANE_TYPE_CURSOR:
11979                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
11980                                 break;
11981                         case DRM_PLANE_TYPE_OVERLAY:
11982                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
11983                                 break;
11984                         }
11985
11986                         mutex_lock(&dev->struct_mutex);
11987                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
11988                         mutex_unlock(&dev->struct_mutex);
11989                 }
11990         }
11991
11992         if (intel_crtc->atomic.wait_for_flips)
11993                 intel_crtc_wait_for_pending_flips(crtc);
11994
11995         if (intel_crtc->atomic.disable_fbc)
11996                 intel_fbc_disable(dev);
11997
11998         if (intel_crtc->atomic.pre_disable_primary)
11999                 intel_pre_disable_primary(crtc);
12000
12001         if (intel_crtc->atomic.update_wm)
12002                 intel_update_watermarks(crtc);
12003
12004         intel_runtime_pm_get(dev_priv);
12005
12006         /* Perform vblank evasion around commit operation */
12007         if (intel_crtc->active)
12008                 intel_crtc->atomic.evade =
12009                         intel_pipe_update_start(intel_crtc,
12010                                                 &intel_crtc->atomic.start_vbl_count);
12011 }
12012
12013 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12014 {
12015         struct drm_device *dev = crtc->dev;
12016         struct drm_i915_private *dev_priv = dev->dev_private;
12017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12018         struct drm_plane *p;
12019
12020         if (intel_crtc->atomic.evade)
12021                 intel_pipe_update_end(intel_crtc,
12022                                       intel_crtc->atomic.start_vbl_count);
12023
12024         intel_runtime_pm_put(dev_priv);
12025
12026         if (intel_crtc->atomic.wait_vblank)
12027                 intel_wait_for_vblank(dev, intel_crtc->pipe);
12028
12029         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12030
12031         if (intel_crtc->atomic.update_fbc) {
12032                 mutex_lock(&dev->struct_mutex);
12033                 intel_fbc_update(dev);
12034                 mutex_unlock(&dev->struct_mutex);
12035         }
12036
12037         if (intel_crtc->atomic.post_enable_primary)
12038                 intel_post_enable_primary(crtc);
12039
12040         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12041                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12042                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12043                                                        false, false);
12044
12045         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12046 }
12047
12048 /**
12049  * intel_plane_destroy - destroy a plane
12050  * @plane: plane to destroy
12051  *
12052  * Common destruction function for all types of planes (primary, cursor,
12053  * sprite).
12054  */
12055 void intel_plane_destroy(struct drm_plane *plane)
12056 {
12057         struct intel_plane *intel_plane = to_intel_plane(plane);
12058         drm_plane_cleanup(plane);
12059         kfree(intel_plane);
12060 }
12061
12062 const struct drm_plane_funcs intel_plane_funcs = {
12063         .update_plane = drm_atomic_helper_update_plane,
12064         .disable_plane = drm_atomic_helper_disable_plane,
12065         .destroy = intel_plane_destroy,
12066         .set_property = drm_atomic_helper_plane_set_property,
12067         .atomic_get_property = intel_plane_atomic_get_property,
12068         .atomic_set_property = intel_plane_atomic_set_property,
12069         .atomic_duplicate_state = intel_plane_duplicate_state,
12070         .atomic_destroy_state = intel_plane_destroy_state,
12071
12072 };
12073
12074 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12075                                                     int pipe)
12076 {
12077         struct intel_plane *primary;
12078         struct intel_plane_state *state;
12079         const uint32_t *intel_primary_formats;
12080         int num_formats;
12081
12082         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12083         if (primary == NULL)
12084                 return NULL;
12085
12086         state = intel_create_plane_state(&primary->base);
12087         if (!state) {
12088                 kfree(primary);
12089                 return NULL;
12090         }
12091         primary->base.state = &state->base;
12092
12093         primary->can_scale = false;
12094         primary->max_downscale = 1;
12095         primary->pipe = pipe;
12096         primary->plane = pipe;
12097         primary->check_plane = intel_check_primary_plane;
12098         primary->commit_plane = intel_commit_primary_plane;
12099         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12100                 primary->plane = !pipe;
12101
12102         if (INTEL_INFO(dev)->gen <= 3) {
12103                 intel_primary_formats = intel_primary_formats_gen2;
12104                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12105         } else {
12106                 intel_primary_formats = intel_primary_formats_gen4;
12107                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12108         }
12109
12110         drm_universal_plane_init(dev, &primary->base, 0,
12111                                  &intel_plane_funcs,
12112                                  intel_primary_formats, num_formats,
12113                                  DRM_PLANE_TYPE_PRIMARY);
12114
12115         if (INTEL_INFO(dev)->gen >= 4) {
12116                 if (!dev->mode_config.rotation_property)
12117                         dev->mode_config.rotation_property =
12118                                 drm_mode_create_rotation_property(dev,
12119                                                         BIT(DRM_ROTATE_0) |
12120                                                         BIT(DRM_ROTATE_180));
12121                 if (dev->mode_config.rotation_property)
12122                         drm_object_attach_property(&primary->base.base,
12123                                 dev->mode_config.rotation_property,
12124                                 state->base.rotation);
12125         }
12126
12127         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12128
12129         return &primary->base;
12130 }
12131
12132 static int
12133 intel_check_cursor_plane(struct drm_plane *plane,
12134                          struct intel_plane_state *state)
12135 {
12136         struct drm_crtc *crtc = state->base.crtc;
12137         struct drm_device *dev = plane->dev;
12138         struct drm_framebuffer *fb = state->base.fb;
12139         struct drm_rect *dest = &state->dst;
12140         struct drm_rect *src = &state->src;
12141         const struct drm_rect *clip = &state->clip;
12142         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12143         struct intel_crtc *intel_crtc;
12144         unsigned stride;
12145         int ret;
12146
12147         crtc = crtc ? crtc : plane->crtc;
12148         intel_crtc = to_intel_crtc(crtc);
12149
12150         ret = drm_plane_helper_check_update(plane, crtc, fb,
12151                                             src, dest, clip,
12152                                             DRM_PLANE_HELPER_NO_SCALING,
12153                                             DRM_PLANE_HELPER_NO_SCALING,
12154                                             true, true, &state->visible);
12155         if (ret)
12156                 return ret;
12157
12158
12159         /* if we want to turn off the cursor ignore width and height */
12160         if (!obj)
12161                 goto finish;
12162
12163         /* Check for which cursor types we support */
12164         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12165                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12166                           state->base.crtc_w, state->base.crtc_h);
12167                 return -EINVAL;
12168         }
12169
12170         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12171         if (obj->base.size < stride * state->base.crtc_h) {
12172                 DRM_DEBUG_KMS("buffer is too small\n");
12173                 return -ENOMEM;
12174         }
12175
12176         if (fb == crtc->cursor->fb)
12177                 return 0;
12178
12179         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12180                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12181                 ret = -EINVAL;
12182         }
12183
12184 finish:
12185         if (intel_crtc->active) {
12186                 if (intel_crtc->cursor_width != state->base.crtc_w)
12187                         intel_crtc->atomic.update_wm = true;
12188
12189                 intel_crtc->atomic.fb_bits |=
12190                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12191         }
12192
12193         return ret;
12194 }
12195
12196 static void
12197 intel_commit_cursor_plane(struct drm_plane *plane,
12198                           struct intel_plane_state *state)
12199 {
12200         struct drm_crtc *crtc = state->base.crtc;
12201         struct drm_device *dev = plane->dev;
12202         struct intel_crtc *intel_crtc;
12203         struct intel_plane *intel_plane = to_intel_plane(plane);
12204         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12205         uint32_t addr;
12206
12207         crtc = crtc ? crtc : plane->crtc;
12208         intel_crtc = to_intel_crtc(crtc);
12209
12210         plane->fb = state->base.fb;
12211         crtc->cursor_x = state->base.crtc_x;
12212         crtc->cursor_y = state->base.crtc_y;
12213
12214         intel_plane->obj = obj;
12215
12216         if (intel_crtc->cursor_bo == obj)
12217                 goto update;
12218
12219         if (!obj)
12220                 addr = 0;
12221         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12222                 addr = i915_gem_obj_ggtt_offset(obj);
12223         else
12224                 addr = obj->phys_handle->busaddr;
12225
12226         intel_crtc->cursor_addr = addr;
12227         intel_crtc->cursor_bo = obj;
12228 update:
12229         intel_crtc->cursor_width = state->base.crtc_w;
12230         intel_crtc->cursor_height = state->base.crtc_h;
12231
12232         if (intel_crtc->active)
12233                 intel_crtc_update_cursor(crtc, state->visible);
12234 }
12235
12236 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12237                                                    int pipe)
12238 {
12239         struct intel_plane *cursor;
12240         struct intel_plane_state *state;
12241
12242         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12243         if (cursor == NULL)
12244                 return NULL;
12245
12246         state = intel_create_plane_state(&cursor->base);
12247         if (!state) {
12248                 kfree(cursor);
12249                 return NULL;
12250         }
12251         cursor->base.state = &state->base;
12252
12253         cursor->can_scale = false;
12254         cursor->max_downscale = 1;
12255         cursor->pipe = pipe;
12256         cursor->plane = pipe;
12257         cursor->check_plane = intel_check_cursor_plane;
12258         cursor->commit_plane = intel_commit_cursor_plane;
12259
12260         drm_universal_plane_init(dev, &cursor->base, 0,
12261                                  &intel_plane_funcs,
12262                                  intel_cursor_formats,
12263                                  ARRAY_SIZE(intel_cursor_formats),
12264                                  DRM_PLANE_TYPE_CURSOR);
12265
12266         if (INTEL_INFO(dev)->gen >= 4) {
12267                 if (!dev->mode_config.rotation_property)
12268                         dev->mode_config.rotation_property =
12269                                 drm_mode_create_rotation_property(dev,
12270                                                         BIT(DRM_ROTATE_0) |
12271                                                         BIT(DRM_ROTATE_180));
12272                 if (dev->mode_config.rotation_property)
12273                         drm_object_attach_property(&cursor->base.base,
12274                                 dev->mode_config.rotation_property,
12275                                 state->base.rotation);
12276         }
12277
12278         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12279
12280         return &cursor->base;
12281 }
12282
12283 static void intel_crtc_init(struct drm_device *dev, int pipe)
12284 {
12285         struct drm_i915_private *dev_priv = dev->dev_private;
12286         struct intel_crtc *intel_crtc;
12287         struct intel_crtc_state *crtc_state = NULL;
12288         struct drm_plane *primary = NULL;
12289         struct drm_plane *cursor = NULL;
12290         int i, ret;
12291
12292         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12293         if (intel_crtc == NULL)
12294                 return;
12295
12296         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12297         if (!crtc_state)
12298                 goto fail;
12299         intel_crtc_set_state(intel_crtc, crtc_state);
12300
12301         primary = intel_primary_plane_create(dev, pipe);
12302         if (!primary)
12303                 goto fail;
12304
12305         cursor = intel_cursor_plane_create(dev, pipe);
12306         if (!cursor)
12307                 goto fail;
12308
12309         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12310                                         cursor, &intel_crtc_funcs);
12311         if (ret)
12312                 goto fail;
12313
12314         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12315         for (i = 0; i < 256; i++) {
12316                 intel_crtc->lut_r[i] = i;
12317                 intel_crtc->lut_g[i] = i;
12318                 intel_crtc->lut_b[i] = i;
12319         }
12320
12321         /*
12322          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12323          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12324          */
12325         intel_crtc->pipe = pipe;
12326         intel_crtc->plane = pipe;
12327         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12328                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12329                 intel_crtc->plane = !pipe;
12330         }
12331
12332         intel_crtc->cursor_base = ~0;
12333         intel_crtc->cursor_cntl = ~0;
12334         intel_crtc->cursor_size = ~0;
12335
12336         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12337                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12338         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12339         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12340
12341         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12342
12343         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12344
12345         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12346         return;
12347
12348 fail:
12349         if (primary)
12350                 drm_plane_cleanup(primary);
12351         if (cursor)
12352                 drm_plane_cleanup(cursor);
12353         kfree(crtc_state);
12354         kfree(intel_crtc);
12355 }
12356
12357 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12358 {
12359         struct drm_encoder *encoder = connector->base.encoder;
12360         struct drm_device *dev = connector->base.dev;
12361
12362         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12363
12364         if (!encoder || WARN_ON(!encoder->crtc))
12365                 return INVALID_PIPE;
12366
12367         return to_intel_crtc(encoder->crtc)->pipe;
12368 }
12369
12370 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12371                                 struct drm_file *file)
12372 {
12373         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12374         struct drm_crtc *drmmode_crtc;
12375         struct intel_crtc *crtc;
12376
12377         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12378                 return -ENODEV;
12379
12380         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12381
12382         if (!drmmode_crtc) {
12383                 DRM_ERROR("no such CRTC id\n");
12384                 return -ENOENT;
12385         }
12386
12387         crtc = to_intel_crtc(drmmode_crtc);
12388         pipe_from_crtc_id->pipe = crtc->pipe;
12389
12390         return 0;
12391 }
12392
12393 static int intel_encoder_clones(struct intel_encoder *encoder)
12394 {
12395         struct drm_device *dev = encoder->base.dev;
12396         struct intel_encoder *source_encoder;
12397         int index_mask = 0;
12398         int entry = 0;
12399
12400         for_each_intel_encoder(dev, source_encoder) {
12401                 if (encoders_cloneable(encoder, source_encoder))
12402                         index_mask |= (1 << entry);
12403
12404                 entry++;
12405         }
12406
12407         return index_mask;
12408 }
12409
12410 static bool has_edp_a(struct drm_device *dev)
12411 {
12412         struct drm_i915_private *dev_priv = dev->dev_private;
12413
12414         if (!IS_MOBILE(dev))
12415                 return false;
12416
12417         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12418                 return false;
12419
12420         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12421                 return false;
12422
12423         return true;
12424 }
12425
12426 static bool intel_crt_present(struct drm_device *dev)
12427 {
12428         struct drm_i915_private *dev_priv = dev->dev_private;
12429
12430         if (INTEL_INFO(dev)->gen >= 9)
12431                 return false;
12432
12433         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12434                 return false;
12435
12436         if (IS_CHERRYVIEW(dev))
12437                 return false;
12438
12439         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12440                 return false;
12441
12442         return true;
12443 }
12444
12445 static void intel_setup_outputs(struct drm_device *dev)
12446 {
12447         struct drm_i915_private *dev_priv = dev->dev_private;
12448         struct intel_encoder *encoder;
12449         struct drm_connector *connector;
12450         bool dpd_is_edp = false;
12451
12452         intel_lvds_init(dev);
12453
12454         if (intel_crt_present(dev))
12455                 intel_crt_init(dev);
12456
12457         if (HAS_DDI(dev)) {
12458                 int found;
12459
12460                 /* Haswell uses DDI functions to detect digital outputs */
12461                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12462                 /* DDI A only supports eDP */
12463                 if (found)
12464                         intel_ddi_init(dev, PORT_A);
12465
12466                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12467                  * register */
12468                 found = I915_READ(SFUSE_STRAP);
12469
12470                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12471                         intel_ddi_init(dev, PORT_B);
12472                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12473                         intel_ddi_init(dev, PORT_C);
12474                 if (found & SFUSE_STRAP_DDID_DETECTED)
12475                         intel_ddi_init(dev, PORT_D);
12476         } else if (HAS_PCH_SPLIT(dev)) {
12477                 int found;
12478                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12479
12480                 if (has_edp_a(dev))
12481                         intel_dp_init(dev, DP_A, PORT_A);
12482
12483                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12484                         /* PCH SDVOB multiplex with HDMIB */
12485                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12486                         if (!found)
12487                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12488                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12489                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12490                 }
12491
12492                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12493                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12494
12495                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12496                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12497
12498                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12499                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12500
12501                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12502                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12503         } else if (IS_VALLEYVIEW(dev)) {
12504                 /*
12505                  * The DP_DETECTED bit is the latched state of the DDC
12506                  * SDA pin at boot. However since eDP doesn't require DDC
12507                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12508                  * eDP ports may have been muxed to an alternate function.
12509                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12510                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12511                  * detect eDP ports.
12512                  */
12513                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12514                     !intel_dp_is_edp(dev, PORT_B))
12515                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12516                                         PORT_B);
12517                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12518                     intel_dp_is_edp(dev, PORT_B))
12519                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12520
12521                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12522                     !intel_dp_is_edp(dev, PORT_C))
12523                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12524                                         PORT_C);
12525                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12526                     intel_dp_is_edp(dev, PORT_C))
12527                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12528
12529                 if (IS_CHERRYVIEW(dev)) {
12530                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12531                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12532                                                 PORT_D);
12533                         /* eDP not supported on port D, so don't check VBT */
12534                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12535                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12536                 }
12537
12538                 intel_dsi_init(dev);
12539         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12540                 bool found = false;
12541
12542                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12543                         DRM_DEBUG_KMS("probing SDVOB\n");
12544                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12545                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12546                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12547                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12548                         }
12549
12550                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12551                                 intel_dp_init(dev, DP_B, PORT_B);
12552                 }
12553
12554                 /* Before G4X SDVOC doesn't have its own detect register */
12555
12556                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12557                         DRM_DEBUG_KMS("probing SDVOC\n");
12558                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12559                 }
12560
12561                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12562
12563                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12564                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12565                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12566                         }
12567                         if (SUPPORTS_INTEGRATED_DP(dev))
12568                                 intel_dp_init(dev, DP_C, PORT_C);
12569                 }
12570
12571                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12572                     (I915_READ(DP_D) & DP_DETECTED))
12573                         intel_dp_init(dev, DP_D, PORT_D);
12574         } else if (IS_GEN2(dev))
12575                 intel_dvo_init(dev);
12576
12577         if (SUPPORTS_TV(dev))
12578                 intel_tv_init(dev);
12579
12580         /*
12581          * FIXME:  We don't have full atomic support yet, but we want to be
12582          * able to enable/test plane updates via the atomic interface in the
12583          * meantime.  However as soon as we flip DRIVER_ATOMIC on, the DRM core
12584          * will take some atomic codepaths to lookup properties during
12585          * drmModeGetConnector() that unconditionally dereference
12586          * connector->state.
12587          *
12588          * We create a dummy connector state here for each connector to ensure
12589          * the DRM core doesn't try to dereference a NULL connector->state.
12590          * The actual connector properties will never be updated or contain
12591          * useful information, but since we're doing this specifically for
12592          * testing/debug of the plane operations (and only when a specific
12593          * kernel module option is given), that shouldn't really matter.
12594          *
12595          * Once atomic support for crtc's + connectors lands, this loop should
12596          * be removed since we'll be setting up real connector state, which
12597          * will contain Intel-specific properties.
12598          */
12599         if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12600                 list_for_each_entry(connector,
12601                                     &dev->mode_config.connector_list,
12602                                     head) {
12603                         if (!WARN_ON(connector->state)) {
12604                                 connector->state =
12605                                         kzalloc(sizeof(*connector->state),
12606                                                 GFP_KERNEL);
12607                         }
12608                 }
12609         }
12610
12611         intel_psr_init(dev);
12612
12613         for_each_intel_encoder(dev, encoder) {
12614                 encoder->base.possible_crtcs = encoder->crtc_mask;
12615                 encoder->base.possible_clones =
12616                         intel_encoder_clones(encoder);
12617         }
12618
12619         intel_init_pch_refclk(dev);
12620
12621         drm_helper_move_panel_connectors_to_head(dev);
12622 }
12623
12624 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12625 {
12626         struct drm_device *dev = fb->dev;
12627         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12628
12629         drm_framebuffer_cleanup(fb);
12630         mutex_lock(&dev->struct_mutex);
12631         WARN_ON(!intel_fb->obj->framebuffer_references--);
12632         drm_gem_object_unreference(&intel_fb->obj->base);
12633         mutex_unlock(&dev->struct_mutex);
12634         kfree(intel_fb);
12635 }
12636
12637 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12638                                                 struct drm_file *file,
12639                                                 unsigned int *handle)
12640 {
12641         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12642         struct drm_i915_gem_object *obj = intel_fb->obj;
12643
12644         return drm_gem_handle_create(file, &obj->base, handle);
12645 }
12646
12647 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12648         .destroy = intel_user_framebuffer_destroy,
12649         .create_handle = intel_user_framebuffer_create_handle,
12650 };
12651
12652 static int intel_framebuffer_init(struct drm_device *dev,
12653                                   struct intel_framebuffer *intel_fb,
12654                                   struct drm_mode_fb_cmd2 *mode_cmd,
12655                                   struct drm_i915_gem_object *obj)
12656 {
12657         int aligned_height;
12658         int pitch_limit;
12659         int ret;
12660
12661         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12662
12663         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12664                 /* Enforce that fb modifier and tiling mode match, but only for
12665                  * X-tiled. This is needed for FBC. */
12666                 if (!!(obj->tiling_mode == I915_TILING_X) !=
12667                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12668                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12669                         return -EINVAL;
12670                 }
12671         } else {
12672                 if (obj->tiling_mode == I915_TILING_X)
12673                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12674                 else if (obj->tiling_mode == I915_TILING_Y) {
12675                         DRM_DEBUG("No Y tiling for legacy addfb\n");
12676                         return -EINVAL;
12677                 }
12678         }
12679
12680         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED) {
12681                 DRM_DEBUG("hardware does not support tiling Y\n");
12682                 return -EINVAL;
12683         }
12684
12685         if (mode_cmd->pitches[0] & 63) {
12686                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12687                           mode_cmd->pitches[0]);
12688                 return -EINVAL;
12689         }
12690
12691         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12692                 pitch_limit = 32*1024;
12693         } else if (INTEL_INFO(dev)->gen >= 4) {
12694                 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)
12695                         pitch_limit = 16*1024;
12696                 else
12697                         pitch_limit = 32*1024;
12698         } else if (INTEL_INFO(dev)->gen >= 3) {
12699                 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)
12700                         pitch_limit = 8*1024;
12701                 else
12702                         pitch_limit = 16*1024;
12703         } else
12704                 /* XXX DSPC is limited to 4k tiled */
12705                 pitch_limit = 8*1024;
12706
12707         if (mode_cmd->pitches[0] > pitch_limit) {
12708                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12709                           mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED ?
12710                           "tiled" : "linear",
12711                           mode_cmd->pitches[0], pitch_limit);
12712                 return -EINVAL;
12713         }
12714
12715         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12716             mode_cmd->pitches[0] != obj->stride) {
12717                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12718                           mode_cmd->pitches[0], obj->stride);
12719                 return -EINVAL;
12720         }
12721
12722         /* Reject formats not supported by any plane early. */
12723         switch (mode_cmd->pixel_format) {
12724         case DRM_FORMAT_C8:
12725         case DRM_FORMAT_RGB565:
12726         case DRM_FORMAT_XRGB8888:
12727         case DRM_FORMAT_ARGB8888:
12728                 break;
12729         case DRM_FORMAT_XRGB1555:
12730         case DRM_FORMAT_ARGB1555:
12731                 if (INTEL_INFO(dev)->gen > 3) {
12732                         DRM_DEBUG("unsupported pixel format: %s\n",
12733                                   drm_get_format_name(mode_cmd->pixel_format));
12734                         return -EINVAL;
12735                 }
12736                 break;
12737         case DRM_FORMAT_XBGR8888:
12738         case DRM_FORMAT_ABGR8888:
12739         case DRM_FORMAT_XRGB2101010:
12740         case DRM_FORMAT_ARGB2101010:
12741         case DRM_FORMAT_XBGR2101010:
12742         case DRM_FORMAT_ABGR2101010:
12743                 if (INTEL_INFO(dev)->gen < 4) {
12744                         DRM_DEBUG("unsupported pixel format: %s\n",
12745                                   drm_get_format_name(mode_cmd->pixel_format));
12746                         return -EINVAL;
12747                 }
12748                 break;
12749         case DRM_FORMAT_YUYV:
12750         case DRM_FORMAT_UYVY:
12751         case DRM_FORMAT_YVYU:
12752         case DRM_FORMAT_VYUY:
12753                 if (INTEL_INFO(dev)->gen < 5) {
12754                         DRM_DEBUG("unsupported pixel format: %s\n",
12755                                   drm_get_format_name(mode_cmd->pixel_format));
12756                         return -EINVAL;
12757                 }
12758                 break;
12759         default:
12760                 DRM_DEBUG("unsupported pixel format: %s\n",
12761                           drm_get_format_name(mode_cmd->pixel_format));
12762                 return -EINVAL;
12763         }
12764
12765         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12766         if (mode_cmd->offsets[0] != 0)
12767                 return -EINVAL;
12768
12769         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12770                                                mode_cmd->pixel_format,
12771                                                mode_cmd->modifier[0]);
12772         /* FIXME drm helper for size checks (especially planar formats)? */
12773         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12774                 return -EINVAL;
12775
12776         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12777         intel_fb->obj = obj;
12778         intel_fb->obj->framebuffer_references++;
12779
12780         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12781         if (ret) {
12782                 DRM_ERROR("framebuffer init failed %d\n", ret);
12783                 return ret;
12784         }
12785
12786         return 0;
12787 }
12788
12789 static struct drm_framebuffer *
12790 intel_user_framebuffer_create(struct drm_device *dev,
12791                               struct drm_file *filp,
12792                               struct drm_mode_fb_cmd2 *mode_cmd)
12793 {
12794         struct drm_i915_gem_object *obj;
12795
12796         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12797                                                 mode_cmd->handles[0]));
12798         if (&obj->base == NULL)
12799                 return ERR_PTR(-ENOENT);
12800
12801         return intel_framebuffer_create(dev, mode_cmd, obj);
12802 }
12803
12804 #ifndef CONFIG_DRM_I915_FBDEV
12805 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12806 {
12807 }
12808 #endif
12809
12810 static const struct drm_mode_config_funcs intel_mode_funcs = {
12811         .fb_create = intel_user_framebuffer_create,
12812         .output_poll_changed = intel_fbdev_output_poll_changed,
12813         .atomic_check = intel_atomic_check,
12814         .atomic_commit = intel_atomic_commit,
12815 };
12816
12817 /* Set up chip specific display functions */
12818 static void intel_init_display(struct drm_device *dev)
12819 {
12820         struct drm_i915_private *dev_priv = dev->dev_private;
12821
12822         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12823                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12824         else if (IS_CHERRYVIEW(dev))
12825                 dev_priv->display.find_dpll = chv_find_best_dpll;
12826         else if (IS_VALLEYVIEW(dev))
12827                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12828         else if (IS_PINEVIEW(dev))
12829                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12830         else
12831                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12832
12833         if (INTEL_INFO(dev)->gen >= 9) {
12834                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12835                 dev_priv->display.get_initial_plane_config =
12836                         skylake_get_initial_plane_config;
12837                 dev_priv->display.crtc_compute_clock =
12838                         haswell_crtc_compute_clock;
12839                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12840                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12841                 dev_priv->display.off = ironlake_crtc_off;
12842                 dev_priv->display.update_primary_plane =
12843                         skylake_update_primary_plane;
12844         } else if (HAS_DDI(dev)) {
12845                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12846                 dev_priv->display.get_initial_plane_config =
12847                         ironlake_get_initial_plane_config;
12848                 dev_priv->display.crtc_compute_clock =
12849                         haswell_crtc_compute_clock;
12850                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12851                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12852                 dev_priv->display.off = ironlake_crtc_off;
12853                 dev_priv->display.update_primary_plane =
12854                         ironlake_update_primary_plane;
12855         } else if (HAS_PCH_SPLIT(dev)) {
12856                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12857                 dev_priv->display.get_initial_plane_config =
12858                         ironlake_get_initial_plane_config;
12859                 dev_priv->display.crtc_compute_clock =
12860                         ironlake_crtc_compute_clock;
12861                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12862                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12863                 dev_priv->display.off = ironlake_crtc_off;
12864                 dev_priv->display.update_primary_plane =
12865                         ironlake_update_primary_plane;
12866         } else if (IS_VALLEYVIEW(dev)) {
12867                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12868                 dev_priv->display.get_initial_plane_config =
12869                         i9xx_get_initial_plane_config;
12870                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12871                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12872                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12873                 dev_priv->display.off = i9xx_crtc_off;
12874                 dev_priv->display.update_primary_plane =
12875                         i9xx_update_primary_plane;
12876         } else {
12877                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12878                 dev_priv->display.get_initial_plane_config =
12879                         i9xx_get_initial_plane_config;
12880                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12881                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12882                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12883                 dev_priv->display.off = i9xx_crtc_off;
12884                 dev_priv->display.update_primary_plane =
12885                         i9xx_update_primary_plane;
12886         }
12887
12888         /* Returns the core display clock speed */
12889         if (IS_VALLEYVIEW(dev))
12890                 dev_priv->display.get_display_clock_speed =
12891                         valleyview_get_display_clock_speed;
12892         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12893                 dev_priv->display.get_display_clock_speed =
12894                         i945_get_display_clock_speed;
12895         else if (IS_I915G(dev))
12896                 dev_priv->display.get_display_clock_speed =
12897                         i915_get_display_clock_speed;
12898         else if (IS_I945GM(dev) || IS_845G(dev))
12899                 dev_priv->display.get_display_clock_speed =
12900                         i9xx_misc_get_display_clock_speed;
12901         else if (IS_PINEVIEW(dev))
12902                 dev_priv->display.get_display_clock_speed =
12903                         pnv_get_display_clock_speed;
12904         else if (IS_I915GM(dev))
12905                 dev_priv->display.get_display_clock_speed =
12906                         i915gm_get_display_clock_speed;
12907         else if (IS_I865G(dev))
12908                 dev_priv->display.get_display_clock_speed =
12909                         i865_get_display_clock_speed;
12910         else if (IS_I85X(dev))
12911                 dev_priv->display.get_display_clock_speed =
12912                         i855_get_display_clock_speed;
12913         else /* 852, 830 */
12914                 dev_priv->display.get_display_clock_speed =
12915                         i830_get_display_clock_speed;
12916
12917         if (IS_GEN5(dev)) {
12918                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12919         } else if (IS_GEN6(dev)) {
12920                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12921         } else if (IS_IVYBRIDGE(dev)) {
12922                 /* FIXME: detect B0+ stepping and use auto training */
12923                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12924                 dev_priv->display.modeset_global_resources =
12925                         ivb_modeset_global_resources;
12926         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12927                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12928         } else if (IS_VALLEYVIEW(dev)) {
12929                 dev_priv->display.modeset_global_resources =
12930                         valleyview_modeset_global_resources;
12931         }
12932
12933         switch (INTEL_INFO(dev)->gen) {
12934         case 2:
12935                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12936                 break;
12937
12938         case 3:
12939                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12940                 break;
12941
12942         case 4:
12943         case 5:
12944                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12945                 break;
12946
12947         case 6:
12948                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12949                 break;
12950         case 7:
12951         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12952                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12953                 break;
12954         case 9:
12955                 /* Drop through - unsupported since execlist only. */
12956         default:
12957                 /* Default just returns -ENODEV to indicate unsupported */
12958                 dev_priv->display.queue_flip = intel_default_queue_flip;
12959         }
12960
12961         intel_panel_init_backlight_funcs(dev);
12962
12963         mutex_init(&dev_priv->pps_mutex);
12964 }
12965
12966 /*
12967  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12968  * resume, or other times.  This quirk makes sure that's the case for
12969  * affected systems.
12970  */
12971 static void quirk_pipea_force(struct drm_device *dev)
12972 {
12973         struct drm_i915_private *dev_priv = dev->dev_private;
12974
12975         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12976         DRM_INFO("applying pipe a force quirk\n");
12977 }
12978
12979 static void quirk_pipeb_force(struct drm_device *dev)
12980 {
12981         struct drm_i915_private *dev_priv = dev->dev_private;
12982
12983         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12984         DRM_INFO("applying pipe b force quirk\n");
12985 }
12986
12987 /*
12988  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12989  */
12990 static void quirk_ssc_force_disable(struct drm_device *dev)
12991 {
12992         struct drm_i915_private *dev_priv = dev->dev_private;
12993         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12994         DRM_INFO("applying lvds SSC disable quirk\n");
12995 }
12996
12997 /*
12998  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12999  * brightness value
13000  */
13001 static void quirk_invert_brightness(struct drm_device *dev)
13002 {
13003         struct drm_i915_private *dev_priv = dev->dev_private;
13004         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13005         DRM_INFO("applying inverted panel brightness quirk\n");
13006 }
13007
13008 /* Some VBT's incorrectly indicate no backlight is present */
13009 static void quirk_backlight_present(struct drm_device *dev)
13010 {
13011         struct drm_i915_private *dev_priv = dev->dev_private;
13012         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13013         DRM_INFO("applying backlight present quirk\n");
13014 }
13015
13016 struct intel_quirk {
13017         int device;
13018         int subsystem_vendor;
13019         int subsystem_device;
13020         void (*hook)(struct drm_device *dev);
13021 };
13022
13023 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13024 struct intel_dmi_quirk {
13025         void (*hook)(struct drm_device *dev);
13026         const struct dmi_system_id (*dmi_id_list)[];
13027 };
13028
13029 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13030 {
13031         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13032         return 1;
13033 }
13034
13035 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13036         {
13037                 .dmi_id_list = &(const struct dmi_system_id[]) {
13038                         {
13039                                 .callback = intel_dmi_reverse_brightness,
13040                                 .ident = "NCR Corporation",
13041                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13042                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
13043                                 },
13044                         },
13045                         { }  /* terminating entry */
13046                 },
13047                 .hook = quirk_invert_brightness,
13048         },
13049 };
13050
13051 static struct intel_quirk intel_quirks[] = {
13052         /* HP Mini needs pipe A force quirk (LP: #322104) */
13053         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13054
13055         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13056         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13057
13058         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13059         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13060
13061         /* 830 needs to leave pipe A & dpll A up */
13062         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13063
13064         /* 830 needs to leave pipe B & dpll B up */
13065         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13066
13067         /* Lenovo U160 cannot use SSC on LVDS */
13068         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13069
13070         /* Sony Vaio Y cannot use SSC on LVDS */
13071         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13072
13073         /* Acer Aspire 5734Z must invert backlight brightness */
13074         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13075
13076         /* Acer/eMachines G725 */
13077         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13078
13079         /* Acer/eMachines e725 */
13080         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13081
13082         /* Acer/Packard Bell NCL20 */
13083         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13084
13085         /* Acer Aspire 4736Z */
13086         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13087
13088         /* Acer Aspire 5336 */
13089         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13090
13091         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13092         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13093
13094         /* Acer C720 Chromebook (Core i3 4005U) */
13095         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13096
13097         /* Apple Macbook 2,1 (Core 2 T7400) */
13098         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13099
13100         /* Toshiba CB35 Chromebook (Celeron 2955U) */
13101         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13102
13103         /* HP Chromebook 14 (Celeron 2955U) */
13104         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13105 };
13106
13107 static void intel_init_quirks(struct drm_device *dev)
13108 {
13109         struct pci_dev *d = dev->pdev;
13110         int i;
13111
13112         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13113                 struct intel_quirk *q = &intel_quirks[i];
13114
13115                 if (d->device == q->device &&
13116                     (d->subsystem_vendor == q->subsystem_vendor ||
13117                      q->subsystem_vendor == PCI_ANY_ID) &&
13118                     (d->subsystem_device == q->subsystem_device ||
13119                      q->subsystem_device == PCI_ANY_ID))
13120                         q->hook(dev);
13121         }
13122         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13123                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13124                         intel_dmi_quirks[i].hook(dev);
13125         }
13126 }
13127
13128 /* Disable the VGA plane that we never use */
13129 static void i915_disable_vga(struct drm_device *dev)
13130 {
13131         struct drm_i915_private *dev_priv = dev->dev_private;
13132         u8 sr1;
13133         u32 vga_reg = i915_vgacntrl_reg(dev);
13134
13135         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13136         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13137         outb(SR01, VGA_SR_INDEX);
13138         sr1 = inb(VGA_SR_DATA);
13139         outb(sr1 | 1<<5, VGA_SR_DATA);
13140         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13141         udelay(300);
13142
13143         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13144         POSTING_READ(vga_reg);
13145 }
13146
13147 void intel_modeset_init_hw(struct drm_device *dev)
13148 {
13149         intel_prepare_ddi(dev);
13150
13151         if (IS_VALLEYVIEW(dev))
13152                 vlv_update_cdclk(dev);
13153
13154         intel_init_clock_gating(dev);
13155
13156         intel_enable_gt_powersave(dev);
13157 }
13158
13159 void intel_modeset_init(struct drm_device *dev)
13160 {
13161         struct drm_i915_private *dev_priv = dev->dev_private;
13162         int sprite, ret;
13163         enum pipe pipe;
13164         struct intel_crtc *crtc;
13165
13166         drm_mode_config_init(dev);
13167
13168         dev->mode_config.min_width = 0;
13169         dev->mode_config.min_height = 0;
13170
13171         dev->mode_config.preferred_depth = 24;
13172         dev->mode_config.prefer_shadow = 1;
13173
13174         dev->mode_config.allow_fb_modifiers = true;
13175
13176         dev->mode_config.funcs = &intel_mode_funcs;
13177
13178         intel_init_quirks(dev);
13179
13180         intel_init_pm(dev);
13181
13182         if (INTEL_INFO(dev)->num_pipes == 0)
13183                 return;
13184
13185         intel_init_display(dev);
13186         intel_init_audio(dev);
13187
13188         if (IS_GEN2(dev)) {
13189                 dev->mode_config.max_width = 2048;
13190                 dev->mode_config.max_height = 2048;
13191         } else if (IS_GEN3(dev)) {
13192                 dev->mode_config.max_width = 4096;
13193                 dev->mode_config.max_height = 4096;
13194         } else {
13195                 dev->mode_config.max_width = 8192;
13196                 dev->mode_config.max_height = 8192;
13197         }
13198
13199         if (IS_845G(dev) || IS_I865G(dev)) {
13200                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13201                 dev->mode_config.cursor_height = 1023;
13202         } else if (IS_GEN2(dev)) {
13203                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13204                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13205         } else {
13206                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13207                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13208         }
13209
13210         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13211
13212         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13213                       INTEL_INFO(dev)->num_pipes,
13214                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13215
13216         for_each_pipe(dev_priv, pipe) {
13217                 intel_crtc_init(dev, pipe);
13218                 for_each_sprite(pipe, sprite) {
13219                         ret = intel_plane_init(dev, pipe, sprite);
13220                         if (ret)
13221                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13222                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13223                 }
13224         }
13225
13226         intel_init_dpio(dev);
13227
13228         intel_shared_dpll_init(dev);
13229
13230         /* Just disable it once at startup */
13231         i915_disable_vga(dev);
13232         intel_setup_outputs(dev);
13233
13234         /* Just in case the BIOS is doing something questionable. */
13235         intel_fbc_disable(dev);
13236
13237         drm_modeset_lock_all(dev);
13238         intel_modeset_setup_hw_state(dev, false);
13239         drm_modeset_unlock_all(dev);
13240
13241         for_each_intel_crtc(dev, crtc) {
13242                 if (!crtc->active)
13243                         continue;
13244
13245                 /*
13246                  * Note that reserving the BIOS fb up front prevents us
13247                  * from stuffing other stolen allocations like the ring
13248                  * on top.  This prevents some ugliness at boot time, and
13249                  * can even allow for smooth boot transitions if the BIOS
13250                  * fb is large enough for the active pipe configuration.
13251                  */
13252                 if (dev_priv->display.get_initial_plane_config) {
13253                         dev_priv->display.get_initial_plane_config(crtc,
13254                                                            &crtc->plane_config);
13255                         /*
13256                          * If the fb is shared between multiple heads, we'll
13257                          * just get the first one.
13258                          */
13259                         intel_find_plane_obj(crtc, &crtc->plane_config);
13260                 }
13261         }
13262 }
13263
13264 static void intel_enable_pipe_a(struct drm_device *dev)
13265 {
13266         struct intel_connector *connector;
13267         struct drm_connector *crt = NULL;
13268         struct intel_load_detect_pipe load_detect_temp;
13269         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13270
13271         /* We can't just switch on the pipe A, we need to set things up with a
13272          * proper mode and output configuration. As a gross hack, enable pipe A
13273          * by enabling the load detect pipe once. */
13274         list_for_each_entry(connector,
13275                             &dev->mode_config.connector_list,
13276                             base.head) {
13277                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13278                         crt = &connector->base;
13279                         break;
13280                 }
13281         }
13282
13283         if (!crt)
13284                 return;
13285
13286         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13287                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13288 }
13289
13290 static bool
13291 intel_check_plane_mapping(struct intel_crtc *crtc)
13292 {
13293         struct drm_device *dev = crtc->base.dev;
13294         struct drm_i915_private *dev_priv = dev->dev_private;
13295         u32 reg, val;
13296
13297         if (INTEL_INFO(dev)->num_pipes == 1)
13298                 return true;
13299
13300         reg = DSPCNTR(!crtc->plane);
13301         val = I915_READ(reg);
13302
13303         if ((val & DISPLAY_PLANE_ENABLE) &&
13304             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13305                 return false;
13306
13307         return true;
13308 }
13309
13310 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13311 {
13312         struct drm_device *dev = crtc->base.dev;
13313         struct drm_i915_private *dev_priv = dev->dev_private;
13314         u32 reg;
13315
13316         /* Clear any frame start delays used for debugging left by the BIOS */
13317         reg = PIPECONF(crtc->config->cpu_transcoder);
13318         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13319
13320         /* restore vblank interrupts to correct state */
13321         if (crtc->active) {
13322                 update_scanline_offset(crtc);
13323                 drm_vblank_on(dev, crtc->pipe);
13324         } else
13325                 drm_vblank_off(dev, crtc->pipe);
13326
13327         /* We need to sanitize the plane -> pipe mapping first because this will
13328          * disable the crtc (and hence change the state) if it is wrong. Note
13329          * that gen4+ has a fixed plane -> pipe mapping.  */
13330         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13331                 struct intel_connector *connector;
13332                 bool plane;
13333
13334                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13335                               crtc->base.base.id);
13336
13337                 /* Pipe has the wrong plane attached and the plane is active.
13338                  * Temporarily change the plane mapping and disable everything
13339                  * ...  */
13340                 plane = crtc->plane;
13341                 crtc->plane = !plane;
13342                 crtc->primary_enabled = true;
13343                 dev_priv->display.crtc_disable(&crtc->base);
13344                 crtc->plane = plane;
13345
13346                 /* ... and break all links. */
13347                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13348                                     base.head) {
13349                         if (connector->encoder->base.crtc != &crtc->base)
13350                                 continue;
13351
13352                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13353                         connector->base.encoder = NULL;
13354                 }
13355                 /* multiple connectors may have the same encoder:
13356                  *  handle them and break crtc link separately */
13357                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13358                                     base.head)
13359                         if (connector->encoder->base.crtc == &crtc->base) {
13360                                 connector->encoder->base.crtc = NULL;
13361                                 connector->encoder->connectors_active = false;
13362                         }
13363
13364                 WARN_ON(crtc->active);
13365                 crtc->base.enabled = false;
13366         }
13367
13368         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13369             crtc->pipe == PIPE_A && !crtc->active) {
13370                 /* BIOS forgot to enable pipe A, this mostly happens after
13371                  * resume. Force-enable the pipe to fix this, the update_dpms
13372                  * call below we restore the pipe to the right state, but leave
13373                  * the required bits on. */
13374                 intel_enable_pipe_a(dev);
13375         }
13376
13377         /* Adjust the state of the output pipe according to whether we
13378          * have active connectors/encoders. */
13379         intel_crtc_update_dpms(&crtc->base);
13380
13381         if (crtc->active != crtc->base.enabled) {
13382                 struct intel_encoder *encoder;
13383
13384                 /* This can happen either due to bugs in the get_hw_state
13385                  * functions or because the pipe is force-enabled due to the
13386                  * pipe A quirk. */
13387                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13388                               crtc->base.base.id,
13389                               crtc->base.enabled ? "enabled" : "disabled",
13390                               crtc->active ? "enabled" : "disabled");
13391
13392                 crtc->base.enabled = crtc->active;
13393
13394                 /* Because we only establish the connector -> encoder ->
13395                  * crtc links if something is active, this means the
13396                  * crtc is now deactivated. Break the links. connector
13397                  * -> encoder links are only establish when things are
13398                  *  actually up, hence no need to break them. */
13399                 WARN_ON(crtc->active);
13400
13401                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13402                         WARN_ON(encoder->connectors_active);
13403                         encoder->base.crtc = NULL;
13404                 }
13405         }
13406
13407         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13408                 /*
13409                  * We start out with underrun reporting disabled to avoid races.
13410                  * For correct bookkeeping mark this on active crtcs.
13411                  *
13412                  * Also on gmch platforms we dont have any hardware bits to
13413                  * disable the underrun reporting. Which means we need to start
13414                  * out with underrun reporting disabled also on inactive pipes,
13415                  * since otherwise we'll complain about the garbage we read when
13416                  * e.g. coming up after runtime pm.
13417                  *
13418                  * No protection against concurrent access is required - at
13419                  * worst a fifo underrun happens which also sets this to false.
13420                  */
13421                 crtc->cpu_fifo_underrun_disabled = true;
13422                 crtc->pch_fifo_underrun_disabled = true;
13423         }
13424 }
13425
13426 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13427 {
13428         struct intel_connector *connector;
13429         struct drm_device *dev = encoder->base.dev;
13430
13431         /* We need to check both for a crtc link (meaning that the
13432          * encoder is active and trying to read from a pipe) and the
13433          * pipe itself being active. */
13434         bool has_active_crtc = encoder->base.crtc &&
13435                 to_intel_crtc(encoder->base.crtc)->active;
13436
13437         if (encoder->connectors_active && !has_active_crtc) {
13438                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13439                               encoder->base.base.id,
13440                               encoder->base.name);
13441
13442                 /* Connector is active, but has no active pipe. This is
13443                  * fallout from our resume register restoring. Disable
13444                  * the encoder manually again. */
13445                 if (encoder->base.crtc) {
13446                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13447                                       encoder->base.base.id,
13448                                       encoder->base.name);
13449                         encoder->disable(encoder);
13450                         if (encoder->post_disable)
13451                                 encoder->post_disable(encoder);
13452                 }
13453                 encoder->base.crtc = NULL;
13454                 encoder->connectors_active = false;
13455
13456                 /* Inconsistent output/port/pipe state happens presumably due to
13457                  * a bug in one of the get_hw_state functions. Or someplace else
13458                  * in our code, like the register restore mess on resume. Clamp
13459                  * things to off as a safer default. */
13460                 list_for_each_entry(connector,
13461                                     &dev->mode_config.connector_list,
13462                                     base.head) {
13463                         if (connector->encoder != encoder)
13464                                 continue;
13465                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13466                         connector->base.encoder = NULL;
13467                 }
13468         }
13469         /* Enabled encoders without active connectors will be fixed in
13470          * the crtc fixup. */
13471 }
13472
13473 void i915_redisable_vga_power_on(struct drm_device *dev)
13474 {
13475         struct drm_i915_private *dev_priv = dev->dev_private;
13476         u32 vga_reg = i915_vgacntrl_reg(dev);
13477
13478         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13479                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13480                 i915_disable_vga(dev);
13481         }
13482 }
13483
13484 void i915_redisable_vga(struct drm_device *dev)
13485 {
13486         struct drm_i915_private *dev_priv = dev->dev_private;
13487
13488         /* This function can be called both from intel_modeset_setup_hw_state or
13489          * at a very early point in our resume sequence, where the power well
13490          * structures are not yet restored. Since this function is at a very
13491          * paranoid "someone might have enabled VGA while we were not looking"
13492          * level, just check if the power well is enabled instead of trying to
13493          * follow the "don't touch the power well if we don't need it" policy
13494          * the rest of the driver uses. */
13495         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13496                 return;
13497
13498         i915_redisable_vga_power_on(dev);
13499 }
13500
13501 static bool primary_get_hw_state(struct intel_crtc *crtc)
13502 {
13503         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13504
13505         if (!crtc->active)
13506                 return false;
13507
13508         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13509 }
13510
13511 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13512 {
13513         struct drm_i915_private *dev_priv = dev->dev_private;
13514         enum pipe pipe;
13515         struct intel_crtc *crtc;
13516         struct intel_encoder *encoder;
13517         struct intel_connector *connector;
13518         int i;
13519
13520         for_each_intel_crtc(dev, crtc) {
13521                 memset(crtc->config, 0, sizeof(*crtc->config));
13522
13523                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13524
13525                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13526                                                                  crtc->config);
13527
13528                 crtc->base.enabled = crtc->active;
13529                 crtc->primary_enabled = primary_get_hw_state(crtc);
13530
13531                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13532                               crtc->base.base.id,
13533                               crtc->active ? "enabled" : "disabled");
13534         }
13535
13536         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13537                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13538
13539                 pll->on = pll->get_hw_state(dev_priv, pll,
13540                                             &pll->config.hw_state);
13541                 pll->active = 0;
13542                 pll->config.crtc_mask = 0;
13543                 for_each_intel_crtc(dev, crtc) {
13544                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13545                                 pll->active++;
13546                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13547                         }
13548                 }
13549
13550                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13551                               pll->name, pll->config.crtc_mask, pll->on);
13552
13553                 if (pll->config.crtc_mask)
13554                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13555         }
13556
13557         for_each_intel_encoder(dev, encoder) {
13558                 pipe = 0;
13559
13560                 if (encoder->get_hw_state(encoder, &pipe)) {
13561                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13562                         encoder->base.crtc = &crtc->base;
13563                         encoder->get_config(encoder, crtc->config);
13564                 } else {
13565                         encoder->base.crtc = NULL;
13566                 }
13567
13568                 encoder->connectors_active = false;
13569                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13570                               encoder->base.base.id,
13571                               encoder->base.name,
13572                               encoder->base.crtc ? "enabled" : "disabled",
13573                               pipe_name(pipe));
13574         }
13575
13576         list_for_each_entry(connector, &dev->mode_config.connector_list,
13577                             base.head) {
13578                 if (connector->get_hw_state(connector)) {
13579                         connector->base.dpms = DRM_MODE_DPMS_ON;
13580                         connector->encoder->connectors_active = true;
13581                         connector->base.encoder = &connector->encoder->base;
13582                 } else {
13583                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13584                         connector->base.encoder = NULL;
13585                 }
13586                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13587                               connector->base.base.id,
13588                               connector->base.name,
13589                               connector->base.encoder ? "enabled" : "disabled");
13590         }
13591 }
13592
13593 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13594  * and i915 state tracking structures. */
13595 void intel_modeset_setup_hw_state(struct drm_device *dev,
13596                                   bool force_restore)
13597 {
13598         struct drm_i915_private *dev_priv = dev->dev_private;
13599         enum pipe pipe;
13600         struct intel_crtc *crtc;
13601         struct intel_encoder *encoder;
13602         int i;
13603
13604         intel_modeset_readout_hw_state(dev);
13605
13606         /*
13607          * Now that we have the config, copy it to each CRTC struct
13608          * Note that this could go away if we move to using crtc_config
13609          * checking everywhere.
13610          */
13611         for_each_intel_crtc(dev, crtc) {
13612                 if (crtc->active && i915.fastboot) {
13613                         intel_mode_from_pipe_config(&crtc->base.mode,
13614                                                     crtc->config);
13615                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13616                                       crtc->base.base.id);
13617                         drm_mode_debug_printmodeline(&crtc->base.mode);
13618                 }
13619         }
13620
13621         /* HW state is read out, now we need to sanitize this mess. */
13622         for_each_intel_encoder(dev, encoder) {
13623                 intel_sanitize_encoder(encoder);
13624         }
13625
13626         for_each_pipe(dev_priv, pipe) {
13627                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13628                 intel_sanitize_crtc(crtc);
13629                 intel_dump_pipe_config(crtc, crtc->config,
13630                                        "[setup_hw_state]");
13631         }
13632
13633         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13634                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13635
13636                 if (!pll->on || pll->active)
13637                         continue;
13638
13639                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13640
13641                 pll->disable(dev_priv, pll);
13642                 pll->on = false;
13643         }
13644
13645         if (IS_GEN9(dev))
13646                 skl_wm_get_hw_state(dev);
13647         else if (HAS_PCH_SPLIT(dev))
13648                 ilk_wm_get_hw_state(dev);
13649
13650         if (force_restore) {
13651                 i915_redisable_vga(dev);
13652
13653                 /*
13654                  * We need to use raw interfaces for restoring state to avoid
13655                  * checking (bogus) intermediate states.
13656                  */
13657                 for_each_pipe(dev_priv, pipe) {
13658                         struct drm_crtc *crtc =
13659                                 dev_priv->pipe_to_crtc_mapping[pipe];
13660
13661                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13662                                        crtc->primary->fb);
13663                 }
13664         } else {
13665                 intel_modeset_update_staged_output_state(dev);
13666         }
13667
13668         intel_modeset_check_state(dev);
13669 }
13670
13671 void intel_modeset_gem_init(struct drm_device *dev)
13672 {
13673         struct drm_i915_private *dev_priv = dev->dev_private;
13674         struct drm_crtc *c;
13675         struct drm_i915_gem_object *obj;
13676
13677         mutex_lock(&dev->struct_mutex);
13678         intel_init_gt_powersave(dev);
13679         mutex_unlock(&dev->struct_mutex);
13680
13681         /*
13682          * There may be no VBT; and if the BIOS enabled SSC we can
13683          * just keep using it to avoid unnecessary flicker.  Whereas if the
13684          * BIOS isn't using it, don't assume it will work even if the VBT
13685          * indicates as much.
13686          */
13687         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13688                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13689                                                 DREF_SSC1_ENABLE);
13690
13691         intel_modeset_init_hw(dev);
13692
13693         intel_setup_overlay(dev);
13694
13695         /*
13696          * Make sure any fbs we allocated at startup are properly
13697          * pinned & fenced.  When we do the allocation it's too early
13698          * for this.
13699          */
13700         mutex_lock(&dev->struct_mutex);
13701         for_each_crtc(dev, c) {
13702                 obj = intel_fb_obj(c->primary->fb);
13703                 if (obj == NULL)
13704                         continue;
13705
13706                 if (intel_pin_and_fence_fb_obj(c->primary,
13707                                                c->primary->fb,
13708                                                NULL)) {
13709                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13710                                   to_intel_crtc(c)->pipe);
13711                         drm_framebuffer_unreference(c->primary->fb);
13712                         c->primary->fb = NULL;
13713                         update_state_fb(c->primary);
13714                 }
13715         }
13716         mutex_unlock(&dev->struct_mutex);
13717
13718         intel_backlight_register(dev);
13719 }
13720
13721 void intel_connector_unregister(struct intel_connector *intel_connector)
13722 {
13723         struct drm_connector *connector = &intel_connector->base;
13724
13725         intel_panel_destroy_backlight(connector);
13726         drm_connector_unregister(connector);
13727 }
13728
13729 void intel_modeset_cleanup(struct drm_device *dev)
13730 {
13731         struct drm_i915_private *dev_priv = dev->dev_private;
13732         struct drm_connector *connector;
13733
13734         intel_disable_gt_powersave(dev);
13735
13736         intel_backlight_unregister(dev);
13737
13738         /*
13739          * Interrupts and polling as the first thing to avoid creating havoc.
13740          * Too much stuff here (turning of connectors, ...) would
13741          * experience fancy races otherwise.
13742          */
13743         intel_irq_uninstall(dev_priv);
13744
13745         /*
13746          * Due to the hpd irq storm handling the hotplug work can re-arm the
13747          * poll handlers. Hence disable polling after hpd handling is shut down.
13748          */
13749         drm_kms_helper_poll_fini(dev);
13750
13751         mutex_lock(&dev->struct_mutex);
13752
13753         intel_unregister_dsm_handler();
13754
13755         intel_fbc_disable(dev);
13756
13757         ironlake_teardown_rc6(dev);
13758
13759         mutex_unlock(&dev->struct_mutex);
13760
13761         /* flush any delayed tasks or pending work */
13762         flush_scheduled_work();
13763
13764         /* destroy the backlight and sysfs files before encoders/connectors */
13765         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13766                 struct intel_connector *intel_connector;
13767
13768                 intel_connector = to_intel_connector(connector);
13769                 intel_connector->unregister(intel_connector);
13770         }
13771
13772         drm_mode_config_cleanup(dev);
13773
13774         intel_cleanup_overlay(dev);
13775
13776         mutex_lock(&dev->struct_mutex);
13777         intel_cleanup_gt_powersave(dev);
13778         mutex_unlock(&dev->struct_mutex);
13779 }
13780
13781 /*
13782  * Return which encoder is currently attached for connector.
13783  */
13784 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13785 {
13786         return &intel_attached_encoder(connector)->base;
13787 }
13788
13789 void intel_connector_attach_encoder(struct intel_connector *connector,
13790                                     struct intel_encoder *encoder)
13791 {
13792         connector->encoder = encoder;
13793         drm_mode_connector_attach_encoder(&connector->base,
13794                                           &encoder->base);
13795 }
13796
13797 /*
13798  * set vga decode state - true == enable VGA decode
13799  */
13800 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13801 {
13802         struct drm_i915_private *dev_priv = dev->dev_private;
13803         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13804         u16 gmch_ctrl;
13805
13806         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13807                 DRM_ERROR("failed to read control word\n");
13808                 return -EIO;
13809         }
13810
13811         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13812                 return 0;
13813
13814         if (state)
13815                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13816         else
13817                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13818
13819         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13820                 DRM_ERROR("failed to write control word\n");
13821                 return -EIO;
13822         }
13823
13824         return 0;
13825 }
13826
13827 struct intel_display_error_state {
13828
13829         u32 power_well_driver;
13830
13831         int num_transcoders;
13832
13833         struct intel_cursor_error_state {
13834                 u32 control;
13835                 u32 position;
13836                 u32 base;
13837                 u32 size;
13838         } cursor[I915_MAX_PIPES];
13839
13840         struct intel_pipe_error_state {
13841                 bool power_domain_on;
13842                 u32 source;
13843                 u32 stat;
13844         } pipe[I915_MAX_PIPES];
13845
13846         struct intel_plane_error_state {
13847                 u32 control;
13848                 u32 stride;
13849                 u32 size;
13850                 u32 pos;
13851                 u32 addr;
13852                 u32 surface;
13853                 u32 tile_offset;
13854         } plane[I915_MAX_PIPES];
13855
13856         struct intel_transcoder_error_state {
13857                 bool power_domain_on;
13858                 enum transcoder cpu_transcoder;
13859
13860                 u32 conf;
13861
13862                 u32 htotal;
13863                 u32 hblank;
13864                 u32 hsync;
13865                 u32 vtotal;
13866                 u32 vblank;
13867                 u32 vsync;
13868         } transcoder[4];
13869 };
13870
13871 struct intel_display_error_state *
13872 intel_display_capture_error_state(struct drm_device *dev)
13873 {
13874         struct drm_i915_private *dev_priv = dev->dev_private;
13875         struct intel_display_error_state *error;
13876         int transcoders[] = {
13877                 TRANSCODER_A,
13878                 TRANSCODER_B,
13879                 TRANSCODER_C,
13880                 TRANSCODER_EDP,
13881         };
13882         int i;
13883
13884         if (INTEL_INFO(dev)->num_pipes == 0)
13885                 return NULL;
13886
13887         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13888         if (error == NULL)
13889                 return NULL;
13890
13891         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13892                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13893
13894         for_each_pipe(dev_priv, i) {
13895                 error->pipe[i].power_domain_on =
13896                         __intel_display_power_is_enabled(dev_priv,
13897                                                          POWER_DOMAIN_PIPE(i));
13898                 if (!error->pipe[i].power_domain_on)
13899                         continue;
13900
13901                 error->cursor[i].control = I915_READ(CURCNTR(i));
13902                 error->cursor[i].position = I915_READ(CURPOS(i));
13903                 error->cursor[i].base = I915_READ(CURBASE(i));
13904
13905                 error->plane[i].control = I915_READ(DSPCNTR(i));
13906                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13907                 if (INTEL_INFO(dev)->gen <= 3) {
13908                         error->plane[i].size = I915_READ(DSPSIZE(i));
13909                         error->plane[i].pos = I915_READ(DSPPOS(i));
13910                 }
13911                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13912                         error->plane[i].addr = I915_READ(DSPADDR(i));
13913                 if (INTEL_INFO(dev)->gen >= 4) {
13914                         error->plane[i].surface = I915_READ(DSPSURF(i));
13915                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13916                 }
13917
13918                 error->pipe[i].source = I915_READ(PIPESRC(i));
13919
13920                 if (HAS_GMCH_DISPLAY(dev))
13921                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13922         }
13923
13924         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13925         if (HAS_DDI(dev_priv->dev))
13926                 error->num_transcoders++; /* Account for eDP. */
13927
13928         for (i = 0; i < error->num_transcoders; i++) {
13929                 enum transcoder cpu_transcoder = transcoders[i];
13930
13931                 error->transcoder[i].power_domain_on =
13932                         __intel_display_power_is_enabled(dev_priv,
13933                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13934                 if (!error->transcoder[i].power_domain_on)
13935                         continue;
13936
13937                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13938
13939                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13940                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13941                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13942                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13943                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13944                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13945                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13946         }
13947
13948         return error;
13949 }
13950
13951 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13952
13953 void
13954 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13955                                 struct drm_device *dev,
13956                                 struct intel_display_error_state *error)
13957 {
13958         struct drm_i915_private *dev_priv = dev->dev_private;
13959         int i;
13960
13961         if (!error)
13962                 return;
13963
13964         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13965         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13966                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13967                            error->power_well_driver);
13968         for_each_pipe(dev_priv, i) {
13969                 err_printf(m, "Pipe [%d]:\n", i);
13970                 err_printf(m, "  Power: %s\n",
13971                            error->pipe[i].power_domain_on ? "on" : "off");
13972                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13973                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13974
13975                 err_printf(m, "Plane [%d]:\n", i);
13976                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13977                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13978                 if (INTEL_INFO(dev)->gen <= 3) {
13979                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13980                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13981                 }
13982                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13983                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13984                 if (INTEL_INFO(dev)->gen >= 4) {
13985                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13986                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13987                 }
13988
13989                 err_printf(m, "Cursor [%d]:\n", i);
13990                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13991                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13992                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13993         }
13994
13995         for (i = 0; i < error->num_transcoders; i++) {
13996                 err_printf(m, "CPU transcoder: %c\n",
13997                            transcoder_name(error->transcoder[i].cpu_transcoder));
13998                 err_printf(m, "  Power: %s\n",
13999                            error->transcoder[i].power_domain_on ? "on" : "off");
14000                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
14001                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
14002                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
14003                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
14004                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
14005                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
14006                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
14007         }
14008 }
14009
14010 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14011 {
14012         struct intel_crtc *crtc;
14013
14014         for_each_intel_crtc(dev, crtc) {
14015                 struct intel_unpin_work *work;
14016
14017                 spin_lock_irq(&dev->event_lock);
14018
14019                 work = crtc->unpin_work;
14020
14021                 if (work && work->event &&
14022                     work->event->base.file_priv == file) {
14023                         kfree(work->event);
14024                         work->event = NULL;
14025                 }
14026
14027                 spin_unlock_irq(&dev->event_lock);
14028         }
14029 }