drivers/gpu/drm/bridge/ti-sn65dsi83.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI SN65DSI83,84,85 driver
   4  *
   5  * Currently supported:
   6  * - SN65DSI83
   7  *   = 1x Single-link DSI ~ 1x Single-link LVDS
   8  *   - Supported
   9  *   - Single-link LVDS mode tested
  10  * - SN65DSI84
  11  *   = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
  12  *   - Supported
  13  *   - Dual-link LVDS mode tested
  14  *   - 2x Single-link LVDS mode unsupported
  15  *     (should be easy to add by someone who has the HW)
  16  * - SN65DSI85
  17  *   = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS
  18  *   - Unsupported
  19  *     (should be easy to add by someone who has the HW)
  20  *
  21  * Copyright (C) 2021 Marek Vasut <[email protected]>
  22  *
  23  * Based on previous work of:
  24  * Valentin Raevsky <[email protected]>
  25  * Philippe Schenker <[email protected]>
  26  */
  27
  28 #include <linux/bits.h>
  29 #include <linux/clk.h>
  30 #include <linux/gpio/consumer.h>
  31 #include <linux/i2c.h>
  32 #include <linux/module.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_graph.h>
  35 #include <linux/regmap.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_bridge.h>
  39 #include <drm/drm_mipi_dsi.h>
  40 #include <drm/drm_of.h>
  41 #include <drm/drm_panel.h>
  42 #include <drm/drm_print.h>
  43 #include <drm/drm_probe_helper.h>
  44
  45 /* ID registers */
  46 #define REG_ID(n)                               (0x00 + (n))
  47 /* Reset and clock registers */
  48 #define REG_RC_RESET                            0x09
  49 #define  REG_RC_RESET_SOFT_RESET                BIT(0)
  50 #define REG_RC_LVDS_PLL                         0x0a
  51 #define  REG_RC_LVDS_PLL_PLL_EN_STAT            BIT(7)
  52 #define  REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n)      (((n) & 0x7) << 1)
  53 #define  REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY        BIT(0)
  54 #define REG_RC_DSI_CLK                          0x0b
  55 #define  REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n)      (((n) & 0x1f) << 3)
  56 #define  REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n)    ((n) & 0x3)
  57 #define REG_RC_PLL_EN                           0x0d
  58 #define  REG_RC_PLL_EN_PLL_EN                   BIT(0)
  59 /* DSI registers */
  60 #define REG_DSI_LANE                            0x10
  61 #define  REG_DSI_LANE_LEFT_RIGHT_PIXELS         BIT(7)  /* DSI85-only */
  62 #define  REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL     0       /* DSI85-only */
  63 #define  REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE  BIT(6)  /* DSI85-only */
  64 #define  REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE   BIT(5)
  65 #define  REG_DSI_LANE_CHA_DSI_LANES(n)          (((n) & 0x3) << 3)
  66 #define  REG_DSI_LANE_CHB_DSI_LANES(n)          (((n) & 0x3) << 1)
  67 #define  REG_DSI_LANE_SOT_ERR_TOL_DIS           BIT(0)
  68 #define REG_DSI_EQ                              0x11
  69 #define  REG_DSI_EQ_CHA_DSI_DATA_EQ(n)          (((n) & 0x3) << 6)
  70 #define  REG_DSI_EQ_CHA_DSI_CLK_EQ(n)           (((n) & 0x3) << 2)
  71 #define REG_DSI_CLK                             0x12
  72 #define  REG_DSI_CLK_CHA_DSI_CLK_RANGE(n)       ((n) & 0xff)
  73 /* LVDS registers */
  74 #define REG_LVDS_FMT                            0x18
  75 #define  REG_LVDS_FMT_DE_NEG_POLARITY           BIT(7)
  76 #define  REG_LVDS_FMT_HS_NEG_POLARITY           BIT(6)
  77 #define  REG_LVDS_FMT_VS_NEG_POLARITY           BIT(5)
  78 #define  REG_LVDS_FMT_LVDS_LINK_CFG             BIT(4)  /* 0:AB 1:A-only */
  79 #define  REG_LVDS_FMT_CHA_24BPP_MODE            BIT(3)
  80 #define  REG_LVDS_FMT_CHB_24BPP_MODE            BIT(2)
  81 #define  REG_LVDS_FMT_CHA_24BPP_FORMAT1         BIT(1)
  82 #define  REG_LVDS_FMT_CHB_24BPP_FORMAT1         BIT(0)
  83 #define REG_LVDS_VCOM                           0x19
  84 #define  REG_LVDS_VCOM_CHA_LVDS_VOCM            BIT(6)
  85 #define  REG_LVDS_VCOM_CHB_LVDS_VOCM            BIT(4)
  86 #define  REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n)    (((n) & 0x3) << 2)
  87 #define  REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n)    ((n) & 0x3)
  88 #define REG_LVDS_LANE                           0x1a
  89 #define  REG_LVDS_LANE_EVEN_ODD_SWAP            BIT(6)
  90 #define  REG_LVDS_LANE_CHA_REVERSE_LVDS         BIT(5)
  91 #define  REG_LVDS_LANE_CHB_REVERSE_LVDS         BIT(4)
  92 #define  REG_LVDS_LANE_CHA_LVDS_TERM            BIT(1)
  93 #define  REG_LVDS_LANE_CHB_LVDS_TERM            BIT(0)
  94 #define REG_LVDS_CM                             0x1b
  95 #define  REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n)      (((n) & 0x3) << 4)
  96 #define  REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n)      ((n) & 0x3)
  97 /* Video registers */
  98 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW      0x20
  99 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH     0x21
 100 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW   0x24
 101 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH  0x25
 102 #define REG_VID_CHA_SYNC_DELAY_LOW              0x28
 103 #define REG_VID_CHA_SYNC_DELAY_HIGH             0x29
 104 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW       0x2c
 105 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH      0x2d
 106 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW       0x30
 107 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH      0x31
 108 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH       0x34
 109 #define REG_VID_CHA_VERTICAL_BACK_PORCH         0x36
 110 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH      0x38
 111 #define REG_VID_CHA_VERTICAL_FRONT_PORCH        0x3a
 112 #define REG_VID_CHA_TEST_PATTERN                0x3c
 113 /* IRQ registers */
 114 #define REG_IRQ_GLOBAL                          0xe0
 115 #define  REG_IRQ_GLOBAL_IRQ_EN                  BIT(0)
 116 #define REG_IRQ_EN                              0xe1
 117 #define  REG_IRQ_EN_CHA_SYNCH_ERR_EN            BIT(7)
 118 #define  REG_IRQ_EN_CHA_CRC_ERR_EN              BIT(6)
 119 #define  REG_IRQ_EN_CHA_UNC_ECC_ERR_EN          BIT(5)
 120 #define  REG_IRQ_EN_CHA_COR_ECC_ERR_EN          BIT(4)
 121 #define  REG_IRQ_EN_CHA_LLP_ERR_EN              BIT(3)
 122 #define  REG_IRQ_EN_CHA_SOT_BIT_ERR_EN          BIT(2)
 123 #define  REG_IRQ_EN_CHA_PLL_UNLOCK_EN           BIT(0)
 124 #define REG_IRQ_STAT                            0xe5
 125 #define  REG_IRQ_STAT_CHA_SYNCH_ERR             BIT(7)
 126 #define  REG_IRQ_STAT_CHA_CRC_ERR               BIT(6)
 127 #define  REG_IRQ_STAT_CHA_UNC_ECC_ERR           BIT(5)
 128 #define  REG_IRQ_STAT_CHA_COR_ECC_ERR           BIT(4)
 129 #define  REG_IRQ_STAT_CHA_LLP_ERR               BIT(3)
 130 #define  REG_IRQ_STAT_CHA_SOT_BIT_ERR           BIT(2)
 131 #define  REG_IRQ_STAT_CHA_PLL_UNLOCK            BIT(0)
 132
 133 enum sn65dsi83_model {
 134         MODEL_SN65DSI83,
 135         MODEL_SN65DSI84,
 136 };
 137
 138 struct sn65dsi83 {
 139         struct drm_bridge               bridge;
 140         struct device                   *dev;
 141         struct regmap                   *regmap;
 142         struct device_node              *host_node;
 143         struct mipi_dsi_device          *dsi;
 144         struct drm_bridge               *panel_bridge;
 145         struct gpio_desc                *enable_gpio;
 146         int                             dsi_lanes;
 147         bool                            lvds_dual_link;
 148         bool                            lvds_dual_link_even_odd_swap;
 149 };
 150
 151 static const struct regmap_range sn65dsi83_readable_ranges[] = {
 152         regmap_reg_range(REG_ID(0), REG_ID(8)),
 153         regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK),
 154         regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
 155         regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
 156         regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
 157         regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
 158                          REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
 159         regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
 160                          REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
 161         regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
 162                          REG_VID_CHA_SYNC_DELAY_HIGH),
 163         regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
 164                          REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
 165         regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
 166                          REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
 167         regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
 168                          REG_VID_CHA_HORIZONTAL_BACK_PORCH),
 169         regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
 170                          REG_VID_CHA_VERTICAL_BACK_PORCH),
 171         regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
 172                          REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
 173         regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
 174                          REG_VID_CHA_VERTICAL_FRONT_PORCH),
 175         regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
 176         regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
 177         regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
 178 };
 179
 180 static const struct regmap_access_table sn65dsi83_readable_table = {
 181         .yes_ranges = sn65dsi83_readable_ranges,
 182         .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges),
 183 };
 184
 185 static const struct regmap_range sn65dsi83_writeable_ranges[] = {
 186         regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK),
 187         regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
 188         regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
 189         regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
 190         regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
 191                          REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
 192         regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
 193                          REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
 194         regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
 195                          REG_VID_CHA_SYNC_DELAY_HIGH),
 196         regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
 197                          REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
 198         regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
 199                          REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
 200         regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
 201                          REG_VID_CHA_HORIZONTAL_BACK_PORCH),
 202         regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
 203                          REG_VID_CHA_VERTICAL_BACK_PORCH),
 204         regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
 205                          REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
 206         regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
 207                          REG_VID_CHA_VERTICAL_FRONT_PORCH),
 208         regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
 209         regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
 210         regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
 211 };
 212
 213 static const struct regmap_access_table sn65dsi83_writeable_table = {
 214         .yes_ranges = sn65dsi83_writeable_ranges,
 215         .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges),
 216 };
 217
 218 static const struct regmap_range sn65dsi83_volatile_ranges[] = {
 219         regmap_reg_range(REG_RC_RESET, REG_RC_RESET),
 220         regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL),
 221         regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
 222 };
 223
 224 static const struct regmap_access_table sn65dsi83_volatile_table = {
 225         .yes_ranges = sn65dsi83_volatile_ranges,
 226         .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges),
 227 };
 228
 229 static const struct regmap_config sn65dsi83_regmap_config = {
 230         .reg_bits = 8,
 231         .val_bits = 8,
 232         .rd_table = &sn65dsi83_readable_table,
 233         .wr_table = &sn65dsi83_writeable_table,
 234         .volatile_table = &sn65dsi83_volatile_table,
 235         .cache_type = REGCACHE_RBTREE,
 236         .max_register = REG_IRQ_STAT,
 237 };
 238
 239 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge)
 240 {
 241         return container_of(bridge, struct sn65dsi83, bridge);
 242 }
 243
 244 static int sn65dsi83_attach(struct drm_bridge *bridge,
 245                             enum drm_bridge_attach_flags flags)
 246 {
 247         struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
 248         struct device *dev = ctx->dev;
 249         struct mipi_dsi_device *dsi;
 250         struct mipi_dsi_host *host;
 251         int ret = 0;
 252
 253         const struct mipi_dsi_device_info info = {
 254                 .type = "sn65dsi83",
 255                 .channel = 0,
 256                 .node = NULL,
 257         };
 258
 259         host = of_find_mipi_dsi_host_by_node(ctx->host_node);
 260         if (!host) {
 261                 dev_err(dev, "failed to find dsi host\n");
 262                 return -EPROBE_DEFER;
 263         }
 264
 265         dsi = mipi_dsi_device_register_full(host, &info);
 266         if (IS_ERR(dsi)) {
 267                 return dev_err_probe(dev, PTR_ERR(dsi),
 268                                      "failed to create dsi device\n");
 269         }
 270
 271         ctx->dsi = dsi;
 272
 273         dsi->lanes = ctx->dsi_lanes;
 274         dsi->format = MIPI_DSI_FMT_RGB888;
 275         dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST;
 276
 277         ret = mipi_dsi_attach(dsi);
 278         if (ret < 0) {
 279                 dev_err(dev, "failed to attach dsi to host\n");
 280                 goto err_dsi_attach;
 281         }
 282
 283         return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
 284                                  &ctx->bridge, flags);
 285
 286 err_dsi_attach:
 287         mipi_dsi_device_unregister(dsi);
 288         return ret;
 289 }
 290
 291 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
 292                                         struct drm_bridge_state *old_bridge_state)
 293 {
 294         struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
 295
 296         /*
 297          * Reset the chip, pull EN line low for t_reset=10ms,
 298          * then high for t_en=1ms.
 299          */
 300         regcache_mark_dirty(ctx->regmap);
 301         gpiod_set_value(ctx->enable_gpio, 0);
 302         usleep_range(10000, 11000);
 303         gpiod_set_value(ctx->enable_gpio, 1);
 304         usleep_range(1000, 1100);
 305 }
 306
 307 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx,
 308                                    const struct drm_display_mode *mode)
 309 {
 310         /*
 311          * The encoding of the LVDS_CLK_RANGE is as follows:
 312          * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz
 313          * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz
 314          * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz
 315          * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz
 316          * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz
 317          * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz
 318          * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that
 319          * the ends of the ranges are clamped to the supported range. Since
 320          * sn65dsi83_mode_valid() already filters the valid modes and limits
 321          * the clock to 25..154 MHz, the range calculation can be simplified
 322          * as follows:
 323          */
 324         int mode_clock = mode->clock;
 325
 326         if (ctx->lvds_dual_link)
 327                 mode_clock /= 2;
 328
 329         return (mode_clock - 12500) / 25000;
 330 }
 331
 332 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
 333                                   const struct drm_display_mode *mode)
 334 {
 335         /*
 336          * The encoding of the CHA_DSI_CLK_RANGE is as follows:
 337          * 0x00 through 0x07 - Reserved
 338          * 0x08 - 40 <= DSI_CLK < 45 MHz
 339          * 0x09 - 45 <= DSI_CLK < 50 MHz
 340          * ...
 341          * 0x63 - 495 <= DSI_CLK < 500 MHz
 342          * 0x64 - 500 MHz
 343          * 0x65 through 0xFF - Reserved
 344          * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz.
 345          * The DSI clock are calculated as:
 346          *  DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
 347          * the 2 is there because the bus is DDR.
 348          */
 349         return DIV_ROUND_UP(clamp((unsigned int)mode->clock *
 350                             mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
 351                             ctx->dsi_lanes / 2, 40000U, 500000U), 5000U);
 352 }
 353
 354 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
 355 {
 356         /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */
 357         unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format);
 358
 359         dsi_div /= ctx->dsi_lanes;
 360
 361         if (!ctx->lvds_dual_link)
 362                 dsi_div /= 2;
 363
 364         return dsi_div - 1;
 365 }
 366
 367 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
 368                                     struct drm_bridge_state *old_bridge_state)
 369 {
 370         struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
 371         struct drm_atomic_state *state = old_bridge_state->base.state;
 372         const struct drm_bridge_state *bridge_state;
 373         const struct drm_crtc_state *crtc_state;
 374         const struct drm_display_mode *mode;
 375         struct drm_connector *connector;
 376         struct drm_crtc *crtc;
 377         bool lvds_format_24bpp;
 378         bool lvds_format_jeida;
 379         unsigned int pval;
 380         __le16 le16val;
 381         u16 val;
 382         int ret;
 383
 384         /* Get the LVDS format from the bridge state. */
 385         bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
 386
 387         switch (bridge_state->output_bus_cfg.format) {
 388         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 389                 lvds_format_24bpp = false;
 390                 lvds_format_jeida = true;
 391                 break;
 392         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 393                 lvds_format_24bpp = true;
 394                 lvds_format_jeida = true;
 395                 break;
 396         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 397                 lvds_format_24bpp = true;
 398                 lvds_format_jeida = false;
 399                 break;
 400         default:
 401                 /*
 402                  * Some bridges still don't set the correct
 403                  * LVDS bus pixel format, use SPWG24 default
 404                  * format until those are fixed.
 405                  */
 406                 lvds_format_24bpp = true;
 407                 lvds_format_jeida = false;
 408                 dev_warn(ctx->dev,
 409                          "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
 410                          bridge_state->output_bus_cfg.format);
 411                 break;
 412         }
 413
 414         /*
 415          * Retrieve the CRTC adjusted mode. This requires a little dance to go
 416          * from the bridge to the encoder, to the connector and to the CRTC.
 417          */
 418         connector = drm_atomic_get_new_connector_for_encoder(state,
 419                                                              bridge->encoder);
 420         crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
 421         crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
 422         mode = &crtc_state->adjusted_mode;
 423
 424         /* Clear reset, disable PLL */
 425         regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
 426         regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
 427
 428         /* Reference clock derived from DSI link clock. */
 429         regmap_write(ctx->regmap, REG_RC_LVDS_PLL,
 430                      REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) |
 431                      REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
 432         regmap_write(ctx->regmap, REG_DSI_CLK,
 433                      REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode)));
 434         regmap_write(ctx->regmap, REG_RC_DSI_CLK,
 435                      REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
 436
 437         /* Set number of DSI lanes and LVDS link config. */
 438         regmap_write(ctx->regmap, REG_DSI_LANE,
 439                      REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE |
 440                      REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi_lanes - 1)) |
 441                      /* CHB is DSI85-only, set to default on DSI83/DSI84 */
 442                      REG_DSI_LANE_CHB_DSI_LANES(3));
 443         /* No equalization. */
 444         regmap_write(ctx->regmap, REG_DSI_EQ, 0x00);
 445
 446         /* Set up sync signal polarity. */
 447         val = (mode->flags & DRM_MODE_FLAG_NHSYNC ?
 448                REG_LVDS_FMT_HS_NEG_POLARITY : 0) |
 449               (mode->flags & DRM_MODE_FLAG_NVSYNC ?
 450                REG_LVDS_FMT_VS_NEG_POLARITY : 0);
 451
 452         /* Set up bits-per-pixel, 18bpp or 24bpp. */
 453         if (lvds_format_24bpp) {
 454                 val |= REG_LVDS_FMT_CHA_24BPP_MODE;
 455                 if (ctx->lvds_dual_link)
 456                         val |= REG_LVDS_FMT_CHB_24BPP_MODE;
 457         }
 458
 459         /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */
 460         if (lvds_format_jeida) {
 461                 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1;
 462                 if (ctx->lvds_dual_link)
 463                         val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1;
 464         }
 465
 466         /* Set up LVDS output config (DSI84,DSI85) */
 467         if (!ctx->lvds_dual_link)
 468                 val |= REG_LVDS_FMT_LVDS_LINK_CFG;
 469
 470         regmap_write(ctx->regmap, REG_LVDS_FMT, val);
 471         regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05);
 472         regmap_write(ctx->regmap, REG_LVDS_LANE,
 473                      (ctx->lvds_dual_link_even_odd_swap ?
 474                       REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
 475                      REG_LVDS_LANE_CHA_LVDS_TERM |
 476                      REG_LVDS_LANE_CHB_LVDS_TERM);
 477         regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
 478
 479         le16val = cpu_to_le16(mode->hdisplay);
 480         regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
 481                           &le16val, 2);
 482         le16val = cpu_to_le16(mode->vdisplay);
 483         regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
 484                           &le16val, 2);
 485         /* 32 + 1 pixel clock to ensure proper operation */
 486         le16val = cpu_to_le16(32 + 1);
 487         regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);
 488         le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start);
 489         regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
 490                           &le16val, 2);
 491         le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start);
 492         regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
 493                           &le16val, 2);
 494         regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
 495                      mode->htotal - mode->hsync_end);
 496         regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
 497                      mode->vtotal - mode->vsync_end);
 498         regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
 499                      mode->hsync_start - mode->hdisplay);
 500         regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
 501                      mode->vsync_start - mode->vdisplay);
 502         regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
 503
 504         /* Enable PLL */
 505         regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);
 506         usleep_range(3000, 4000);
 507         ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval,
 508                                        pval & REG_RC_LVDS_PLL_PLL_EN_STAT,
 509                                        1000, 100000);
 510         if (ret) {
 511                 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
 512                 /* On failure, disable PLL again and exit. */
 513                 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
 514                 return;
 515         }
 516
 517         /* Trigger reset after CSR register update. */
 518         regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET);
 519
 520         /* Clear all errors that got asserted during initialization. */
 521         regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
 522         regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
 523 }
 524
 525 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge,
 526                                      struct drm_bridge_state *old_bridge_state)
 527 {
 528         struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
 529
 530         /* Clear reset, disable PLL */
 531         regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
 532         regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
 533 }
 534
 535 static void sn65dsi83_atomic_post_disable(struct drm_bridge *bridge,
 536                                           struct drm_bridge_state *old_bridge_state)
 537 {
 538         struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
 539
 540         /* Put the chip in reset, pull EN line low. */
 541         gpiod_set_value(ctx->enable_gpio, 0);
 542 }
 543
 544 static enum drm_mode_status
 545 sn65dsi83_mode_valid(struct drm_bridge *bridge,
 546                      const struct drm_display_info *info,
 547                      const struct drm_display_mode *mode)
 548 {
 549         /* LVDS output clock range 25..154 MHz */
 550         if (mode->clock < 25000)
 551                 return MODE_CLOCK_LOW;
 552         if (mode->clock > 154000)
 553                 return MODE_CLOCK_HIGH;
 554
 555         return MODE_OK;
 556 }
 557
 558 #define MAX_INPUT_SEL_FORMATS   1
 559
 560 static u32 *
 561 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 562                                     struct drm_bridge_state *bridge_state,
 563                                     struct drm_crtc_state *crtc_state,
 564                                     struct drm_connector_state *conn_state,
 565                                     u32 output_fmt,
 566                                     unsigned int *num_input_fmts)
 567 {
 568         u32 *input_fmts;
 569
 570         *num_input_fmts = 0;
 571
 572         input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
 573                              GFP_KERNEL);
 574         if (!input_fmts)
 575                 return NULL;
 576
 577         /* This is the DSI-end bus format */
 578         input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
 579         *num_input_fmts = 1;
 580
 581         return input_fmts;
 582 }
 583
 584 static const struct drm_bridge_funcs sn65dsi83_funcs = {
 585         .attach                 = sn65dsi83_attach,
 586         .atomic_pre_enable      = sn65dsi83_atomic_pre_enable,
 587         .atomic_enable          = sn65dsi83_atomic_enable,
 588         .atomic_disable         = sn65dsi83_atomic_disable,
 589         .atomic_post_disable    = sn65dsi83_atomic_post_disable,
 590         .mode_valid             = sn65dsi83_mode_valid,
 591
 592         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 593         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 594         .atomic_reset = drm_atomic_helper_bridge_reset,
 595         .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts,
 596 };
 597
 598 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model)
 599 {
 600         struct drm_bridge *panel_bridge;
 601         struct device *dev = ctx->dev;
 602         struct device_node *endpoint;
 603         struct drm_panel *panel;
 604         int ret;
 605
 606         endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
 607         ctx->dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
 608         ctx->host_node = of_graph_get_remote_port_parent(endpoint);
 609         of_node_put(endpoint);
 610
 611         if (ctx->dsi_lanes < 0 || ctx->dsi_lanes > 4)
 612                 return -EINVAL;
 613         if (!ctx->host_node)
 614                 return -ENODEV;
 615
 616         ctx->lvds_dual_link = false;
 617         ctx->lvds_dual_link_even_odd_swap = false;
 618         if (model != MODEL_SN65DSI83) {
 619                 struct device_node *port2, *port3;
 620                 int dual_link;
 621
 622                 port2 = of_graph_get_port_by_id(dev->of_node, 2);
 623                 port3 = of_graph_get_port_by_id(dev->of_node, 3);
 624                 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3);
 625                 of_node_put(port2);
 626                 of_node_put(port3);
 627
 628                 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
 629                         ctx->lvds_dual_link = true;
 630                         /* Odd pixels to LVDS Channel A, even pixels to B */
 631                         ctx->lvds_dual_link_even_odd_swap = false;
 632                 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
 633                         ctx->lvds_dual_link = true;
 634                         /* Even pixels to LVDS Channel A, odd pixels to B */
 635                         ctx->lvds_dual_link_even_odd_swap = true;
 636                 }
 637         }
 638
 639         ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge);
 640         if (ret < 0)
 641                 return ret;
 642         if (panel) {
 643                 panel_bridge = devm_drm_panel_bridge_add(dev, panel);
 644                 if (IS_ERR(panel_bridge))
 645                         return PTR_ERR(panel_bridge);
 646         }
 647
 648         ctx->panel_bridge = panel_bridge;
 649
 650         return 0;
 651 }
 652
 653 static int sn65dsi83_probe(struct i2c_client *client,
 654                            const struct i2c_device_id *id)
 655 {
 656         struct device *dev = &client->dev;
 657         enum sn65dsi83_model model;
 658         struct sn65dsi83 *ctx;
 659         int ret;
 660
 661         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 662         if (!ctx)
 663                 return -ENOMEM;
 664
 665         ctx->dev = dev;
 666
 667         if (dev->of_node) {
 668                 model = (enum sn65dsi83_model)(uintptr_t)
 669                         of_device_get_match_data(dev);
 670         } else {
 671                 model = id->driver_data;
 672         }
 673
 674         ctx->enable_gpio = devm_gpiod_get(ctx->dev, "enable", GPIOD_OUT_LOW);
 675         if (IS_ERR(ctx->enable_gpio))
 676                 return PTR_ERR(ctx->enable_gpio);
 677
 678         ret = sn65dsi83_parse_dt(ctx, model);
 679         if (ret)
 680                 return ret;
 681
 682         ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config);
 683         if (IS_ERR(ctx->regmap))
 684                 return PTR_ERR(ctx->regmap);
 685
 686         dev_set_drvdata(dev, ctx);
 687         i2c_set_clientdata(client, ctx);
 688
 689         ctx->bridge.funcs = &sn65dsi83_funcs;
 690         ctx->bridge.of_node = dev->of_node;
 691         drm_bridge_add(&ctx->bridge);
 692
 693         return 0;
 694 }
 695
 696 static int sn65dsi83_remove(struct i2c_client *client)
 697 {
 698         struct sn65dsi83 *ctx = i2c_get_clientdata(client);
 699
 700         mipi_dsi_detach(ctx->dsi);
 701         mipi_dsi_device_unregister(ctx->dsi);
 702         drm_bridge_remove(&ctx->bridge);
 703         of_node_put(ctx->host_node);
 704
 705         return 0;
 706 }
 707
 708 static struct i2c_device_id sn65dsi83_id[] = {
 709         { "ti,sn65dsi83", MODEL_SN65DSI83 },
 710         { "ti,sn65dsi84", MODEL_SN65DSI84 },
 711         {},
 712 };
 713 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id);
 714
 715 static const struct of_device_id sn65dsi83_match_table[] = {
 716         { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 },
 717         { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 },
 718         {},
 719 };
 720 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table);
 721
 722 static struct i2c_driver sn65dsi83_driver = {
 723         .probe = sn65dsi83_probe,
 724         .remove = sn65dsi83_remove,
 725         .id_table = sn65dsi83_id,
 726         .driver = {
 727                 .name = "sn65dsi83",
 728                 .of_match_table = sn65dsi83_match_table,
 729         },
 730 };
 731 module_i2c_driver(sn65dsi83_driver);
 732
 733 MODULE_AUTHOR("Marek Vasut <[email protected]>");
 734 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver");
 735 MODULE_LICENSE("GPL v2");