drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15d.h"
  29 #include "soc15_common.h"
  30 #include "mmsch_v1_0.h"
  31
  32 #include "vega10/soc15ip.h"
  33 #include "vega10/UVD/uvd_7_0_offset.h"
  34 #include "vega10/UVD/uvd_7_0_sh_mask.h"
  35 #include "vega10/VCE/vce_4_0_offset.h"
  36 #include "vega10/VCE/vce_4_0_default.h"
  37 #include "vega10/VCE/vce_4_0_sh_mask.h"
  38 #include "vega10/NBIF/nbif_6_1_offset.h"
  39 #include "vega10/HDP/hdp_4_0_offset.h"
  40 #include "vega10/MMHUB/mmhub_1_0_offset.h"
  41 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  42
  43 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  44 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  45 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  46 static int uvd_v7_0_start(struct amdgpu_device *adev);
  47 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  48 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  49
  50 /**
  51  * uvd_v7_0_ring_get_rptr - get read pointer
  52  *
  53  * @ring: amdgpu_ring pointer
  54  *
  55  * Returns the current hardware read pointer
  56  */
  57 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  58 {
  59         struct amdgpu_device *adev = ring->adev;
  60
  61         return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR));
  62 }
  63
  64 /**
  65  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware enc read pointer
  70  */
  71 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         if (ring == &adev->uvd.ring_enc[0])
  76                 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR));
  77         else
  78                 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2));
  79 }
  80
  81 /**
  82  * uvd_v7_0_ring_get_wptr - get write pointer
  83  *
  84  * @ring: amdgpu_ring pointer
  85  *
  86  * Returns the current hardware write pointer
  87  */
  88 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
  89 {
  90         struct amdgpu_device *adev = ring->adev;
  91
  92         return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR));
  93 }
  94
  95 /**
  96  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
  97  *
  98  * @ring: amdgpu_ring pointer
  99  *
 100  * Returns the current hardware enc write pointer
 101  */
 102 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 103 {
 104         struct amdgpu_device *adev = ring->adev;
 105
 106         if (ring->use_doorbell)
 107                 return adev->wb.wb[ring->wptr_offs];
 108
 109         if (ring == &adev->uvd.ring_enc[0])
 110                 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR));
 111         else
 112                 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2));
 113 }
 114
 115 /**
 116  * uvd_v7_0_ring_set_wptr - set write pointer
 117  *
 118  * @ring: amdgpu_ring pointer
 119  *
 120  * Commits the write pointer to the hardware
 121  */
 122 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 123 {
 124         struct amdgpu_device *adev = ring->adev;
 125
 126         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), lower_32_bits(ring->wptr));
 127 }
 128
 129 /**
 130  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 131  *
 132  * @ring: amdgpu_ring pointer
 133  *
 134  * Commits the enc write pointer to the hardware
 135  */
 136 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 137 {
 138         struct amdgpu_device *adev = ring->adev;
 139
 140         if (ring->use_doorbell) {
 141                 /* XXX check if swapping is necessary on BE */
 142                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 143                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 144                 return;
 145         }
 146
 147         if (ring == &adev->uvd.ring_enc[0])
 148                 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR),
 149                         lower_32_bits(ring->wptr));
 150         else
 151                 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2),
 152                         lower_32_bits(ring->wptr));
 153 }
 154
 155 /**
 156  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 157  *
 158  * @ring: the engine to test on
 159  *
 160  */
 161 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 162 {
 163         struct amdgpu_device *adev = ring->adev;
 164         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 165         unsigned i;
 166         int r;
 167
 168         r = amdgpu_ring_alloc(ring, 16);
 169         if (r) {
 170                 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
 171                           ring->idx, r);
 172                 return r;
 173         }
 174         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 175         amdgpu_ring_commit(ring);
 176
 177         for (i = 0; i < adev->usec_timeout; i++) {
 178                 if (amdgpu_ring_get_rptr(ring) != rptr)
 179                         break;
 180                 DRM_UDELAY(1);
 181         }
 182
 183         if (i < adev->usec_timeout) {
 184                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 185                          ring->idx, i);
 186         } else {
 187                 DRM_ERROR("amdgpu: ring %d test failed\n",
 188                           ring->idx);
 189                 r = -ETIMEDOUT;
 190         }
 191
 192         return r;
 193 }
 194
 195 /**
 196  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 197  *
 198  * @adev: amdgpu_device pointer
 199  * @ring: ring we should submit the msg to
 200  * @handle: session handle to use
 201  * @fence: optional fence to return
 202  *
 203  * Open up a stream for HW test
 204  */
 205 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 206                                        struct dma_fence **fence)
 207 {
 208         const unsigned ib_size_dw = 16;
 209         struct amdgpu_job *job;
 210         struct amdgpu_ib *ib;
 211         struct dma_fence *f = NULL;
 212         uint64_t dummy;
 213         int i, r;
 214
 215         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 216         if (r)
 217                 return r;
 218
 219         ib = &job->ibs[0];
 220         dummy = ib->gpu_addr + 1024;
 221
 222         ib->length_dw = 0;
 223         ib->ptr[ib->length_dw++] = 0x00000018;
 224         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 225         ib->ptr[ib->length_dw++] = handle;
 226         ib->ptr[ib->length_dw++] = 0x00000000;
 227         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 228         ib->ptr[ib->length_dw++] = dummy;
 229
 230         ib->ptr[ib->length_dw++] = 0x00000014;
 231         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 232         ib->ptr[ib->length_dw++] = 0x0000001c;
 233         ib->ptr[ib->length_dw++] = 0x00000000;
 234         ib->ptr[ib->length_dw++] = 0x00000000;
 235
 236         ib->ptr[ib->length_dw++] = 0x00000008;
 237         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 238
 239         for (i = ib->length_dw; i < ib_size_dw; ++i)
 240                 ib->ptr[i] = 0x0;
 241
 242         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 243         job->fence = dma_fence_get(f);
 244         if (r)
 245                 goto err;
 246
 247         amdgpu_job_free(job);
 248         if (fence)
 249                 *fence = dma_fence_get(f);
 250         dma_fence_put(f);
 251         return 0;
 252
 253 err:
 254         amdgpu_job_free(job);
 255         return r;
 256 }
 257
 258 /**
 259  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 260  *
 261  * @adev: amdgpu_device pointer
 262  * @ring: ring we should submit the msg to
 263  * @handle: session handle to use
 264  * @fence: optional fence to return
 265  *
 266  * Close up a stream for HW test or if userspace failed to do so
 267  */
 268 int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 269                                  bool direct, struct dma_fence **fence)
 270 {
 271         const unsigned ib_size_dw = 16;
 272         struct amdgpu_job *job;
 273         struct amdgpu_ib *ib;
 274         struct dma_fence *f = NULL;
 275         uint64_t dummy;
 276         int i, r;
 277
 278         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 279         if (r)
 280                 return r;
 281
 282         ib = &job->ibs[0];
 283         dummy = ib->gpu_addr + 1024;
 284
 285         ib->length_dw = 0;
 286         ib->ptr[ib->length_dw++] = 0x00000018;
 287         ib->ptr[ib->length_dw++] = 0x00000001;
 288         ib->ptr[ib->length_dw++] = handle;
 289         ib->ptr[ib->length_dw++] = 0x00000000;
 290         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 291         ib->ptr[ib->length_dw++] = dummy;
 292
 293         ib->ptr[ib->length_dw++] = 0x00000014;
 294         ib->ptr[ib->length_dw++] = 0x00000002;
 295         ib->ptr[ib->length_dw++] = 0x0000001c;
 296         ib->ptr[ib->length_dw++] = 0x00000000;
 297         ib->ptr[ib->length_dw++] = 0x00000000;
 298
 299         ib->ptr[ib->length_dw++] = 0x00000008;
 300         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 301
 302         for (i = ib->length_dw; i < ib_size_dw; ++i)
 303                 ib->ptr[i] = 0x0;
 304
 305         if (direct) {
 306                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 307                 job->fence = dma_fence_get(f);
 308                 if (r)
 309                         goto err;
 310
 311                 amdgpu_job_free(job);
 312         } else {
 313                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 314                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 315                 if (r)
 316                         goto err;
 317         }
 318
 319         if (fence)
 320                 *fence = dma_fence_get(f);
 321         dma_fence_put(f);
 322         return 0;
 323
 324 err:
 325         amdgpu_job_free(job);
 326         return r;
 327 }
 328
 329 /**
 330  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 331  *
 332  * @ring: the engine to test on
 333  *
 334  */
 335 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 336 {
 337         struct dma_fence *fence = NULL;
 338         long r;
 339
 340         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 341         if (r) {
 342                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 343                 goto error;
 344         }
 345
 346         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence);
 347         if (r) {
 348                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 349                 goto error;
 350         }
 351
 352         r = dma_fence_wait_timeout(fence, false, timeout);
 353         if (r == 0) {
 354                 DRM_ERROR("amdgpu: IB test timed out.\n");
 355                 r = -ETIMEDOUT;
 356         } else if (r < 0) {
 357                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 358         } else {
 359                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 360                 r = 0;
 361         }
 362 error:
 363         dma_fence_put(fence);
 364         return r;
 365 }
 366
 367 static int uvd_v7_0_early_init(void *handle)
 368 {
 369         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 370
 371         if (amdgpu_sriov_vf(adev))
 372                 adev->uvd.num_enc_rings = 1;
 373         else
 374                 adev->uvd.num_enc_rings = 2;
 375         uvd_v7_0_set_ring_funcs(adev);
 376         uvd_v7_0_set_enc_ring_funcs(adev);
 377         uvd_v7_0_set_irq_funcs(adev);
 378
 379         return 0;
 380 }
 381
 382 static int uvd_v7_0_sw_init(void *handle)
 383 {
 384         struct amdgpu_ring *ring;
 385         struct amd_sched_rq *rq;
 386         int i, r;
 387         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 388
 389         /* UVD TRAP */
 390         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
 391         if (r)
 392                 return r;
 393
 394         /* UVD ENC TRAP */
 395         for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 396                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
 397                 if (r)
 398                         return r;
 399         }
 400
 401         r = amdgpu_uvd_sw_init(adev);
 402         if (r)
 403                 return r;
 404
 405         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 406                 const struct common_firmware_header *hdr;
 407                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 408                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 409                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 410                 adev->firmware.fw_size +=
 411                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 412                 DRM_INFO("PSP loading UVD firmware\n");
 413         }
 414
 415         ring = &adev->uvd.ring_enc[0];
 416         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
 417         r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
 418                                   rq, amdgpu_sched_jobs);
 419         if (r) {
 420                 DRM_ERROR("Failed setting up UVD ENC run queue.\n");
 421                 return r;
 422         }
 423
 424         r = amdgpu_uvd_resume(adev);
 425         if (r)
 426                 return r;
 427         if (!amdgpu_sriov_vf(adev)) {
 428                 ring = &adev->uvd.ring;
 429                 sprintf(ring->name, "uvd");
 430                 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 431                 if (r)
 432                         return r;
 433         }
 434
 435
 436         for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 437                 ring = &adev->uvd.ring_enc[i];
 438                 sprintf(ring->name, "uvd_enc%d", i);
 439                 if (amdgpu_sriov_vf(adev)) {
 440                         ring->use_doorbell = true;
 441                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
 442                 }
 443                 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 444                 if (r)
 445                         return r;
 446         }
 447
 448         r = amdgpu_virt_alloc_mm_table(adev);
 449         if (r)
 450                 return r;
 451
 452         return r;
 453 }
 454
 455 static int uvd_v7_0_sw_fini(void *handle)
 456 {
 457         int i, r;
 458         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 459
 460         amdgpu_virt_free_mm_table(adev);
 461
 462         r = amdgpu_uvd_suspend(adev);
 463         if (r)
 464                 return r;
 465
 466         amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
 467
 468         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 469                 amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
 470
 471         return amdgpu_uvd_sw_fini(adev);
 472 }
 473
 474 /**
 475  * uvd_v7_0_hw_init - start and test UVD block
 476  *
 477  * @adev: amdgpu_device pointer
 478  *
 479  * Initialize the hardware, boot up the VCPU and do some testing
 480  */
 481 static int uvd_v7_0_hw_init(void *handle)
 482 {
 483         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 484         struct amdgpu_ring *ring = &adev->uvd.ring;
 485         uint32_t tmp;
 486         int i, r;
 487
 488         if (amdgpu_sriov_vf(adev))
 489                 r = uvd_v7_0_sriov_start(adev);
 490         else
 491                 r = uvd_v7_0_start(adev);
 492         if (r)
 493                 goto done;
 494
 495         if (!amdgpu_sriov_vf(adev)) {
 496                 ring->ready = true;
 497                 r = amdgpu_ring_test_ring(ring);
 498                 if (r) {
 499                         ring->ready = false;
 500                         goto done;
 501                 }
 502
 503                 r = amdgpu_ring_alloc(ring, 10);
 504                 if (r) {
 505                         DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 506                         goto done;
 507                 }
 508
 509                 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
 510                         mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 511                 amdgpu_ring_write(ring, tmp);
 512                 amdgpu_ring_write(ring, 0xFFFFF);
 513
 514                 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
 515                         mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 516                 amdgpu_ring_write(ring, tmp);
 517                 amdgpu_ring_write(ring, 0xFFFFF);
 518
 519                 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
 520                         mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 521                 amdgpu_ring_write(ring, tmp);
 522                 amdgpu_ring_write(ring, 0xFFFFF);
 523
 524                 /* Clear timeout status bits */
 525                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
 526                         mmUVD_SEMA_TIMEOUT_STATUS), 0));
 527                 amdgpu_ring_write(ring, 0x8);
 528
 529                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
 530                         mmUVD_SEMA_CNTL), 0));
 531                 amdgpu_ring_write(ring, 3);
 532
 533                 amdgpu_ring_commit(ring);
 534         }
 535
 536         for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 537                 ring = &adev->uvd.ring_enc[i];
 538                 ring->ready = true;
 539                 r = amdgpu_ring_test_ring(ring);
 540                 if (r) {
 541                         ring->ready = false;
 542                         goto done;
 543                 }
 544         }
 545
 546 done:
 547         if (!r)
 548                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 549
 550         return r;
 551 }
 552
 553 /**
 554  * uvd_v7_0_hw_fini - stop the hardware block
 555  *
 556  * @adev: amdgpu_device pointer
 557  *
 558  * Stop the UVD block, mark ring as not ready any more
 559  */
 560 static int uvd_v7_0_hw_fini(void *handle)
 561 {
 562         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 563         struct amdgpu_ring *ring = &adev->uvd.ring;
 564
 565         uvd_v7_0_stop(adev);
 566         ring->ready = false;
 567
 568         return 0;
 569 }
 570
 571 static int uvd_v7_0_suspend(void *handle)
 572 {
 573         int r;
 574         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 575
 576         r = uvd_v7_0_hw_fini(adev);
 577         if (r)
 578                 return r;
 579
 580         /* Skip this for APU for now */
 581         if (!(adev->flags & AMD_IS_APU))
 582                 r = amdgpu_uvd_suspend(adev);
 583
 584         return r;
 585 }
 586
 587 static int uvd_v7_0_resume(void *handle)
 588 {
 589         int r;
 590         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 591
 592         /* Skip this for APU for now */
 593         if (!(adev->flags & AMD_IS_APU)) {
 594                 r = amdgpu_uvd_resume(adev);
 595                 if (r)
 596                         return r;
 597         }
 598         return uvd_v7_0_hw_init(adev);
 599 }
 600
 601 /**
 602  * uvd_v7_0_mc_resume - memory controller programming
 603  *
 604  * @adev: amdgpu_device pointer
 605  *
 606  * Let the UVD memory controller know it's offsets
 607  */
 608 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 609 {
 610         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 611         uint32_t offset;
 612
 613         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 614                 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 615                         lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 616                 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 617                         upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 618                 offset = 0;
 619         } else {
 620                 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 621                         lower_32_bits(adev->uvd.gpu_addr));
 622                 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 623                         upper_32_bits(adev->uvd.gpu_addr));
 624                 offset = size;
 625         }
 626
 627         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
 628                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 629         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
 630
 631         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 632                         lower_32_bits(adev->uvd.gpu_addr + offset));
 633         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 634                         upper_32_bits(adev->uvd.gpu_addr + offset));
 635         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 636         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 637
 638         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 639                         lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 640         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 641                         upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 642         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 643         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
 644                         AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 645
 646         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG),
 647                         adev->gfx.config.gb_addr_config);
 648         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG),
 649                         adev->gfx.config.gb_addr_config);
 650         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG),
 651                         adev->gfx.config.gb_addr_config);
 652
 653         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 654 }
 655
 656 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 657                                 struct amdgpu_mm_table *table)
 658 {
 659         uint32_t data = 0, loop;
 660         uint64_t addr = table->gpu_addr;
 661         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 662         uint32_t size;
 663
 664         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 665
 666         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 667         WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));
 668         WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));
 669
 670         /* 2, update vmid of descriptor */
 671         data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));
 672         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 673         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 674         WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data);
 675
 676         /* 3, notify mmsch about the size of this descriptor */
 677         WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size);
 678
 679         /* 4, set resp to zero */
 680         WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
 681
 682         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 683         WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);
 684
 685         data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
 686         loop = 1000;
 687         while ((data & 0x10000002) != 0x10000002) {
 688                 udelay(10);
 689                 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
 690                 loop--;
 691                 if (!loop)
 692                         break;
 693         }
 694
 695         if (!loop) {
 696                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 697                 return -EBUSY;
 698         }
 699
 700         return 0;
 701 }
 702
 703 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 704 {
 705         struct amdgpu_ring *ring;
 706         uint32_t offset, size, tmp;
 707         uint32_t table_size = 0;
 708         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 709         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 710         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 711         struct mmsch_v1_0_cmd_end end = { {0} };
 712         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 713         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 714
 715         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 716         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 717         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 718         end.cmd_header.command_type = MMSCH_COMMAND__END;
 719
 720         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 721                 header->version = MMSCH_VERSION;
 722                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 723
 724                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 725                         header->uvd_table_offset = header->header_size;
 726                 else
 727                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 728
 729                 init_table += header->uvd_table_offset;
 730
 731                 ring = &adev->uvd.ring;
 732                 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 733
 734                 /* disable clock gating */
 735                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
 736                                                    ~UVD_POWER_STATUS__UVD_PG_MODE_MASK, 0);
 737                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
 738                                                    0xFFFFFFFF, 0x00000004);
 739                 /* mc resume*/
 740                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 741                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 742                                                     lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 743                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 744                                                     upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 745                         offset = 0;
 746                 } else {
 747                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 748                                                     lower_32_bits(adev->uvd.gpu_addr));
 749                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 750                                                     upper_32_bits(adev->uvd.gpu_addr));
 751                         offset = size;
 752                 }
 753
 754                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
 755                                             AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 756                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
 757
 758                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 759                                             lower_32_bits(adev->uvd.gpu_addr + offset));
 760                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 761                                             upper_32_bits(adev->uvd.gpu_addr + offset));
 762                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 763                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 764
 765                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 766                                             lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 767                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 768                                             upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 769                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 770                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
 771                                             AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 772
 773                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG),
 774                                             adev->gfx.config.gb_addr_config);
 775                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG),
 776                                             adev->gfx.config.gb_addr_config);
 777                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG),
 778                                             adev->gfx.config.gb_addr_config);
 779                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 780                 /* mc resume end*/
 781
 782                 /* disable clock gating */
 783                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL),
 784                                                    ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 785
 786                 /* disable interupt */
 787                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 788                                                    ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 789
 790                 /* stall UMC and register bus before resetting VCPU */
 791                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 792                                                    ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 793                                                    UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 794
 795                 /* put LMI, VCPU, RBC etc... into reset */
 796                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 797                                             (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 798                                                        UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 799                                                        UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 800                                                        UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 801                                                        UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 802                                                        UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 803                                                        UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 804                                                        UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 805
 806                 /* initialize UVD memory controller */
 807                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
 808                                             (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 809                                                        UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 810                                                        UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 811                                                        UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 812                                                        UVD_LMI_CTRL__REQ_MODE_MASK |
 813                                                        0x00100000L));
 814
 815                 /* disable byte swapping */
 816                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), 0);
 817                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MP_SWAP_CNTL), 0);
 818
 819                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040);
 820                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0);
 821                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040);
 822                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0);
 823                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0);
 824                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88);
 825
 826                 /* take all subblocks out of reset, except VCPU */
 827                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 828                                             UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 829
 830                 /* enable VCPU clock */
 831                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
 832                                             UVD_VCPU_CNTL__CLK_EN_MASK);
 833
 834                 /* enable UMC */
 835                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 836                                                    ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 837
 838                 /* boot up the VCPU */
 839                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
 840
 841                 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0x02, 0x02);
 842
 843                 /* enable master interrupt */
 844                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 845                                                    ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 846                                                    (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 847
 848                 /* clear the bit 4 of UVD_STATUS */
 849                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
 850                                                    ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 851
 852                 /* force RBC into idle state */
 853                 size = order_base_2(ring->ring_size);
 854                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 855                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 856                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 857                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 858                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 859                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 860                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
 861
 862                 /* set the write pointer delay */
 863                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0);
 864
 865                 /* set the wb address */
 866                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR),
 867                                             (upper_32_bits(ring->gpu_addr) >> 2));
 868
 869                 /* programm the RB_BASE for ring buffer */
 870                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
 871                                             lower_32_bits(ring->gpu_addr));
 872                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
 873                                             upper_32_bits(ring->gpu_addr));
 874
 875                 ring->wptr = 0;
 876                 ring = &adev->uvd.ring_enc[0];
 877                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
 878                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 879                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
 880
 881                 /* add end packet */
 882                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 883                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 884                 header->uvd_table_size = table_size;
 885
 886                 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 887         }
 888         return -EINVAL; /* already initializaed ? */
 889 }
 890
 891 /**
 892  * uvd_v7_0_start - start UVD block
 893  *
 894  * @adev: amdgpu_device pointer
 895  *
 896  * Setup and start the UVD block
 897  */
 898 static int uvd_v7_0_start(struct amdgpu_device *adev)
 899 {
 900         struct amdgpu_ring *ring = &adev->uvd.ring;
 901         uint32_t rb_bufsz, tmp;
 902         uint32_t lmi_swap_cntl;
 903         uint32_t mp_swap_cntl;
 904         int i, j, r;
 905
 906         /* disable DPG */
 907         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
 908                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 909
 910         /* disable byte swapping */
 911         lmi_swap_cntl = 0;
 912         mp_swap_cntl = 0;
 913
 914         uvd_v7_0_mc_resume(adev);
 915
 916         /* disable clock gating */
 917         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0,
 918                         ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 919
 920         /* disable interupt */
 921         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 922                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 923
 924         /* stall UMC and register bus before resetting VCPU */
 925         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 926                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 927                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 928         mdelay(1);
 929
 930         /* put LMI, VCPU, RBC etc... into reset */
 931         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 932                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 933                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 934                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 935                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 936                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 937                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 938                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 939                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 940         mdelay(5);
 941
 942         /* initialize UVD memory controller */
 943         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
 944                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 945                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 946                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 947                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 948                 UVD_LMI_CTRL__REQ_MODE_MASK |
 949                 0x00100000L);
 950
 951 #ifdef __BIG_ENDIAN
 952         /* swap (8 in 32) RB and IB */
 953         lmi_swap_cntl = 0xa;
 954         mp_swap_cntl = 0;
 955 #endif
 956         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), lmi_swap_cntl);
 957         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MP_SWAP_CNTL), mp_swap_cntl);
 958
 959         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040);
 960         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0);
 961         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040);
 962         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0);
 963         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0);
 964         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88);
 965
 966         /* take all subblocks out of reset, except VCPU */
 967         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 968                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 969         mdelay(5);
 970
 971         /* enable VCPU clock */
 972         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
 973                         UVD_VCPU_CNTL__CLK_EN_MASK);
 974
 975         /* enable UMC */
 976         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 977                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 978
 979         /* boot up the VCPU */
 980         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
 981         mdelay(10);
 982
 983         for (i = 0; i < 10; ++i) {
 984                 uint32_t status;
 985
 986                 for (j = 0; j < 100; ++j) {
 987                         status = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS));
 988                         if (status & 2)
 989                                 break;
 990                         mdelay(10);
 991                 }
 992                 r = 0;
 993                 if (status & 2)
 994                         break;
 995
 996                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 997                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 998                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 999                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1000                 mdelay(10);
1001                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1002                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1003                 mdelay(10);
1004                 r = -1;
1005         }
1006
1007         if (r) {
1008                 DRM_ERROR("UVD not responding, giving up!!!\n");
1009                 return r;
1010         }
1011         /* enable master interrupt */
1012         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1013                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1014                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1015
1016         /* clear the bit 4 of UVD_STATUS */
1017         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1018                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1019
1020         /* force RBC into idle state */
1021         rb_bufsz = order_base_2(ring->ring_size);
1022         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1023         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1024         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1025         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1026         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1027         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1028         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
1029
1030         /* set the write pointer delay */
1031         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0);
1032
1033         /* set the wb address */
1034         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR),
1035                         (upper_32_bits(ring->gpu_addr) >> 2));
1036
1037         /* programm the RB_BASE for ring buffer */
1038         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1039                         lower_32_bits(ring->gpu_addr));
1040         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1041                         upper_32_bits(ring->gpu_addr));
1042
1043         /* Initialize the ring buffer's read and write pointers */
1044         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR), 0);
1045
1046         ring->wptr = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR));
1047         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR),
1048                         lower_32_bits(ring->wptr));
1049
1050         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1051                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1052
1053         ring = &adev->uvd.ring_enc[0];
1054         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR), lower_32_bits(ring->wptr));
1055         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), lower_32_bits(ring->wptr));
1056         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
1057         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
1058         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
1059
1060         ring = &adev->uvd.ring_enc[1];
1061         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2), lower_32_bits(ring->wptr));
1062         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), lower_32_bits(ring->wptr));
1063         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr);
1064         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));
1065         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4);
1066
1067         return 0;
1068 }
1069
1070 /**
1071  * uvd_v7_0_stop - stop UVD block
1072  *
1073  * @adev: amdgpu_device pointer
1074  *
1075  * stop the UVD block
1076  */
1077 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1078 {
1079         /* force RBC into idle state */
1080         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0x11010101);
1081
1082         /* Stall UMC and register bus before resetting VCPU */
1083         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1084                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1085                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1086         mdelay(1);
1087
1088         /* put VCPU into reset */
1089         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1090                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1091         mdelay(5);
1092
1093         /* disable VCPU clock */
1094         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0x0);
1095
1096         /* Unstall UMC and register bus */
1097         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1098                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1099 }
1100
1101 /**
1102  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1103  *
1104  * @ring: amdgpu_ring pointer
1105  * @fence: fence to emit
1106  *
1107  * Write a fence and a trap command to the ring.
1108  */
1109 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1110                                      unsigned flags)
1111 {
1112         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1113
1114         amdgpu_ring_write(ring,
1115                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1116         amdgpu_ring_write(ring, seq);
1117         amdgpu_ring_write(ring,
1118                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1119         amdgpu_ring_write(ring, addr & 0xffffffff);
1120         amdgpu_ring_write(ring,
1121                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1122         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1123         amdgpu_ring_write(ring,
1124                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1125         amdgpu_ring_write(ring, 0);
1126
1127         amdgpu_ring_write(ring,
1128                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1129         amdgpu_ring_write(ring, 0);
1130         amdgpu_ring_write(ring,
1131                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1132         amdgpu_ring_write(ring, 0);
1133         amdgpu_ring_write(ring,
1134                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1135         amdgpu_ring_write(ring, 2);
1136 }
1137
1138 /**
1139  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1140  *
1141  * @ring: amdgpu_ring pointer
1142  * @fence: fence to emit
1143  *
1144  * Write enc a fence and a trap command to the ring.
1145  */
1146 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1147                         u64 seq, unsigned flags)
1148 {
1149         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1150
1151         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1152         amdgpu_ring_write(ring, addr);
1153         amdgpu_ring_write(ring, upper_32_bits(addr));
1154         amdgpu_ring_write(ring, seq);
1155         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1156 }
1157
1158 /**
1159  * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush
1160  *
1161  * @ring: amdgpu_ring pointer
1162  *
1163  * Emits an hdp flush.
1164  */
1165 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1166 {
1167         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0,
1168                 mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0));
1169         amdgpu_ring_write(ring, 0);
1170 }
1171
1172 /**
1173  * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate
1174  *
1175  * @ring: amdgpu_ring pointer
1176  *
1177  * Emits an hdp invalidate.
1178  */
1179 static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1180 {
1181         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
1182         amdgpu_ring_write(ring, 1);
1183 }
1184
1185 /**
1186  * uvd_v7_0_ring_test_ring - register write test
1187  *
1188  * @ring: amdgpu_ring pointer
1189  *
1190  * Test if we can successfully write to the context register
1191  */
1192 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1193 {
1194         struct amdgpu_device *adev = ring->adev;
1195         uint32_t tmp = 0;
1196         unsigned i;
1197         int r;
1198
1199         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
1200         r = amdgpu_ring_alloc(ring, 3);
1201         if (r) {
1202                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
1203                           ring->idx, r);
1204                 return r;
1205         }
1206         amdgpu_ring_write(ring,
1207                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1208         amdgpu_ring_write(ring, 0xDEADBEEF);
1209         amdgpu_ring_commit(ring);
1210         for (i = 0; i < adev->usec_timeout; i++) {
1211                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
1212                 if (tmp == 0xDEADBEEF)
1213                         break;
1214                 DRM_UDELAY(1);
1215         }
1216
1217         if (i < adev->usec_timeout) {
1218                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
1219                          ring->idx, i);
1220         } else {
1221                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1222                           ring->idx, tmp);
1223                 r = -EINVAL;
1224         }
1225         return r;
1226 }
1227
1228 /**
1229  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1230  *
1231  * @ring: amdgpu_ring pointer
1232  * @ib: indirect buffer to execute
1233  *
1234  * Write ring commands to execute the indirect buffer
1235  */
1236 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1237                                   struct amdgpu_ib *ib,
1238                                   unsigned vm_id, bool ctx_switch)
1239 {
1240         amdgpu_ring_write(ring,
1241                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1242         amdgpu_ring_write(ring, vm_id);
1243
1244         amdgpu_ring_write(ring,
1245                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1246         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1247         amdgpu_ring_write(ring,
1248                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1249         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1250         amdgpu_ring_write(ring,
1251                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1252         amdgpu_ring_write(ring, ib->length_dw);
1253 }
1254
1255 /**
1256  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1257  *
1258  * @ring: amdgpu_ring pointer
1259  * @ib: indirect buffer to execute
1260  *
1261  * Write enc ring commands to execute the indirect buffer
1262  */
1263 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1264                 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
1265 {
1266         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1267         amdgpu_ring_write(ring, vm_id);
1268         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1269         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1270         amdgpu_ring_write(ring, ib->length_dw);
1271 }
1272
1273 static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
1274                                 uint32_t data0, uint32_t data1)
1275 {
1276         amdgpu_ring_write(ring,
1277                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1278         amdgpu_ring_write(ring, data0);
1279         amdgpu_ring_write(ring,
1280                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1281         amdgpu_ring_write(ring, data1);
1282         amdgpu_ring_write(ring,
1283                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1284         amdgpu_ring_write(ring, 8);
1285 }
1286
1287 static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
1288                                 uint32_t data0, uint32_t data1, uint32_t mask)
1289 {
1290         amdgpu_ring_write(ring,
1291                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1292         amdgpu_ring_write(ring, data0);
1293         amdgpu_ring_write(ring,
1294                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1295         amdgpu_ring_write(ring, data1);
1296         amdgpu_ring_write(ring,
1297                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1298         amdgpu_ring_write(ring, mask);
1299         amdgpu_ring_write(ring,
1300                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1301         amdgpu_ring_write(ring, 12);
1302 }
1303
1304 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1305                                         unsigned vm_id, uint64_t pd_addr)
1306 {
1307         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1308         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1309         uint32_t data0, data1, mask;
1310         unsigned eng = ring->vm_inv_eng;
1311
1312         pd_addr = pd_addr | 0x1; /* valid bit */
1313         /* now only use physical base address of PDE and valid */
1314         BUG_ON(pd_addr & 0xFFFF00000000003EULL);
1315
1316         data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
1317         data1 = upper_32_bits(pd_addr);
1318         uvd_v7_0_vm_reg_write(ring, data0, data1);
1319
1320         data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1321         data1 = lower_32_bits(pd_addr);
1322         uvd_v7_0_vm_reg_write(ring, data0, data1);
1323
1324         data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1325         data1 = lower_32_bits(pd_addr);
1326         mask = 0xffffffff;
1327         uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
1328
1329         /* flush TLB */
1330         data0 = (hub->vm_inv_eng0_req + eng) << 2;
1331         data1 = req;
1332         uvd_v7_0_vm_reg_write(ring, data0, data1);
1333
1334         /* wait for flush */
1335         data0 = (hub->vm_inv_eng0_ack + eng) << 2;
1336         data1 = 1 << vm_id;
1337         mask =  1 << vm_id;
1338         uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
1339 }
1340
1341 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1342 {
1343         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1344 }
1345
1346 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1347                          unsigned int vm_id, uint64_t pd_addr)
1348 {
1349         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1350         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1351         unsigned eng = ring->vm_inv_eng;
1352
1353         pd_addr = pd_addr | 0x1; /* valid bit */
1354         /* now only use physical base address of PDE and valid */
1355         BUG_ON(pd_addr & 0xFFFF00000000003EULL);
1356
1357         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1358         amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
1359         amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1360
1361         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1362         amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1363         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1364
1365         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1366         amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1367         amdgpu_ring_write(ring, 0xffffffff);
1368         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1369
1370         /* flush TLB */
1371         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1372         amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2);
1373         amdgpu_ring_write(ring, req);
1374
1375         /* wait for flush */
1376         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1377         amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1378         amdgpu_ring_write(ring, 1 << vm_id);
1379         amdgpu_ring_write(ring, 1 << vm_id);
1380 }
1381
1382 #if 0
1383 static bool uvd_v7_0_is_idle(void *handle)
1384 {
1385         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1386
1387         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1388 }
1389
1390 static int uvd_v7_0_wait_for_idle(void *handle)
1391 {
1392         unsigned i;
1393         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1394
1395         for (i = 0; i < adev->usec_timeout; i++) {
1396                 if (uvd_v7_0_is_idle(handle))
1397                         return 0;
1398         }
1399         return -ETIMEDOUT;
1400 }
1401
1402 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1403 static bool uvd_v7_0_check_soft_reset(void *handle)
1404 {
1405         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1406         u32 srbm_soft_reset = 0;
1407         u32 tmp = RREG32(mmSRBM_STATUS);
1408
1409         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1410             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1411             (RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS) &
1412                     AMDGPU_UVD_STATUS_BUSY_MASK)))
1413                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1414                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1415
1416         if (srbm_soft_reset) {
1417                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
1418                 return true;
1419         } else {
1420                 adev->uvd.srbm_soft_reset = 0;
1421                 return false;
1422         }
1423 }
1424
1425 static int uvd_v7_0_pre_soft_reset(void *handle)
1426 {
1427         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1428
1429         if (!adev->uvd.srbm_soft_reset)
1430                 return 0;
1431
1432         uvd_v7_0_stop(adev);
1433         return 0;
1434 }
1435
1436 static int uvd_v7_0_soft_reset(void *handle)
1437 {
1438         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1439         u32 srbm_soft_reset;
1440
1441         if (!adev->uvd.srbm_soft_reset)
1442                 return 0;
1443         srbm_soft_reset = adev->uvd.srbm_soft_reset;
1444
1445         if (srbm_soft_reset) {
1446                 u32 tmp;
1447
1448                 tmp = RREG32(mmSRBM_SOFT_RESET);
1449                 tmp |= srbm_soft_reset;
1450                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1451                 WREG32(mmSRBM_SOFT_RESET, tmp);
1452                 tmp = RREG32(mmSRBM_SOFT_RESET);
1453
1454                 udelay(50);
1455
1456                 tmp &= ~srbm_soft_reset;
1457                 WREG32(mmSRBM_SOFT_RESET, tmp);
1458                 tmp = RREG32(mmSRBM_SOFT_RESET);
1459
1460                 /* Wait a little for things to settle down */
1461                 udelay(50);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int uvd_v7_0_post_soft_reset(void *handle)
1468 {
1469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1470
1471         if (!adev->uvd.srbm_soft_reset)
1472                 return 0;
1473
1474         mdelay(5);
1475
1476         return uvd_v7_0_start(adev);
1477 }
1478 #endif
1479
1480 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1481                                         struct amdgpu_irq_src *source,
1482                                         unsigned type,
1483                                         enum amdgpu_interrupt_state state)
1484 {
1485         // TODO
1486         return 0;
1487 }
1488
1489 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1490                                       struct amdgpu_irq_src *source,
1491                                       struct amdgpu_iv_entry *entry)
1492 {
1493         DRM_DEBUG("IH: UVD TRAP\n");
1494         switch (entry->src_id) {
1495         case 124:
1496                 amdgpu_fence_process(&adev->uvd.ring);
1497                 break;
1498         case 119:
1499                 amdgpu_fence_process(&adev->uvd.ring_enc[0]);
1500                 break;
1501         case 120:
1502                 if (!amdgpu_sriov_vf(adev))
1503                         amdgpu_fence_process(&adev->uvd.ring_enc[1]);
1504                 break;
1505         default:
1506                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1507                           entry->src_id, entry->src_data[0]);
1508                 break;
1509         }
1510
1511         return 0;
1512 }
1513
1514 #if 0
1515 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1516 {
1517         uint32_t data, data1, data2, suvd_flags;
1518
1519         data = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL));
1520         data1 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE));
1521         data2 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_CTRL));
1522
1523         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1524                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1525
1526         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1527                      UVD_SUVD_CGC_GATE__SIT_MASK |
1528                      UVD_SUVD_CGC_GATE__SMP_MASK |
1529                      UVD_SUVD_CGC_GATE__SCM_MASK |
1530                      UVD_SUVD_CGC_GATE__SDB_MASK;
1531
1532         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1533                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1534                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1535
1536         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1537                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1538                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1539                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1540                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1541                         UVD_CGC_CTRL__SYS_MODE_MASK |
1542                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1543                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1544                         UVD_CGC_CTRL__REGS_MODE_MASK |
1545                         UVD_CGC_CTRL__RBC_MODE_MASK |
1546                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1547                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1548                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1549                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1550                         UVD_CGC_CTRL__MPC_MODE_MASK |
1551                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1552                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1553                         UVD_CGC_CTRL__WCB_MODE_MASK |
1554                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1555                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1556                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1557                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1558         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1559                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1560                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1561                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1562                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1563         data1 |= suvd_flags;
1564
1565         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), data);
1566         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE), 0);
1567         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE), data1);
1568         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_CTRL), data2);
1569 }
1570
1571 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1572 {
1573         uint32_t data, data1, cgc_flags, suvd_flags;
1574
1575         data = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE));
1576         data1 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE));
1577
1578         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1579                 UVD_CGC_GATE__UDEC_MASK |
1580                 UVD_CGC_GATE__MPEG2_MASK |
1581                 UVD_CGC_GATE__RBC_MASK |
1582                 UVD_CGC_GATE__LMI_MC_MASK |
1583                 UVD_CGC_GATE__IDCT_MASK |
1584                 UVD_CGC_GATE__MPRD_MASK |
1585                 UVD_CGC_GATE__MPC_MASK |
1586                 UVD_CGC_GATE__LBSI_MASK |
1587                 UVD_CGC_GATE__LRBBM_MASK |
1588                 UVD_CGC_GATE__UDEC_RE_MASK |
1589                 UVD_CGC_GATE__UDEC_CM_MASK |
1590                 UVD_CGC_GATE__UDEC_IT_MASK |
1591                 UVD_CGC_GATE__UDEC_DB_MASK |
1592                 UVD_CGC_GATE__UDEC_MP_MASK |
1593                 UVD_CGC_GATE__WCB_MASK |
1594                 UVD_CGC_GATE__VCPU_MASK |
1595                 UVD_CGC_GATE__SCPU_MASK |
1596                 UVD_CGC_GATE__JPEG_MASK |
1597                 UVD_CGC_GATE__JPEG2_MASK;
1598
1599         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1600                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1601                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1602                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1603                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1604
1605         data |= cgc_flags;
1606         data1 |= suvd_flags;
1607
1608         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE), data);
1609         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE), data1);
1610 }
1611
1612 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1613 {
1614         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1615
1616         if (enable)
1617                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1618                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1619         else
1620                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1621                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1622
1623         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1624 }
1625
1626
1627 static int uvd_v7_0_set_clockgating_state(void *handle,
1628                                           enum amd_clockgating_state state)
1629 {
1630         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1631         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1632
1633         uvd_v7_0_set_bypass_mode(adev, enable);
1634
1635         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1636                 return 0;
1637
1638         if (enable) {
1639                 /* disable HW gating and enable Sw gating */
1640                 uvd_v7_0_set_sw_clock_gating(adev);
1641         } else {
1642                 /* wait for STATUS to clear */
1643                 if (uvd_v7_0_wait_for_idle(handle))
1644                         return -EBUSY;
1645
1646                 /* enable HW gates because UVD is idle */
1647                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1648         }
1649
1650         return 0;
1651 }
1652
1653 static int uvd_v7_0_set_powergating_state(void *handle,
1654                                           enum amd_powergating_state state)
1655 {
1656         /* This doesn't actually powergate the UVD block.
1657          * That's done in the dpm code via the SMC.  This
1658          * just re-inits the block as necessary.  The actual
1659          * gating still happens in the dpm code.  We should
1660          * revisit this when there is a cleaner line between
1661          * the smc and the hw blocks
1662          */
1663         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1664
1665         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1666                 return 0;
1667
1668         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), UVD_POWER_STATUS__UVD_PG_EN_MASK);
1669
1670         if (state == AMD_PG_STATE_GATE) {
1671                 uvd_v7_0_stop(adev);
1672                 return 0;
1673         } else {
1674                 return uvd_v7_0_start(adev);
1675         }
1676 }
1677 #endif
1678
1679 static int uvd_v7_0_set_clockgating_state(void *handle,
1680                                           enum amd_clockgating_state state)
1681 {
1682         /* needed for driver unload*/
1683         return 0;
1684 }
1685
1686 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1687         .name = "uvd_v7_0",
1688         .early_init = uvd_v7_0_early_init,
1689         .late_init = NULL,
1690         .sw_init = uvd_v7_0_sw_init,
1691         .sw_fini = uvd_v7_0_sw_fini,
1692         .hw_init = uvd_v7_0_hw_init,
1693         .hw_fini = uvd_v7_0_hw_fini,
1694         .suspend = uvd_v7_0_suspend,
1695         .resume = uvd_v7_0_resume,
1696         .is_idle = NULL /* uvd_v7_0_is_idle */,
1697         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1698         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1699         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1700         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1701         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1702         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1703         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1704 };
1705
1706 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1707         .type = AMDGPU_RING_TYPE_UVD,
1708         .align_mask = 0xf,
1709         .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
1710         .support_64bit_ptrs = false,
1711         .vmhub = AMDGPU_MMHUB,
1712         .get_rptr = uvd_v7_0_ring_get_rptr,
1713         .get_wptr = uvd_v7_0_ring_get_wptr,
1714         .set_wptr = uvd_v7_0_ring_set_wptr,
1715         .emit_frame_size =
1716                 2 + /* uvd_v7_0_ring_emit_hdp_flush */
1717                 2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
1718                 34 + /* uvd_v7_0_ring_emit_vm_flush */
1719                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1720         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1721         .emit_ib = uvd_v7_0_ring_emit_ib,
1722         .emit_fence = uvd_v7_0_ring_emit_fence,
1723         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1724         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1725         .emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate,
1726         .test_ring = uvd_v7_0_ring_test_ring,
1727         .test_ib = amdgpu_uvd_ring_test_ib,
1728         .insert_nop = amdgpu_ring_insert_nop,
1729         .pad_ib = amdgpu_ring_generic_pad_ib,
1730         .begin_use = amdgpu_uvd_ring_begin_use,
1731         .end_use = amdgpu_uvd_ring_end_use,
1732 };
1733
1734 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1735         .type = AMDGPU_RING_TYPE_UVD_ENC,
1736         .align_mask = 0x3f,
1737         .nop = HEVC_ENC_CMD_NO_OP,
1738         .support_64bit_ptrs = false,
1739         .vmhub = AMDGPU_MMHUB,
1740         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1741         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1742         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1743         .emit_frame_size =
1744                 17 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1745                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1746                 1, /* uvd_v7_0_enc_ring_insert_end */
1747         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1748         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1749         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1750         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1751         .test_ring = uvd_v7_0_enc_ring_test_ring,
1752         .test_ib = uvd_v7_0_enc_ring_test_ib,
1753         .insert_nop = amdgpu_ring_insert_nop,
1754         .insert_end = uvd_v7_0_enc_ring_insert_end,
1755         .pad_ib = amdgpu_ring_generic_pad_ib,
1756         .begin_use = amdgpu_uvd_ring_begin_use,
1757         .end_use = amdgpu_uvd_ring_end_use,
1758 };
1759
1760 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1761 {
1762         adev->uvd.ring.funcs = &uvd_v7_0_ring_vm_funcs;
1763         DRM_INFO("UVD is enabled in VM mode\n");
1764 }
1765
1766 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1767 {
1768         int i;
1769
1770         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1771                 adev->uvd.ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1772
1773         DRM_INFO("UVD ENC is enabled in VM mode\n");
1774 }
1775
1776 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1777         .set = uvd_v7_0_set_interrupt_state,
1778         .process = uvd_v7_0_process_interrupt,
1779 };
1780
1781 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1782 {
1783         adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
1784         adev->uvd.irq.funcs = &uvd_v7_0_irq_funcs;
1785 }
1786
1787 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1788 {
1789                 .type = AMD_IP_BLOCK_TYPE_UVD,
1790                 .major = 7,
1791                 .minor = 0,
1792                 .rev = 0,
1793                 .funcs = &uvd_v7_0_ip_funcs,
1794 };