2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/string.h>
23 #include <linux/log2.h>
24 #include <linux/pci-aspm.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/interrupt.h>
27 #include <linux/device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pci_hotplug.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pci-ats.h>
32 #include <asm/setup.h>
34 #include <linux/aer.h>
37 const char *pci_power_names[] = {
38 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
40 EXPORT_SYMBOL_GPL(pci_power_names);
42 int isa_dma_bridge_buggy;
43 EXPORT_SYMBOL(isa_dma_bridge_buggy);
46 EXPORT_SYMBOL(pci_pci_problems);
48 unsigned int pci_pm_d3_delay;
50 static void pci_pme_list_scan(struct work_struct *work);
52 static LIST_HEAD(pci_pme_list);
53 static DEFINE_MUTEX(pci_pme_list_mutex);
54 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
55 static DEFINE_MUTEX(pci_bridge_mutex);
57 struct pci_pme_device {
58 struct list_head list;
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
64 static void pci_dev_d3_sleep(struct pci_dev *dev)
66 unsigned int delay = dev->d3_delay;
68 if (delay < pci_pm_d3_delay)
69 delay = pci_pm_d3_delay;
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported = 1;
79 #define DEFAULT_CARDBUS_IO_SIZE (256)
80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
83 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
85 #define DEFAULT_HOTPLUG_IO_SIZE (256)
86 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
87 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
88 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
89 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
91 #define DEFAULT_HOTPLUG_BUS_SIZE 1
92 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
94 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
97 * The default CLS is used if arch didn't set CLS explicitly and not
98 * all pci devices agree on the same value. Arch can override either
99 * the dfl or actual value as it sees fit. Don't forget this is
100 * measured in 32-bit words, not bytes.
102 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
103 u8 pci_cache_line_size;
106 * If we set up a device for bus mastering, we need to check the latency
107 * timer as certain BIOSes forget to set it properly.
109 unsigned int pcibios_max_latency = 255;
111 /* If set, the PCIe ARI capability will not be used. */
112 static bool pcie_ari_disabled;
114 /* Disable bridge_d3 for all PCIe ports */
115 static bool pci_bridge_d3_disable;
116 /* Force bridge_d3 for all PCIe ports */
117 static bool pci_bridge_d3_force;
119 static int __init pcie_port_pm_setup(char *str)
121 if (!strcmp(str, "off"))
122 pci_bridge_d3_disable = true;
123 else if (!strcmp(str, "force"))
124 pci_bridge_d3_force = true;
127 __setup("pcie_port_pm=", pcie_port_pm_setup);
130 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
131 * @bus: pointer to PCI bus structure to search
133 * Given a PCI bus, returns the highest PCI bus number present in the set
134 * including the given PCI bus and its list of child PCI buses.
136 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
139 unsigned char max, n;
141 max = bus->busn_res.end;
142 list_for_each_entry(tmp, &bus->children, node) {
143 n = pci_bus_max_busnr(tmp);
149 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
151 #ifdef CONFIG_HAS_IOMEM
152 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
154 struct resource *res = &pdev->resource[bar];
157 * Make sure the BAR is actually a memory resource, not an IO resource
159 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
160 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
163 return ioremap_nocache(res->start, resource_size(res));
165 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
167 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
170 * Make sure the BAR is actually a memory resource, not an IO resource
172 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
176 return ioremap_wc(pci_resource_start(pdev, bar),
177 pci_resource_len(pdev, bar));
179 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
183 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
184 u8 pos, int cap, int *ttl)
189 pci_bus_read_config_byte(bus, devfn, pos, &pos);
195 pci_bus_read_config_word(bus, devfn, pos, &ent);
207 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
210 int ttl = PCI_FIND_CAP_TTL;
212 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
215 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
217 return __pci_find_next_cap(dev->bus, dev->devfn,
218 pos + PCI_CAP_LIST_NEXT, cap);
220 EXPORT_SYMBOL_GPL(pci_find_next_capability);
222 static int __pci_bus_find_cap_start(struct pci_bus *bus,
223 unsigned int devfn, u8 hdr_type)
227 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
228 if (!(status & PCI_STATUS_CAP_LIST))
232 case PCI_HEADER_TYPE_NORMAL:
233 case PCI_HEADER_TYPE_BRIDGE:
234 return PCI_CAPABILITY_LIST;
235 case PCI_HEADER_TYPE_CARDBUS:
236 return PCI_CB_CAPABILITY_LIST;
243 * pci_find_capability - query for devices' capabilities
244 * @dev: PCI device to query
245 * @cap: capability code
247 * Tell if a device supports a given PCI capability.
248 * Returns the address of the requested capability structure within the
249 * device's PCI configuration space or 0 in case the device does not
250 * support it. Possible values for @cap:
252 * %PCI_CAP_ID_PM Power Management
253 * %PCI_CAP_ID_AGP Accelerated Graphics Port
254 * %PCI_CAP_ID_VPD Vital Product Data
255 * %PCI_CAP_ID_SLOTID Slot Identification
256 * %PCI_CAP_ID_MSI Message Signalled Interrupts
257 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
258 * %PCI_CAP_ID_PCIX PCI-X
259 * %PCI_CAP_ID_EXP PCI Express
261 int pci_find_capability(struct pci_dev *dev, int cap)
265 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
267 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
271 EXPORT_SYMBOL(pci_find_capability);
274 * pci_bus_find_capability - query for devices' capabilities
275 * @bus: the PCI bus to query
276 * @devfn: PCI device to query
277 * @cap: capability code
279 * Like pci_find_capability() but works for pci devices that do not have a
280 * pci_dev structure set up yet.
282 * Returns the address of the requested capability structure within the
283 * device's PCI configuration space or 0 in case the device does not
286 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
291 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
293 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
295 pos = __pci_find_next_cap(bus, devfn, pos, cap);
299 EXPORT_SYMBOL(pci_bus_find_capability);
302 * pci_find_next_ext_capability - Find an extended capability
303 * @dev: PCI device to query
304 * @start: address at which to start looking (0 to start at beginning of list)
305 * @cap: capability code
307 * Returns the address of the next matching extended capability structure
308 * within the device's PCI configuration space or 0 if the device does
309 * not support it. Some capabilities can occur several times, e.g., the
310 * vendor-specific capability, and this provides a way to find them all.
312 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
316 int pos = PCI_CFG_SPACE_SIZE;
318 /* minimum 8 bytes per capability */
319 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
321 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
327 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
331 * If we have no capabilities, this is indicated by cap ID,
332 * cap version and next pointer all being 0.
338 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
341 pos = PCI_EXT_CAP_NEXT(header);
342 if (pos < PCI_CFG_SPACE_SIZE)
345 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
351 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
354 * pci_find_ext_capability - Find an extended capability
355 * @dev: PCI device to query
356 * @cap: capability code
358 * Returns the address of the requested extended capability structure
359 * within the device's PCI configuration space or 0 if the device does
360 * not support it. Possible values for @cap:
362 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
363 * %PCI_EXT_CAP_ID_VC Virtual Channel
364 * %PCI_EXT_CAP_ID_DSN Device Serial Number
365 * %PCI_EXT_CAP_ID_PWR Power Budgeting
367 int pci_find_ext_capability(struct pci_dev *dev, int cap)
369 return pci_find_next_ext_capability(dev, 0, cap);
371 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
373 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
375 int rc, ttl = PCI_FIND_CAP_TTL;
378 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
379 mask = HT_3BIT_CAP_MASK;
381 mask = HT_5BIT_CAP_MASK;
383 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
384 PCI_CAP_ID_HT, &ttl);
386 rc = pci_read_config_byte(dev, pos + 3, &cap);
387 if (rc != PCIBIOS_SUCCESSFUL)
390 if ((cap & mask) == ht_cap)
393 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
394 pos + PCI_CAP_LIST_NEXT,
395 PCI_CAP_ID_HT, &ttl);
401 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
402 * @dev: PCI device to query
403 * @pos: Position from which to continue searching
404 * @ht_cap: Hypertransport capability code
406 * To be used in conjunction with pci_find_ht_capability() to search for
407 * all capabilities matching @ht_cap. @pos should always be a value returned
408 * from pci_find_ht_capability().
410 * NB. To be 100% safe against broken PCI devices, the caller should take
411 * steps to avoid an infinite loop.
413 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
415 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
417 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
420 * pci_find_ht_capability - query a device's Hypertransport capabilities
421 * @dev: PCI device to query
422 * @ht_cap: Hypertransport capability code
424 * Tell if a device supports a given Hypertransport capability.
425 * Returns an address within the device's PCI configuration space
426 * or 0 in case the device does not support the request capability.
427 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
428 * which has a Hypertransport capability matching @ht_cap.
430 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
434 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
436 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
440 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
443 * pci_find_parent_resource - return resource region of parent bus of given region
444 * @dev: PCI device structure contains resources to be searched
445 * @res: child resource record for which parent is sought
447 * For given resource region of given device, return the resource
448 * region of parent bus the given region is contained in.
450 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
451 struct resource *res)
453 const struct pci_bus *bus = dev->bus;
457 pci_bus_for_each_resource(bus, r, i) {
460 if (resource_contains(r, res)) {
463 * If the window is prefetchable but the BAR is
464 * not, the allocator made a mistake.
466 if (r->flags & IORESOURCE_PREFETCH &&
467 !(res->flags & IORESOURCE_PREFETCH))
471 * If we're below a transparent bridge, there may
472 * be both a positively-decoded aperture and a
473 * subtractively-decoded region that contain the BAR.
474 * We want the positively-decoded one, so this depends
475 * on pci_bus_for_each_resource() giving us those
483 EXPORT_SYMBOL(pci_find_parent_resource);
486 * pci_find_resource - Return matching PCI device resource
487 * @dev: PCI device to query
488 * @res: Resource to look for
490 * Goes over standard PCI resources (BARs) and checks if the given resource
491 * is partially or fully contained in any of them. In that case the
492 * matching resource is returned, %NULL otherwise.
494 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
498 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
499 struct resource *r = &dev->resource[i];
501 if (r->start && resource_contains(r, res))
507 EXPORT_SYMBOL(pci_find_resource);
510 * pci_find_pcie_root_port - return PCIe Root Port
511 * @dev: PCI device to query
513 * Traverse up the parent chain and return the PCIe Root Port PCI Device
514 * for a given PCI Device.
516 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
518 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
520 bridge = pci_upstream_bridge(dev);
521 while (bridge && pci_is_pcie(bridge)) {
522 highest_pcie_bridge = bridge;
523 bridge = pci_upstream_bridge(bridge);
526 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
529 return highest_pcie_bridge;
531 EXPORT_SYMBOL(pci_find_pcie_root_port);
534 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
535 * @dev: the PCI device to operate on
536 * @pos: config space offset of status word
537 * @mask: mask of bit(s) to care about in status word
539 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
541 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
545 /* Wait for Transaction Pending bit clean */
546 for (i = 0; i < 4; i++) {
549 msleep((1 << (i - 1)) * 100);
551 pci_read_config_word(dev, pos, &status);
552 if (!(status & mask))
560 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
561 * @dev: PCI device to have its BARs restored
563 * Restore the BAR values for a given device, so as to make it
564 * accessible by its driver.
566 static void pci_restore_bars(struct pci_dev *dev)
570 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
571 pci_update_resource(dev, i);
574 static const struct pci_platform_pm_ops *pci_platform_pm;
576 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
578 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
579 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
581 pci_platform_pm = ops;
585 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
587 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
590 static inline int platform_pci_set_power_state(struct pci_dev *dev,
593 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
596 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
598 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
601 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
603 return pci_platform_pm ?
604 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
607 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
609 return pci_platform_pm ?
610 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
613 static inline bool platform_pci_need_resume(struct pci_dev *dev)
615 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
619 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
621 * @dev: PCI device to handle.
622 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
625 * -EINVAL if the requested state is invalid.
626 * -EIO if device does not support PCI PM or its PM capabilities register has a
627 * wrong version, or device doesn't support the requested state.
628 * 0 if device already is in the requested state.
629 * 0 if device's power state has been successfully changed.
631 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
634 bool need_restore = false;
636 /* Check if we're already there */
637 if (dev->current_state == state)
643 if (state < PCI_D0 || state > PCI_D3hot)
646 /* Validate current state:
647 * Can enter D0 from any state, but if we can only go deeper
648 * to sleep if we're already in a low power state
650 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
651 && dev->current_state > state) {
652 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
653 dev->current_state, state);
657 /* check if this device supports the desired state */
658 if ((state == PCI_D1 && !dev->d1_support)
659 || (state == PCI_D2 && !dev->d2_support))
662 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
664 /* If we're (effectively) in D3, force entire word to 0.
665 * This doesn't affect PME_Status, disables PME_En, and
666 * sets PowerState to 0.
668 switch (dev->current_state) {
672 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
677 case PCI_UNKNOWN: /* Boot-up */
678 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
679 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
681 /* Fall-through: force to D0 */
687 /* enter specified state */
688 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
690 /* Mandatory power management transition delays */
691 /* see PCI PM 1.1 5.6.1 table 18 */
692 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
693 pci_dev_d3_sleep(dev);
694 else if (state == PCI_D2 || dev->current_state == PCI_D2)
695 udelay(PCI_PM_D2_DELAY);
697 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
698 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
699 if (dev->current_state != state && printk_ratelimit())
700 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
704 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
705 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
706 * from D3hot to D0 _may_ perform an internal reset, thereby
707 * going to "D0 Uninitialized" rather than "D0 Initialized".
708 * For example, at least some versions of the 3c905B and the
709 * 3c556B exhibit this behaviour.
711 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
712 * devices in a D3hot state at boot. Consequently, we need to
713 * restore at least the BARs so that the device will be
714 * accessible to its driver.
717 pci_restore_bars(dev);
720 pcie_aspm_pm_state_change(dev->bus->self);
726 * pci_update_current_state - Read power state of given device and cache it
727 * @dev: PCI device to handle.
728 * @state: State to cache in case the device doesn't have the PM capability
730 * The power state is read from the PMCSR register, which however is
731 * inaccessible in D3cold. The platform firmware is therefore queried first
732 * to detect accessibility of the register. In case the platform firmware
733 * reports an incorrect state or the device isn't power manageable by the
734 * platform at all, we try to detect D3cold by testing accessibility of the
735 * vendor ID in config space.
737 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
739 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
740 !pci_device_is_present(dev)) {
741 dev->current_state = PCI_D3cold;
742 } else if (dev->pm_cap) {
745 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
746 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
748 dev->current_state = state;
753 * pci_power_up - Put the given device into D0 forcibly
754 * @dev: PCI device to power up
756 void pci_power_up(struct pci_dev *dev)
758 if (platform_pci_power_manageable(dev))
759 platform_pci_set_power_state(dev, PCI_D0);
761 pci_raw_set_power_state(dev, PCI_D0);
762 pci_update_current_state(dev, PCI_D0);
766 * pci_platform_power_transition - Use platform to change device power state
767 * @dev: PCI device to handle.
768 * @state: State to put the device into.
770 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
774 if (platform_pci_power_manageable(dev)) {
775 error = platform_pci_set_power_state(dev, state);
777 pci_update_current_state(dev, state);
781 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
782 dev->current_state = PCI_D0;
788 * pci_wakeup - Wake up a PCI device
789 * @pci_dev: Device to handle.
790 * @ign: ignored parameter
792 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
794 pci_wakeup_event(pci_dev);
795 pm_request_resume(&pci_dev->dev);
800 * pci_wakeup_bus - Walk given bus and wake up devices on it
801 * @bus: Top bus of the subtree to walk.
803 static void pci_wakeup_bus(struct pci_bus *bus)
806 pci_walk_bus(bus, pci_wakeup, NULL);
810 * __pci_start_power_transition - Start power transition of a PCI device
811 * @dev: PCI device to handle.
812 * @state: State to put the device into.
814 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
816 if (state == PCI_D0) {
817 pci_platform_power_transition(dev, PCI_D0);
819 * Mandatory power management transition delays, see
820 * PCI Express Base Specification Revision 2.0 Section
821 * 6.6.1: Conventional Reset. Do not delay for
822 * devices powered on/off by corresponding bridge,
823 * because have already delayed for the bridge.
825 if (dev->runtime_d3cold) {
826 if (dev->d3cold_delay)
827 msleep(dev->d3cold_delay);
829 * When powering on a bridge from D3cold, the
830 * whole hierarchy may be powered on into
831 * D0uninitialized state, resume them to give
832 * them a chance to suspend again
834 pci_wakeup_bus(dev->subordinate);
840 * __pci_dev_set_current_state - Set current state of a PCI device
841 * @dev: Device to handle
842 * @data: pointer to state to be set
844 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
846 pci_power_t state = *(pci_power_t *)data;
848 dev->current_state = state;
853 * __pci_bus_set_current_state - Walk given bus and set current state of devices
854 * @bus: Top bus of the subtree to walk.
855 * @state: state to be set
857 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
860 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
864 * __pci_complete_power_transition - Complete power transition of a PCI device
865 * @dev: PCI device to handle.
866 * @state: State to put the device into.
868 * This function should not be called directly by device drivers.
870 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
876 ret = pci_platform_power_transition(dev, state);
877 /* Power off the bridge may power off the whole hierarchy */
878 if (!ret && state == PCI_D3cold)
879 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
882 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
885 * pci_set_power_state - Set the power state of a PCI device
886 * @dev: PCI device to handle.
887 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
889 * Transition a device to a new power state, using the platform firmware and/or
890 * the device's PCI PM registers.
893 * -EINVAL if the requested state is invalid.
894 * -EIO if device does not support PCI PM or its PM capabilities register has a
895 * wrong version, or device doesn't support the requested state.
896 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
897 * 0 if device already is in the requested state.
898 * 0 if the transition is to D3 but D3 is not supported.
899 * 0 if device's power state has been successfully changed.
901 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
905 /* bound the state we're entering */
906 if (state > PCI_D3cold)
908 else if (state < PCI_D0)
910 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
912 * If the device or the parent bridge do not support PCI PM,
913 * ignore the request if we're doing anything other than putting
914 * it into D0 (which would only happen on boot).
918 /* Check if we're already there */
919 if (dev->current_state == state)
922 __pci_start_power_transition(dev, state);
924 /* This device is quirked not to be put into D3, so
925 don't put it in D3 */
926 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
930 * To put device in D3cold, we put device into D3hot in native
931 * way, then put device into D3cold with platform ops
933 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
936 if (!__pci_complete_power_transition(dev, state))
941 EXPORT_SYMBOL(pci_set_power_state);
944 * pci_choose_state - Choose the power state of a PCI device
945 * @dev: PCI device to be suspended
946 * @state: target sleep state for the whole system. This is the value
947 * that is passed to suspend() function.
949 * Returns PCI power state suitable for given device and given system
953 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
960 ret = platform_pci_choose_state(dev);
961 if (ret != PCI_POWER_ERROR)
964 switch (state.event) {
967 case PM_EVENT_FREEZE:
968 case PM_EVENT_PRETHAW:
969 /* REVISIT both freeze and pre-thaw "should" use D0 */
970 case PM_EVENT_SUSPEND:
971 case PM_EVENT_HIBERNATE:
974 dev_info(&dev->dev, "unrecognized suspend event %d\n",
980 EXPORT_SYMBOL(pci_choose_state);
982 #define PCI_EXP_SAVE_REGS 7
984 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
985 u16 cap, bool extended)
987 struct pci_cap_saved_state *tmp;
989 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
990 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
996 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
998 return _pci_find_saved_cap(dev, cap, false);
1001 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1003 return _pci_find_saved_cap(dev, cap, true);
1006 static int pci_save_pcie_state(struct pci_dev *dev)
1009 struct pci_cap_saved_state *save_state;
1012 if (!pci_is_pcie(dev))
1015 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1017 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1021 cap = (u16 *)&save_state->cap.data[0];
1022 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1023 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1024 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1025 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1026 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1027 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1028 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1033 static void pci_restore_pcie_state(struct pci_dev *dev)
1036 struct pci_cap_saved_state *save_state;
1039 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1043 cap = (u16 *)&save_state->cap.data[0];
1044 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1045 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1046 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1047 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1048 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1049 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1050 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1054 static int pci_save_pcix_state(struct pci_dev *dev)
1057 struct pci_cap_saved_state *save_state;
1059 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1063 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1065 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1069 pci_read_config_word(dev, pos + PCI_X_CMD,
1070 (u16 *)save_state->cap.data);
1075 static void pci_restore_pcix_state(struct pci_dev *dev)
1078 struct pci_cap_saved_state *save_state;
1081 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1082 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1083 if (!save_state || !pos)
1085 cap = (u16 *)&save_state->cap.data[0];
1087 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1092 * pci_save_state - save the PCI configuration space of a device before suspending
1093 * @dev: - PCI device that we're dealing with
1095 int pci_save_state(struct pci_dev *dev)
1098 /* XXX: 100% dword access ok here? */
1099 for (i = 0; i < 16; i++)
1100 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1101 dev->state_saved = true;
1103 i = pci_save_pcie_state(dev);
1107 i = pci_save_pcix_state(dev);
1111 return pci_save_vc_state(dev);
1113 EXPORT_SYMBOL(pci_save_state);
1115 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1116 u32 saved_val, int retry)
1120 pci_read_config_dword(pdev, offset, &val);
1121 if (val == saved_val)
1125 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1126 offset, val, saved_val);
1127 pci_write_config_dword(pdev, offset, saved_val);
1131 pci_read_config_dword(pdev, offset, &val);
1132 if (val == saved_val)
1139 static void pci_restore_config_space_range(struct pci_dev *pdev,
1140 int start, int end, int retry)
1144 for (index = end; index >= start; index--)
1145 pci_restore_config_dword(pdev, 4 * index,
1146 pdev->saved_config_space[index],
1150 static void pci_restore_config_space(struct pci_dev *pdev)
1152 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1153 pci_restore_config_space_range(pdev, 10, 15, 0);
1154 /* Restore BARs before the command register. */
1155 pci_restore_config_space_range(pdev, 4, 9, 10);
1156 pci_restore_config_space_range(pdev, 0, 3, 0);
1158 pci_restore_config_space_range(pdev, 0, 15, 0);
1163 * pci_restore_state - Restore the saved state of a PCI device
1164 * @dev: - PCI device that we're dealing with
1166 void pci_restore_state(struct pci_dev *dev)
1168 if (!dev->state_saved)
1171 /* PCI Express register must be restored first */
1172 pci_restore_pcie_state(dev);
1173 pci_restore_pasid_state(dev);
1174 pci_restore_pri_state(dev);
1175 pci_restore_ats_state(dev);
1176 pci_restore_vc_state(dev);
1178 pci_cleanup_aer_error_status_regs(dev);
1180 pci_restore_config_space(dev);
1182 pci_restore_pcix_state(dev);
1183 pci_restore_msi_state(dev);
1185 /* Restore ACS and IOV configuration state */
1186 pci_enable_acs(dev);
1187 pci_restore_iov_state(dev);
1189 dev->state_saved = false;
1191 EXPORT_SYMBOL(pci_restore_state);
1193 struct pci_saved_state {
1194 u32 config_space[16];
1195 struct pci_cap_saved_data cap[0];
1199 * pci_store_saved_state - Allocate and return an opaque struct containing
1200 * the device saved state.
1201 * @dev: PCI device that we're dealing with
1203 * Return NULL if no state or error.
1205 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1207 struct pci_saved_state *state;
1208 struct pci_cap_saved_state *tmp;
1209 struct pci_cap_saved_data *cap;
1212 if (!dev->state_saved)
1215 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1217 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1218 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1220 state = kzalloc(size, GFP_KERNEL);
1224 memcpy(state->config_space, dev->saved_config_space,
1225 sizeof(state->config_space));
1228 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1229 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1230 memcpy(cap, &tmp->cap, len);
1231 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1233 /* Empty cap_save terminates list */
1237 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1240 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1241 * @dev: PCI device that we're dealing with
1242 * @state: Saved state returned from pci_store_saved_state()
1244 int pci_load_saved_state(struct pci_dev *dev,
1245 struct pci_saved_state *state)
1247 struct pci_cap_saved_data *cap;
1249 dev->state_saved = false;
1254 memcpy(dev->saved_config_space, state->config_space,
1255 sizeof(state->config_space));
1259 struct pci_cap_saved_state *tmp;
1261 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1262 if (!tmp || tmp->cap.size != cap->size)
1265 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1266 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1267 sizeof(struct pci_cap_saved_data) + cap->size);
1270 dev->state_saved = true;
1273 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1276 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1277 * and free the memory allocated for it.
1278 * @dev: PCI device that we're dealing with
1279 * @state: Pointer to saved state returned from pci_store_saved_state()
1281 int pci_load_and_free_saved_state(struct pci_dev *dev,
1282 struct pci_saved_state **state)
1284 int ret = pci_load_saved_state(dev, *state);
1289 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1291 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1293 return pci_enable_resources(dev, bars);
1296 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1299 struct pci_dev *bridge;
1303 err = pci_set_power_state(dev, PCI_D0);
1304 if (err < 0 && err != -EIO)
1307 bridge = pci_upstream_bridge(dev);
1309 pcie_aspm_powersave_config_link(bridge);
1311 err = pcibios_enable_device(dev, bars);
1314 pci_fixup_device(pci_fixup_enable, dev);
1316 if (dev->msi_enabled || dev->msix_enabled)
1319 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1321 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1322 if (cmd & PCI_COMMAND_INTX_DISABLE)
1323 pci_write_config_word(dev, PCI_COMMAND,
1324 cmd & ~PCI_COMMAND_INTX_DISABLE);
1331 * pci_reenable_device - Resume abandoned device
1332 * @dev: PCI device to be resumed
1334 * Note this function is a backend of pci_default_resume and is not supposed
1335 * to be called by normal code, write proper resume handler and use it instead.
1337 int pci_reenable_device(struct pci_dev *dev)
1339 if (pci_is_enabled(dev))
1340 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1343 EXPORT_SYMBOL(pci_reenable_device);
1345 static void pci_enable_bridge(struct pci_dev *dev)
1347 struct pci_dev *bridge;
1350 bridge = pci_upstream_bridge(dev);
1352 pci_enable_bridge(bridge);
1355 * Hold pci_bridge_mutex to prevent a race when enabling two
1356 * devices below the bridge simultaneously. The race may cause a
1357 * PCI_COMMAND_MEMORY update to be lost (see changelog).
1359 mutex_lock(&pci_bridge_mutex);
1360 if (pci_is_enabled(dev)) {
1361 if (!dev->is_busmaster)
1362 pci_set_master(dev);
1366 retval = pci_enable_device(dev);
1368 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1370 pci_set_master(dev);
1372 mutex_unlock(&pci_bridge_mutex);
1375 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1377 struct pci_dev *bridge;
1382 * Power state could be unknown at this point, either due to a fresh
1383 * boot or a device removal call. So get the current power state
1384 * so that things like MSI message writing will behave as expected
1385 * (e.g. if the device really is in D0 at enable time).
1389 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1390 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1393 if (atomic_inc_return(&dev->enable_cnt) > 1)
1394 return 0; /* already enabled */
1396 bridge = pci_upstream_bridge(dev);
1397 if (bridge && !pci_is_enabled(bridge))
1398 pci_enable_bridge(bridge);
1400 /* only skip sriov related */
1401 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1402 if (dev->resource[i].flags & flags)
1404 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1405 if (dev->resource[i].flags & flags)
1408 err = do_pci_enable_device(dev, bars);
1410 atomic_dec(&dev->enable_cnt);
1415 * pci_enable_device_io - Initialize a device for use with IO space
1416 * @dev: PCI device to be initialized
1418 * Initialize device before it's used by a driver. Ask low-level code
1419 * to enable I/O resources. Wake up the device if it was suspended.
1420 * Beware, this function can fail.
1422 int pci_enable_device_io(struct pci_dev *dev)
1424 return pci_enable_device_flags(dev, IORESOURCE_IO);
1426 EXPORT_SYMBOL(pci_enable_device_io);
1429 * pci_enable_device_mem - Initialize a device for use with Memory space
1430 * @dev: PCI device to be initialized
1432 * Initialize device before it's used by a driver. Ask low-level code
1433 * to enable Memory resources. Wake up the device if it was suspended.
1434 * Beware, this function can fail.
1436 int pci_enable_device_mem(struct pci_dev *dev)
1438 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1440 EXPORT_SYMBOL(pci_enable_device_mem);
1443 * pci_enable_device - Initialize device before it's used by a driver.
1444 * @dev: PCI device to be initialized
1446 * Initialize device before it's used by a driver. Ask low-level code
1447 * to enable I/O and memory. Wake up the device if it was suspended.
1448 * Beware, this function can fail.
1450 * Note we don't actually enable the device many times if we call
1451 * this function repeatedly (we just increment the count).
1453 int pci_enable_device(struct pci_dev *dev)
1455 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1457 EXPORT_SYMBOL(pci_enable_device);
1460 * Managed PCI resources. This manages device on/off, intx/msi/msix
1461 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1462 * there's no need to track it separately. pci_devres is initialized
1463 * when a device is enabled using managed PCI device enable interface.
1466 unsigned int enabled:1;
1467 unsigned int pinned:1;
1468 unsigned int orig_intx:1;
1469 unsigned int restore_intx:1;
1473 static void pcim_release(struct device *gendev, void *res)
1475 struct pci_dev *dev = to_pci_dev(gendev);
1476 struct pci_devres *this = res;
1479 if (dev->msi_enabled)
1480 pci_disable_msi(dev);
1481 if (dev->msix_enabled)
1482 pci_disable_msix(dev);
1484 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1485 if (this->region_mask & (1 << i))
1486 pci_release_region(dev, i);
1488 if (this->restore_intx)
1489 pci_intx(dev, this->orig_intx);
1491 if (this->enabled && !this->pinned)
1492 pci_disable_device(dev);
1495 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1497 struct pci_devres *dr, *new_dr;
1499 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1503 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1506 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1509 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1511 if (pci_is_managed(pdev))
1512 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1517 * pcim_enable_device - Managed pci_enable_device()
1518 * @pdev: PCI device to be initialized
1520 * Managed pci_enable_device().
1522 int pcim_enable_device(struct pci_dev *pdev)
1524 struct pci_devres *dr;
1527 dr = get_pci_dr(pdev);
1533 rc = pci_enable_device(pdev);
1535 pdev->is_managed = 1;
1540 EXPORT_SYMBOL(pcim_enable_device);
1543 * pcim_pin_device - Pin managed PCI device
1544 * @pdev: PCI device to pin
1546 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1547 * driver detach. @pdev must have been enabled with
1548 * pcim_enable_device().
1550 void pcim_pin_device(struct pci_dev *pdev)
1552 struct pci_devres *dr;
1554 dr = find_pci_dr(pdev);
1555 WARN_ON(!dr || !dr->enabled);
1559 EXPORT_SYMBOL(pcim_pin_device);
1562 * pcibios_add_device - provide arch specific hooks when adding device dev
1563 * @dev: the PCI device being added
1565 * Permits the platform to provide architecture specific functionality when
1566 * devices are added. This is the default implementation. Architecture
1567 * implementations can override this.
1569 int __weak pcibios_add_device(struct pci_dev *dev)
1575 * pcibios_release_device - provide arch specific hooks when releasing device dev
1576 * @dev: the PCI device being released
1578 * Permits the platform to provide architecture specific functionality when
1579 * devices are released. This is the default implementation. Architecture
1580 * implementations can override this.
1582 void __weak pcibios_release_device(struct pci_dev *dev) {}
1585 * pcibios_disable_device - disable arch specific PCI resources for device dev
1586 * @dev: the PCI device to disable
1588 * Disables architecture specific PCI resources for the device. This
1589 * is the default implementation. Architecture implementations can
1592 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1595 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1596 * @irq: ISA IRQ to penalize
1597 * @active: IRQ active or not
1599 * Permits the platform to provide architecture-specific functionality when
1600 * penalizing ISA IRQs. This is the default implementation. Architecture
1601 * implementations can override this.
1603 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1605 static void do_pci_disable_device(struct pci_dev *dev)
1609 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1610 if (pci_command & PCI_COMMAND_MASTER) {
1611 pci_command &= ~PCI_COMMAND_MASTER;
1612 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1615 pcibios_disable_device(dev);
1619 * pci_disable_enabled_device - Disable device without updating enable_cnt
1620 * @dev: PCI device to disable
1622 * NOTE: This function is a backend of PCI power management routines and is
1623 * not supposed to be called drivers.
1625 void pci_disable_enabled_device(struct pci_dev *dev)
1627 if (pci_is_enabled(dev))
1628 do_pci_disable_device(dev);
1632 * pci_disable_device - Disable PCI device after use
1633 * @dev: PCI device to be disabled
1635 * Signal to the system that the PCI device is not in use by the system
1636 * anymore. This only involves disabling PCI bus-mastering, if active.
1638 * Note we don't actually disable the device until all callers of
1639 * pci_enable_device() have called pci_disable_device().
1641 void pci_disable_device(struct pci_dev *dev)
1643 struct pci_devres *dr;
1645 dr = find_pci_dr(dev);
1649 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1650 "disabling already-disabled device");
1652 if (atomic_dec_return(&dev->enable_cnt) != 0)
1655 do_pci_disable_device(dev);
1657 dev->is_busmaster = 0;
1659 EXPORT_SYMBOL(pci_disable_device);
1662 * pcibios_set_pcie_reset_state - set reset state for device dev
1663 * @dev: the PCIe device reset
1664 * @state: Reset state to enter into
1667 * Sets the PCIe reset state for the device. This is the default
1668 * implementation. Architecture implementations can override this.
1670 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1671 enum pcie_reset_state state)
1677 * pci_set_pcie_reset_state - set reset state for device dev
1678 * @dev: the PCIe device reset
1679 * @state: Reset state to enter into
1682 * Sets the PCI reset state for the device.
1684 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1686 return pcibios_set_pcie_reset_state(dev, state);
1688 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1691 * pci_check_pme_status - Check if given device has generated PME.
1692 * @dev: Device to check.
1694 * Check the PME status of the device and if set, clear it and clear PME enable
1695 * (if set). Return 'true' if PME status and PME enable were both set or
1696 * 'false' otherwise.
1698 bool pci_check_pme_status(struct pci_dev *dev)
1707 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1708 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1709 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1712 /* Clear PME status. */
1713 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1714 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1715 /* Disable PME to avoid interrupt flood. */
1716 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1720 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1726 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1727 * @dev: Device to handle.
1728 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1730 * Check if @dev has generated PME and queue a resume request for it in that
1733 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1735 if (pme_poll_reset && dev->pme_poll)
1736 dev->pme_poll = false;
1738 if (pci_check_pme_status(dev)) {
1739 pci_wakeup_event(dev);
1740 pm_request_resume(&dev->dev);
1746 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1747 * @bus: Top bus of the subtree to walk.
1749 void pci_pme_wakeup_bus(struct pci_bus *bus)
1752 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1757 * pci_pme_capable - check the capability of PCI device to generate PME#
1758 * @dev: PCI device to handle.
1759 * @state: PCI state from which device will issue PME#.
1761 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1766 return !!(dev->pme_support & (1 << state));
1768 EXPORT_SYMBOL(pci_pme_capable);
1770 static void pci_pme_list_scan(struct work_struct *work)
1772 struct pci_pme_device *pme_dev, *n;
1774 mutex_lock(&pci_pme_list_mutex);
1775 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1776 if (pme_dev->dev->pme_poll) {
1777 struct pci_dev *bridge;
1779 bridge = pme_dev->dev->bus->self;
1781 * If bridge is in low power state, the
1782 * configuration space of subordinate devices
1783 * may be not accessible
1785 if (bridge && bridge->current_state != PCI_D0)
1787 pci_pme_wakeup(pme_dev->dev, NULL);
1789 list_del(&pme_dev->list);
1793 if (!list_empty(&pci_pme_list))
1794 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1795 msecs_to_jiffies(PME_TIMEOUT));
1796 mutex_unlock(&pci_pme_list_mutex);
1799 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1803 if (!dev->pme_support)
1806 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1807 /* Clear PME_Status by writing 1 to it and enable PME# */
1808 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1810 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1812 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1816 * pci_pme_restore - Restore PME configuration after config space restore.
1817 * @dev: PCI device to update.
1819 void pci_pme_restore(struct pci_dev *dev)
1823 if (!dev->pme_support)
1826 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1827 if (dev->wakeup_prepared) {
1828 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
1829 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
1831 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1832 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1834 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1838 * pci_pme_active - enable or disable PCI device's PME# function
1839 * @dev: PCI device to handle.
1840 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1842 * The caller must verify that the device is capable of generating PME# before
1843 * calling this function with @enable equal to 'true'.
1845 void pci_pme_active(struct pci_dev *dev, bool enable)
1847 __pci_pme_active(dev, enable);
1850 * PCI (as opposed to PCIe) PME requires that the device have
1851 * its PME# line hooked up correctly. Not all hardware vendors
1852 * do this, so the PME never gets delivered and the device
1853 * remains asleep. The easiest way around this is to
1854 * periodically walk the list of suspended devices and check
1855 * whether any have their PME flag set. The assumption is that
1856 * we'll wake up often enough anyway that this won't be a huge
1857 * hit, and the power savings from the devices will still be a
1860 * Although PCIe uses in-band PME message instead of PME# line
1861 * to report PME, PME does not work for some PCIe devices in
1862 * reality. For example, there are devices that set their PME
1863 * status bits, but don't really bother to send a PME message;
1864 * there are PCI Express Root Ports that don't bother to
1865 * trigger interrupts when they receive PME messages from the
1866 * devices below. So PME poll is used for PCIe devices too.
1869 if (dev->pme_poll) {
1870 struct pci_pme_device *pme_dev;
1872 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1875 dev_warn(&dev->dev, "can't enable PME#\n");
1879 mutex_lock(&pci_pme_list_mutex);
1880 list_add(&pme_dev->list, &pci_pme_list);
1881 if (list_is_singular(&pci_pme_list))
1882 queue_delayed_work(system_freezable_wq,
1884 msecs_to_jiffies(PME_TIMEOUT));
1885 mutex_unlock(&pci_pme_list_mutex);
1887 mutex_lock(&pci_pme_list_mutex);
1888 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1889 if (pme_dev->dev == dev) {
1890 list_del(&pme_dev->list);
1895 mutex_unlock(&pci_pme_list_mutex);
1899 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1901 EXPORT_SYMBOL(pci_pme_active);
1904 * pci_enable_wake - enable PCI device as wakeup event source
1905 * @dev: PCI device affected
1906 * @state: PCI state from which device will issue wakeup events
1907 * @enable: True to enable event generation; false to disable
1909 * This enables the device as a wakeup event source, or disables it.
1910 * When such events involves platform-specific hooks, those hooks are
1911 * called automatically by this routine.
1913 * Devices with legacy power management (no standard PCI PM capabilities)
1914 * always require such platform hooks.
1917 * 0 is returned on success
1918 * -EINVAL is returned if device is not supposed to wake up the system
1919 * Error code depending on the platform is returned if both the platform and
1920 * the native mechanism fail to enable the generation of wake-up events
1922 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1926 /* Don't do the same thing twice in a row for one device. */
1927 if (!!enable == !!dev->wakeup_prepared)
1931 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1932 * Anderson we should be doing PME# wake enable followed by ACPI wake
1933 * enable. To disable wake-up we call the platform first, for symmetry.
1939 if (pci_pme_capable(dev, state))
1940 pci_pme_active(dev, true);
1943 error = platform_pci_set_wakeup(dev, true);
1947 dev->wakeup_prepared = true;
1949 platform_pci_set_wakeup(dev, false);
1950 pci_pme_active(dev, false);
1951 dev->wakeup_prepared = false;
1956 EXPORT_SYMBOL(pci_enable_wake);
1959 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1960 * @dev: PCI device to prepare
1961 * @enable: True to enable wake-up event generation; false to disable
1963 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1964 * and this function allows them to set that up cleanly - pci_enable_wake()
1965 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1966 * ordering constraints.
1968 * This function only returns error code if the device is not capable of
1969 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1970 * enable wake-up power for it.
1972 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1974 return pci_pme_capable(dev, PCI_D3cold) ?
1975 pci_enable_wake(dev, PCI_D3cold, enable) :
1976 pci_enable_wake(dev, PCI_D3hot, enable);
1978 EXPORT_SYMBOL(pci_wake_from_d3);
1981 * pci_target_state - find an appropriate low power state for a given PCI dev
1983 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
1985 * Use underlying platform code to find a supported low power state for @dev.
1986 * If the platform can't manage @dev, return the deepest state from which it
1987 * can generate wake events, based on any available PME info.
1989 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
1991 pci_power_t target_state = PCI_D3hot;
1993 if (platform_pci_power_manageable(dev)) {
1995 * Call the platform to choose the target state of the device
1996 * and enable wake-up from this state if supported.
1998 pci_power_t state = platform_pci_choose_state(dev);
2001 case PCI_POWER_ERROR:
2006 if (pci_no_d1d2(dev))
2009 target_state = state;
2012 return target_state;
2016 target_state = PCI_D0;
2019 * If the device is in D3cold even though it's not power-manageable by
2020 * the platform, it may have been powered down by non-standard means.
2021 * Best to let it slumber.
2023 if (dev->current_state == PCI_D3cold)
2024 target_state = PCI_D3cold;
2028 * Find the deepest state from which the device can generate
2029 * wake-up events, make it the target state and enable device
2032 if (dev->pme_support) {
2034 && !(dev->pme_support & (1 << target_state)))
2039 return target_state;
2043 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2044 * @dev: Device to handle.
2046 * Choose the power state appropriate for the device depending on whether
2047 * it can wake up the system and/or is power manageable by the platform
2048 * (PCI_D3hot is the default) and put the device into that state.
2050 int pci_prepare_to_sleep(struct pci_dev *dev)
2052 bool wakeup = device_may_wakeup(&dev->dev);
2053 pci_power_t target_state = pci_target_state(dev, wakeup);
2056 if (target_state == PCI_POWER_ERROR)
2059 pci_enable_wake(dev, target_state, wakeup);
2061 error = pci_set_power_state(dev, target_state);
2064 pci_enable_wake(dev, target_state, false);
2068 EXPORT_SYMBOL(pci_prepare_to_sleep);
2071 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2072 * @dev: Device to handle.
2074 * Disable device's system wake-up capability and put it into D0.
2076 int pci_back_from_sleep(struct pci_dev *dev)
2078 pci_enable_wake(dev, PCI_D0, false);
2079 return pci_set_power_state(dev, PCI_D0);
2081 EXPORT_SYMBOL(pci_back_from_sleep);
2084 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2085 * @dev: PCI device being suspended.
2087 * Prepare @dev to generate wake-up events at run time and put it into a low
2090 int pci_finish_runtime_suspend(struct pci_dev *dev)
2092 pci_power_t target_state;
2095 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2096 if (target_state == PCI_POWER_ERROR)
2099 dev->runtime_d3cold = target_state == PCI_D3cold;
2101 pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2103 error = pci_set_power_state(dev, target_state);
2106 pci_enable_wake(dev, target_state, false);
2107 dev->runtime_d3cold = false;
2114 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2115 * @dev: Device to check.
2117 * Return true if the device itself is capable of generating wake-up events
2118 * (through the platform or using the native PCIe PME) or if the device supports
2119 * PME and one of its upstream bridges can generate wake-up events.
2121 bool pci_dev_run_wake(struct pci_dev *dev)
2123 struct pci_bus *bus = dev->bus;
2125 if (device_can_wakeup(&dev->dev))
2128 if (!dev->pme_support)
2131 /* PME-capable in principle, but not from the target power state */
2132 if (!pci_pme_capable(dev, pci_target_state(dev, false)))
2135 while (bus->parent) {
2136 struct pci_dev *bridge = bus->self;
2138 if (device_can_wakeup(&bridge->dev))
2144 /* We have reached the root bus. */
2146 return device_can_wakeup(bus->bridge);
2150 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2153 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2154 * @pci_dev: Device to check.
2156 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2157 * reconfigured due to wakeup settings difference between system and runtime
2158 * suspend and the current power state of it is suitable for the upcoming
2159 * (system) transition.
2161 * If the device is not configured for system wakeup, disable PME for it before
2162 * returning 'true' to prevent it from waking up the system unnecessarily.
2164 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2166 struct device *dev = &pci_dev->dev;
2167 bool wakeup = device_may_wakeup(dev);
2169 if (!pm_runtime_suspended(dev)
2170 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2171 || platform_pci_need_resume(pci_dev)
2172 || (pci_dev->dev_flags & PCI_DEV_FLAGS_NEEDS_RESUME))
2176 * At this point the device is good to go unless it's been configured
2177 * to generate PME at the runtime suspend time, but it is not supposed
2178 * to wake up the system. In that case, simply disable PME for it
2179 * (it will have to be re-enabled on exit from system resume).
2181 * If the device's power state is D3cold and the platform check above
2182 * hasn't triggered, the device's configuration is suitable and we don't
2183 * need to manipulate it at all.
2185 spin_lock_irq(&dev->power.lock);
2187 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2189 __pci_pme_active(pci_dev, false);
2191 spin_unlock_irq(&dev->power.lock);
2196 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2197 * @pci_dev: Device to handle.
2199 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2200 * it might have been disabled during the prepare phase of system suspend if
2201 * the device was not configured for system wakeup.
2203 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2205 struct device *dev = &pci_dev->dev;
2207 if (!pci_dev_run_wake(pci_dev))
2210 spin_lock_irq(&dev->power.lock);
2212 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2213 __pci_pme_active(pci_dev, true);
2215 spin_unlock_irq(&dev->power.lock);
2218 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2220 struct device *dev = &pdev->dev;
2221 struct device *parent = dev->parent;
2224 pm_runtime_get_sync(parent);
2225 pm_runtime_get_noresume(dev);
2227 * pdev->current_state is set to PCI_D3cold during suspending,
2228 * so wait until suspending completes
2230 pm_runtime_barrier(dev);
2232 * Only need to resume devices in D3cold, because config
2233 * registers are still accessible for devices suspended but
2236 if (pdev->current_state == PCI_D3cold)
2237 pm_runtime_resume(dev);
2240 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2242 struct device *dev = &pdev->dev;
2243 struct device *parent = dev->parent;
2245 pm_runtime_put(dev);
2247 pm_runtime_put_sync(parent);
2251 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2252 * @bridge: Bridge to check
2254 * This function checks if it is possible to move the bridge to D3.
2255 * Currently we only allow D3 for recent enough PCIe ports.
2257 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2261 if (!pci_is_pcie(bridge))
2264 switch (pci_pcie_type(bridge)) {
2265 case PCI_EXP_TYPE_ROOT_PORT:
2266 case PCI_EXP_TYPE_UPSTREAM:
2267 case PCI_EXP_TYPE_DOWNSTREAM:
2268 if (pci_bridge_d3_disable)
2272 * Hotplug interrupts cannot be delivered if the link is down,
2273 * so parents of a hotplug port must stay awake. In addition,
2274 * hotplug ports handled by firmware in System Management Mode
2275 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2276 * For simplicity, disallow in general for now.
2278 if (bridge->is_hotplug_bridge)
2281 if (pci_bridge_d3_force)
2285 * It should be safe to put PCIe ports from 2015 or newer
2288 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2298 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2300 bool *d3cold_ok = data;
2302 if (/* The device needs to be allowed to go D3cold ... */
2303 dev->no_d3cold || !dev->d3cold_allowed ||
2305 /* ... and if it is wakeup capable to do so from D3cold. */
2306 (device_may_wakeup(&dev->dev) &&
2307 !pci_pme_capable(dev, PCI_D3cold)) ||
2309 /* If it is a bridge it must be allowed to go to D3. */
2310 !pci_power_manageable(dev))
2318 * pci_bridge_d3_update - Update bridge D3 capabilities
2319 * @dev: PCI device which is changed
2321 * Update upstream bridge PM capabilities accordingly depending on if the
2322 * device PM configuration was changed or the device is being removed. The
2323 * change is also propagated upstream.
2325 void pci_bridge_d3_update(struct pci_dev *dev)
2327 bool remove = !device_is_registered(&dev->dev);
2328 struct pci_dev *bridge;
2329 bool d3cold_ok = true;
2331 bridge = pci_upstream_bridge(dev);
2332 if (!bridge || !pci_bridge_d3_possible(bridge))
2336 * If D3 is currently allowed for the bridge, removing one of its
2337 * children won't change that.
2339 if (remove && bridge->bridge_d3)
2343 * If D3 is currently allowed for the bridge and a child is added or
2344 * changed, disallowance of D3 can only be caused by that child, so
2345 * we only need to check that single device, not any of its siblings.
2347 * If D3 is currently not allowed for the bridge, checking the device
2348 * first may allow us to skip checking its siblings.
2351 pci_dev_check_d3cold(dev, &d3cold_ok);
2354 * If D3 is currently not allowed for the bridge, this may be caused
2355 * either by the device being changed/removed or any of its siblings,
2356 * so we need to go through all children to find out if one of them
2357 * continues to block D3.
2359 if (d3cold_ok && !bridge->bridge_d3)
2360 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2363 if (bridge->bridge_d3 != d3cold_ok) {
2364 bridge->bridge_d3 = d3cold_ok;
2365 /* Propagate change to upstream bridges */
2366 pci_bridge_d3_update(bridge);
2371 * pci_d3cold_enable - Enable D3cold for device
2372 * @dev: PCI device to handle
2374 * This function can be used in drivers to enable D3cold from the device
2375 * they handle. It also updates upstream PCI bridge PM capabilities
2378 void pci_d3cold_enable(struct pci_dev *dev)
2380 if (dev->no_d3cold) {
2381 dev->no_d3cold = false;
2382 pci_bridge_d3_update(dev);
2385 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2388 * pci_d3cold_disable - Disable D3cold for device
2389 * @dev: PCI device to handle
2391 * This function can be used in drivers to disable D3cold from the device
2392 * they handle. It also updates upstream PCI bridge PM capabilities
2395 void pci_d3cold_disable(struct pci_dev *dev)
2397 if (!dev->no_d3cold) {
2398 dev->no_d3cold = true;
2399 pci_bridge_d3_update(dev);
2402 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2405 * pci_pm_init - Initialize PM functions of given PCI device
2406 * @dev: PCI device to handle.
2408 void pci_pm_init(struct pci_dev *dev)
2413 pm_runtime_forbid(&dev->dev);
2414 pm_runtime_set_active(&dev->dev);
2415 pm_runtime_enable(&dev->dev);
2416 device_enable_async_suspend(&dev->dev);
2417 dev->wakeup_prepared = false;
2420 dev->pme_support = 0;
2422 /* find PCI PM capability in list */
2423 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2426 /* Check device's ability to generate PME# */
2427 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2429 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2430 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2431 pmc & PCI_PM_CAP_VER_MASK);
2436 dev->d3_delay = PCI_PM_D3_WAIT;
2437 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2438 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2439 dev->d3cold_allowed = true;
2441 dev->d1_support = false;
2442 dev->d2_support = false;
2443 if (!pci_no_d1d2(dev)) {
2444 if (pmc & PCI_PM_CAP_D1)
2445 dev->d1_support = true;
2446 if (pmc & PCI_PM_CAP_D2)
2447 dev->d2_support = true;
2449 if (dev->d1_support || dev->d2_support)
2450 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2451 dev->d1_support ? " D1" : "",
2452 dev->d2_support ? " D2" : "");
2455 pmc &= PCI_PM_CAP_PME_MASK;
2457 dev_printk(KERN_DEBUG, &dev->dev,
2458 "PME# supported from%s%s%s%s%s\n",
2459 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2460 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2461 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2462 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2463 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2464 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2465 dev->pme_poll = true;
2467 * Make device's PM flags reflect the wake-up capability, but
2468 * let the user space enable it to wake up the system as needed.
2470 device_set_wakeup_capable(&dev->dev, true);
2471 /* Disable the PME# generation functionality */
2472 pci_pme_active(dev, false);
2476 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2478 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2482 case PCI_EA_P_VF_MEM:
2483 flags |= IORESOURCE_MEM;
2485 case PCI_EA_P_MEM_PREFETCH:
2486 case PCI_EA_P_VF_MEM_PREFETCH:
2487 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2490 flags |= IORESOURCE_IO;
2499 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2502 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2503 return &dev->resource[bei];
2504 #ifdef CONFIG_PCI_IOV
2505 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2506 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2507 return &dev->resource[PCI_IOV_RESOURCES +
2508 bei - PCI_EA_BEI_VF_BAR0];
2510 else if (bei == PCI_EA_BEI_ROM)
2511 return &dev->resource[PCI_ROM_RESOURCE];
2516 /* Read an Enhanced Allocation (EA) entry */
2517 static int pci_ea_read(struct pci_dev *dev, int offset)
2519 struct resource *res;
2520 int ent_size, ent_offset = offset;
2521 resource_size_t start, end;
2522 unsigned long flags;
2523 u32 dw0, bei, base, max_offset;
2525 bool support_64 = (sizeof(resource_size_t) >= 8);
2527 pci_read_config_dword(dev, ent_offset, &dw0);
2530 /* Entry size field indicates DWORDs after 1st */
2531 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2533 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2536 bei = (dw0 & PCI_EA_BEI) >> 4;
2537 prop = (dw0 & PCI_EA_PP) >> 8;
2540 * If the Property is in the reserved range, try the Secondary
2543 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2544 prop = (dw0 & PCI_EA_SP) >> 16;
2545 if (prop > PCI_EA_P_BRIDGE_IO)
2548 res = pci_ea_get_resource(dev, bei, prop);
2550 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2554 flags = pci_ea_flags(dev, prop);
2556 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2561 pci_read_config_dword(dev, ent_offset, &base);
2562 start = (base & PCI_EA_FIELD_MASK);
2565 /* Read MaxOffset */
2566 pci_read_config_dword(dev, ent_offset, &max_offset);
2569 /* Read Base MSBs (if 64-bit entry) */
2570 if (base & PCI_EA_IS_64) {
2573 pci_read_config_dword(dev, ent_offset, &base_upper);
2576 flags |= IORESOURCE_MEM_64;
2578 /* entry starts above 32-bit boundary, can't use */
2579 if (!support_64 && base_upper)
2583 start |= ((u64)base_upper << 32);
2586 end = start + (max_offset | 0x03);
2588 /* Read MaxOffset MSBs (if 64-bit entry) */
2589 if (max_offset & PCI_EA_IS_64) {
2590 u32 max_offset_upper;
2592 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2595 flags |= IORESOURCE_MEM_64;
2597 /* entry too big, can't use */
2598 if (!support_64 && max_offset_upper)
2602 end += ((u64)max_offset_upper << 32);
2606 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2610 if (ent_size != ent_offset - offset) {
2612 "EA Entry Size (%d) does not match length read (%d)\n",
2613 ent_size, ent_offset - offset);
2617 res->name = pci_name(dev);
2622 if (bei <= PCI_EA_BEI_BAR5)
2623 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2625 else if (bei == PCI_EA_BEI_ROM)
2626 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2628 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2629 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2630 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2632 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2636 return offset + ent_size;
2639 /* Enhanced Allocation Initialization */
2640 void pci_ea_init(struct pci_dev *dev)
2647 /* find PCI EA capability in list */
2648 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2652 /* determine the number of entries */
2653 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2655 num_ent &= PCI_EA_NUM_ENT_MASK;
2657 offset = ea + PCI_EA_FIRST_ENT;
2659 /* Skip DWORD 2 for type 1 functions */
2660 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2663 /* parse each EA entry */
2664 for (i = 0; i < num_ent; ++i)
2665 offset = pci_ea_read(dev, offset);
2668 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2669 struct pci_cap_saved_state *new_cap)
2671 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2675 * _pci_add_cap_save_buffer - allocate buffer for saving given
2676 * capability registers
2677 * @dev: the PCI device
2678 * @cap: the capability to allocate the buffer for
2679 * @extended: Standard or Extended capability ID
2680 * @size: requested size of the buffer
2682 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2683 bool extended, unsigned int size)
2686 struct pci_cap_saved_state *save_state;
2689 pos = pci_find_ext_capability(dev, cap);
2691 pos = pci_find_capability(dev, cap);
2696 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2700 save_state->cap.cap_nr = cap;
2701 save_state->cap.cap_extended = extended;
2702 save_state->cap.size = size;
2703 pci_add_saved_cap(dev, save_state);
2708 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2710 return _pci_add_cap_save_buffer(dev, cap, false, size);
2713 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2715 return _pci_add_cap_save_buffer(dev, cap, true, size);
2719 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2720 * @dev: the PCI device
2722 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2726 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2727 PCI_EXP_SAVE_REGS * sizeof(u16));
2730 "unable to preallocate PCI Express save buffer\n");
2732 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2735 "unable to preallocate PCI-X save buffer\n");
2737 pci_allocate_vc_save_buffers(dev);
2740 void pci_free_cap_save_buffers(struct pci_dev *dev)
2742 struct pci_cap_saved_state *tmp;
2743 struct hlist_node *n;
2745 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2750 * pci_configure_ari - enable or disable ARI forwarding
2751 * @dev: the PCI device
2753 * If @dev and its upstream bridge both support ARI, enable ARI in the
2754 * bridge. Otherwise, disable ARI in the bridge.
2756 void pci_configure_ari(struct pci_dev *dev)
2759 struct pci_dev *bridge;
2761 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2764 bridge = dev->bus->self;
2768 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2769 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2772 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2773 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2774 PCI_EXP_DEVCTL2_ARI);
2775 bridge->ari_enabled = 1;
2777 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2778 PCI_EXP_DEVCTL2_ARI);
2779 bridge->ari_enabled = 0;
2783 static int pci_acs_enable;
2786 * pci_request_acs - ask for ACS to be enabled if supported
2788 void pci_request_acs(void)
2794 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2795 * @dev: the PCI device
2797 static void pci_std_enable_acs(struct pci_dev *dev)
2803 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2807 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2808 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2810 /* Source Validation */
2811 ctrl |= (cap & PCI_ACS_SV);
2813 /* P2P Request Redirect */
2814 ctrl |= (cap & PCI_ACS_RR);
2816 /* P2P Completion Redirect */
2817 ctrl |= (cap & PCI_ACS_CR);
2819 /* Upstream Forwarding */
2820 ctrl |= (cap & PCI_ACS_UF);
2822 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2826 * pci_enable_acs - enable ACS if hardware support it
2827 * @dev: the PCI device
2829 void pci_enable_acs(struct pci_dev *dev)
2831 if (!pci_acs_enable)
2834 if (!pci_dev_specific_enable_acs(dev))
2837 pci_std_enable_acs(dev);
2840 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2845 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2850 * Except for egress control, capabilities are either required
2851 * or only required if controllable. Features missing from the
2852 * capability field can therefore be assumed as hard-wired enabled.
2854 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2855 acs_flags &= (cap | PCI_ACS_EC);
2857 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2858 return (ctrl & acs_flags) == acs_flags;
2862 * pci_acs_enabled - test ACS against required flags for a given device
2863 * @pdev: device to test
2864 * @acs_flags: required PCI ACS flags
2866 * Return true if the device supports the provided flags. Automatically
2867 * filters out flags that are not implemented on multifunction devices.
2869 * Note that this interface checks the effective ACS capabilities of the
2870 * device rather than the actual capabilities. For instance, most single
2871 * function endpoints are not required to support ACS because they have no
2872 * opportunity for peer-to-peer access. We therefore return 'true'
2873 * regardless of whether the device exposes an ACS capability. This makes
2874 * it much easier for callers of this function to ignore the actual type
2875 * or topology of the device when testing ACS support.
2877 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2881 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2886 * Conventional PCI and PCI-X devices never support ACS, either
2887 * effectively or actually. The shared bus topology implies that
2888 * any device on the bus can receive or snoop DMA.
2890 if (!pci_is_pcie(pdev))
2893 switch (pci_pcie_type(pdev)) {
2895 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2896 * but since their primary interface is PCI/X, we conservatively
2897 * handle them as we would a non-PCIe device.
2899 case PCI_EXP_TYPE_PCIE_BRIDGE:
2901 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2902 * applicable... must never implement an ACS Extended Capability...".
2903 * This seems arbitrary, but we take a conservative interpretation
2904 * of this statement.
2906 case PCI_EXP_TYPE_PCI_BRIDGE:
2907 case PCI_EXP_TYPE_RC_EC:
2910 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2911 * implement ACS in order to indicate their peer-to-peer capabilities,
2912 * regardless of whether they are single- or multi-function devices.
2914 case PCI_EXP_TYPE_DOWNSTREAM:
2915 case PCI_EXP_TYPE_ROOT_PORT:
2916 return pci_acs_flags_enabled(pdev, acs_flags);
2918 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2919 * implemented by the remaining PCIe types to indicate peer-to-peer
2920 * capabilities, but only when they are part of a multifunction
2921 * device. The footnote for section 6.12 indicates the specific
2922 * PCIe types included here.
2924 case PCI_EXP_TYPE_ENDPOINT:
2925 case PCI_EXP_TYPE_UPSTREAM:
2926 case PCI_EXP_TYPE_LEG_END:
2927 case PCI_EXP_TYPE_RC_END:
2928 if (!pdev->multifunction)
2931 return pci_acs_flags_enabled(pdev, acs_flags);
2935 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2936 * to single function devices with the exception of downstream ports.
2942 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2943 * @start: starting downstream device
2944 * @end: ending upstream device or NULL to search to the root bus
2945 * @acs_flags: required flags
2947 * Walk up a device tree from start to end testing PCI ACS support. If
2948 * any step along the way does not support the required flags, return false.
2950 bool pci_acs_path_enabled(struct pci_dev *start,
2951 struct pci_dev *end, u16 acs_flags)
2953 struct pci_dev *pdev, *parent = start;
2958 if (!pci_acs_enabled(pdev, acs_flags))
2961 if (pci_is_root_bus(pdev->bus))
2962 return (end == NULL);
2964 parent = pdev->bus->self;
2965 } while (pdev != end);
2971 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2972 * @dev: the PCI device
2973 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2975 * Perform INTx swizzling for a device behind one level of bridge. This is
2976 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2977 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2978 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2979 * the PCI Express Base Specification, Revision 2.1)
2981 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2985 if (pci_ari_enabled(dev->bus))
2988 slot = PCI_SLOT(dev->devfn);
2990 return (((pin - 1) + slot) % 4) + 1;
2993 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3001 while (!pci_is_root_bus(dev->bus)) {
3002 pin = pci_swizzle_interrupt_pin(dev, pin);
3003 dev = dev->bus->self;
3010 * pci_common_swizzle - swizzle INTx all the way to root bridge
3011 * @dev: the PCI device
3012 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3014 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3015 * bridges all the way up to a PCI root bus.
3017 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3021 while (!pci_is_root_bus(dev->bus)) {
3022 pin = pci_swizzle_interrupt_pin(dev, pin);
3023 dev = dev->bus->self;
3026 return PCI_SLOT(dev->devfn);
3028 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3031 * pci_release_region - Release a PCI bar
3032 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3033 * @bar: BAR to release
3035 * Releases the PCI I/O and memory resources previously reserved by a
3036 * successful call to pci_request_region. Call this function only
3037 * after all use of the PCI regions has ceased.
3039 void pci_release_region(struct pci_dev *pdev, int bar)
3041 struct pci_devres *dr;
3043 if (pci_resource_len(pdev, bar) == 0)
3045 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3046 release_region(pci_resource_start(pdev, bar),
3047 pci_resource_len(pdev, bar));
3048 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3049 release_mem_region(pci_resource_start(pdev, bar),
3050 pci_resource_len(pdev, bar));
3052 dr = find_pci_dr(pdev);
3054 dr->region_mask &= ~(1 << bar);
3056 EXPORT_SYMBOL(pci_release_region);
3059 * __pci_request_region - Reserved PCI I/O and memory resource
3060 * @pdev: PCI device whose resources are to be reserved
3061 * @bar: BAR to be reserved
3062 * @res_name: Name to be associated with resource.
3063 * @exclusive: whether the region access is exclusive or not
3065 * Mark the PCI region associated with PCI device @pdev BR @bar as
3066 * being reserved by owner @res_name. Do not access any
3067 * address inside the PCI regions unless this call returns
3070 * If @exclusive is set, then the region is marked so that userspace
3071 * is explicitly not allowed to map the resource via /dev/mem or
3072 * sysfs MMIO access.
3074 * Returns 0 on success, or %EBUSY on error. A warning
3075 * message is also printed on failure.
3077 static int __pci_request_region(struct pci_dev *pdev, int bar,
3078 const char *res_name, int exclusive)
3080 struct pci_devres *dr;
3082 if (pci_resource_len(pdev, bar) == 0)
3085 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3086 if (!request_region(pci_resource_start(pdev, bar),
3087 pci_resource_len(pdev, bar), res_name))
3089 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3090 if (!__request_mem_region(pci_resource_start(pdev, bar),
3091 pci_resource_len(pdev, bar), res_name,
3096 dr = find_pci_dr(pdev);
3098 dr->region_mask |= 1 << bar;
3103 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
3104 &pdev->resource[bar]);
3109 * pci_request_region - Reserve PCI I/O and memory resource
3110 * @pdev: PCI device whose resources are to be reserved
3111 * @bar: BAR to be reserved
3112 * @res_name: Name to be associated with resource
3114 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3115 * being reserved by owner @res_name. Do not access any
3116 * address inside the PCI regions unless this call returns
3119 * Returns 0 on success, or %EBUSY on error. A warning
3120 * message is also printed on failure.
3122 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3124 return __pci_request_region(pdev, bar, res_name, 0);
3126 EXPORT_SYMBOL(pci_request_region);
3129 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3130 * @pdev: PCI device whose resources are to be reserved
3131 * @bar: BAR to be reserved
3132 * @res_name: Name to be associated with resource.
3134 * Mark the PCI region associated with PCI device @pdev BR @bar as
3135 * being reserved by owner @res_name. Do not access any
3136 * address inside the PCI regions unless this call returns
3139 * Returns 0 on success, or %EBUSY on error. A warning
3140 * message is also printed on failure.
3142 * The key difference that _exclusive makes it that userspace is
3143 * explicitly not allowed to map the resource via /dev/mem or
3146 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3147 const char *res_name)
3149 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3151 EXPORT_SYMBOL(pci_request_region_exclusive);
3154 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3155 * @pdev: PCI device whose resources were previously reserved
3156 * @bars: Bitmask of BARs to be released
3158 * Release selected PCI I/O and memory resources previously reserved.
3159 * Call this function only after all use of the PCI regions has ceased.
3161 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3165 for (i = 0; i < 6; i++)
3166 if (bars & (1 << i))
3167 pci_release_region(pdev, i);
3169 EXPORT_SYMBOL(pci_release_selected_regions);
3171 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3172 const char *res_name, int excl)
3176 for (i = 0; i < 6; i++)
3177 if (bars & (1 << i))
3178 if (__pci_request_region(pdev, i, res_name, excl))
3184 if (bars & (1 << i))
3185 pci_release_region(pdev, i);
3192 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3193 * @pdev: PCI device whose resources are to be reserved
3194 * @bars: Bitmask of BARs to be requested
3195 * @res_name: Name to be associated with resource
3197 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3198 const char *res_name)
3200 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3202 EXPORT_SYMBOL(pci_request_selected_regions);
3204 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3205 const char *res_name)
3207 return __pci_request_selected_regions(pdev, bars, res_name,
3208 IORESOURCE_EXCLUSIVE);
3210 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3213 * pci_release_regions - Release reserved PCI I/O and memory resources
3214 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3216 * Releases all PCI I/O and memory resources previously reserved by a
3217 * successful call to pci_request_regions. Call this function only
3218 * after all use of the PCI regions has ceased.
3221 void pci_release_regions(struct pci_dev *pdev)
3223 pci_release_selected_regions(pdev, (1 << 6) - 1);
3225 EXPORT_SYMBOL(pci_release_regions);
3228 * pci_request_regions - Reserved PCI I/O and memory resources
3229 * @pdev: PCI device whose resources are to be reserved
3230 * @res_name: Name to be associated with resource.
3232 * Mark all PCI regions associated with PCI device @pdev as
3233 * being reserved by owner @res_name. Do not access any
3234 * address inside the PCI regions unless this call returns
3237 * Returns 0 on success, or %EBUSY on error. A warning
3238 * message is also printed on failure.
3240 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3242 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3244 EXPORT_SYMBOL(pci_request_regions);
3247 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3248 * @pdev: PCI device whose resources are to be reserved
3249 * @res_name: Name to be associated with resource.
3251 * Mark all PCI regions associated with PCI device @pdev as
3252 * being reserved by owner @res_name. Do not access any
3253 * address inside the PCI regions unless this call returns
3256 * pci_request_regions_exclusive() will mark the region so that
3257 * /dev/mem and the sysfs MMIO access will not be allowed.
3259 * Returns 0 on success, or %EBUSY on error. A warning
3260 * message is also printed on failure.
3262 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3264 return pci_request_selected_regions_exclusive(pdev,
3265 ((1 << 6) - 1), res_name);
3267 EXPORT_SYMBOL(pci_request_regions_exclusive);
3271 struct list_head list;
3273 resource_size_t size;
3276 static LIST_HEAD(io_range_list);
3277 static DEFINE_SPINLOCK(io_range_lock);
3281 * Record the PCI IO range (expressed as CPU physical address + size).
3282 * Return a negative value if an error has occured, zero otherwise
3284 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3289 struct io_range *range;
3290 resource_size_t allocated_size = 0;
3292 /* check if the range hasn't been previously recorded */
3293 spin_lock(&io_range_lock);
3294 list_for_each_entry(range, &io_range_list, list) {
3295 if (addr >= range->start && addr + size <= range->start + size) {
3296 /* range already registered, bail out */
3299 allocated_size += range->size;
3302 /* range not registed yet, check for available space */
3303 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3304 /* if it's too big check if 64K space can be reserved */
3305 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3311 pr_warn("Requested IO range too big, new size set to 64K\n");
3314 /* add the range to the list */
3315 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3321 range->start = addr;
3324 list_add_tail(&range->list, &io_range_list);
3327 spin_unlock(&io_range_lock);
3333 phys_addr_t pci_pio_to_address(unsigned long pio)
3335 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3338 struct io_range *range;
3339 resource_size_t allocated_size = 0;
3341 if (pio > IO_SPACE_LIMIT)
3344 spin_lock(&io_range_lock);
3345 list_for_each_entry(range, &io_range_list, list) {
3346 if (pio >= allocated_size && pio < allocated_size + range->size) {
3347 address = range->start + pio - allocated_size;
3350 allocated_size += range->size;
3352 spin_unlock(&io_range_lock);
3358 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3361 struct io_range *res;
3362 resource_size_t offset = 0;
3363 unsigned long addr = -1;
3365 spin_lock(&io_range_lock);
3366 list_for_each_entry(res, &io_range_list, list) {
3367 if (address >= res->start && address < res->start + res->size) {
3368 addr = address - res->start + offset;
3371 offset += res->size;
3373 spin_unlock(&io_range_lock);
3377 if (address > IO_SPACE_LIMIT)
3378 return (unsigned long)-1;
3380 return (unsigned long) address;
3385 * pci_remap_iospace - Remap the memory mapped I/O space
3386 * @res: Resource describing the I/O space
3387 * @phys_addr: physical address of range to be mapped
3389 * Remap the memory mapped I/O space described by the @res
3390 * and the CPU physical address @phys_addr into virtual address space.
3391 * Only architectures that have memory mapped IO functions defined
3392 * (and the PCI_IOBASE value defined) should call this function.
3394 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3396 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3397 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3399 if (!(res->flags & IORESOURCE_IO))
3402 if (res->end > IO_SPACE_LIMIT)
3405 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3406 pgprot_device(PAGE_KERNEL));
3408 /* this architecture does not have memory mapped I/O space,
3409 so this function should never be called */
3410 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3414 EXPORT_SYMBOL(pci_remap_iospace);
3417 * pci_unmap_iospace - Unmap the memory mapped I/O space
3418 * @res: resource to be unmapped
3420 * Unmap the CPU virtual address @res from virtual address space.
3421 * Only architectures that have memory mapped IO functions defined
3422 * (and the PCI_IOBASE value defined) should call this function.
3424 void pci_unmap_iospace(struct resource *res)
3426 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3427 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3429 unmap_kernel_range(vaddr, resource_size(res));
3432 EXPORT_SYMBOL(pci_unmap_iospace);
3435 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3436 * @dev: Generic device to remap IO address for
3437 * @offset: Resource address to map
3438 * @size: Size of map
3440 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3443 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3444 resource_size_t offset,
3445 resource_size_t size)
3447 void __iomem **ptr, *addr;
3449 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3453 addr = pci_remap_cfgspace(offset, size);
3456 devres_add(dev, ptr);
3462 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3465 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3466 * @dev: generic device to handle the resource for
3467 * @res: configuration space resource to be handled
3469 * Checks that a resource is a valid memory region, requests the memory
3470 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3471 * proper PCI configuration space memory attributes are guaranteed.
3473 * All operations are managed and will be undone on driver detach.
3475 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3476 * on failure. Usage example:
3478 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3479 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3481 * return PTR_ERR(base);
3483 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3484 struct resource *res)
3486 resource_size_t size;
3488 void __iomem *dest_ptr;
3492 if (!res || resource_type(res) != IORESOURCE_MEM) {
3493 dev_err(dev, "invalid resource\n");
3494 return IOMEM_ERR_PTR(-EINVAL);
3497 size = resource_size(res);
3498 name = res->name ?: dev_name(dev);
3500 if (!devm_request_mem_region(dev, res->start, size, name)) {
3501 dev_err(dev, "can't request region for resource %pR\n", res);
3502 return IOMEM_ERR_PTR(-EBUSY);
3505 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3507 dev_err(dev, "ioremap failed for resource %pR\n", res);
3508 devm_release_mem_region(dev, res->start, size);
3509 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3514 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3516 static void __pci_set_master(struct pci_dev *dev, bool enable)
3520 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3522 cmd = old_cmd | PCI_COMMAND_MASTER;
3524 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3525 if (cmd != old_cmd) {
3526 dev_dbg(&dev->dev, "%s bus mastering\n",
3527 enable ? "enabling" : "disabling");
3528 pci_write_config_word(dev, PCI_COMMAND, cmd);
3530 dev->is_busmaster = enable;
3534 * pcibios_setup - process "pci=" kernel boot arguments
3535 * @str: string used to pass in "pci=" kernel boot arguments
3537 * Process kernel boot arguments. This is the default implementation.
3538 * Architecture specific implementations can override this as necessary.
3540 char * __weak __init pcibios_setup(char *str)
3546 * pcibios_set_master - enable PCI bus-mastering for device dev
3547 * @dev: the PCI device to enable
3549 * Enables PCI bus-mastering for the device. This is the default
3550 * implementation. Architecture specific implementations can override
3551 * this if necessary.
3553 void __weak pcibios_set_master(struct pci_dev *dev)
3557 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3558 if (pci_is_pcie(dev))
3561 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3563 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3564 else if (lat > pcibios_max_latency)
3565 lat = pcibios_max_latency;
3569 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3573 * pci_set_master - enables bus-mastering for device dev
3574 * @dev: the PCI device to enable
3576 * Enables bus-mastering on the device and calls pcibios_set_master()
3577 * to do the needed arch specific settings.
3579 void pci_set_master(struct pci_dev *dev)
3581 __pci_set_master(dev, true);
3582 pcibios_set_master(dev);
3584 EXPORT_SYMBOL(pci_set_master);
3587 * pci_clear_master - disables bus-mastering for device dev
3588 * @dev: the PCI device to disable
3590 void pci_clear_master(struct pci_dev *dev)
3592 __pci_set_master(dev, false);
3594 EXPORT_SYMBOL(pci_clear_master);
3597 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3598 * @dev: the PCI device for which MWI is to be enabled
3600 * Helper function for pci_set_mwi.
3601 * Originally copied from drivers/net/acenic.c.
3604 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3606 int pci_set_cacheline_size(struct pci_dev *dev)
3610 if (!pci_cache_line_size)
3613 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3614 equal to or multiple of the right value. */
3615 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3616 if (cacheline_size >= pci_cache_line_size &&
3617 (cacheline_size % pci_cache_line_size) == 0)
3620 /* Write the correct value. */
3621 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3623 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3624 if (cacheline_size == pci_cache_line_size)
3627 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3628 pci_cache_line_size << 2);
3632 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3635 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3636 * @dev: the PCI device for which MWI is enabled
3638 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3640 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3642 int pci_set_mwi(struct pci_dev *dev)
3644 #ifdef PCI_DISABLE_MWI
3650 rc = pci_set_cacheline_size(dev);
3654 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3655 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3656 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3657 cmd |= PCI_COMMAND_INVALIDATE;
3658 pci_write_config_word(dev, PCI_COMMAND, cmd);
3663 EXPORT_SYMBOL(pci_set_mwi);
3666 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3667 * @dev: the PCI device for which MWI is enabled
3669 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3670 * Callers are not required to check the return value.
3672 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3674 int pci_try_set_mwi(struct pci_dev *dev)
3676 #ifdef PCI_DISABLE_MWI
3679 return pci_set_mwi(dev);
3682 EXPORT_SYMBOL(pci_try_set_mwi);
3685 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3686 * @dev: the PCI device to disable
3688 * Disables PCI Memory-Write-Invalidate transaction on the device
3690 void pci_clear_mwi(struct pci_dev *dev)
3692 #ifndef PCI_DISABLE_MWI
3695 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3696 if (cmd & PCI_COMMAND_INVALIDATE) {
3697 cmd &= ~PCI_COMMAND_INVALIDATE;
3698 pci_write_config_word(dev, PCI_COMMAND, cmd);
3702 EXPORT_SYMBOL(pci_clear_mwi);
3705 * pci_intx - enables/disables PCI INTx for device dev
3706 * @pdev: the PCI device to operate on
3707 * @enable: boolean: whether to enable or disable PCI INTx
3709 * Enables/disables PCI INTx for device dev
3711 void pci_intx(struct pci_dev *pdev, int enable)
3713 u16 pci_command, new;
3715 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3718 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3720 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3722 if (new != pci_command) {
3723 struct pci_devres *dr;
3725 pci_write_config_word(pdev, PCI_COMMAND, new);
3727 dr = find_pci_dr(pdev);
3728 if (dr && !dr->restore_intx) {
3729 dr->restore_intx = 1;
3730 dr->orig_intx = !enable;
3734 EXPORT_SYMBOL_GPL(pci_intx);
3736 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3738 struct pci_bus *bus = dev->bus;
3739 bool mask_updated = true;
3740 u32 cmd_status_dword;
3741 u16 origcmd, newcmd;
3742 unsigned long flags;
3746 * We do a single dword read to retrieve both command and status.
3747 * Document assumptions that make this possible.
3749 BUILD_BUG_ON(PCI_COMMAND % 4);
3750 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3752 raw_spin_lock_irqsave(&pci_lock, flags);
3754 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3756 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3759 * Check interrupt status register to see whether our device
3760 * triggered the interrupt (when masking) or the next IRQ is
3761 * already pending (when unmasking).
3763 if (mask != irq_pending) {
3764 mask_updated = false;
3768 origcmd = cmd_status_dword;
3769 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3771 newcmd |= PCI_COMMAND_INTX_DISABLE;
3772 if (newcmd != origcmd)
3773 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3776 raw_spin_unlock_irqrestore(&pci_lock, flags);
3778 return mask_updated;
3782 * pci_check_and_mask_intx - mask INTx on pending interrupt
3783 * @dev: the PCI device to operate on
3785 * Check if the device dev has its INTx line asserted, mask it and
3786 * return true in that case. False is returned if no interrupt was
3789 bool pci_check_and_mask_intx(struct pci_dev *dev)
3791 return pci_check_and_set_intx_mask(dev, true);
3793 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3796 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3797 * @dev: the PCI device to operate on
3799 * Check if the device dev has its INTx line asserted, unmask it if not
3800 * and return true. False is returned and the mask remains active if
3801 * there was still an interrupt pending.
3803 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3805 return pci_check_and_set_intx_mask(dev, false);
3807 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3810 * pci_wait_for_pending_transaction - waits for pending transaction
3811 * @dev: the PCI device to operate on
3813 * Return 0 if transaction is pending 1 otherwise.
3815 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3817 if (!pci_is_pcie(dev))
3820 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3821 PCI_EXP_DEVSTA_TRPND);
3823 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3825 static void pci_flr_wait(struct pci_dev *dev)
3827 int delay = 1, timeout = 60000;
3831 * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
3832 * 100ms, but may silently discard requests while the FLR is in
3833 * progress. Wait 100ms before trying to access the device.
3838 * After 100ms, the device should not silently discard config
3839 * requests, but it may still indicate that it needs more time by
3840 * responding to them with CRS completions. The Root Port will
3841 * generally synthesize ~0 data to complete the read (except when
3842 * CRS SV is enabled and the read was for the Vendor ID; in that
3843 * case it synthesizes 0x0001 data).
3845 * Wait for the device to return a non-CRS completion. Read the
3846 * Command register instead of Vendor ID so we don't have to
3847 * contend with the CRS SV value.
3849 pci_read_config_dword(dev, PCI_COMMAND, &id);
3851 if (delay > timeout) {
3852 dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n",
3858 dev_info(&dev->dev, "not ready %dms after FLR; waiting\n",
3863 pci_read_config_dword(dev, PCI_COMMAND, &id);
3867 dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1);
3871 * pcie_has_flr - check if a device supports function level resets
3872 * @dev: device to check
3874 * Returns true if the device advertises support for PCIe function level
3877 static bool pcie_has_flr(struct pci_dev *dev)
3881 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
3884 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3885 return cap & PCI_EXP_DEVCAP_FLR;
3889 * pcie_flr - initiate a PCIe function level reset
3890 * @dev: device to reset
3892 * Initiate a function level reset on @dev. The caller should ensure the
3893 * device supports FLR before calling this function, e.g. by using the
3894 * pcie_has_flr() helper.
3896 void pcie_flr(struct pci_dev *dev)
3898 if (!pci_wait_for_pending_transaction(dev))
3899 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3901 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3904 EXPORT_SYMBOL_GPL(pcie_flr);
3906 static int pci_af_flr(struct pci_dev *dev, int probe)
3911 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3915 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
3918 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3919 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3926 * Wait for Transaction Pending bit to clear. A word-aligned test
3927 * is used, so we use the conrol offset rather than status and shift
3928 * the test bit to match.
3930 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3931 PCI_AF_STATUS_TP << 8))
3932 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3934 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3940 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3941 * @dev: Device to reset.
3942 * @probe: If set, only check if the device can be reset this way.
3944 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3945 * unset, it will be reinitialized internally when going from PCI_D3hot to
3946 * PCI_D0. If that's the case and the device is not in a low-power state
3947 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3949 * NOTE: This causes the caller to sleep for twice the device power transition
3950 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3951 * by default (i.e. unless the @dev's d3_delay field has a different value).
3952 * Moreover, only devices in D0 can be reset by this function.
3954 static int pci_pm_reset(struct pci_dev *dev, int probe)
3958 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3961 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3962 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3968 if (dev->current_state != PCI_D0)
3971 csr &= ~PCI_PM_CTRL_STATE_MASK;
3973 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3974 pci_dev_d3_sleep(dev);
3976 csr &= ~PCI_PM_CTRL_STATE_MASK;
3978 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3979 pci_dev_d3_sleep(dev);
3984 void pci_reset_secondary_bus(struct pci_dev *dev)
3988 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3989 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3990 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3992 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3993 * this to 2ms to ensure that we meet the minimum requirement.
3997 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3998 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4001 * Trhfa for conventional PCI is 2^25 clock cycles.
4002 * Assuming a minimum 33MHz clock this results in a 1s
4003 * delay before we can consider subordinate devices to
4004 * be re-initialized. PCIe has some ways to shorten this,
4005 * but we don't make use of them yet.
4010 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4012 pci_reset_secondary_bus(dev);
4016 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4017 * @dev: Bridge device
4019 * Use the bridge control register to assert reset on the secondary bus.
4020 * Devices on the secondary bus are left in power-on state.
4022 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
4024 pcibios_reset_secondary_bus(dev);
4026 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
4028 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4030 struct pci_dev *pdev;
4032 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4033 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4036 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4043 pci_reset_bridge_secondary_bus(dev->bus->self);
4048 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4052 if (!hotplug || !try_module_get(hotplug->ops->owner))
4055 if (hotplug->ops->reset_slot)
4056 rc = hotplug->ops->reset_slot(hotplug, probe);
4058 module_put(hotplug->ops->owner);
4063 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4065 struct pci_dev *pdev;
4067 if (dev->subordinate || !dev->slot ||
4068 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4071 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4072 if (pdev != dev && pdev->slot == dev->slot)
4075 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4078 static void pci_dev_lock(struct pci_dev *dev)
4080 pci_cfg_access_lock(dev);
4081 /* block PM suspend, driver probe, etc. */
4082 device_lock(&dev->dev);
4085 /* Return 1 on successful lock, 0 on contention */
4086 static int pci_dev_trylock(struct pci_dev *dev)
4088 if (pci_cfg_access_trylock(dev)) {
4089 if (device_trylock(&dev->dev))
4091 pci_cfg_access_unlock(dev);
4097 static void pci_dev_unlock(struct pci_dev *dev)
4099 device_unlock(&dev->dev);
4100 pci_cfg_access_unlock(dev);
4103 static void pci_dev_save_and_disable(struct pci_dev *dev)
4105 const struct pci_error_handlers *err_handler =
4106 dev->driver ? dev->driver->err_handler : NULL;
4109 * dev->driver->err_handler->reset_prepare() is protected against
4110 * races with ->remove() by the device lock, which must be held by
4113 if (err_handler && err_handler->reset_prepare)
4114 err_handler->reset_prepare(dev);
4117 * Wake-up device prior to save. PM registers default to D0 after
4118 * reset and a simple register restore doesn't reliably return
4119 * to a non-D0 state anyway.
4121 pci_set_power_state(dev, PCI_D0);
4123 pci_save_state(dev);
4125 * Disable the device by clearing the Command register, except for
4126 * INTx-disable which is set. This not only disables MMIO and I/O port
4127 * BARs, but also prevents the device from being Bus Master, preventing
4128 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4129 * compliant devices, INTx-disable prevents legacy interrupts.
4131 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4134 static void pci_dev_restore(struct pci_dev *dev)
4136 const struct pci_error_handlers *err_handler =
4137 dev->driver ? dev->driver->err_handler : NULL;
4139 pci_restore_state(dev);
4142 * dev->driver->err_handler->reset_done() is protected against
4143 * races with ->remove() by the device lock, which must be held by
4146 if (err_handler && err_handler->reset_done)
4147 err_handler->reset_done(dev);
4151 * __pci_reset_function - reset a PCI device function
4152 * @dev: PCI device to reset
4154 * Some devices allow an individual function to be reset without affecting
4155 * other functions in the same device. The PCI device must be responsive
4156 * to PCI config space in order to use this function.
4158 * The device function is presumed to be unused when this function is called.
4159 * Resetting the device will make the contents of PCI configuration space
4160 * random, so any caller of this must be prepared to reinitialise the
4161 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4164 * Returns 0 if the device function was successfully reset or negative if the
4165 * device doesn't support resetting a single function.
4167 int __pci_reset_function(struct pci_dev *dev)
4172 ret = __pci_reset_function_locked(dev);
4173 pci_dev_unlock(dev);
4177 EXPORT_SYMBOL_GPL(__pci_reset_function);
4180 * __pci_reset_function_locked - reset a PCI device function while holding
4181 * the @dev mutex lock.
4182 * @dev: PCI device to reset
4184 * Some devices allow an individual function to be reset without affecting
4185 * other functions in the same device. The PCI device must be responsive
4186 * to PCI config space in order to use this function.
4188 * The device function is presumed to be unused and the caller is holding
4189 * the device mutex lock when this function is called.
4190 * Resetting the device will make the contents of PCI configuration space
4191 * random, so any caller of this must be prepared to reinitialise the
4192 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4195 * Returns 0 if the device function was successfully reset or negative if the
4196 * device doesn't support resetting a single function.
4198 int __pci_reset_function_locked(struct pci_dev *dev)
4204 rc = pci_dev_specific_reset(dev, 0);
4207 if (pcie_has_flr(dev)) {
4211 rc = pci_af_flr(dev, 0);
4214 rc = pci_pm_reset(dev, 0);
4217 rc = pci_dev_reset_slot_function(dev, 0);
4220 return pci_parent_bus_reset(dev, 0);
4222 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4225 * pci_probe_reset_function - check whether the device can be safely reset
4226 * @dev: PCI device to reset
4228 * Some devices allow an individual function to be reset without affecting
4229 * other functions in the same device. The PCI device must be responsive
4230 * to PCI config space in order to use this function.
4232 * Returns 0 if the device function can be reset or negative if the
4233 * device doesn't support resetting a single function.
4235 int pci_probe_reset_function(struct pci_dev *dev)
4241 rc = pci_dev_specific_reset(dev, 1);
4244 if (pcie_has_flr(dev))
4246 rc = pci_af_flr(dev, 1);
4249 rc = pci_pm_reset(dev, 1);
4252 rc = pci_dev_reset_slot_function(dev, 1);
4256 return pci_parent_bus_reset(dev, 1);
4260 * pci_reset_function - quiesce and reset a PCI device function
4261 * @dev: PCI device to reset
4263 * Some devices allow an individual function to be reset without affecting
4264 * other functions in the same device. The PCI device must be responsive
4265 * to PCI config space in order to use this function.
4267 * This function does not just reset the PCI portion of a device, but
4268 * clears all the state associated with the device. This function differs
4269 * from __pci_reset_function in that it saves and restores device state
4272 * Returns 0 if the device function was successfully reset or negative if the
4273 * device doesn't support resetting a single function.
4275 int pci_reset_function(struct pci_dev *dev)
4279 rc = pci_probe_reset_function(dev);
4284 pci_dev_save_and_disable(dev);
4286 rc = __pci_reset_function_locked(dev);
4288 pci_dev_restore(dev);
4289 pci_dev_unlock(dev);
4293 EXPORT_SYMBOL_GPL(pci_reset_function);
4296 * pci_try_reset_function - quiesce and reset a PCI device function
4297 * @dev: PCI device to reset
4299 * Same as above, except return -EAGAIN if unable to lock device.
4301 int pci_try_reset_function(struct pci_dev *dev)
4305 rc = pci_probe_reset_function(dev);
4309 if (!pci_dev_trylock(dev))
4312 pci_dev_save_and_disable(dev);
4313 rc = __pci_reset_function_locked(dev);
4314 pci_dev_unlock(dev);
4316 pci_dev_restore(dev);
4319 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4321 /* Do any devices on or below this bus prevent a bus reset? */
4322 static bool pci_bus_resetable(struct pci_bus *bus)
4324 struct pci_dev *dev;
4326 list_for_each_entry(dev, &bus->devices, bus_list) {
4327 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4328 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4335 /* Lock devices from the top of the tree down */
4336 static void pci_bus_lock(struct pci_bus *bus)
4338 struct pci_dev *dev;
4340 list_for_each_entry(dev, &bus->devices, bus_list) {
4342 if (dev->subordinate)
4343 pci_bus_lock(dev->subordinate);
4347 /* Unlock devices from the bottom of the tree up */
4348 static void pci_bus_unlock(struct pci_bus *bus)
4350 struct pci_dev *dev;
4352 list_for_each_entry(dev, &bus->devices, bus_list) {
4353 if (dev->subordinate)
4354 pci_bus_unlock(dev->subordinate);
4355 pci_dev_unlock(dev);
4359 /* Return 1 on successful lock, 0 on contention */
4360 static int pci_bus_trylock(struct pci_bus *bus)
4362 struct pci_dev *dev;
4364 list_for_each_entry(dev, &bus->devices, bus_list) {
4365 if (!pci_dev_trylock(dev))
4367 if (dev->subordinate) {
4368 if (!pci_bus_trylock(dev->subordinate)) {
4369 pci_dev_unlock(dev);
4377 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4378 if (dev->subordinate)
4379 pci_bus_unlock(dev->subordinate);
4380 pci_dev_unlock(dev);
4385 /* Do any devices on or below this slot prevent a bus reset? */
4386 static bool pci_slot_resetable(struct pci_slot *slot)
4388 struct pci_dev *dev;
4390 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4391 if (!dev->slot || dev->slot != slot)
4393 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4394 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4401 /* Lock devices from the top of the tree down */
4402 static void pci_slot_lock(struct pci_slot *slot)
4404 struct pci_dev *dev;
4406 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4407 if (!dev->slot || dev->slot != slot)
4410 if (dev->subordinate)
4411 pci_bus_lock(dev->subordinate);
4415 /* Unlock devices from the bottom of the tree up */
4416 static void pci_slot_unlock(struct pci_slot *slot)
4418 struct pci_dev *dev;
4420 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4421 if (!dev->slot || dev->slot != slot)
4423 if (dev->subordinate)
4424 pci_bus_unlock(dev->subordinate);
4425 pci_dev_unlock(dev);
4429 /* Return 1 on successful lock, 0 on contention */
4430 static int pci_slot_trylock(struct pci_slot *slot)
4432 struct pci_dev *dev;
4434 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4435 if (!dev->slot || dev->slot != slot)
4437 if (!pci_dev_trylock(dev))
4439 if (dev->subordinate) {
4440 if (!pci_bus_trylock(dev->subordinate)) {
4441 pci_dev_unlock(dev);
4449 list_for_each_entry_continue_reverse(dev,
4450 &slot->bus->devices, bus_list) {
4451 if (!dev->slot || dev->slot != slot)
4453 if (dev->subordinate)
4454 pci_bus_unlock(dev->subordinate);
4455 pci_dev_unlock(dev);
4460 /* Save and disable devices from the top of the tree down */
4461 static void pci_bus_save_and_disable(struct pci_bus *bus)
4463 struct pci_dev *dev;
4465 list_for_each_entry(dev, &bus->devices, bus_list) {
4467 pci_dev_save_and_disable(dev);
4468 pci_dev_unlock(dev);
4469 if (dev->subordinate)
4470 pci_bus_save_and_disable(dev->subordinate);
4475 * Restore devices from top of the tree down - parent bridges need to be
4476 * restored before we can get to subordinate devices.
4478 static void pci_bus_restore(struct pci_bus *bus)
4480 struct pci_dev *dev;
4482 list_for_each_entry(dev, &bus->devices, bus_list) {
4484 pci_dev_restore(dev);
4485 pci_dev_unlock(dev);
4486 if (dev->subordinate)
4487 pci_bus_restore(dev->subordinate);
4491 /* Save and disable devices from the top of the tree down */
4492 static void pci_slot_save_and_disable(struct pci_slot *slot)
4494 struct pci_dev *dev;
4496 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4497 if (!dev->slot || dev->slot != slot)
4499 pci_dev_save_and_disable(dev);
4500 if (dev->subordinate)
4501 pci_bus_save_and_disable(dev->subordinate);
4506 * Restore devices from top of the tree down - parent bridges need to be
4507 * restored before we can get to subordinate devices.
4509 static void pci_slot_restore(struct pci_slot *slot)
4511 struct pci_dev *dev;
4513 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4514 if (!dev->slot || dev->slot != slot)
4516 pci_dev_restore(dev);
4517 if (dev->subordinate)
4518 pci_bus_restore(dev->subordinate);
4522 static int pci_slot_reset(struct pci_slot *slot, int probe)
4526 if (!slot || !pci_slot_resetable(slot))
4530 pci_slot_lock(slot);
4534 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4537 pci_slot_unlock(slot);
4543 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4544 * @slot: PCI slot to probe
4546 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4548 int pci_probe_reset_slot(struct pci_slot *slot)
4550 return pci_slot_reset(slot, 1);
4552 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4555 * pci_reset_slot - reset a PCI slot
4556 * @slot: PCI slot to reset
4558 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4559 * independent of other slots. For instance, some slots may support slot power
4560 * control. In the case of a 1:1 bus to slot architecture, this function may
4561 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4562 * Generally a slot reset should be attempted before a bus reset. All of the
4563 * function of the slot and any subordinate buses behind the slot are reset
4564 * through this function. PCI config space of all devices in the slot and
4565 * behind the slot is saved before and restored after reset.
4567 * Return 0 on success, non-zero on error.
4569 int pci_reset_slot(struct pci_slot *slot)
4573 rc = pci_slot_reset(slot, 1);
4577 pci_slot_save_and_disable(slot);
4579 rc = pci_slot_reset(slot, 0);
4581 pci_slot_restore(slot);
4585 EXPORT_SYMBOL_GPL(pci_reset_slot);
4588 * pci_try_reset_slot - Try to reset a PCI slot
4589 * @slot: PCI slot to reset
4591 * Same as above except return -EAGAIN if the slot cannot be locked
4593 int pci_try_reset_slot(struct pci_slot *slot)
4597 rc = pci_slot_reset(slot, 1);
4601 pci_slot_save_and_disable(slot);
4603 if (pci_slot_trylock(slot)) {
4605 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4606 pci_slot_unlock(slot);
4610 pci_slot_restore(slot);
4614 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4616 static int pci_bus_reset(struct pci_bus *bus, int probe)
4618 if (!bus->self || !pci_bus_resetable(bus))
4628 pci_reset_bridge_secondary_bus(bus->self);
4630 pci_bus_unlock(bus);
4636 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4637 * @bus: PCI bus to probe
4639 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4641 int pci_probe_reset_bus(struct pci_bus *bus)
4643 return pci_bus_reset(bus, 1);
4645 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4648 * pci_reset_bus - reset a PCI bus
4649 * @bus: top level PCI bus to reset
4651 * Do a bus reset on the given bus and any subordinate buses, saving
4652 * and restoring state of all devices.
4654 * Return 0 on success, non-zero on error.
4656 int pci_reset_bus(struct pci_bus *bus)
4660 rc = pci_bus_reset(bus, 1);
4664 pci_bus_save_and_disable(bus);
4666 rc = pci_bus_reset(bus, 0);
4668 pci_bus_restore(bus);
4672 EXPORT_SYMBOL_GPL(pci_reset_bus);
4675 * pci_try_reset_bus - Try to reset a PCI bus
4676 * @bus: top level PCI bus to reset
4678 * Same as above except return -EAGAIN if the bus cannot be locked
4680 int pci_try_reset_bus(struct pci_bus *bus)
4684 rc = pci_bus_reset(bus, 1);
4688 pci_bus_save_and_disable(bus);
4690 if (pci_bus_trylock(bus)) {
4692 pci_reset_bridge_secondary_bus(bus->self);
4693 pci_bus_unlock(bus);
4697 pci_bus_restore(bus);
4701 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4704 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4705 * @dev: PCI device to query
4707 * Returns mmrbc: maximum designed memory read count in bytes
4708 * or appropriate error value.
4710 int pcix_get_max_mmrbc(struct pci_dev *dev)
4715 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4719 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4722 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4724 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4727 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4728 * @dev: PCI device to query
4730 * Returns mmrbc: maximum memory read count in bytes
4731 * or appropriate error value.
4733 int pcix_get_mmrbc(struct pci_dev *dev)
4738 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4742 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4745 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4747 EXPORT_SYMBOL(pcix_get_mmrbc);
4750 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4751 * @dev: PCI device to query
4752 * @mmrbc: maximum memory read count in bytes
4753 * valid values are 512, 1024, 2048, 4096
4755 * If possible sets maximum memory read byte count, some bridges have erratas
4756 * that prevent this.
4758 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4764 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4767 v = ffs(mmrbc) - 10;
4769 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4773 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4776 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4779 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4782 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4784 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4787 cmd &= ~PCI_X_CMD_MAX_READ;
4789 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4794 EXPORT_SYMBOL(pcix_set_mmrbc);
4797 * pcie_get_readrq - get PCI Express read request size
4798 * @dev: PCI device to query
4800 * Returns maximum memory read request in bytes
4801 * or appropriate error value.
4803 int pcie_get_readrq(struct pci_dev *dev)
4807 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4809 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4811 EXPORT_SYMBOL(pcie_get_readrq);
4814 * pcie_set_readrq - set PCI Express maximum memory read request
4815 * @dev: PCI device to query
4816 * @rq: maximum memory read count in bytes
4817 * valid values are 128, 256, 512, 1024, 2048, 4096
4819 * If possible sets maximum memory read request in bytes
4821 int pcie_set_readrq(struct pci_dev *dev, int rq)
4825 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4829 * If using the "performance" PCIe config, we clamp the
4830 * read rq size to the max packet size to prevent the
4831 * host bridge generating requests larger than we can
4834 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4835 int mps = pcie_get_mps(dev);
4841 v = (ffs(rq) - 8) << 12;
4843 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4844 PCI_EXP_DEVCTL_READRQ, v);
4846 EXPORT_SYMBOL(pcie_set_readrq);
4849 * pcie_get_mps - get PCI Express maximum payload size
4850 * @dev: PCI device to query
4852 * Returns maximum payload size in bytes
4854 int pcie_get_mps(struct pci_dev *dev)
4858 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4860 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4862 EXPORT_SYMBOL(pcie_get_mps);
4865 * pcie_set_mps - set PCI Express maximum payload size
4866 * @dev: PCI device to query
4867 * @mps: maximum payload size in bytes
4868 * valid values are 128, 256, 512, 1024, 2048, 4096
4870 * If possible sets maximum payload size
4872 int pcie_set_mps(struct pci_dev *dev, int mps)
4876 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4880 if (v > dev->pcie_mpss)
4884 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4885 PCI_EXP_DEVCTL_PAYLOAD, v);
4887 EXPORT_SYMBOL(pcie_set_mps);
4890 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4891 * @dev: PCI device to query
4892 * @speed: storage for minimum speed
4893 * @width: storage for minimum width
4895 * This function will walk up the PCI device chain and determine the minimum
4896 * link width and speed of the device.
4898 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4899 enum pcie_link_width *width)
4903 *speed = PCI_SPEED_UNKNOWN;
4904 *width = PCIE_LNK_WIDTH_UNKNOWN;
4908 enum pci_bus_speed next_speed;
4909 enum pcie_link_width next_width;
4911 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4915 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4916 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4917 PCI_EXP_LNKSTA_NLW_SHIFT;
4919 if (next_speed < *speed)
4920 *speed = next_speed;
4922 if (next_width < *width)
4923 *width = next_width;
4925 dev = dev->bus->self;
4930 EXPORT_SYMBOL(pcie_get_minimum_link);
4933 * pci_select_bars - Make BAR mask from the type of resource
4934 * @dev: the PCI device for which BAR mask is made
4935 * @flags: resource type mask to be selected
4937 * This helper routine makes bar mask from the type of resource.
4939 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4942 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4943 if (pci_resource_flags(dev, i) & flags)
4947 EXPORT_SYMBOL(pci_select_bars);
4949 /* Some architectures require additional programming to enable VGA */
4950 static arch_set_vga_state_t arch_set_vga_state;
4952 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4954 arch_set_vga_state = func; /* NULL disables */
4957 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4958 unsigned int command_bits, u32 flags)
4960 if (arch_set_vga_state)
4961 return arch_set_vga_state(dev, decode, command_bits,
4967 * pci_set_vga_state - set VGA decode state on device and parents if requested
4968 * @dev: the PCI device
4969 * @decode: true = enable decoding, false = disable decoding
4970 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4971 * @flags: traverse ancestors and change bridges
4972 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4974 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4975 unsigned int command_bits, u32 flags)
4977 struct pci_bus *bus;
4978 struct pci_dev *bridge;
4982 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4984 /* ARCH specific VGA enables */
4985 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4989 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4990 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4992 cmd |= command_bits;
4994 cmd &= ~command_bits;
4995 pci_write_config_word(dev, PCI_COMMAND, cmd);
4998 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5005 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5008 cmd |= PCI_BRIDGE_CTL_VGA;
5010 cmd &= ~PCI_BRIDGE_CTL_VGA;
5011 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5020 * pci_add_dma_alias - Add a DMA devfn alias for a device
5021 * @dev: the PCI device for which alias is added
5022 * @devfn: alias slot and function
5024 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5025 * It should be called early, preferably as PCI fixup header quirk.
5027 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5029 if (!dev->dma_alias_mask)
5030 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5031 sizeof(long), GFP_KERNEL);
5032 if (!dev->dma_alias_mask) {
5033 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
5037 set_bit(devfn, dev->dma_alias_mask);
5038 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
5039 PCI_SLOT(devfn), PCI_FUNC(devfn));
5042 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5044 return (dev1->dma_alias_mask &&
5045 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5046 (dev2->dma_alias_mask &&
5047 test_bit(dev1->devfn, dev2->dma_alias_mask));
5050 bool pci_device_is_present(struct pci_dev *pdev)
5054 if (pci_dev_is_disconnected(pdev))
5056 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5058 EXPORT_SYMBOL_GPL(pci_device_is_present);
5060 void pci_ignore_hotplug(struct pci_dev *dev)
5062 struct pci_dev *bridge = dev->bus->self;
5064 dev->ignore_hotplug = 1;
5065 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5067 bridge->ignore_hotplug = 1;
5069 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5071 resource_size_t __weak pcibios_default_alignment(void)
5076 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5077 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5078 static DEFINE_SPINLOCK(resource_alignment_lock);
5081 * pci_specified_resource_alignment - get resource alignment specified by user.
5082 * @dev: the PCI device to get
5083 * @resize: whether or not to change resources' size when reassigning alignment
5085 * RETURNS: Resource alignment if it is specified.
5086 * Zero if it is not specified.
5088 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5091 int seg, bus, slot, func, align_order, count;
5092 unsigned short vendor, device, subsystem_vendor, subsystem_device;
5093 resource_size_t align = pcibios_default_alignment();
5096 spin_lock(&resource_alignment_lock);
5097 p = resource_alignment_param;
5100 if (pci_has_flag(PCI_PROBE_ONLY)) {
5102 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5108 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5114 if (strncmp(p, "pci:", 4) == 0) {
5115 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5117 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
5118 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
5119 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
5120 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
5124 subsystem_vendor = subsystem_device = 0;
5127 if ((!vendor || (vendor == dev->vendor)) &&
5128 (!device || (device == dev->device)) &&
5129 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5130 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5132 if (align_order == -1)
5135 align = 1 << align_order;
5141 if (sscanf(p, "%x:%x:%x.%x%n",
5142 &seg, &bus, &slot, &func, &count) != 4) {
5144 if (sscanf(p, "%x:%x.%x%n",
5145 &bus, &slot, &func, &count) != 3) {
5146 /* Invalid format */
5147 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5153 if (seg == pci_domain_nr(dev->bus) &&
5154 bus == dev->bus->number &&
5155 slot == PCI_SLOT(dev->devfn) &&
5156 func == PCI_FUNC(dev->devfn)) {
5158 if (align_order == -1)
5161 align = 1 << align_order;
5166 if (*p != ';' && *p != ',') {
5167 /* End of param or invalid format */
5173 spin_unlock(&resource_alignment_lock);
5177 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5178 resource_size_t align, bool resize)
5180 struct resource *r = &dev->resource[bar];
5181 resource_size_t size;
5183 if (!(r->flags & IORESOURCE_MEM))
5186 if (r->flags & IORESOURCE_PCI_FIXED) {
5187 dev_info(&dev->dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5188 bar, r, (unsigned long long)align);
5192 size = resource_size(r);
5197 * Increase the alignment of the resource. There are two ways we
5200 * 1) Increase the size of the resource. BARs are aligned on their
5201 * size, so when we reallocate space for this resource, we'll
5202 * allocate it with the larger alignment. This also prevents
5203 * assignment of any other BARs inside the alignment region, so
5204 * if we're requesting page alignment, this means no other BARs
5205 * will share the page.
5207 * The disadvantage is that this makes the resource larger than
5208 * the hardware BAR, which may break drivers that compute things
5209 * based on the resource size, e.g., to find registers at a
5210 * fixed offset before the end of the BAR.
5212 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5213 * set r->start to the desired alignment. By itself this
5214 * doesn't prevent other BARs being put inside the alignment
5215 * region, but if we realign *every* resource of every device in
5216 * the system, none of them will share an alignment region.
5218 * When the user has requested alignment for only some devices via
5219 * the "pci=resource_alignment" argument, "resize" is true and we
5220 * use the first method. Otherwise we assume we're aligning all
5221 * devices and we use the second.
5224 dev_info(&dev->dev, "BAR%d %pR: requesting alignment to %#llx\n",
5225 bar, r, (unsigned long long)align);
5231 r->flags &= ~IORESOURCE_SIZEALIGN;
5232 r->flags |= IORESOURCE_STARTALIGN;
5234 r->end = r->start + size - 1;
5236 r->flags |= IORESOURCE_UNSET;
5240 * This function disables memory decoding and releases memory resources
5241 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5242 * It also rounds up size to specified alignment.
5243 * Later on, the kernel will assign page-aligned memory resource back
5246 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5250 resource_size_t align;
5252 bool resize = false;
5255 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5256 * 3.4.1.11. Their resources are allocated from the space
5257 * described by the VF BARx register in the PF's SR-IOV capability.
5258 * We can't influence their alignment here.
5263 /* check if specified PCI is target device to reassign */
5264 align = pci_specified_resource_alignment(dev, &resize);
5268 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5269 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5271 "Can't reassign resources to host bridge.\n");
5276 "Disabling memory decoding and releasing memory resources.\n");
5277 pci_read_config_word(dev, PCI_COMMAND, &command);
5278 command &= ~PCI_COMMAND_MEMORY;
5279 pci_write_config_word(dev, PCI_COMMAND, command);
5281 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5282 pci_request_resource_alignment(dev, i, align, resize);
5285 * Need to disable bridge's resource window,
5286 * to enable the kernel to reassign new resource
5289 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5290 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5291 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5292 r = &dev->resource[i];
5293 if (!(r->flags & IORESOURCE_MEM))
5295 r->flags |= IORESOURCE_UNSET;
5296 r->end = resource_size(r) - 1;
5299 pci_disable_bridge_window(dev);
5303 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5305 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5306 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5307 spin_lock(&resource_alignment_lock);
5308 strncpy(resource_alignment_param, buf, count);
5309 resource_alignment_param[count] = '\0';
5310 spin_unlock(&resource_alignment_lock);
5314 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5317 spin_lock(&resource_alignment_lock);
5318 count = snprintf(buf, size, "%s", resource_alignment_param);
5319 spin_unlock(&resource_alignment_lock);
5323 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5325 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5328 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5329 const char *buf, size_t count)
5331 return pci_set_resource_alignment_param(buf, count);
5334 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5335 pci_resource_alignment_store);
5337 static int __init pci_resource_alignment_sysfs_init(void)
5339 return bus_create_file(&pci_bus_type,
5340 &bus_attr_resource_alignment);
5342 late_initcall(pci_resource_alignment_sysfs_init);
5344 static void pci_no_domains(void)
5346 #ifdef CONFIG_PCI_DOMAINS
5347 pci_domains_supported = 0;
5351 #ifdef CONFIG_PCI_DOMAINS
5352 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5354 int pci_get_new_domain_nr(void)
5356 return atomic_inc_return(&__domain_nr);
5359 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5360 static int of_pci_bus_find_domain_nr(struct device *parent)
5362 static int use_dt_domains = -1;
5366 domain = of_get_pci_domain_nr(parent->of_node);
5368 * Check DT domain and use_dt_domains values.
5370 * If DT domain property is valid (domain >= 0) and
5371 * use_dt_domains != 0, the DT assignment is valid since this means
5372 * we have not previously allocated a domain number by using
5373 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5374 * 1, to indicate that we have just assigned a domain number from
5377 * If DT domain property value is not valid (ie domain < 0), and we
5378 * have not previously assigned a domain number from DT
5379 * (use_dt_domains != 1) we should assign a domain number by
5382 * pci_get_new_domain_nr()
5384 * API and update the use_dt_domains value to keep track of method we
5385 * are using to assign domain numbers (use_dt_domains = 0).
5387 * All other combinations imply we have a platform that is trying
5388 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5389 * which is a recipe for domain mishandling and it is prevented by
5390 * invalidating the domain value (domain = -1) and printing a
5391 * corresponding error.
5393 if (domain >= 0 && use_dt_domains) {
5395 } else if (domain < 0 && use_dt_domains != 1) {
5397 domain = pci_get_new_domain_nr();
5399 dev_err(parent, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n",
5407 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5409 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5410 acpi_pci_bus_find_domain_nr(bus);
5416 * pci_ext_cfg_avail - can we access extended PCI config space?
5418 * Returns 1 if we can access PCI extended config space (offsets
5419 * greater than 0xff). This is the default implementation. Architecture
5420 * implementations can override this.
5422 int __weak pci_ext_cfg_avail(void)
5427 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5430 EXPORT_SYMBOL(pci_fixup_cardbus);
5432 static int __init pci_setup(char *str)
5435 char *k = strchr(str, ',');
5438 if (*str && (str = pcibios_setup(str)) && *str) {
5439 if (!strcmp(str, "nomsi")) {
5441 } else if (!strcmp(str, "noaer")) {
5443 } else if (!strncmp(str, "realloc=", 8)) {
5444 pci_realloc_get_opt(str + 8);
5445 } else if (!strncmp(str, "realloc", 7)) {
5446 pci_realloc_get_opt("on");
5447 } else if (!strcmp(str, "nodomains")) {
5449 } else if (!strncmp(str, "noari", 5)) {
5450 pcie_ari_disabled = true;
5451 } else if (!strncmp(str, "cbiosize=", 9)) {
5452 pci_cardbus_io_size = memparse(str + 9, &str);
5453 } else if (!strncmp(str, "cbmemsize=", 10)) {
5454 pci_cardbus_mem_size = memparse(str + 10, &str);
5455 } else if (!strncmp(str, "resource_alignment=", 19)) {
5456 pci_set_resource_alignment_param(str + 19,
5458 } else if (!strncmp(str, "ecrc=", 5)) {
5459 pcie_ecrc_get_policy(str + 5);
5460 } else if (!strncmp(str, "hpiosize=", 9)) {
5461 pci_hotplug_io_size = memparse(str + 9, &str);
5462 } else if (!strncmp(str, "hpmemsize=", 10)) {
5463 pci_hotplug_mem_size = memparse(str + 10, &str);
5464 } else if (!strncmp(str, "hpbussize=", 10)) {
5465 pci_hotplug_bus_size =
5466 simple_strtoul(str + 10, &str, 0);
5467 if (pci_hotplug_bus_size > 0xff)
5468 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5469 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5470 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5471 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5472 pcie_bus_config = PCIE_BUS_SAFE;
5473 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5474 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5475 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5476 pcie_bus_config = PCIE_BUS_PEER2PEER;
5477 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5478 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5480 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5488 early_param("pci", pci_setup);