drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_ras.h"
  25 #include "mmhub_v9_4.h"
  26
  27 #include "mmhub/mmhub_9_4_1_offset.h"
  28 #include "mmhub/mmhub_9_4_1_sh_mask.h"
  29 #include "mmhub/mmhub_9_4_1_default.h"
  30 #include "athub/athub_1_0_offset.h"
  31 #include "athub/athub_1_0_sh_mask.h"
  32 #include "vega10_enum.h"
  33 #include "soc15.h"
  34 #include "soc15_common.h"
  35
  36 #define MMHUB_NUM_INSTANCES                     2
  37 #define MMHUB_INSTANCE_REGISTER_OFFSET          0x3000
  38
  39 u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
  40 {
  41         /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
  42         u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
  43         u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);
  44
  45         base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  46         base <<= 24;
  47
  48         top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  49         top <<= 24;
  50
  51         adev->gmc.fb_start = base;
  52         adev->gmc.fb_end = top;
  53
  54         return base;
  55 }
  56
  57 static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
  58                                 uint32_t vmid, uint64_t value)
  59 {
  60         /* two registers distance between mmVML2VC0_VM_CONTEXT0_* to
  61          * mmVML2VC0_VM_CONTEXT1_*
  62          */
  63         int dist = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
  64                         - mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
  65
  66         WREG32_SOC15_OFFSET(MMHUB, 0,
  67                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  68                             dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  69                             lower_32_bits(value));
  70
  71         WREG32_SOC15_OFFSET(MMHUB, 0,
  72                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  73                             dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  74                             upper_32_bits(value));
  75
  76 }
  77
  78 static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
  79                                                int hubid)
  80 {
  81         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  82
  83         mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
  84
  85         WREG32_SOC15_OFFSET(MMHUB, 0,
  86                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  87                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  88                             (u32)(adev->gmc.gart_start >> 12));
  89         WREG32_SOC15_OFFSET(MMHUB, 0,
  90                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  91                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  92                             (u32)(adev->gmc.gart_start >> 44));
  93
  94         WREG32_SOC15_OFFSET(MMHUB, 0,
  95                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  96                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  97                             (u32)(adev->gmc.gart_end >> 12));
  98         WREG32_SOC15_OFFSET(MMHUB, 0,
  99                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 100                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 101                             (u32)(adev->gmc.gart_end >> 44));
 102 }
 103
 104 void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 105                                 uint64_t page_table_base)
 106 {
 107         int i;
 108
 109         for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
 110                 mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
 111                                 page_table_base);
 112 }
 113
 114 static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
 115                                                  int hubid)
 116 {
 117         uint64_t value;
 118         uint32_t tmp;
 119
 120         /* Program the AGP BAR */
 121         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
 122                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 123                             0);
 124         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
 125                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 126                             adev->gmc.agp_end >> 24);
 127         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
 128                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 129                             adev->gmc.agp_start >> 24);
 130
 131         if (!amdgpu_sriov_vf(adev)) {
 132                 /* Program the system aperture low logical page number. */
 133                 WREG32_SOC15_OFFSET(
 134                         MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 135                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 136                         min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 137                 WREG32_SOC15_OFFSET(
 138                         MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 139                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 140                         max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 141
 142                 /* Set default page address. */
 143                 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
 144                         adev->vm_manager.vram_base_offset;
 145                 WREG32_SOC15_OFFSET(
 146                         MMHUB, 0,
 147                         mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 148                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 149                         (u32)(value >> 12));
 150                 WREG32_SOC15_OFFSET(
 151                         MMHUB, 0,
 152                         mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 153                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 154                         (u32)(value >> 44));
 155
 156                 /* Program "protection fault". */
 157                 WREG32_SOC15_OFFSET(
 158                         MMHUB, 0,
 159                         mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 160                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 161                         (u32)(adev->dummy_page_addr >> 12));
 162                 WREG32_SOC15_OFFSET(
 163                         MMHUB, 0,
 164                         mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 165                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 166                         (u32)((u64)adev->dummy_page_addr >> 44));
 167
 168                 tmp = RREG32_SOC15_OFFSET(
 169                         MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
 170                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 171                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
 172                                     ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 173                 WREG32_SOC15_OFFSET(MMHUB, 0,
 174                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
 175                                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 176                                     tmp);
 177         }
 178 }
 179
 180 static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
 181 {
 182         uint32_t tmp;
 183
 184         /* Setup TLB control */
 185         tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 186                            mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 187                            hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 188
 189         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 190                             ENABLE_L1_TLB, 1);
 191         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 192                             SYSTEM_ACCESS_MODE, 3);
 193         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 194                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 195         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 196                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 197         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 198                             ECO_BITS, 0);
 199         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 200                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 201         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 202                             ATC_EN, 1);
 203
 204         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 205                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 206 }
 207
 208 static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
 209 {
 210         uint32_t tmp;
 211
 212         /* Setup L2 cache */
 213         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 214                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 215         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 216                             ENABLE_L2_CACHE, 1);
 217         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 218                             ENABLE_L2_FRAGMENT_PROCESSING, 1);
 219         /* XXX for emulation, Refer to closed source code.*/
 220         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 221                             L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 222         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 223                             PDE_FAULT_CLASSIFICATION, 0);
 224         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 225                             CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 226         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 227                             IDENTITY_MODE_FRAGMENT_SIZE, 0);
 228         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 229                      hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 230
 231         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
 232                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 233         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
 234                             INVALIDATE_ALL_L1_TLBS, 1);
 235         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
 236                             INVALIDATE_L2_CACHE, 1);
 237         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
 238                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 239
 240         tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
 241         if (adev->gmc.translate_further) {
 242                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
 243                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
 244                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 245         } else {
 246                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
 247                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
 248                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 249         }
 250         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
 251                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 252
 253         tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
 254         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
 255                             VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 256         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
 257                             VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 258         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
 259                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 260 }
 261
 262 static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
 263                                             int hubid)
 264 {
 265         uint32_t tmp;
 266
 267         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
 268                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 269         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 270         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 271         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
 272                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 273         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
 274                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 275 }
 276
 277 static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
 278                                                  int hubid)
 279 {
 280         WREG32_SOC15_OFFSET(MMHUB, 0,
 281                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 282                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF);
 283         WREG32_SOC15_OFFSET(MMHUB, 0,
 284                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 285                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F);
 286
 287         WREG32_SOC15_OFFSET(MMHUB, 0,
 288                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 289                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 290         WREG32_SOC15_OFFSET(MMHUB, 0,
 291                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 292                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 293
 294         WREG32_SOC15_OFFSET(MMHUB, 0,
 295                     mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 296                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 297         WREG32_SOC15_OFFSET(MMHUB, 0,
 298                     mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 299                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 300 }
 301
 302 static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
 303 {
 304         uint32_t tmp;
 305         int i;
 306
 307         for (i = 0; i <= 14; i++) {
 308                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
 309                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
 310                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 311                                     ENABLE_CONTEXT, 1);
 312                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 313                                     PAGE_TABLE_DEPTH,
 314                                     adev->vm_manager.num_level);
 315                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 316                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 317                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 318                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 319                                     1);
 320                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 321                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 322                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 323                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 324                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 325                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 326                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 327                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 328                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 329                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 330                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 331                                     PAGE_TABLE_BLOCK_SIZE,
 332                                     adev->vm_manager.block_size - 9);
 333                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 334                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 335                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 336                                     !amdgpu_noretry);
 337                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
 338                                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i,
 339                                     tmp);
 340                 WREG32_SOC15_OFFSET(MMHUB, 0,
 341                             mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 342                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
 343                 WREG32_SOC15_OFFSET(MMHUB, 0,
 344                             mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 345                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
 346                 WREG32_SOC15_OFFSET(MMHUB, 0,
 347                                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 348                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
 349                                 lower_32_bits(adev->vm_manager.max_pfn - 1));
 350                 WREG32_SOC15_OFFSET(MMHUB, 0,
 351                                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 352                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
 353                                 upper_32_bits(adev->vm_manager.max_pfn - 1));
 354         }
 355 }
 356
 357 static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
 358                                             int hubid)
 359 {
 360         unsigned i;
 361
 362         for (i = 0; i < 18; ++i) {
 363                 WREG32_SOC15_OFFSET(MMHUB, 0,
 364                                 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 365                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
 366                                 0xffffffff);
 367                 WREG32_SOC15_OFFSET(MMHUB, 0,
 368                                 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 369                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
 370                                 0x1f);
 371         }
 372 }
 373
 374 int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
 375 {
 376         int i;
 377
 378         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 379                 /* GART Enable. */
 380                 mmhub_v9_4_init_gart_aperture_regs(adev, i);
 381                 mmhub_v9_4_init_system_aperture_regs(adev, i);
 382                 mmhub_v9_4_init_tlb_regs(adev, i);
 383                 if (!amdgpu_sriov_vf(adev))
 384                         mmhub_v9_4_init_cache_regs(adev, i);
 385
 386                 mmhub_v9_4_enable_system_domain(adev, i);
 387                 if (!amdgpu_sriov_vf(adev))
 388                         mmhub_v9_4_disable_identity_aperture(adev, i);
 389                 mmhub_v9_4_setup_vmid_config(adev, i);
 390                 mmhub_v9_4_program_invalidation(adev, i);
 391         }
 392
 393         return 0;
 394 }
 395
 396 void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
 397 {
 398         u32 tmp;
 399         u32 i, j;
 400
 401         for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
 402                 /* Disable all tables */
 403                 for (i = 0; i < 16; i++)
 404                         WREG32_SOC15_OFFSET(MMHUB, 0,
 405                                             mmVML2VC0_VM_CONTEXT0_CNTL,
 406                                             j * MMHUB_INSTANCE_REGISTER_OFFSET +
 407                                             i, 0);
 408
 409                 /* Setup TLB control */
 410                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 411                                    mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 412                                    j * MMHUB_INSTANCE_REGISTER_OFFSET);
 413                 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 414                                     ENABLE_L1_TLB, 0);
 415                 tmp = REG_SET_FIELD(tmp,
 416                                     VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 417                                     ENABLE_ADVANCED_DRIVER_MODEL, 0);
 418                 WREG32_SOC15_OFFSET(MMHUB, 0,
 419                                     mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 420                                     j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 421
 422                 /* Setup L2 cache */
 423                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 424                                           j * MMHUB_INSTANCE_REGISTER_OFFSET);
 425                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 426                                     ENABLE_L2_CACHE, 0);
 427                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 428                                     j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 429                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
 430                                     j * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 431         }
 432 }
 433
 434 /**
 435  * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 436  *
 437  * @adev: amdgpu_device pointer
 438  * @value: true redirects VM faults to the default page
 439  */
 440 void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 441 {
 442         u32 tmp;
 443         int i;
 444
 445         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 446                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 447                                           mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 448                                           i * MMHUB_INSTANCE_REGISTER_OFFSET);
 449                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 450                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 451                                     value);
 452                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 453                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,
 454                                     value);
 455                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 456                                     PDE1_PROTECTION_FAULT_ENABLE_DEFAULT,
 457                                     value);
 458                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 459                                     PDE2_PROTECTION_FAULT_ENABLE_DEFAULT,
 460                                     value);
 461                 tmp = REG_SET_FIELD(tmp,
 462                             VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 463                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 464                             value);
 465                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 466                                     NACK_PROTECTION_FAULT_ENABLE_DEFAULT,
 467                                     value);
 468                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 469                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 470                                     value);
 471                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 472                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT,
 473                                     value);
 474                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 475                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT,
 476                                     value);
 477                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 478                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,
 479                                     value);
 480                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 481                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,
 482                                     value);
 483                 if (!value) {
 484                         tmp = REG_SET_FIELD(tmp,
 485                                             VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 486                                             CRASH_ON_NO_RETRY_FAULT, 1);
 487                         tmp = REG_SET_FIELD(tmp,
 488                                             VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 489                                             CRASH_ON_RETRY_FAULT, 1);
 490                 }
 491
 492                 WREG32_SOC15_OFFSET(MMHUB, 0,
 493                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 494                                     i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 495         }
 496 }
 497
 498 void mmhub_v9_4_init(struct amdgpu_device *adev)
 499 {
 500         struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
 501                 {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
 502         int i;
 503
 504         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 505                 hub[i]->ctx0_ptb_addr_lo32 =
 506                         SOC15_REG_OFFSET(MMHUB, 0,
 507                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) +
 508                             i * MMHUB_INSTANCE_REGISTER_OFFSET;
 509                 hub[i]->ctx0_ptb_addr_hi32 =
 510                         SOC15_REG_OFFSET(MMHUB, 0,
 511                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
 512                             i * MMHUB_INSTANCE_REGISTER_OFFSET;
 513                 hub[i]->vm_inv_eng0_sem =
 514                         SOC15_REG_OFFSET(MMHUB, 0,
 515                                          mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
 516                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 517                 hub[i]->vm_inv_eng0_req =
 518                         SOC15_REG_OFFSET(MMHUB, 0,
 519                                          mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
 520                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 521                 hub[i]->vm_inv_eng0_ack =
 522                         SOC15_REG_OFFSET(MMHUB, 0,
 523                                          mmVML2VC0_VM_INVALIDATE_ENG0_ACK) +
 524                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 525                 hub[i]->vm_context0_cntl =
 526                         SOC15_REG_OFFSET(MMHUB, 0,
 527                                          mmVML2VC0_VM_CONTEXT0_CNTL) +
 528                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 529                 hub[i]->vm_l2_pro_fault_status =
 530                         SOC15_REG_OFFSET(MMHUB, 0,
 531                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) +
 532                                     i * MMHUB_INSTANCE_REGISTER_OFFSET;
 533                 hub[i]->vm_l2_pro_fault_cntl =
 534                         SOC15_REG_OFFSET(MMHUB, 0,
 535                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) +
 536                                     i * MMHUB_INSTANCE_REGISTER_OFFSET;
 537         }
 538 }
 539
 540 static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 541                                                         bool enable)
 542 {
 543         uint32_t def, data, def1, data1;
 544         int i, j;
 545         int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
 546
 547         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 548                 def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
 549                                         mmATCL2_0_ATC_L2_MISC_CG,
 550                                         i * MMHUB_INSTANCE_REGISTER_OFFSET);
 551
 552                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 553                         data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
 554                 else
 555                         data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
 556
 557                 if (def != data)
 558                         WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
 559                                 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
 560
 561                 for (j = 0; j < 5; j++) {
 562                         def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
 563                                         mmDAGB0_CNTL_MISC2,
 564                                         i * MMHUB_INSTANCE_REGISTER_OFFSET +
 565                                         j * dist);
 566                         if (enable &&
 567                             (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 568                                 data1 &=
 569                                     ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 570                                     DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 571                                     DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 572                                     DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 573                                     DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 574                                     DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 575                         } else {
 576                                 data1 |=
 577                                     (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 578                                     DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 579                                     DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 580                                     DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 581                                     DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 582                                     DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 583                         }
 584
 585                         if (def1 != data1)
 586                                 WREG32_SOC15_OFFSET(MMHUB, 0,
 587                                         mmDAGB0_CNTL_MISC2,
 588                                         i * MMHUB_INSTANCE_REGISTER_OFFSET +
 589                                         j * dist, data1);
 590
 591                         if (i == 1 && j == 3)
 592                                 break;
 593                 }
 594         }
 595 }
 596
 597 static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 598                                                        bool enable)
 599 {
 600         uint32_t def, data;
 601         int i;
 602
 603         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 604                 def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
 605                                         mmATCL2_0_ATC_L2_MISC_CG,
 606                                         i * MMHUB_INSTANCE_REGISTER_OFFSET);
 607
 608                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 609                         data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 610                 else
 611                         data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 612
 613                 if (def != data)
 614                         WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
 615                                 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
 616         }
 617 }
 618
 619 int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
 620                                enum amd_clockgating_state state)
 621 {
 622         if (amdgpu_sriov_vf(adev))
 623                 return 0;
 624
 625         switch (adev->asic_type) {
 626         case CHIP_ARCTURUS:
 627                 mmhub_v9_4_update_medium_grain_clock_gating(adev,
 628                                 state == AMD_CG_STATE_GATE);
 629                 mmhub_v9_4_update_medium_grain_light_sleep(adev,
 630                                 state == AMD_CG_STATE_GATE);
 631                 break;
 632         default:
 633                 break;
 634         }
 635
 636         return 0;
 637 }
 638
 639 void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 640 {
 641         int data, data1;
 642
 643         if (amdgpu_sriov_vf(adev))
 644                 *flags = 0;
 645
 646         /* AMD_CG_SUPPORT_MC_MGCG */
 647         data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
 648
 649         data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
 650
 651         if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
 652             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 653                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 654                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 655                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 656                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 657                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 658                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 659
 660         /* AMD_CG_SUPPORT_MC_LS */
 661         if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 662                 *flags |= AMD_CG_SUPPORT_MC_LS;
 663 }
 664
 665 static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = {
 666         /* MMHUB Range 0 */
 667         { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 668         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 669         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 670         },
 671         { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 672         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 673         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 674         },
 675         { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 676         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 677         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 678         },
 679         { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 680         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 681         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 682         },
 683         { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 684         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 685         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 686         },
 687         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 688         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 689         0, 0,
 690         },
 691         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 692         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 693         0, 0,
 694         },
 695         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 696         SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 697         0, 0,
 698         },
 699         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 700         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 701         0, 0,
 702         },
 703         { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 704         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
 705         0, 0,
 706         },
 707         { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 708         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 709         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 710         },
 711         { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 712         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 713         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 714         },
 715         { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 716         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 717         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 718         },
 719         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 720         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 721         0, 0,
 722         },
 723         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 724         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 725         0, 0,
 726         },
 727         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 728         0, 0,
 729         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 730         },
 731         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 732         0, 0,
 733         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 734         },
 735         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 736         0, 0,
 737         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 738         },
 739         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 740         0, 0,
 741         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 742         },
 743         { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 744         0, 0,
 745         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
 746         },
 747         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 748         0, 0,
 749         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 750         },
 751         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 752         0, 0,
 753         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 754         },
 755         { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 756         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 757         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 758         },
 759         { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 760         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 761         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 762         },
 763         { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 764         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 765         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 766         },
 767         { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 768         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 769         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 770         },
 771
 772         /* MMHUB Range 1 */
 773         { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 774         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 775         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 776         },
 777         { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 778         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 779         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 780         },
 781         { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 782         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 783         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 784         },
 785         { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 786         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 787         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 788         },
 789         { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 790         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 791         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 792         },
 793         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 794         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 795         0, 0,
 796         },
 797         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 798         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 799         0, 0,
 800         },
 801         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 802         SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 803         0, 0,
 804         },
 805         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 806         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 807         0, 0,
 808         },
 809         { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 810         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
 811         0, 0,
 812         },
 813         { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 814         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 815         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 816         },
 817         { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 818         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 819         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 820         },
 821         { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 822         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 823         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 824         },
 825         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 826         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 827         0, 0,
 828         },
 829         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 830         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 831         0, 0,
 832         },
 833         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 834         0, 0,
 835         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 836         },
 837         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 838         0, 0,
 839         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 840         },
 841         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 842         0, 0,
 843         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 844         },
 845         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 846         0, 0,
 847         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 848         },
 849         { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 850         0, 0,
 851         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
 852         },
 853         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 854         0, 0,
 855         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 856         },
 857         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 858         0, 0,
 859         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 860         },
 861         { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 862         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 863         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 864         },
 865         { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 866         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 867         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 868         },
 869         { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 870         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 871         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 872         },
 873         { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 874         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 875         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 876         },
 877
 878         /* MMHAB Range 2*/
 879         { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 880         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 881         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 882         },
 883         { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 884         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 885         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 886         },
 887         { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 888         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 889         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 890         },
 891         { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 892         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 893         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 894         },
 895         { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 896         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 897         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 898         },
 899         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 900         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 901         0, 0,
 902         },
 903         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 904         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 905         0, 0,
 906         },
 907         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 908         SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 909         0, 0,
 910         },
 911         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 912         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 913         0, 0,
 914         },
 915         { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 916         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
 917         0, 0,
 918         },
 919         { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 920         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 921         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 922         },
 923         { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 924         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 925         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 926         },
 927         { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 928         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 929         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 930         },
 931         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 932         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 933         0, 0,
 934         },
 935         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 936         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 937         0, 0,
 938         },
 939         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 940         0, 0,
 941         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 942         },
 943         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 944         0, 0,
 945         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 946         },
 947         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 948         0, 0,
 949         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 950         },
 951         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 952         0, 0,
 953         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 954         },
 955         { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 956         0, 0,
 957         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
 958         },
 959         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 960         0, 0,
 961         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 962         },
 963         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 964         0, 0,
 965         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 966         },
 967         { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 968         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 969         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 970         },
 971         { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 972         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 973         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 974         },
 975         { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 976         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 977         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 978         },
 979         { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 980         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 981         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 982         },
 983
 984         /* MMHUB Rang 3 */
 985         { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
 986         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 987         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 988         },
 989         { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
 990         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 991         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 992         },
 993         { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
 994         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 995         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 996         },
 997         { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
 998         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 999         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1000         },
1001         { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1002         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1003         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1004         },
1005         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1006         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1007         0, 0,
1008         },
1009         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1010         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1011         0, 0,
1012         },
1013         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1014         SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1015         0, 0,
1016         },
1017         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1018         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1019         0, 0,
1020         },
1021         { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1022         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1023         0, 0,
1024         },
1025         { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1026         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1027         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1028         },
1029         { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1030         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1031         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1032         },
1033         { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1034         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1035         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1036         },
1037         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1038         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1039         0, 0,
1040         },
1041         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1042         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1043         0, 0,
1044         },
1045         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1046         0, 0,
1047         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1048         },
1049         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1050         0, 0,
1051         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1052         },
1053         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1054         0, 0,
1055         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1056         },
1057         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1058         0, 0,
1059         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1060         },
1061         { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1062         0, 0,
1063         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1064         },
1065         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1066         0, 0,
1067         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1068         },
1069         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1070         0, 0,
1071         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1072         },
1073         { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1074         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1075         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1076         },
1077         { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1078         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1079         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1080         },
1081         { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1082         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1083         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1084         },
1085         { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1086         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1087         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1088         },
1089
1090         /* MMHUB Range 4 */
1091         { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1092         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1093         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1094         },
1095         { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1096         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1097         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1098         },
1099         { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1100         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1101         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1102         },
1103         { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1104         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1105         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1106         },
1107         { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1108         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1109         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1110         },
1111         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1112         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1113         0, 0,
1114         },
1115         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1116         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1117         0, 0,
1118         },
1119         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1120         SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1121         0, 0,
1122         },
1123         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1124         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1125         0, 0,
1126         },
1127         { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1128         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1129         0, 0,
1130         },
1131         { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1132         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1133         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1134         },
1135         { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1136         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1137         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1138         },
1139         { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1140         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1141         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1142         },
1143         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1144         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1145         0, 0,
1146         },
1147         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1148         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1149         0, 0,
1150         },
1151         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1152         0, 0,
1153         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1154         },
1155         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1156         0, 0,
1157         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1158         },
1159         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1160         0, 0,
1161         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1162         },
1163         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1164         0, 0,
1165         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1166         },
1167         { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1168         0, 0,
1169         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1170         },
1171         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1172         0, 0,
1173         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1174         },
1175         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1176         0, 0,
1177         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1178         },
1179         { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1180         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1181         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1182         },
1183         { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1184         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1185         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1186         },
1187         { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1188         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1189         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1190         },
1191         { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1192         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1193         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1194         },
1195
1196         /* MMHUAB Range 5 */
1197         { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1198         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1199         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1200         },
1201         { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1202         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1203         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1204         },
1205         { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1206         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1207         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1208         },
1209         { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1210         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1211         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1212         },
1213         { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1214         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1215         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1216         },
1217         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1218         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1219         0, 0,
1220         },
1221         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1222         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1223         0, 0,
1224         },
1225         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1226         SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1227         0, 0,
1228         },
1229         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1230         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1231         0, 0,
1232         },
1233         { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1234         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1235         0, 0,
1236         },
1237         { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1238         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1239         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1240         },
1241         { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1242         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1243         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1244         },
1245         { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1246         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1247         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1248         },
1249         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1250         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1251         0, 0,
1252         },
1253         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1254         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1255         0, 0,
1256         },
1257         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1258         0, 0,
1259         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1260         },
1261         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1262         0, 0,
1263         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1264         },
1265         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1266         0, 0,
1267         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1268         },
1269         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1270         0, 0,
1271         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1272         },
1273         { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1274         0, 0,
1275         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1276         },
1277         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1278         0, 0,
1279         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1280         },
1281         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1282         0, 0,
1283         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1284         },
1285         { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1286         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1287         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1288         },
1289         { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1290         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1291         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1292         },
1293         { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1294         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1295         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1296         },
1297         { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1298         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1299         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1300         },
1301
1302         /* MMHUB Range 6 */
1303         { "MMEA6_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1304         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1305         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1306         },
1307         { "MMEA6_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1308         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1309         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1310         },
1311         { "MMEA6_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1312         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1313         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1314         },
1315         { "MMEA6_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1316         SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1317         SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1318         },
1319         { "MMEA6_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1320         SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1321         SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1322         },
1323         { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1324         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1325         0, 0,
1326         },
1327         { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1328         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1329         0, 0,
1330         },
1331         { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1332         SOC15_REG_FIELD(MMEA6_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1333         0, 0,
1334         },
1335         { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1336         SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1337         0, 0,
1338         },
1339         { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1340         SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1341         0, 0,
1342         },
1343         { "MMEA6_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1344         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1345         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1346         },
1347         { "MMEA6_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1348         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1349         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1350         },
1351         { "MMEA6_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1352         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1353         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1354         },
1355         { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1356         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1357         0, 0,
1358         },
1359         { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1360         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1361         0, 0,
1362         },
1363         { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1364         0, 0,
1365         SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1366         },
1367         { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1368         0, 0,
1369         SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1370         },
1371         { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1372         0, 0,
1373         SOC15_REG_FIELD(MMEA6_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1374         },
1375         { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1376         0, 0,
1377         SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1378         },
1379         { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1380         0, 0,
1381         SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1382         },
1383         { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1384         0, 0,
1385         SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1386         },
1387         { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1388         0, 0,
1389         SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1390         },
1391         { "MMEA6_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1392         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1393         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1394         },
1395         { "MMEA6_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1396         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1397         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1398         },
1399         { "MMEA6_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1400         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1401         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1402         },
1403         { "MMEA6_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1404         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1405         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1406         },
1407
1408         /* MMHUB Range 7*/
1409         { "MMEA7_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1410         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1411         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1412         },
1413         { "MMEA7_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1414         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1415         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1416         },
1417         { "MMEA7_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1418         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1419         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1420         },
1421         { "MMEA7_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1422         SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1423         SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1424         },
1425         { "MMEA7_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1426         SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1427         SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1428         },
1429         { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1430         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1431         0, 0,
1432         },
1433         { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1434         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1435         0, 0,
1436         },
1437         { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1438         SOC15_REG_FIELD(MMEA7_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1439         0, 0,
1440         },
1441         { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1442         SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1443         0, 0,
1444         },
1445         { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1446         SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1447         0, 0,
1448         },
1449         { "MMEA7_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1450         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1451         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1452         },
1453         { "MMEA7_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1454         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1455         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1456         },
1457         { "MMEA7_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1458         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1459         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1460         },
1461         { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1462         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1463         0, 0,
1464         },
1465         { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1466         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1467         0, 0,
1468         },
1469         { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1470         0, 0,
1471         SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1472         },
1473         { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1474         0, 0,
1475         SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1476         },
1477         { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1478         0, 0,
1479         SOC15_REG_FIELD(MMEA7_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1480         },
1481         { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1482         0, 0,
1483         SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1484         },
1485         { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1486         0, 0,
1487         SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1488         },
1489         { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1490         0, 0,
1491         SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1492         },
1493         { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1494         0, 0,
1495         SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1496         },
1497         { "MMEA7_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1498         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1499         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1500         },
1501         { "MMEA7_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1502         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1503         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1504         },
1505         { "MMEA7_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1506         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1507         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1508         },
1509         { "MMEA7_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1510         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1511         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1512         }
1513 };
1514
1515 static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
1516         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 },
1517         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 },
1518         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 },
1519         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 },
1520         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 },
1521         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0 },
1522         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 },
1523         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 0, 0, 0 },
1524         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 0, 0, 0 },
1525         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 },
1526         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 0, 0, 0 },
1527         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 0, 0, 0 },
1528         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 },
1529         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 0, 0, 0 },
1530         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 0, 0, 0 },
1531         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 },
1532         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 0, 0, 0 },
1533         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 0, 0, 0 },
1534         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 },
1535         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 0, 0, 0 },
1536         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 0, 0, 0 },
1537         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 0, 0, 0 },
1538         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 0, 0, 0 },
1539         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 },
1540 };
1541
1542 static int mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev,
1543                                           const struct soc15_reg_entry *reg,
1544                                           uint32_t value,
1545                                           uint32_t *sec_count,
1546                                           uint32_t *ded_count)
1547 {
1548         uint32_t i;
1549         uint32_t sec_cnt, ded_cnt;
1550
1551         for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) {
1552                 if(mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
1553                         continue;
1554
1555                 sec_cnt = (value &
1556                                 mmhub_v9_4_ras_fields[i].sec_count_mask) >>
1557                                 mmhub_v9_4_ras_fields[i].sec_count_shift;
1558                 if (sec_cnt) {
1559                         dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1560                                 mmhub_v9_4_ras_fields[i].name,
1561                                 sec_cnt);
1562                         *sec_count += sec_cnt;
1563                 }
1564
1565                 ded_cnt = (value &
1566                                 mmhub_v9_4_ras_fields[i].ded_count_mask) >>
1567                                 mmhub_v9_4_ras_fields[i].ded_count_shift;
1568                 if (ded_cnt) {
1569                         dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1570                                 mmhub_v9_4_ras_fields[i].name,
1571                                 ded_cnt);
1572                         *ded_count += ded_cnt;
1573                 }
1574         }
1575
1576         return 0;
1577 }
1578
1579 static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
1580                                            void *ras_error_status)
1581 {
1582         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1583         uint32_t sec_count = 0, ded_count = 0;
1584         uint32_t i;
1585         uint32_t reg_value;
1586
1587         err_data->ue_count = 0;
1588         err_data->ce_count = 0;
1589
1590         for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) {
1591                 reg_value =
1592                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1593                 if (reg_value)
1594                         mmhub_v9_4_get_ras_error_count(adev, &mmhub_v9_4_edc_cnt_regs[i],
1595                                 reg_value, &sec_count, &ded_count);
1596         }
1597
1598         err_data->ce_count += sec_count;
1599         err_data->ue_count += ded_count;
1600 }
1601
1602 static void mmhub_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
1603 {
1604         uint32_t i;
1605
1606         /* read back edc counter registers to reset the counters to 0 */
1607         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1608                 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++)
1609                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1610         }
1611 }
1612
1613 const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
1614         .ras_late_init = amdgpu_mmhub_ras_late_init,
1615         .query_ras_error_count = mmhub_v9_4_query_ras_error_count,
1616         .reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,
1617 };