drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_smu.h"
  33 #include "atom.h"
  34 #include <linux/pci.h>
  35 #include <linux/hwmon.h>
  36 #include <linux/hwmon-sysfs.h>
  37 #include <linux/nospec.h>
  38 #include <linux/pm_runtime.h>
  39 #include <asm/processor.h>
  40 #include "hwmgr.h"
  41
  42 static const struct cg_flag_name clocks[] = {
  43         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  45         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  47         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  49         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  55         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  57         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  60         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  63         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  66         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  67         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  68         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
  69         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
  70         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
  71         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
  72         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
  73
  74         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  75         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  76         {0, NULL},
  77 };
  78
  79 static const struct hwmon_temp_label {
  80         enum PP_HWMON_TEMP channel;
  81         const char *label;
  82 } temp_label[] = {
  83         {PP_TEMP_EDGE, "edge"},
  84         {PP_TEMP_JUNCTION, "junction"},
  85         {PP_TEMP_MEM, "mem"},
  86 };
  87
  88 /**
  89  * DOC: power_dpm_state
  90  *
  91  * The power_dpm_state file is a legacy interface and is only provided for
  92  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  93  * certain power related parameters.  The file power_dpm_state is used for this.
  94  * It accepts the following arguments:
  95  *
  96  * - battery
  97  *
  98  * - balanced
  99  *
 100  * - performance
 101  *
 102  * battery
 103  *
 104  * On older GPUs, the vbios provided a special power state for battery
 105  * operation.  Selecting battery switched to this state.  This is no
 106  * longer provided on newer GPUs so the option does nothing in that case.
 107  *
 108  * balanced
 109  *
 110  * On older GPUs, the vbios provided a special power state for balanced
 111  * operation.  Selecting balanced switched to this state.  This is no
 112  * longer provided on newer GPUs so the option does nothing in that case.
 113  *
 114  * performance
 115  *
 116  * On older GPUs, the vbios provided a special power state for performance
 117  * operation.  Selecting performance switched to this state.  This is no
 118  * longer provided on newer GPUs so the option does nothing in that case.
 119  *
 120  */
 121
 122 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 123                                           struct device_attribute *attr,
 124                                           char *buf)
 125 {
 126         struct drm_device *ddev = dev_get_drvdata(dev);
 127         struct amdgpu_device *adev = drm_to_adev(ddev);
 128         enum amd_pm_state_type pm;
 129         int ret;
 130
 131         if (amdgpu_in_reset(adev))
 132                 return -EPERM;
 133
 134         ret = pm_runtime_get_sync(ddev->dev);
 135         if (ret < 0) {
 136                 pm_runtime_put_autosuspend(ddev->dev);
 137                 return ret;
 138         }
 139
 140         if (is_support_sw_smu(adev)) {
 141                 if (adev->smu.ppt_funcs->get_current_power_state)
 142                         pm = smu_get_current_power_state(&adev->smu);
 143                 else
 144                         pm = adev->pm.dpm.user_state;
 145         } else if (adev->powerplay.pp_funcs->get_current_power_state) {
 146                 pm = amdgpu_dpm_get_current_power_state(adev);
 147         } else {
 148                 pm = adev->pm.dpm.user_state;
 149         }
 150
 151         pm_runtime_mark_last_busy(ddev->dev);
 152         pm_runtime_put_autosuspend(ddev->dev);
 153
 154         return snprintf(buf, PAGE_SIZE, "%s\n",
 155                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 156                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 157 }
 158
 159 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 160                                           struct device_attribute *attr,
 161                                           const char *buf,
 162                                           size_t count)
 163 {
 164         struct drm_device *ddev = dev_get_drvdata(dev);
 165         struct amdgpu_device *adev = drm_to_adev(ddev);
 166         enum amd_pm_state_type  state;
 167         int ret;
 168
 169         if (amdgpu_in_reset(adev))
 170                 return -EPERM;
 171
 172         if (strncmp("battery", buf, strlen("battery")) == 0)
 173                 state = POWER_STATE_TYPE_BATTERY;
 174         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 175                 state = POWER_STATE_TYPE_BALANCED;
 176         else if (strncmp("performance", buf, strlen("performance")) == 0)
 177                 state = POWER_STATE_TYPE_PERFORMANCE;
 178         else
 179                 return -EINVAL;
 180
 181         ret = pm_runtime_get_sync(ddev->dev);
 182         if (ret < 0) {
 183                 pm_runtime_put_autosuspend(ddev->dev);
 184                 return ret;
 185         }
 186
 187         if (is_support_sw_smu(adev)) {
 188                 mutex_lock(&adev->pm.mutex);
 189                 adev->pm.dpm.user_state = state;
 190                 mutex_unlock(&adev->pm.mutex);
 191         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 192                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 193         } else {
 194                 mutex_lock(&adev->pm.mutex);
 195                 adev->pm.dpm.user_state = state;
 196                 mutex_unlock(&adev->pm.mutex);
 197
 198                 amdgpu_pm_compute_clocks(adev);
 199         }
 200         pm_runtime_mark_last_busy(ddev->dev);
 201         pm_runtime_put_autosuspend(ddev->dev);
 202
 203         return count;
 204 }
 205
 206
 207 /**
 208  * DOC: power_dpm_force_performance_level
 209  *
 210  * The amdgpu driver provides a sysfs API for adjusting certain power
 211  * related parameters.  The file power_dpm_force_performance_level is
 212  * used for this.  It accepts the following arguments:
 213  *
 214  * - auto
 215  *
 216  * - low
 217  *
 218  * - high
 219  *
 220  * - manual
 221  *
 222  * - profile_standard
 223  *
 224  * - profile_min_sclk
 225  *
 226  * - profile_min_mclk
 227  *
 228  * - profile_peak
 229  *
 230  * auto
 231  *
 232  * When auto is selected, the driver will attempt to dynamically select
 233  * the optimal power profile for current conditions in the driver.
 234  *
 235  * low
 236  *
 237  * When low is selected, the clocks are forced to the lowest power state.
 238  *
 239  * high
 240  *
 241  * When high is selected, the clocks are forced to the highest power state.
 242  *
 243  * manual
 244  *
 245  * When manual is selected, the user can manually adjust which power states
 246  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 247  * and pp_dpm_pcie files and adjust the power state transition heuristics
 248  * via the pp_power_profile_mode sysfs file.
 249  *
 250  * profile_standard
 251  * profile_min_sclk
 252  * profile_min_mclk
 253  * profile_peak
 254  *
 255  * When the profiling modes are selected, clock and power gating are
 256  * disabled and the clocks are set for different profiling cases. This
 257  * mode is recommended for profiling specific work loads where you do
 258  * not want clock or power gating for clock fluctuation to interfere
 259  * with your results. profile_standard sets the clocks to a fixed clock
 260  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 261  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 262  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 263  *
 264  */
 265
 266 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 267                                                             struct device_attribute *attr,
 268                                                             char *buf)
 269 {
 270         struct drm_device *ddev = dev_get_drvdata(dev);
 271         struct amdgpu_device *adev = drm_to_adev(ddev);
 272         enum amd_dpm_forced_level level = 0xff;
 273         int ret;
 274
 275         if (amdgpu_in_reset(adev))
 276                 return -EPERM;
 277
 278         ret = pm_runtime_get_sync(ddev->dev);
 279         if (ret < 0) {
 280                 pm_runtime_put_autosuspend(ddev->dev);
 281                 return ret;
 282         }
 283
 284         if (is_support_sw_smu(adev))
 285                 level = smu_get_performance_level(&adev->smu);
 286         else if (adev->powerplay.pp_funcs->get_performance_level)
 287                 level = amdgpu_dpm_get_performance_level(adev);
 288         else
 289                 level = adev->pm.dpm.forced_level;
 290
 291         pm_runtime_mark_last_busy(ddev->dev);
 292         pm_runtime_put_autosuspend(ddev->dev);
 293
 294         return snprintf(buf, PAGE_SIZE, "%s\n",
 295                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 296                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 297                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 298                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 299                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 300                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 301                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 302                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 303                         "unknown");
 304 }
 305
 306 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 307                                                             struct device_attribute *attr,
 308                                                             const char *buf,
 309                                                             size_t count)
 310 {
 311         struct drm_device *ddev = dev_get_drvdata(dev);
 312         struct amdgpu_device *adev = drm_to_adev(ddev);
 313         enum amd_dpm_forced_level level;
 314         enum amd_dpm_forced_level current_level = 0xff;
 315         int ret = 0;
 316
 317         if (amdgpu_in_reset(adev))
 318                 return -EPERM;
 319
 320         if (strncmp("low", buf, strlen("low")) == 0) {
 321                 level = AMD_DPM_FORCED_LEVEL_LOW;
 322         } else if (strncmp("high", buf, strlen("high")) == 0) {
 323                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 324         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 325                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 326         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 327                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 328         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 329                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 330         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 331                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 332         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 333                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 334         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 335                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 336         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 337                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 338         }  else {
 339                 return -EINVAL;
 340         }
 341
 342         ret = pm_runtime_get_sync(ddev->dev);
 343         if (ret < 0) {
 344                 pm_runtime_put_autosuspend(ddev->dev);
 345                 return ret;
 346         }
 347
 348         if (is_support_sw_smu(adev))
 349                 current_level = smu_get_performance_level(&adev->smu);
 350         else if (adev->powerplay.pp_funcs->get_performance_level)
 351                 current_level = amdgpu_dpm_get_performance_level(adev);
 352
 353         if (current_level == level) {
 354                 pm_runtime_mark_last_busy(ddev->dev);
 355                 pm_runtime_put_autosuspend(ddev->dev);
 356                 return count;
 357         }
 358
 359         if (adev->asic_type == CHIP_RAVEN) {
 360                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 361                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
 362                                 amdgpu_gfx_off_ctrl(adev, false);
 363                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 364                                 amdgpu_gfx_off_ctrl(adev, true);
 365                 }
 366         }
 367
 368         /* profile_exit setting is valid only when current mode is in profile mode */
 369         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 370             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 371             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 372             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 373             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 374                 pr_err("Currently not in any profile mode!\n");
 375                 pm_runtime_mark_last_busy(ddev->dev);
 376                 pm_runtime_put_autosuspend(ddev->dev);
 377                 return -EINVAL;
 378         }
 379
 380         if (is_support_sw_smu(adev)) {
 381                 ret = smu_force_performance_level(&adev->smu, level);
 382                 if (ret) {
 383                         pm_runtime_mark_last_busy(ddev->dev);
 384                         pm_runtime_put_autosuspend(ddev->dev);
 385                         return -EINVAL;
 386                 }
 387         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 388                 mutex_lock(&adev->pm.mutex);
 389                 if (adev->pm.dpm.thermal_active) {
 390                         mutex_unlock(&adev->pm.mutex);
 391                         pm_runtime_mark_last_busy(ddev->dev);
 392                         pm_runtime_put_autosuspend(ddev->dev);
 393                         return -EINVAL;
 394                 }
 395                 ret = amdgpu_dpm_force_performance_level(adev, level);
 396                 if (ret) {
 397                         mutex_unlock(&adev->pm.mutex);
 398                         pm_runtime_mark_last_busy(ddev->dev);
 399                         pm_runtime_put_autosuspend(ddev->dev);
 400                         return -EINVAL;
 401                 } else {
 402                         adev->pm.dpm.forced_level = level;
 403                 }
 404                 mutex_unlock(&adev->pm.mutex);
 405         }
 406         pm_runtime_mark_last_busy(ddev->dev);
 407         pm_runtime_put_autosuspend(ddev->dev);
 408
 409         return count;
 410 }
 411
 412 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 413                 struct device_attribute *attr,
 414                 char *buf)
 415 {
 416         struct drm_device *ddev = dev_get_drvdata(dev);
 417         struct amdgpu_device *adev = drm_to_adev(ddev);
 418         struct pp_states_info data;
 419         int i, buf_len, ret;
 420
 421         if (amdgpu_in_reset(adev))
 422                 return -EPERM;
 423
 424         ret = pm_runtime_get_sync(ddev->dev);
 425         if (ret < 0) {
 426                 pm_runtime_put_autosuspend(ddev->dev);
 427                 return ret;
 428         }
 429
 430         if (is_support_sw_smu(adev)) {
 431                 ret = smu_get_power_num_states(&adev->smu, &data);
 432                 if (ret)
 433                         return ret;
 434         } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
 435                 amdgpu_dpm_get_pp_num_states(adev, &data);
 436         } else {
 437                 memset(&data, 0, sizeof(data));
 438         }
 439
 440         pm_runtime_mark_last_busy(ddev->dev);
 441         pm_runtime_put_autosuspend(ddev->dev);
 442
 443         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 444         for (i = 0; i < data.nums; i++)
 445                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 446                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 447                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 448                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 449                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 450
 451         return buf_len;
 452 }
 453
 454 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 455                 struct device_attribute *attr,
 456                 char *buf)
 457 {
 458         struct drm_device *ddev = dev_get_drvdata(dev);
 459         struct amdgpu_device *adev = drm_to_adev(ddev);
 460         struct pp_states_info data;
 461         struct smu_context *smu = &adev->smu;
 462         enum amd_pm_state_type pm = 0;
 463         int i = 0, ret = 0;
 464
 465         if (amdgpu_in_reset(adev))
 466                 return -EPERM;
 467
 468         ret = pm_runtime_get_sync(ddev->dev);
 469         if (ret < 0) {
 470                 pm_runtime_put_autosuspend(ddev->dev);
 471                 return ret;
 472         }
 473
 474         if (is_support_sw_smu(adev)) {
 475                 pm = smu_get_current_power_state(smu);
 476                 ret = smu_get_power_num_states(smu, &data);
 477                 if (ret)
 478                         return ret;
 479         } else if (adev->powerplay.pp_funcs->get_current_power_state
 480                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 481                 pm = amdgpu_dpm_get_current_power_state(adev);
 482                 amdgpu_dpm_get_pp_num_states(adev, &data);
 483         }
 484
 485         pm_runtime_mark_last_busy(ddev->dev);
 486         pm_runtime_put_autosuspend(ddev->dev);
 487
 488         for (i = 0; i < data.nums; i++) {
 489                 if (pm == data.states[i])
 490                         break;
 491         }
 492
 493         if (i == data.nums)
 494                 i = -EINVAL;
 495
 496         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 497 }
 498
 499 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 500                 struct device_attribute *attr,
 501                 char *buf)
 502 {
 503         struct drm_device *ddev = dev_get_drvdata(dev);
 504         struct amdgpu_device *adev = drm_to_adev(ddev);
 505
 506         if (amdgpu_in_reset(adev))
 507                 return -EPERM;
 508
 509         if (adev->pp_force_state_enabled)
 510                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 511         else
 512                 return snprintf(buf, PAGE_SIZE, "\n");
 513 }
 514
 515 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 516                 struct device_attribute *attr,
 517                 const char *buf,
 518                 size_t count)
 519 {
 520         struct drm_device *ddev = dev_get_drvdata(dev);
 521         struct amdgpu_device *adev = drm_to_adev(ddev);
 522         enum amd_pm_state_type state = 0;
 523         unsigned long idx;
 524         int ret;
 525
 526         if (amdgpu_in_reset(adev))
 527                 return -EPERM;
 528
 529         if (strlen(buf) == 1)
 530                 adev->pp_force_state_enabled = false;
 531         else if (is_support_sw_smu(adev))
 532                 adev->pp_force_state_enabled = false;
 533         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 534                         adev->powerplay.pp_funcs->get_pp_num_states) {
 535                 struct pp_states_info data;
 536
 537                 ret = kstrtoul(buf, 0, &idx);
 538                 if (ret || idx >= ARRAY_SIZE(data.states))
 539                         return -EINVAL;
 540
 541                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 542
 543                 amdgpu_dpm_get_pp_num_states(adev, &data);
 544                 state = data.states[idx];
 545
 546                 ret = pm_runtime_get_sync(ddev->dev);
 547                 if (ret < 0) {
 548                         pm_runtime_put_autosuspend(ddev->dev);
 549                         return ret;
 550                 }
 551
 552                 /* only set user selected power states */
 553                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 554                     state != POWER_STATE_TYPE_DEFAULT) {
 555                         amdgpu_dpm_dispatch_task(adev,
 556                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 557                         adev->pp_force_state_enabled = true;
 558                 }
 559                 pm_runtime_mark_last_busy(ddev->dev);
 560                 pm_runtime_put_autosuspend(ddev->dev);
 561         }
 562
 563         return count;
 564 }
 565
 566 /**
 567  * DOC: pp_table
 568  *
 569  * The amdgpu driver provides a sysfs API for uploading new powerplay
 570  * tables.  The file pp_table is used for this.  Reading the file
 571  * will dump the current power play table.  Writing to the file
 572  * will attempt to upload a new powerplay table and re-initialize
 573  * powerplay using that new table.
 574  *
 575  */
 576
 577 static ssize_t amdgpu_get_pp_table(struct device *dev,
 578                 struct device_attribute *attr,
 579                 char *buf)
 580 {
 581         struct drm_device *ddev = dev_get_drvdata(dev);
 582         struct amdgpu_device *adev = drm_to_adev(ddev);
 583         char *table = NULL;
 584         int size, ret;
 585
 586         if (amdgpu_in_reset(adev))
 587                 return -EPERM;
 588
 589         ret = pm_runtime_get_sync(ddev->dev);
 590         if (ret < 0) {
 591                 pm_runtime_put_autosuspend(ddev->dev);
 592                 return ret;
 593         }
 594
 595         if (is_support_sw_smu(adev)) {
 596                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 597                 pm_runtime_mark_last_busy(ddev->dev);
 598                 pm_runtime_put_autosuspend(ddev->dev);
 599                 if (size < 0)
 600                         return size;
 601         } else if (adev->powerplay.pp_funcs->get_pp_table) {
 602                 size = amdgpu_dpm_get_pp_table(adev, &table);
 603                 pm_runtime_mark_last_busy(ddev->dev);
 604                 pm_runtime_put_autosuspend(ddev->dev);
 605                 if (size < 0)
 606                         return size;
 607         } else {
 608                 pm_runtime_mark_last_busy(ddev->dev);
 609                 pm_runtime_put_autosuspend(ddev->dev);
 610                 return 0;
 611         }
 612
 613         if (size >= PAGE_SIZE)
 614                 size = PAGE_SIZE - 1;
 615
 616         memcpy(buf, table, size);
 617
 618         return size;
 619 }
 620
 621 static ssize_t amdgpu_set_pp_table(struct device *dev,
 622                 struct device_attribute *attr,
 623                 const char *buf,
 624                 size_t count)
 625 {
 626         struct drm_device *ddev = dev_get_drvdata(dev);
 627         struct amdgpu_device *adev = drm_to_adev(ddev);
 628         int ret = 0;
 629
 630         if (amdgpu_in_reset(adev))
 631                 return -EPERM;
 632
 633         ret = pm_runtime_get_sync(ddev->dev);
 634         if (ret < 0) {
 635                 pm_runtime_put_autosuspend(ddev->dev);
 636                 return ret;
 637         }
 638
 639         if (is_support_sw_smu(adev)) {
 640                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 641                 if (ret) {
 642                         pm_runtime_mark_last_busy(ddev->dev);
 643                         pm_runtime_put_autosuspend(ddev->dev);
 644                         return ret;
 645                 }
 646         } else if (adev->powerplay.pp_funcs->set_pp_table)
 647                 amdgpu_dpm_set_pp_table(adev, buf, count);
 648
 649         pm_runtime_mark_last_busy(ddev->dev);
 650         pm_runtime_put_autosuspend(ddev->dev);
 651
 652         return count;
 653 }
 654
 655 /**
 656  * DOC: pp_od_clk_voltage
 657  *
 658  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 659  * in each power level within a power state.  The pp_od_clk_voltage is used for
 660  * this.
 661  *
 662  * Note that the actual memory controller clock rate are exposed, not
 663  * the effective memory clock of the DRAMs. To translate it, use the
 664  * following formula:
 665  *
 666  * Clock conversion (Mhz):
 667  *
 668  * HBM: effective_memory_clock = memory_controller_clock * 1
 669  *
 670  * G5: effective_memory_clock = memory_controller_clock * 1
 671  *
 672  * G6: effective_memory_clock = memory_controller_clock * 2
 673  *
 674  * DRAM data rate (MT/s):
 675  *
 676  * HBM: effective_memory_clock * 2 = data_rate
 677  *
 678  * G5: effective_memory_clock * 4 = data_rate
 679  *
 680  * G6: effective_memory_clock * 8 = data_rate
 681  *
 682  * Bandwidth (MB/s):
 683  *
 684  * data_rate * vram_bit_width / 8 = memory_bandwidth
 685  *
 686  * Some examples:
 687  *
 688  * G5 on RX460:
 689  *
 690  * memory_controller_clock = 1750 Mhz
 691  *
 692  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 693  *
 694  * data rate = 1750 * 4 = 7000 MT/s
 695  *
 696  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 697  *
 698  * G6 on RX5700:
 699  *
 700  * memory_controller_clock = 875 Mhz
 701  *
 702  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 703  *
 704  * data rate = 1750 * 8 = 14000 MT/s
 705  *
 706  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 707  *
 708  * < For Vega10 and previous ASICs >
 709  *
 710  * Reading the file will display:
 711  *
 712  * - a list of engine clock levels and voltages labeled OD_SCLK
 713  *
 714  * - a list of memory clock levels and voltages labeled OD_MCLK
 715  *
 716  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 717  *
 718  * To manually adjust these settings, first select manual using
 719  * power_dpm_force_performance_level. Enter a new value for each
 720  * level by writing a string that contains "s/m level clock voltage" to
 721  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 722  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 723  * 810 mV.  When you have edited all of the states as needed, write
 724  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 725  * default power levels, write "r" (reset) to the file to reset them.
 726  *
 727  *
 728  * < For Vega20 and newer ASICs >
 729  *
 730  * Reading the file will display:
 731  *
 732  * - minimum and maximum engine clock labeled OD_SCLK
 733  *
 734  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 735  *   clock labeled OD_MCLK
 736  *
 737  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 738  *   They can be used to calibrate the sclk voltage curve.
 739  *
 740  * - voltage offset(in mV) applied on target voltage calculation.
 741  *   This is available for Sienna Cichlid, Navy Flounder and Dimgrey
 742  *   Cavefish. For these ASICs, the target voltage calculation can be
 743  *   illustrated by "voltage = voltage calculated from v/f curve +
 744  *   overdrive vddgfx offset"
 745  *
 746  * - a list of valid ranges for sclk, mclk, and voltage curve points
 747  *   labeled OD_RANGE
 748  *
 749  * To manually adjust these settings:
 750  *
 751  * - First select manual using power_dpm_force_performance_level
 752  *
 753  * - For clock frequency setting, enter a new value by writing a
 754  *   string that contains "s/m index clock" to the file. The index
 755  *   should be 0 if to set minimum clock. And 1 if to set maximum
 756  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 757  *   "m 1 800" will update maximum mclk to be 800Mhz.
 758  *
 759  *   For sclk voltage curve, enter the new values by writing a
 760  *   string that contains "vc point clock voltage" to the file. The
 761  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 762  *   update point1 with clock set as 300Mhz and voltage as
 763  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 764  *   as 1000Mhz and voltage 1000mV.
 765  *
 766  *   To update the voltage offset applied for gfxclk/voltage calculation,
 767  *   enter the new value by writing a string that contains "vo offset".
 768  *   This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
 769  *   And the offset can be a positive or negative value.
 770  *
 771  * - When you have edited all of the states as needed, write "c" (commit)
 772  *   to the file to commit your changes
 773  *
 774  * - If you want to reset to the default power levels, write "r" (reset)
 775  *   to the file to reset them
 776  *
 777  */
 778
 779 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 780                 struct device_attribute *attr,
 781                 const char *buf,
 782                 size_t count)
 783 {
 784         struct drm_device *ddev = dev_get_drvdata(dev);
 785         struct amdgpu_device *adev = drm_to_adev(ddev);
 786         int ret;
 787         uint32_t parameter_size = 0;
 788         long parameter[64];
 789         char buf_cpy[128];
 790         char *tmp_str;
 791         char *sub_str;
 792         const char delimiter[3] = {' ', '\n', '\0'};
 793         uint32_t type;
 794
 795         if (amdgpu_in_reset(adev))
 796                 return -EPERM;
 797
 798         if (count > 127)
 799                 return -EINVAL;
 800
 801         if (*buf == 's')
 802                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 803         else if (*buf == 'p')
 804                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 805         else if (*buf == 'm')
 806                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 807         else if(*buf == 'r')
 808                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 809         else if (*buf == 'c')
 810                 type = PP_OD_COMMIT_DPM_TABLE;
 811         else if (!strncmp(buf, "vc", 2))
 812                 type = PP_OD_EDIT_VDDC_CURVE;
 813         else if (!strncmp(buf, "vo", 2))
 814                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 815         else
 816                 return -EINVAL;
 817
 818         memcpy(buf_cpy, buf, count+1);
 819
 820         tmp_str = buf_cpy;
 821
 822         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 823              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 824                 tmp_str++;
 825         while (isspace(*++tmp_str));
 826
 827         while (tmp_str[0]) {
 828                 sub_str = strsep(&tmp_str, delimiter);
 829                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 830                 if (ret)
 831                         return -EINVAL;
 832                 parameter_size++;
 833
 834                 while (isspace(*tmp_str))
 835                         tmp_str++;
 836         }
 837
 838         ret = pm_runtime_get_sync(ddev->dev);
 839         if (ret < 0) {
 840                 pm_runtime_put_autosuspend(ddev->dev);
 841                 return ret;
 842         }
 843
 844         if (is_support_sw_smu(adev)) {
 845                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 846                                             parameter, parameter_size);
 847
 848                 if (ret) {
 849                         pm_runtime_mark_last_busy(ddev->dev);
 850                         pm_runtime_put_autosuspend(ddev->dev);
 851                         return -EINVAL;
 852                 }
 853         } else {
 854
 855                 if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
 856                         ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
 857                                                                 parameter,
 858                                                                 parameter_size);
 859                         if (ret) {
 860                                 pm_runtime_mark_last_busy(ddev->dev);
 861                                 pm_runtime_put_autosuspend(ddev->dev);
 862                                 return -EINVAL;
 863                         }
 864                 }
 865
 866                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 867                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 868                                                 parameter, parameter_size);
 869                         if (ret) {
 870                                 pm_runtime_mark_last_busy(ddev->dev);
 871                                 pm_runtime_put_autosuspend(ddev->dev);
 872                                 return -EINVAL;
 873                         }
 874                 }
 875
 876                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 877                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 878                                 amdgpu_dpm_dispatch_task(adev,
 879                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 880                                                 NULL);
 881                                 pm_runtime_mark_last_busy(ddev->dev);
 882                                 pm_runtime_put_autosuspend(ddev->dev);
 883                                 return count;
 884                         } else {
 885                                 pm_runtime_mark_last_busy(ddev->dev);
 886                                 pm_runtime_put_autosuspend(ddev->dev);
 887                                 return -EINVAL;
 888                         }
 889                 }
 890         }
 891         pm_runtime_mark_last_busy(ddev->dev);
 892         pm_runtime_put_autosuspend(ddev->dev);
 893
 894         return count;
 895 }
 896
 897 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 898                 struct device_attribute *attr,
 899                 char *buf)
 900 {
 901         struct drm_device *ddev = dev_get_drvdata(dev);
 902         struct amdgpu_device *adev = drm_to_adev(ddev);
 903         ssize_t size;
 904         int ret;
 905
 906         if (amdgpu_in_reset(adev))
 907                 return -EPERM;
 908
 909         ret = pm_runtime_get_sync(ddev->dev);
 910         if (ret < 0) {
 911                 pm_runtime_put_autosuspend(ddev->dev);
 912                 return ret;
 913         }
 914
 915         if (is_support_sw_smu(adev)) {
 916                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 917                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 918                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 919                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDGFX_OFFSET, buf+size);
 920                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 921                 size += smu_print_clk_levels(&adev->smu, SMU_OD_CCLK, buf+size);
 922         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 923                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 924                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 925                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 926                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 927         } else {
 928                 size = snprintf(buf, PAGE_SIZE, "\n");
 929         }
 930         pm_runtime_mark_last_busy(ddev->dev);
 931         pm_runtime_put_autosuspend(ddev->dev);
 932
 933         return size;
 934 }
 935
 936 /**
 937  * DOC: pp_features
 938  *
 939  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 940  * features to be enabled. The file pp_features is used for this. And
 941  * this is only available for Vega10 and later dGPUs.
 942  *
 943  * Reading back the file will show you the followings:
 944  * - Current ppfeature masks
 945  * - List of the all supported powerplay features with their naming,
 946  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 947  *
 948  * To manually enable or disable a specific feature, just set or clear
 949  * the corresponding bit from original ppfeature masks and input the
 950  * new ppfeature masks.
 951  */
 952 static ssize_t amdgpu_set_pp_features(struct device *dev,
 953                                       struct device_attribute *attr,
 954                                       const char *buf,
 955                                       size_t count)
 956 {
 957         struct drm_device *ddev = dev_get_drvdata(dev);
 958         struct amdgpu_device *adev = drm_to_adev(ddev);
 959         uint64_t featuremask;
 960         int ret;
 961
 962         if (amdgpu_in_reset(adev))
 963                 return -EPERM;
 964
 965         ret = kstrtou64(buf, 0, &featuremask);
 966         if (ret)
 967                 return -EINVAL;
 968
 969         ret = pm_runtime_get_sync(ddev->dev);
 970         if (ret < 0) {
 971                 pm_runtime_put_autosuspend(ddev->dev);
 972                 return ret;
 973         }
 974
 975         if (is_support_sw_smu(adev)) {
 976                 ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 977                 if (ret) {
 978                         pm_runtime_mark_last_busy(ddev->dev);
 979                         pm_runtime_put_autosuspend(ddev->dev);
 980                         return -EINVAL;
 981                 }
 982         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 983                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 984                 if (ret) {
 985                         pm_runtime_mark_last_busy(ddev->dev);
 986                         pm_runtime_put_autosuspend(ddev->dev);
 987                         return -EINVAL;
 988                 }
 989         }
 990         pm_runtime_mark_last_busy(ddev->dev);
 991         pm_runtime_put_autosuspend(ddev->dev);
 992
 993         return count;
 994 }
 995
 996 static ssize_t amdgpu_get_pp_features(struct device *dev,
 997                                       struct device_attribute *attr,
 998                                       char *buf)
 999 {
1000         struct drm_device *ddev = dev_get_drvdata(dev);
1001         struct amdgpu_device *adev = drm_to_adev(ddev);
1002         ssize_t size;
1003         int ret;
1004
1005         if (amdgpu_in_reset(adev))
1006                 return -EPERM;
1007
1008         ret = pm_runtime_get_sync(ddev->dev);
1009         if (ret < 0) {
1010                 pm_runtime_put_autosuspend(ddev->dev);
1011                 return ret;
1012         }
1013
1014         if (is_support_sw_smu(adev))
1015                 size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
1016         else if (adev->powerplay.pp_funcs->get_ppfeature_status)
1017                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
1018         else
1019                 size = snprintf(buf, PAGE_SIZE, "\n");
1020
1021         pm_runtime_mark_last_busy(ddev->dev);
1022         pm_runtime_put_autosuspend(ddev->dev);
1023
1024         return size;
1025 }
1026
1027 /**
1028  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
1029  *
1030  * The amdgpu driver provides a sysfs API for adjusting what power levels
1031  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
1032  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
1033  * this.
1034  *
1035  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
1036  * Vega10 and later ASICs.
1037  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
1038  *
1039  * Reading back the files will show you the available power levels within
1040  * the power state and the clock information for those levels.
1041  *
1042  * To manually adjust these states, first select manual using
1043  * power_dpm_force_performance_level.
1044  * Secondly, enter a new value for each level by inputing a string that
1045  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1046  * E.g.,
1047  *
1048  * .. code-block:: bash
1049  *
1050  *      echo "4 5 6" > pp_dpm_sclk
1051  *
1052  * will enable sclk levels 4, 5, and 6.
1053  *
1054  * NOTE: change to the dcefclk max dpm level is not supported now
1055  */
1056
1057 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1058                 struct device_attribute *attr,
1059                 char *buf)
1060 {
1061         struct drm_device *ddev = dev_get_drvdata(dev);
1062         struct amdgpu_device *adev = drm_to_adev(ddev);
1063         ssize_t size;
1064         int ret;
1065
1066         if (amdgpu_in_reset(adev))
1067                 return -EPERM;
1068
1069         ret = pm_runtime_get_sync(ddev->dev);
1070         if (ret < 0) {
1071                 pm_runtime_put_autosuspend(ddev->dev);
1072                 return ret;
1073         }
1074
1075         if (is_support_sw_smu(adev))
1076                 size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
1077         else if (adev->powerplay.pp_funcs->print_clock_levels)
1078                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
1079         else
1080                 size = snprintf(buf, PAGE_SIZE, "\n");
1081
1082         pm_runtime_mark_last_busy(ddev->dev);
1083         pm_runtime_put_autosuspend(ddev->dev);
1084
1085         return size;
1086 }
1087
1088 /*
1089  * Worst case: 32 bits individually specified, in octal at 12 characters
1090  * per line (+1 for \n).
1091  */
1092 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1093
1094 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1095 {
1096         int ret;
1097         long level;
1098         char *sub_str = NULL;
1099         char *tmp;
1100         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1101         const char delimiter[3] = {' ', '\n', '\0'};
1102         size_t bytes;
1103
1104         *mask = 0;
1105
1106         bytes = min(count, sizeof(buf_cpy) - 1);
1107         memcpy(buf_cpy, buf, bytes);
1108         buf_cpy[bytes] = '\0';
1109         tmp = buf_cpy;
1110         while (tmp[0]) {
1111                 sub_str = strsep(&tmp, delimiter);
1112                 if (strlen(sub_str)) {
1113                         ret = kstrtol(sub_str, 0, &level);
1114                         if (ret)
1115                                 return -EINVAL;
1116                         *mask |= 1 << level;
1117                 } else
1118                         break;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1125                 struct device_attribute *attr,
1126                 const char *buf,
1127                 size_t count)
1128 {
1129         struct drm_device *ddev = dev_get_drvdata(dev);
1130         struct amdgpu_device *adev = drm_to_adev(ddev);
1131         int ret;
1132         uint32_t mask = 0;
1133
1134         if (amdgpu_in_reset(adev))
1135                 return -EPERM;
1136
1137         ret = amdgpu_read_mask(buf, count, &mask);
1138         if (ret)
1139                 return ret;
1140
1141         ret = pm_runtime_get_sync(ddev->dev);
1142         if (ret < 0) {
1143                 pm_runtime_put_autosuspend(ddev->dev);
1144                 return ret;
1145         }
1146
1147         if (is_support_sw_smu(adev))
1148                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
1149         else if (adev->powerplay.pp_funcs->force_clock_level)
1150                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
1151
1152         pm_runtime_mark_last_busy(ddev->dev);
1153         pm_runtime_put_autosuspend(ddev->dev);
1154
1155         if (ret)
1156                 return -EINVAL;
1157
1158         return count;
1159 }
1160
1161 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1162                 struct device_attribute *attr,
1163                 char *buf)
1164 {
1165         struct drm_device *ddev = dev_get_drvdata(dev);
1166         struct amdgpu_device *adev = drm_to_adev(ddev);
1167         ssize_t size;
1168         int ret;
1169
1170         if (amdgpu_in_reset(adev))
1171                 return -EPERM;
1172
1173         ret = pm_runtime_get_sync(ddev->dev);
1174         if (ret < 0) {
1175                 pm_runtime_put_autosuspend(ddev->dev);
1176                 return ret;
1177         }
1178
1179         if (is_support_sw_smu(adev))
1180                 size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
1181         else if (adev->powerplay.pp_funcs->print_clock_levels)
1182                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
1183         else
1184                 size = snprintf(buf, PAGE_SIZE, "\n");
1185
1186         pm_runtime_mark_last_busy(ddev->dev);
1187         pm_runtime_put_autosuspend(ddev->dev);
1188
1189         return size;
1190 }
1191
1192 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1193                 struct device_attribute *attr,
1194                 const char *buf,
1195                 size_t count)
1196 {
1197         struct drm_device *ddev = dev_get_drvdata(dev);
1198         struct amdgpu_device *adev = drm_to_adev(ddev);
1199         uint32_t mask = 0;
1200         int ret;
1201
1202         if (amdgpu_in_reset(adev))
1203                 return -EPERM;
1204
1205         ret = amdgpu_read_mask(buf, count, &mask);
1206         if (ret)
1207                 return ret;
1208
1209         ret = pm_runtime_get_sync(ddev->dev);
1210         if (ret < 0) {
1211                 pm_runtime_put_autosuspend(ddev->dev);
1212                 return ret;
1213         }
1214
1215         if (is_support_sw_smu(adev))
1216                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
1217         else if (adev->powerplay.pp_funcs->force_clock_level)
1218                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
1219
1220         pm_runtime_mark_last_busy(ddev->dev);
1221         pm_runtime_put_autosuspend(ddev->dev);
1222
1223         if (ret)
1224                 return -EINVAL;
1225
1226         return count;
1227 }
1228
1229 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1230                 struct device_attribute *attr,
1231                 char *buf)
1232 {
1233         struct drm_device *ddev = dev_get_drvdata(dev);
1234         struct amdgpu_device *adev = drm_to_adev(ddev);
1235         ssize_t size;
1236         int ret;
1237
1238         if (amdgpu_in_reset(adev))
1239                 return -EPERM;
1240
1241         ret = pm_runtime_get_sync(ddev->dev);
1242         if (ret < 0) {
1243                 pm_runtime_put_autosuspend(ddev->dev);
1244                 return ret;
1245         }
1246
1247         if (is_support_sw_smu(adev))
1248                 size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
1249         else if (adev->powerplay.pp_funcs->print_clock_levels)
1250                 size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
1251         else
1252                 size = snprintf(buf, PAGE_SIZE, "\n");
1253
1254         pm_runtime_mark_last_busy(ddev->dev);
1255         pm_runtime_put_autosuspend(ddev->dev);
1256
1257         return size;
1258 }
1259
1260 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1261                 struct device_attribute *attr,
1262                 const char *buf,
1263                 size_t count)
1264 {
1265         struct drm_device *ddev = dev_get_drvdata(dev);
1266         struct amdgpu_device *adev = drm_to_adev(ddev);
1267         int ret;
1268         uint32_t mask = 0;
1269
1270         if (amdgpu_in_reset(adev))
1271                 return -EPERM;
1272
1273         ret = amdgpu_read_mask(buf, count, &mask);
1274         if (ret)
1275                 return ret;
1276
1277         ret = pm_runtime_get_sync(ddev->dev);
1278         if (ret < 0) {
1279                 pm_runtime_put_autosuspend(ddev->dev);
1280                 return ret;
1281         }
1282
1283         if (is_support_sw_smu(adev))
1284                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
1285         else if (adev->powerplay.pp_funcs->force_clock_level)
1286                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
1287         else
1288                 ret = 0;
1289
1290         pm_runtime_mark_last_busy(ddev->dev);
1291         pm_runtime_put_autosuspend(ddev->dev);
1292
1293         if (ret)
1294                 return -EINVAL;
1295
1296         return count;
1297 }
1298
1299 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1300                 struct device_attribute *attr,
1301                 char *buf)
1302 {
1303         struct drm_device *ddev = dev_get_drvdata(dev);
1304         struct amdgpu_device *adev = drm_to_adev(ddev);
1305         ssize_t size;
1306         int ret;
1307
1308         if (amdgpu_in_reset(adev))
1309                 return -EPERM;
1310
1311         ret = pm_runtime_get_sync(ddev->dev);
1312         if (ret < 0) {
1313                 pm_runtime_put_autosuspend(ddev->dev);
1314                 return ret;
1315         }
1316
1317         if (is_support_sw_smu(adev))
1318                 size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1319         else if (adev->powerplay.pp_funcs->print_clock_levels)
1320                 size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1321         else
1322                 size = snprintf(buf, PAGE_SIZE, "\n");
1323
1324         pm_runtime_mark_last_busy(ddev->dev);
1325         pm_runtime_put_autosuspend(ddev->dev);
1326
1327         return size;
1328 }
1329
1330 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1331                 struct device_attribute *attr,
1332                 const char *buf,
1333                 size_t count)
1334 {
1335         struct drm_device *ddev = dev_get_drvdata(dev);
1336         struct amdgpu_device *adev = drm_to_adev(ddev);
1337         int ret;
1338         uint32_t mask = 0;
1339
1340         if (amdgpu_in_reset(adev))
1341                 return -EPERM;
1342
1343         ret = amdgpu_read_mask(buf, count, &mask);
1344         if (ret)
1345                 return ret;
1346
1347         ret = pm_runtime_get_sync(ddev->dev);
1348         if (ret < 0) {
1349                 pm_runtime_put_autosuspend(ddev->dev);
1350                 return ret;
1351         }
1352
1353         if (is_support_sw_smu(adev))
1354                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
1355         else if (adev->powerplay.pp_funcs->force_clock_level)
1356                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1357         else
1358                 ret = 0;
1359
1360         pm_runtime_mark_last_busy(ddev->dev);
1361         pm_runtime_put_autosuspend(ddev->dev);
1362
1363         if (ret)
1364                 return -EINVAL;
1365
1366         return count;
1367 }
1368
1369 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1370                 struct device_attribute *attr,
1371                 char *buf)
1372 {
1373         struct drm_device *ddev = dev_get_drvdata(dev);
1374         struct amdgpu_device *adev = drm_to_adev(ddev);
1375         ssize_t size;
1376         int ret;
1377
1378         if (amdgpu_in_reset(adev))
1379                 return -EPERM;
1380
1381         ret = pm_runtime_get_sync(ddev->dev);
1382         if (ret < 0) {
1383                 pm_runtime_put_autosuspend(ddev->dev);
1384                 return ret;
1385         }
1386
1387         if (is_support_sw_smu(adev))
1388                 size = smu_print_clk_levels(&adev->smu, SMU_VCLK, buf);
1389         else
1390                 size = snprintf(buf, PAGE_SIZE, "\n");
1391
1392         pm_runtime_mark_last_busy(ddev->dev);
1393         pm_runtime_put_autosuspend(ddev->dev);
1394
1395         return size;
1396 }
1397
1398 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1399                 struct device_attribute *attr,
1400                 const char *buf,
1401                 size_t count)
1402 {
1403         struct drm_device *ddev = dev_get_drvdata(dev);
1404         struct amdgpu_device *adev = drm_to_adev(ddev);
1405         int ret;
1406         uint32_t mask = 0;
1407
1408         if (amdgpu_in_reset(adev))
1409                 return -EPERM;
1410
1411         ret = amdgpu_read_mask(buf, count, &mask);
1412         if (ret)
1413                 return ret;
1414
1415         ret = pm_runtime_get_sync(ddev->dev);
1416         if (ret < 0) {
1417                 pm_runtime_put_autosuspend(ddev->dev);
1418                 return ret;
1419         }
1420
1421         if (is_support_sw_smu(adev))
1422                 ret = smu_force_clk_levels(&adev->smu, SMU_VCLK, mask);
1423         else
1424                 ret = 0;
1425
1426         pm_runtime_mark_last_busy(ddev->dev);
1427         pm_runtime_put_autosuspend(ddev->dev);
1428
1429         if (ret)
1430                 return -EINVAL;
1431
1432         return count;
1433 }
1434
1435 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1436                 struct device_attribute *attr,
1437                 char *buf)
1438 {
1439         struct drm_device *ddev = dev_get_drvdata(dev);
1440         struct amdgpu_device *adev = drm_to_adev(ddev);
1441         ssize_t size;
1442         int ret;
1443
1444         if (amdgpu_in_reset(adev))
1445                 return -EPERM;
1446
1447         ret = pm_runtime_get_sync(ddev->dev);
1448         if (ret < 0) {
1449                 pm_runtime_put_autosuspend(ddev->dev);
1450                 return ret;
1451         }
1452
1453         if (is_support_sw_smu(adev))
1454                 size = smu_print_clk_levels(&adev->smu, SMU_DCLK, buf);
1455         else
1456                 size = snprintf(buf, PAGE_SIZE, "\n");
1457
1458         pm_runtime_mark_last_busy(ddev->dev);
1459         pm_runtime_put_autosuspend(ddev->dev);
1460
1461         return size;
1462 }
1463
1464 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1465                 struct device_attribute *attr,
1466                 const char *buf,
1467                 size_t count)
1468 {
1469         struct drm_device *ddev = dev_get_drvdata(dev);
1470         struct amdgpu_device *adev = drm_to_adev(ddev);
1471         int ret;
1472         uint32_t mask = 0;
1473
1474         if (amdgpu_in_reset(adev))
1475                 return -EPERM;
1476
1477         ret = amdgpu_read_mask(buf, count, &mask);
1478         if (ret)
1479                 return ret;
1480
1481         ret = pm_runtime_get_sync(ddev->dev);
1482         if (ret < 0) {
1483                 pm_runtime_put_autosuspend(ddev->dev);
1484                 return ret;
1485         }
1486
1487         if (is_support_sw_smu(adev))
1488                 ret = smu_force_clk_levels(&adev->smu, SMU_DCLK, mask);
1489         else
1490                 ret = 0;
1491
1492         pm_runtime_mark_last_busy(ddev->dev);
1493         pm_runtime_put_autosuspend(ddev->dev);
1494
1495         if (ret)
1496                 return -EINVAL;
1497
1498         return count;
1499 }
1500
1501 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1502                 struct device_attribute *attr,
1503                 char *buf)
1504 {
1505         struct drm_device *ddev = dev_get_drvdata(dev);
1506         struct amdgpu_device *adev = drm_to_adev(ddev);
1507         ssize_t size;
1508         int ret;
1509
1510         if (amdgpu_in_reset(adev))
1511                 return -EPERM;
1512
1513         ret = pm_runtime_get_sync(ddev->dev);
1514         if (ret < 0) {
1515                 pm_runtime_put_autosuspend(ddev->dev);
1516                 return ret;
1517         }
1518
1519         if (is_support_sw_smu(adev))
1520                 size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1521         else if (adev->powerplay.pp_funcs->print_clock_levels)
1522                 size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1523         else
1524                 size = snprintf(buf, PAGE_SIZE, "\n");
1525
1526         pm_runtime_mark_last_busy(ddev->dev);
1527         pm_runtime_put_autosuspend(ddev->dev);
1528
1529         return size;
1530 }
1531
1532 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1533                 struct device_attribute *attr,
1534                 const char *buf,
1535                 size_t count)
1536 {
1537         struct drm_device *ddev = dev_get_drvdata(dev);
1538         struct amdgpu_device *adev = drm_to_adev(ddev);
1539         int ret;
1540         uint32_t mask = 0;
1541
1542         if (amdgpu_in_reset(adev))
1543                 return -EPERM;
1544
1545         ret = amdgpu_read_mask(buf, count, &mask);
1546         if (ret)
1547                 return ret;
1548
1549         ret = pm_runtime_get_sync(ddev->dev);
1550         if (ret < 0) {
1551                 pm_runtime_put_autosuspend(ddev->dev);
1552                 return ret;
1553         }
1554
1555         if (is_support_sw_smu(adev))
1556                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
1557         else if (adev->powerplay.pp_funcs->force_clock_level)
1558                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1559         else
1560                 ret = 0;
1561
1562         pm_runtime_mark_last_busy(ddev->dev);
1563         pm_runtime_put_autosuspend(ddev->dev);
1564
1565         if (ret)
1566                 return -EINVAL;
1567
1568         return count;
1569 }
1570
1571 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1572                 struct device_attribute *attr,
1573                 char *buf)
1574 {
1575         struct drm_device *ddev = dev_get_drvdata(dev);
1576         struct amdgpu_device *adev = drm_to_adev(ddev);
1577         ssize_t size;
1578         int ret;
1579
1580         if (amdgpu_in_reset(adev))
1581                 return -EPERM;
1582
1583         ret = pm_runtime_get_sync(ddev->dev);
1584         if (ret < 0) {
1585                 pm_runtime_put_autosuspend(ddev->dev);
1586                 return ret;
1587         }
1588
1589         if (is_support_sw_smu(adev))
1590                 size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1591         else if (adev->powerplay.pp_funcs->print_clock_levels)
1592                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1593         else
1594                 size = snprintf(buf, PAGE_SIZE, "\n");
1595
1596         pm_runtime_mark_last_busy(ddev->dev);
1597         pm_runtime_put_autosuspend(ddev->dev);
1598
1599         return size;
1600 }
1601
1602 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1603                 struct device_attribute *attr,
1604                 const char *buf,
1605                 size_t count)
1606 {
1607         struct drm_device *ddev = dev_get_drvdata(dev);
1608         struct amdgpu_device *adev = drm_to_adev(ddev);
1609         int ret;
1610         uint32_t mask = 0;
1611
1612         if (amdgpu_in_reset(adev))
1613                 return -EPERM;
1614
1615         ret = amdgpu_read_mask(buf, count, &mask);
1616         if (ret)
1617                 return ret;
1618
1619         ret = pm_runtime_get_sync(ddev->dev);
1620         if (ret < 0) {
1621                 pm_runtime_put_autosuspend(ddev->dev);
1622                 return ret;
1623         }
1624
1625         if (is_support_sw_smu(adev))
1626                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
1627         else if (adev->powerplay.pp_funcs->force_clock_level)
1628                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1629         else
1630                 ret = 0;
1631
1632         pm_runtime_mark_last_busy(ddev->dev);
1633         pm_runtime_put_autosuspend(ddev->dev);
1634
1635         if (ret)
1636                 return -EINVAL;
1637
1638         return count;
1639 }
1640
1641 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1642                 struct device_attribute *attr,
1643                 char *buf)
1644 {
1645         struct drm_device *ddev = dev_get_drvdata(dev);
1646         struct amdgpu_device *adev = drm_to_adev(ddev);
1647         uint32_t value = 0;
1648         int ret;
1649
1650         if (amdgpu_in_reset(adev))
1651                 return -EPERM;
1652
1653         ret = pm_runtime_get_sync(ddev->dev);
1654         if (ret < 0) {
1655                 pm_runtime_put_autosuspend(ddev->dev);
1656                 return ret;
1657         }
1658
1659         if (is_support_sw_smu(adev))
1660                 value = 0;
1661         else if (adev->powerplay.pp_funcs->get_sclk_od)
1662                 value = amdgpu_dpm_get_sclk_od(adev);
1663
1664         pm_runtime_mark_last_busy(ddev->dev);
1665         pm_runtime_put_autosuspend(ddev->dev);
1666
1667         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1668 }
1669
1670 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1671                 struct device_attribute *attr,
1672                 const char *buf,
1673                 size_t count)
1674 {
1675         struct drm_device *ddev = dev_get_drvdata(dev);
1676         struct amdgpu_device *adev = drm_to_adev(ddev);
1677         int ret;
1678         long int value;
1679
1680         if (amdgpu_in_reset(adev))
1681                 return -EPERM;
1682
1683         ret = kstrtol(buf, 0, &value);
1684
1685         if (ret)
1686                 return -EINVAL;
1687
1688         ret = pm_runtime_get_sync(ddev->dev);
1689         if (ret < 0) {
1690                 pm_runtime_put_autosuspend(ddev->dev);
1691                 return ret;
1692         }
1693
1694         if (is_support_sw_smu(adev)) {
1695                 value = 0;
1696         } else {
1697                 if (adev->powerplay.pp_funcs->set_sclk_od)
1698                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1699
1700                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1701                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1702                 } else {
1703                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1704                         amdgpu_pm_compute_clocks(adev);
1705                 }
1706         }
1707
1708         pm_runtime_mark_last_busy(ddev->dev);
1709         pm_runtime_put_autosuspend(ddev->dev);
1710
1711         return count;
1712 }
1713
1714 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1715                 struct device_attribute *attr,
1716                 char *buf)
1717 {
1718         struct drm_device *ddev = dev_get_drvdata(dev);
1719         struct amdgpu_device *adev = drm_to_adev(ddev);
1720         uint32_t value = 0;
1721         int ret;
1722
1723         if (amdgpu_in_reset(adev))
1724                 return -EPERM;
1725
1726         ret = pm_runtime_get_sync(ddev->dev);
1727         if (ret < 0) {
1728                 pm_runtime_put_autosuspend(ddev->dev);
1729                 return ret;
1730         }
1731
1732         if (is_support_sw_smu(adev))
1733                 value = 0;
1734         else if (adev->powerplay.pp_funcs->get_mclk_od)
1735                 value = amdgpu_dpm_get_mclk_od(adev);
1736
1737         pm_runtime_mark_last_busy(ddev->dev);
1738         pm_runtime_put_autosuspend(ddev->dev);
1739
1740         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1741 }
1742
1743 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1744                 struct device_attribute *attr,
1745                 const char *buf,
1746                 size_t count)
1747 {
1748         struct drm_device *ddev = dev_get_drvdata(dev);
1749         struct amdgpu_device *adev = drm_to_adev(ddev);
1750         int ret;
1751         long int value;
1752
1753         if (amdgpu_in_reset(adev))
1754                 return -EPERM;
1755
1756         ret = kstrtol(buf, 0, &value);
1757
1758         if (ret)
1759                 return -EINVAL;
1760
1761         ret = pm_runtime_get_sync(ddev->dev);
1762         if (ret < 0) {
1763                 pm_runtime_put_autosuspend(ddev->dev);
1764                 return ret;
1765         }
1766
1767         if (is_support_sw_smu(adev)) {
1768                 value = 0;
1769         } else {
1770                 if (adev->powerplay.pp_funcs->set_mclk_od)
1771                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1772
1773                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1774                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1775                 } else {
1776                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1777                         amdgpu_pm_compute_clocks(adev);
1778                 }
1779         }
1780
1781         pm_runtime_mark_last_busy(ddev->dev);
1782         pm_runtime_put_autosuspend(ddev->dev);
1783
1784         return count;
1785 }
1786
1787 /**
1788  * DOC: pp_power_profile_mode
1789  *
1790  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1791  * related to switching between power levels in a power state.  The file
1792  * pp_power_profile_mode is used for this.
1793  *
1794  * Reading this file outputs a list of all of the predefined power profiles
1795  * and the relevant heuristics settings for that profile.
1796  *
1797  * To select a profile or create a custom profile, first select manual using
1798  * power_dpm_force_performance_level.  Writing the number of a predefined
1799  * profile to pp_power_profile_mode will enable those heuristics.  To
1800  * create a custom set of heuristics, write a string of numbers to the file
1801  * starting with the number of the custom profile along with a setting
1802  * for each heuristic parameter.  Due to differences across asic families
1803  * the heuristic parameters vary from family to family.
1804  *
1805  */
1806
1807 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1808                 struct device_attribute *attr,
1809                 char *buf)
1810 {
1811         struct drm_device *ddev = dev_get_drvdata(dev);
1812         struct amdgpu_device *adev = drm_to_adev(ddev);
1813         ssize_t size;
1814         int ret;
1815
1816         if (amdgpu_in_reset(adev))
1817                 return -EPERM;
1818
1819         ret = pm_runtime_get_sync(ddev->dev);
1820         if (ret < 0) {
1821                 pm_runtime_put_autosuspend(ddev->dev);
1822                 return ret;
1823         }
1824
1825         if (is_support_sw_smu(adev))
1826                 size = smu_get_power_profile_mode(&adev->smu, buf);
1827         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1828                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1829         else
1830                 size = snprintf(buf, PAGE_SIZE, "\n");
1831
1832         pm_runtime_mark_last_busy(ddev->dev);
1833         pm_runtime_put_autosuspend(ddev->dev);
1834
1835         return size;
1836 }
1837
1838
1839 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1840                 struct device_attribute *attr,
1841                 const char *buf,
1842                 size_t count)
1843 {
1844         int ret;
1845         struct drm_device *ddev = dev_get_drvdata(dev);
1846         struct amdgpu_device *adev = drm_to_adev(ddev);
1847         uint32_t parameter_size = 0;
1848         long parameter[64];
1849         char *sub_str, buf_cpy[128];
1850         char *tmp_str;
1851         uint32_t i = 0;
1852         char tmp[2];
1853         long int profile_mode = 0;
1854         const char delimiter[3] = {' ', '\n', '\0'};
1855
1856         if (amdgpu_in_reset(adev))
1857                 return -EPERM;
1858
1859         tmp[0] = *(buf);
1860         tmp[1] = '\0';
1861         ret = kstrtol(tmp, 0, &profile_mode);
1862         if (ret)
1863                 return -EINVAL;
1864
1865         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1866                 if (count < 2 || count > 127)
1867                         return -EINVAL;
1868                 while (isspace(*++buf))
1869                         i++;
1870                 memcpy(buf_cpy, buf, count-i);
1871                 tmp_str = buf_cpy;
1872                 while (tmp_str[0]) {
1873                         sub_str = strsep(&tmp_str, delimiter);
1874                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1875                         if (ret)
1876                                 return -EINVAL;
1877                         parameter_size++;
1878                         while (isspace(*tmp_str))
1879                                 tmp_str++;
1880                 }
1881         }
1882         parameter[parameter_size] = profile_mode;
1883
1884         ret = pm_runtime_get_sync(ddev->dev);
1885         if (ret < 0) {
1886                 pm_runtime_put_autosuspend(ddev->dev);
1887                 return ret;
1888         }
1889
1890         if (is_support_sw_smu(adev))
1891                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
1892         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1893                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1894
1895         pm_runtime_mark_last_busy(ddev->dev);
1896         pm_runtime_put_autosuspend(ddev->dev);
1897
1898         if (!ret)
1899                 return count;
1900
1901         return -EINVAL;
1902 }
1903
1904 /**
1905  * DOC: gpu_busy_percent
1906  *
1907  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1908  * is as a percentage.  The file gpu_busy_percent is used for this.
1909  * The SMU firmware computes a percentage of load based on the
1910  * aggregate activity level in the IP cores.
1911  */
1912 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1913                                            struct device_attribute *attr,
1914                                            char *buf)
1915 {
1916         struct drm_device *ddev = dev_get_drvdata(dev);
1917         struct amdgpu_device *adev = drm_to_adev(ddev);
1918         int r, value, size = sizeof(value);
1919
1920         if (amdgpu_in_reset(adev))
1921                 return -EPERM;
1922
1923         r = pm_runtime_get_sync(ddev->dev);
1924         if (r < 0) {
1925                 pm_runtime_put_autosuspend(ddev->dev);
1926                 return r;
1927         }
1928
1929         /* read the IP busy sensor */
1930         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1931                                    (void *)&value, &size);
1932
1933         pm_runtime_mark_last_busy(ddev->dev);
1934         pm_runtime_put_autosuspend(ddev->dev);
1935
1936         if (r)
1937                 return r;
1938
1939         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1940 }
1941
1942 /**
1943  * DOC: mem_busy_percent
1944  *
1945  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1946  * is as a percentage.  The file mem_busy_percent is used for this.
1947  * The SMU firmware computes a percentage of load based on the
1948  * aggregate activity level in the IP cores.
1949  */
1950 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1951                                            struct device_attribute *attr,
1952                                            char *buf)
1953 {
1954         struct drm_device *ddev = dev_get_drvdata(dev);
1955         struct amdgpu_device *adev = drm_to_adev(ddev);
1956         int r, value, size = sizeof(value);
1957
1958         if (amdgpu_in_reset(adev))
1959                 return -EPERM;
1960
1961         r = pm_runtime_get_sync(ddev->dev);
1962         if (r < 0) {
1963                 pm_runtime_put_autosuspend(ddev->dev);
1964                 return r;
1965         }
1966
1967         /* read the IP busy sensor */
1968         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1969                                    (void *)&value, &size);
1970
1971         pm_runtime_mark_last_busy(ddev->dev);
1972         pm_runtime_put_autosuspend(ddev->dev);
1973
1974         if (r)
1975                 return r;
1976
1977         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1978 }
1979
1980 /**
1981  * DOC: pcie_bw
1982  *
1983  * The amdgpu driver provides a sysfs API for estimating how much data
1984  * has been received and sent by the GPU in the last second through PCIe.
1985  * The file pcie_bw is used for this.
1986  * The Perf counters count the number of received and sent messages and return
1987  * those values, as well as the maximum payload size of a PCIe packet (mps).
1988  * Note that it is not possible to easily and quickly obtain the size of each
1989  * packet transmitted, so we output the max payload size (mps) to allow for
1990  * quick estimation of the PCIe bandwidth usage
1991  */
1992 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1993                 struct device_attribute *attr,
1994                 char *buf)
1995 {
1996         struct drm_device *ddev = dev_get_drvdata(dev);
1997         struct amdgpu_device *adev = drm_to_adev(ddev);
1998         uint64_t count0 = 0, count1 = 0;
1999         int ret;
2000
2001         if (amdgpu_in_reset(adev))
2002                 return -EPERM;
2003
2004         if (adev->flags & AMD_IS_APU)
2005                 return -ENODATA;
2006
2007         if (!adev->asic_funcs->get_pcie_usage)
2008                 return -ENODATA;
2009
2010         ret = pm_runtime_get_sync(ddev->dev);
2011         if (ret < 0) {
2012                 pm_runtime_put_autosuspend(ddev->dev);
2013                 return ret;
2014         }
2015
2016         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
2017
2018         pm_runtime_mark_last_busy(ddev->dev);
2019         pm_runtime_put_autosuspend(ddev->dev);
2020
2021         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
2022                         count0, count1, pcie_get_mps(adev->pdev));
2023 }
2024
2025 /**
2026  * DOC: unique_id
2027  *
2028  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
2029  * The file unique_id is used for this.
2030  * This will provide a Unique ID that will persist from machine to machine
2031  *
2032  * NOTE: This will only work for GFX9 and newer. This file will be absent
2033  * on unsupported ASICs (GFX8 and older)
2034  */
2035 static ssize_t amdgpu_get_unique_id(struct device *dev,
2036                 struct device_attribute *attr,
2037                 char *buf)
2038 {
2039         struct drm_device *ddev = dev_get_drvdata(dev);
2040         struct amdgpu_device *adev = drm_to_adev(ddev);
2041
2042         if (amdgpu_in_reset(adev))
2043                 return -EPERM;
2044
2045         if (adev->unique_id)
2046                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
2047
2048         return 0;
2049 }
2050
2051 /**
2052  * DOC: thermal_throttling_logging
2053  *
2054  * Thermal throttling pulls down the clock frequency and thus the performance.
2055  * It's an useful mechanism to protect the chip from overheating. Since it
2056  * impacts performance, the user controls whether it is enabled and if so,
2057  * the log frequency.
2058  *
2059  * Reading back the file shows you the status(enabled or disabled) and
2060  * the interval(in seconds) between each thermal logging.
2061  *
2062  * Writing an integer to the file, sets a new logging interval, in seconds.
2063  * The value should be between 1 and 3600. If the value is less than 1,
2064  * thermal logging is disabled. Values greater than 3600 are ignored.
2065  */
2066 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
2067                                                      struct device_attribute *attr,
2068                                                      char *buf)
2069 {
2070         struct drm_device *ddev = dev_get_drvdata(dev);
2071         struct amdgpu_device *adev = drm_to_adev(ddev);
2072
2073         return snprintf(buf, PAGE_SIZE, "%s: thermal throttling logging %s, with interval %d seconds\n",
2074                         adev_to_drm(adev)->unique,
2075                         atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
2076                         adev->throttling_logging_rs.interval / HZ + 1);
2077 }
2078
2079 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
2080                                                      struct device_attribute *attr,
2081                                                      const char *buf,
2082                                                      size_t count)
2083 {
2084         struct drm_device *ddev = dev_get_drvdata(dev);
2085         struct amdgpu_device *adev = drm_to_adev(ddev);
2086         long throttling_logging_interval;
2087         unsigned long flags;
2088         int ret = 0;
2089
2090         ret = kstrtol(buf, 0, &throttling_logging_interval);
2091         if (ret)
2092                 return ret;
2093
2094         if (throttling_logging_interval > 3600)
2095                 return -EINVAL;
2096
2097         if (throttling_logging_interval > 0) {
2098                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
2099                 /*
2100                  * Reset the ratelimit timer internals.
2101                  * This can effectively restart the timer.
2102                  */
2103                 adev->throttling_logging_rs.interval =
2104                         (throttling_logging_interval - 1) * HZ;
2105                 adev->throttling_logging_rs.begin = 0;
2106                 adev->throttling_logging_rs.printed = 0;
2107                 adev->throttling_logging_rs.missed = 0;
2108                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
2109
2110                 atomic_set(&adev->throttling_logging_enabled, 1);
2111         } else {
2112                 atomic_set(&adev->throttling_logging_enabled, 0);
2113         }
2114
2115         return count;
2116 }
2117
2118 /**
2119  * DOC: gpu_metrics
2120  *
2121  * The amdgpu driver provides a sysfs API for retrieving current gpu
2122  * metrics data. The file gpu_metrics is used for this. Reading the
2123  * file will dump all the current gpu metrics data.
2124  *
2125  * These data include temperature, frequency, engines utilization,
2126  * power consume, throttler status, fan speed and cpu core statistics(
2127  * available for APU only). That's it will give a snapshot of all sensors
2128  * at the same time.
2129  */
2130 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
2131                                       struct device_attribute *attr,
2132                                       char *buf)
2133 {
2134         struct drm_device *ddev = dev_get_drvdata(dev);
2135         struct amdgpu_device *adev = drm_to_adev(ddev);
2136         void *gpu_metrics;
2137         ssize_t size = 0;
2138         int ret;
2139
2140         if (amdgpu_in_reset(adev))
2141                 return -EPERM;
2142
2143         ret = pm_runtime_get_sync(ddev->dev);
2144         if (ret < 0) {
2145                 pm_runtime_put_autosuspend(ddev->dev);
2146                 return ret;
2147         }
2148
2149         if (is_support_sw_smu(adev))
2150                 size = smu_sys_get_gpu_metrics(&adev->smu, &gpu_metrics);
2151         else if (adev->powerplay.pp_funcs->get_gpu_metrics)
2152                 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
2153
2154         if (size <= 0)
2155                 goto out;
2156
2157         if (size >= PAGE_SIZE)
2158                 size = PAGE_SIZE - 1;
2159
2160         memcpy(buf, gpu_metrics, size);
2161
2162 out:
2163         pm_runtime_mark_last_busy(ddev->dev);
2164         pm_runtime_put_autosuspend(ddev->dev);
2165
2166         return size;
2167 }
2168
2169 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2170         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2171         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC),
2172         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC),
2173         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC),
2174         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC),
2175         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC),
2176         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2177         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2178         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2179         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2180         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2181         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2182         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC),
2183         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC),
2184         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2185         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2186         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC),
2187         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2188         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC),
2189         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC),
2190         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2191         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC),
2192         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC),
2193         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC),
2194         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC),
2195 };
2196
2197 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2198                                uint32_t mask, enum amdgpu_device_attr_states *states)
2199 {
2200         struct device_attribute *dev_attr = &attr->dev_attr;
2201         const char *attr_name = dev_attr->attr.name;
2202         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2203         enum amd_asic_type asic_type = adev->asic_type;
2204
2205         if (!(attr->flags & mask)) {
2206                 *states = ATTR_STATE_UNSUPPORTED;
2207                 return 0;
2208         }
2209
2210 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2211
2212         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2213                 if (asic_type < CHIP_VEGA10)
2214                         *states = ATTR_STATE_UNSUPPORTED;
2215         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2216                 if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
2217                         *states = ATTR_STATE_UNSUPPORTED;
2218         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2219                 if (asic_type < CHIP_VEGA20)
2220                         *states = ATTR_STATE_UNSUPPORTED;
2221         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2222                 *states = ATTR_STATE_UNSUPPORTED;
2223                 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2224                     (is_support_sw_smu(adev) && adev->smu.is_apu) ||
2225                         (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2226                         *states = ATTR_STATE_SUPPORTED;
2227         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2228                 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
2229                         *states = ATTR_STATE_UNSUPPORTED;
2230         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2231                 /* PCIe Perf counters won't work on APU nodes */
2232                 if (adev->flags & AMD_IS_APU)
2233                         *states = ATTR_STATE_UNSUPPORTED;
2234         } else if (DEVICE_ATTR_IS(unique_id)) {
2235                 if (asic_type != CHIP_VEGA10 &&
2236                     asic_type != CHIP_VEGA20 &&
2237                     asic_type != CHIP_ARCTURUS)
2238                         *states = ATTR_STATE_UNSUPPORTED;
2239         } else if (DEVICE_ATTR_IS(pp_features)) {
2240                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
2241                         *states = ATTR_STATE_UNSUPPORTED;
2242         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2243                 if (asic_type < CHIP_VEGA12)
2244                         *states = ATTR_STATE_UNSUPPORTED;
2245         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2246                 if (!(asic_type == CHIP_VANGOGH))
2247                         *states = ATTR_STATE_UNSUPPORTED;
2248         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2249                 if (!(asic_type == CHIP_VANGOGH))
2250                         *states = ATTR_STATE_UNSUPPORTED;
2251         }
2252
2253         if (asic_type == CHIP_ARCTURUS) {
2254                 /* Arcturus does not support standalone mclk/socclk/fclk level setting */
2255                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2256                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2257                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2258                         dev_attr->attr.mode &= ~S_IWUGO;
2259                         dev_attr->store = NULL;
2260                 }
2261         }
2262
2263 #undef DEVICE_ATTR_IS
2264
2265         return 0;
2266 }
2267
2268
2269 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2270                                      struct amdgpu_device_attr *attr,
2271                                      uint32_t mask, struct list_head *attr_list)
2272 {
2273         int ret = 0;
2274         struct device_attribute *dev_attr = &attr->dev_attr;
2275         const char *name = dev_attr->attr.name;
2276         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2277         struct amdgpu_device_attr_entry *attr_entry;
2278
2279         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2280                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2281
2282         BUG_ON(!attr);
2283
2284         attr_update = attr->attr_update ? attr_update : default_attr_update;
2285
2286         ret = attr_update(adev, attr, mask, &attr_states);
2287         if (ret) {
2288                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2289                         name, ret);
2290                 return ret;
2291         }
2292
2293         if (attr_states == ATTR_STATE_UNSUPPORTED)
2294                 return 0;
2295
2296         ret = device_create_file(adev->dev, dev_attr);
2297         if (ret) {
2298                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2299                         name, ret);
2300         }
2301
2302         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2303         if (!attr_entry)
2304                 return -ENOMEM;
2305
2306         attr_entry->attr = attr;
2307         INIT_LIST_HEAD(&attr_entry->entry);
2308
2309         list_add_tail(&attr_entry->entry, attr_list);
2310
2311         return ret;
2312 }
2313
2314 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2315 {
2316         struct device_attribute *dev_attr = &attr->dev_attr;
2317
2318         device_remove_file(adev->dev, dev_attr);
2319 }
2320
2321 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2322                                              struct list_head *attr_list);
2323
2324 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2325                                             struct amdgpu_device_attr *attrs,
2326                                             uint32_t counts,
2327                                             uint32_t mask,
2328                                             struct list_head *attr_list)
2329 {
2330         int ret = 0;
2331         uint32_t i = 0;
2332
2333         for (i = 0; i < counts; i++) {
2334                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2335                 if (ret)
2336                         goto failed;
2337         }
2338
2339         return 0;
2340
2341 failed:
2342         amdgpu_device_attr_remove_groups(adev, attr_list);
2343
2344         return ret;
2345 }
2346
2347 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2348                                              struct list_head *attr_list)
2349 {
2350         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2351
2352         if (list_empty(attr_list))
2353                 return ;
2354
2355         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2356                 amdgpu_device_attr_remove(adev, entry->attr);
2357                 list_del(&entry->entry);
2358                 kfree(entry);
2359         }
2360 }
2361
2362 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2363                                       struct device_attribute *attr,
2364                                       char *buf)
2365 {
2366         struct amdgpu_device *adev = dev_get_drvdata(dev);
2367         int channel = to_sensor_dev_attr(attr)->index;
2368         int r, temp = 0, size = sizeof(temp);
2369
2370         if (amdgpu_in_reset(adev))
2371                 return -EPERM;
2372
2373         if (channel >= PP_TEMP_MAX)
2374                 return -EINVAL;
2375
2376         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2377         if (r < 0) {
2378                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2379                 return r;
2380         }
2381
2382         switch (channel) {
2383         case PP_TEMP_JUNCTION:
2384                 /* get current junction temperature */
2385                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2386                                            (void *)&temp, &size);
2387                 break;
2388         case PP_TEMP_EDGE:
2389                 /* get current edge temperature */
2390                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2391                                            (void *)&temp, &size);
2392                 break;
2393         case PP_TEMP_MEM:
2394                 /* get current memory temperature */
2395                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2396                                            (void *)&temp, &size);
2397                 break;
2398         default:
2399                 r = -EINVAL;
2400                 break;
2401         }
2402
2403         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2404         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2405
2406         if (r)
2407                 return r;
2408
2409         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2410 }
2411
2412 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2413                                              struct device_attribute *attr,
2414                                              char *buf)
2415 {
2416         struct amdgpu_device *adev = dev_get_drvdata(dev);
2417         int hyst = to_sensor_dev_attr(attr)->index;
2418         int temp;
2419
2420         if (hyst)
2421                 temp = adev->pm.dpm.thermal.min_temp;
2422         else
2423                 temp = adev->pm.dpm.thermal.max_temp;
2424
2425         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2426 }
2427
2428 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2429                                              struct device_attribute *attr,
2430                                              char *buf)
2431 {
2432         struct amdgpu_device *adev = dev_get_drvdata(dev);
2433         int hyst = to_sensor_dev_attr(attr)->index;
2434         int temp;
2435
2436         if (hyst)
2437                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2438         else
2439                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2440
2441         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2442 }
2443
2444 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2445                                              struct device_attribute *attr,
2446                                              char *buf)
2447 {
2448         struct amdgpu_device *adev = dev_get_drvdata(dev);
2449         int hyst = to_sensor_dev_attr(attr)->index;
2450         int temp;
2451
2452         if (hyst)
2453                 temp = adev->pm.dpm.thermal.min_mem_temp;
2454         else
2455                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2456
2457         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2458 }
2459
2460 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2461                                              struct device_attribute *attr,
2462                                              char *buf)
2463 {
2464         int channel = to_sensor_dev_attr(attr)->index;
2465
2466         if (channel >= PP_TEMP_MAX)
2467                 return -EINVAL;
2468
2469         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
2470 }
2471
2472 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2473                                              struct device_attribute *attr,
2474                                              char *buf)
2475 {
2476         struct amdgpu_device *adev = dev_get_drvdata(dev);
2477         int channel = to_sensor_dev_attr(attr)->index;
2478         int temp = 0;
2479
2480         if (channel >= PP_TEMP_MAX)
2481                 return -EINVAL;
2482
2483         switch (channel) {
2484         case PP_TEMP_JUNCTION:
2485                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2486                 break;
2487         case PP_TEMP_EDGE:
2488                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2489                 break;
2490         case PP_TEMP_MEM:
2491                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2492                 break;
2493         }
2494
2495         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2496 }
2497
2498 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2499                                             struct device_attribute *attr,
2500                                             char *buf)
2501 {
2502         struct amdgpu_device *adev = dev_get_drvdata(dev);
2503         u32 pwm_mode = 0;
2504         int ret;
2505
2506         if (amdgpu_in_reset(adev))
2507                 return -EPERM;
2508
2509         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2510         if (ret < 0) {
2511                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2512                 return ret;
2513         }
2514
2515         if (is_support_sw_smu(adev)) {
2516                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2517         } else {
2518                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2519                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2520                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2521                         return -EINVAL;
2522                 }
2523
2524                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2525         }
2526
2527         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2528         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2529
2530         return sprintf(buf, "%i\n", pwm_mode);
2531 }
2532
2533 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2534                                             struct device_attribute *attr,
2535                                             const char *buf,
2536                                             size_t count)
2537 {
2538         struct amdgpu_device *adev = dev_get_drvdata(dev);
2539         int err, ret;
2540         int value;
2541
2542         if (amdgpu_in_reset(adev))
2543                 return -EPERM;
2544
2545         err = kstrtoint(buf, 10, &value);
2546         if (err)
2547                 return err;
2548
2549         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2550         if (ret < 0) {
2551                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2552                 return ret;
2553         }
2554
2555         if (is_support_sw_smu(adev)) {
2556                 smu_set_fan_control_mode(&adev->smu, value);
2557         } else {
2558                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2559                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2560                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2561                         return -EINVAL;
2562                 }
2563
2564                 amdgpu_dpm_set_fan_control_mode(adev, value);
2565         }
2566
2567         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2568         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2569
2570         return count;
2571 }
2572
2573 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2574                                          struct device_attribute *attr,
2575                                          char *buf)
2576 {
2577         return sprintf(buf, "%i\n", 0);
2578 }
2579
2580 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2581                                          struct device_attribute *attr,
2582                                          char *buf)
2583 {
2584         return sprintf(buf, "%i\n", 255);
2585 }
2586
2587 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2588                                      struct device_attribute *attr,
2589                                      const char *buf, size_t count)
2590 {
2591         struct amdgpu_device *adev = dev_get_drvdata(dev);
2592         int err;
2593         u32 value;
2594         u32 pwm_mode;
2595
2596         if (amdgpu_in_reset(adev))
2597                 return -EPERM;
2598
2599         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2600         if (err < 0) {
2601                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2602                 return err;
2603         }
2604
2605         if (is_support_sw_smu(adev))
2606                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2607         else
2608                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2609
2610         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2611                 pr_info("manual fan speed control should be enabled first\n");
2612                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2613                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2614                 return -EINVAL;
2615         }
2616
2617         err = kstrtou32(buf, 10, &value);
2618         if (err) {
2619                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2620                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2621                 return err;
2622         }
2623
2624         value = (value * 100) / 255;
2625
2626         if (is_support_sw_smu(adev))
2627                 err = smu_set_fan_speed_percent(&adev->smu, value);
2628         else if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2629                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2630         else
2631                 err = -EINVAL;
2632
2633         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2634         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2635
2636         if (err)
2637                 return err;
2638
2639         return count;
2640 }
2641
2642 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2643                                      struct device_attribute *attr,
2644                                      char *buf)
2645 {
2646         struct amdgpu_device *adev = dev_get_drvdata(dev);
2647         int err;
2648         u32 speed = 0;
2649
2650         if (amdgpu_in_reset(adev))
2651                 return -EPERM;
2652
2653         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2654         if (err < 0) {
2655                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2656                 return err;
2657         }
2658
2659         if (is_support_sw_smu(adev))
2660                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
2661         else if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2662                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2663         else
2664                 err = -EINVAL;
2665
2666         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2667         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2668
2669         if (err)
2670                 return err;
2671
2672         speed = (speed * 255) / 100;
2673
2674         return sprintf(buf, "%i\n", speed);
2675 }
2676
2677 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2678                                            struct device_attribute *attr,
2679                                            char *buf)
2680 {
2681         struct amdgpu_device *adev = dev_get_drvdata(dev);
2682         int err;
2683         u32 speed = 0;
2684
2685         if (amdgpu_in_reset(adev))
2686                 return -EPERM;
2687
2688         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2689         if (err < 0) {
2690                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2691                 return err;
2692         }
2693
2694         if (is_support_sw_smu(adev))
2695                 err = smu_get_fan_speed_rpm(&adev->smu, &speed);
2696         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2697                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2698         else
2699                 err = -EINVAL;
2700
2701         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2702         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2703
2704         if (err)
2705                 return err;
2706
2707         return sprintf(buf, "%i\n", speed);
2708 }
2709
2710 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2711                                          struct device_attribute *attr,
2712                                          char *buf)
2713 {
2714         struct amdgpu_device *adev = dev_get_drvdata(dev);
2715         u32 min_rpm = 0;
2716         u32 size = sizeof(min_rpm);
2717         int r;
2718
2719         if (amdgpu_in_reset(adev))
2720                 return -EPERM;
2721
2722         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2723         if (r < 0) {
2724                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2725                 return r;
2726         }
2727
2728         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2729                                    (void *)&min_rpm, &size);
2730
2731         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2732         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2733
2734         if (r)
2735                 return r;
2736
2737         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
2738 }
2739
2740 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2741                                          struct device_attribute *attr,
2742                                          char *buf)
2743 {
2744         struct amdgpu_device *adev = dev_get_drvdata(dev);
2745         u32 max_rpm = 0;
2746         u32 size = sizeof(max_rpm);
2747         int r;
2748
2749         if (amdgpu_in_reset(adev))
2750                 return -EPERM;
2751
2752         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2753         if (r < 0) {
2754                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2755                 return r;
2756         }
2757
2758         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2759                                    (void *)&max_rpm, &size);
2760
2761         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2762         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2763
2764         if (r)
2765                 return r;
2766
2767         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
2768 }
2769
2770 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2771                                            struct device_attribute *attr,
2772                                            char *buf)
2773 {
2774         struct amdgpu_device *adev = dev_get_drvdata(dev);
2775         int err;
2776         u32 rpm = 0;
2777
2778         if (amdgpu_in_reset(adev))
2779                 return -EPERM;
2780
2781         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2782         if (err < 0) {
2783                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2784                 return err;
2785         }
2786
2787         if (is_support_sw_smu(adev))
2788                 err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
2789         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2790                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2791         else
2792                 err = -EINVAL;
2793
2794         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2795         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2796
2797         if (err)
2798                 return err;
2799
2800         return sprintf(buf, "%i\n", rpm);
2801 }
2802
2803 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2804                                      struct device_attribute *attr,
2805                                      const char *buf, size_t count)
2806 {
2807         struct amdgpu_device *adev = dev_get_drvdata(dev);
2808         int err;
2809         u32 value;
2810         u32 pwm_mode;
2811
2812         if (amdgpu_in_reset(adev))
2813                 return -EPERM;
2814
2815         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2816         if (err < 0) {
2817                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2818                 return err;
2819         }
2820
2821         if (is_support_sw_smu(adev))
2822                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2823         else
2824                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2825
2826         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2827                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2828                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2829                 return -ENODATA;
2830         }
2831
2832         err = kstrtou32(buf, 10, &value);
2833         if (err) {
2834                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2835                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2836                 return err;
2837         }
2838
2839         if (is_support_sw_smu(adev))
2840                 err = smu_set_fan_speed_rpm(&adev->smu, value);
2841         else if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2842                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2843         else
2844                 err = -EINVAL;
2845
2846         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2847         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2848
2849         if (err)
2850                 return err;
2851
2852         return count;
2853 }
2854
2855 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2856                                             struct device_attribute *attr,
2857                                             char *buf)
2858 {
2859         struct amdgpu_device *adev = dev_get_drvdata(dev);
2860         u32 pwm_mode = 0;
2861         int ret;
2862
2863         if (amdgpu_in_reset(adev))
2864                 return -EPERM;
2865
2866         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2867         if (ret < 0) {
2868                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2869                 return ret;
2870         }
2871
2872         if (is_support_sw_smu(adev)) {
2873                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2874         } else {
2875                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2876                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2877                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2878                         return -EINVAL;
2879                 }
2880
2881                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2882         }
2883
2884         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2885         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2886
2887         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2888 }
2889
2890 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2891                                             struct device_attribute *attr,
2892                                             const char *buf,
2893                                             size_t count)
2894 {
2895         struct amdgpu_device *adev = dev_get_drvdata(dev);
2896         int err;
2897         int value;
2898         u32 pwm_mode;
2899
2900         if (amdgpu_in_reset(adev))
2901                 return -EPERM;
2902
2903         err = kstrtoint(buf, 10, &value);
2904         if (err)
2905                 return err;
2906
2907         if (value == 0)
2908                 pwm_mode = AMD_FAN_CTRL_AUTO;
2909         else if (value == 1)
2910                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2911         else
2912                 return -EINVAL;
2913
2914         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2915         if (err < 0) {
2916                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2917                 return err;
2918         }
2919
2920         if (is_support_sw_smu(adev)) {
2921                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
2922         } else {
2923                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2924                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2925                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2926                         return -EINVAL;
2927                 }
2928                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2929         }
2930
2931         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2932         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2933
2934         return count;
2935 }
2936
2937 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2938                                         struct device_attribute *attr,
2939                                         char *buf)
2940 {
2941         struct amdgpu_device *adev = dev_get_drvdata(dev);
2942         u32 vddgfx;
2943         int r, size = sizeof(vddgfx);
2944
2945         if (amdgpu_in_reset(adev))
2946                 return -EPERM;
2947
2948         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2949         if (r < 0) {
2950                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2951                 return r;
2952         }
2953
2954         /* get the voltage */
2955         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2956                                    (void *)&vddgfx, &size);
2957
2958         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2959         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2960
2961         if (r)
2962                 return r;
2963
2964         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
2965 }
2966
2967 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2968                                               struct device_attribute *attr,
2969                                               char *buf)
2970 {
2971         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
2972 }
2973
2974 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2975                                        struct device_attribute *attr,
2976                                        char *buf)
2977 {
2978         struct amdgpu_device *adev = dev_get_drvdata(dev);
2979         u32 vddnb;
2980         int r, size = sizeof(vddnb);
2981
2982         if (amdgpu_in_reset(adev))
2983                 return -EPERM;
2984
2985         /* only APUs have vddnb */
2986         if  (!(adev->flags & AMD_IS_APU))
2987                 return -EINVAL;
2988
2989         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2990         if (r < 0) {
2991                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2992                 return r;
2993         }
2994
2995         /* get the voltage */
2996         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2997                                    (void *)&vddnb, &size);
2998
2999         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3000         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3001
3002         if (r)
3003                 return r;
3004
3005         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
3006 }
3007
3008 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
3009                                               struct device_attribute *attr,
3010                                               char *buf)
3011 {
3012         return snprintf(buf, PAGE_SIZE, "vddnb\n");
3013 }
3014
3015 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
3016                                            struct device_attribute *attr,
3017                                            char *buf)
3018 {
3019         struct amdgpu_device *adev = dev_get_drvdata(dev);
3020         u32 query = 0;
3021         int r, size = sizeof(u32);
3022         unsigned uw;
3023
3024         if (amdgpu_in_reset(adev))
3025                 return -EPERM;
3026
3027         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3028         if (r < 0) {
3029                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3030                 return r;
3031         }
3032
3033         /* get the voltage */
3034         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
3035                                    (void *)&query, &size);
3036
3037         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3038         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3039
3040         if (r)
3041                 return r;
3042
3043         /* convert to microwatts */
3044         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
3045
3046         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
3047 }
3048
3049 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
3050                                          struct device_attribute *attr,
3051                                          char *buf)
3052 {
3053         return sprintf(buf, "%i\n", 0);
3054 }
3055
3056 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
3057                                          struct device_attribute *attr,
3058                                          char *buf)
3059 {
3060         struct amdgpu_device *adev = dev_get_drvdata(dev);
3061         uint32_t limit = 0;
3062         ssize_t size;
3063         int r;
3064
3065         if (amdgpu_in_reset(adev))
3066                 return -EPERM;
3067
3068         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3069         if (r < 0) {
3070                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3071                 return r;
3072         }
3073
3074         if (is_support_sw_smu(adev)) {
3075                 smu_get_power_limit(&adev->smu, &limit, true);
3076                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
3077         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
3078                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
3079                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
3080         } else {
3081                 size = snprintf(buf, PAGE_SIZE, "\n");
3082         }
3083
3084         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3085         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3086
3087         return size;
3088 }
3089
3090 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
3091                                          struct device_attribute *attr,
3092                                          char *buf)
3093 {
3094         struct amdgpu_device *adev = dev_get_drvdata(dev);
3095         uint32_t limit = 0;
3096         ssize_t size;
3097         int r;
3098
3099         if (amdgpu_in_reset(adev))
3100                 return -EPERM;
3101
3102         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3103         if (r < 0) {
3104                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3105                 return r;
3106         }
3107
3108         if (is_support_sw_smu(adev)) {
3109                 smu_get_power_limit(&adev->smu, &limit, false);
3110                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
3111         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
3112                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
3113                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
3114         } else {
3115                 size = snprintf(buf, PAGE_SIZE, "\n");
3116         }
3117
3118         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3119         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3120
3121         return size;
3122 }
3123
3124
3125 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
3126                 struct device_attribute *attr,
3127                 const char *buf,
3128                 size_t count)
3129 {
3130         struct amdgpu_device *adev = dev_get_drvdata(dev);
3131         int err;
3132         u32 value;
3133
3134         if (amdgpu_in_reset(adev))
3135                 return -EPERM;
3136
3137         if (amdgpu_sriov_vf(adev))
3138                 return -EINVAL;
3139
3140         err = kstrtou32(buf, 10, &value);
3141         if (err)
3142                 return err;
3143
3144         value = value / 1000000; /* convert to Watt */
3145
3146
3147         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3148         if (err < 0) {
3149                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3150                 return err;
3151         }
3152
3153         if (is_support_sw_smu(adev))
3154                 err = smu_set_power_limit(&adev->smu, value);
3155         else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
3156                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
3157         else
3158                 err = -EINVAL;
3159
3160         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3161         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3162
3163         if (err)
3164                 return err;
3165
3166         return count;
3167 }
3168
3169 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3170                                       struct device_attribute *attr,
3171                                       char *buf)
3172 {
3173         struct amdgpu_device *adev = dev_get_drvdata(dev);
3174         uint32_t sclk;
3175         int r, size = sizeof(sclk);
3176
3177         if (amdgpu_in_reset(adev))
3178                 return -EPERM;
3179
3180         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3181         if (r < 0) {
3182                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3183                 return r;
3184         }
3185
3186         /* get the sclk */
3187         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3188                                    (void *)&sclk, &size);
3189
3190         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3191         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3192
3193         if (r)
3194                 return r;
3195
3196         return snprintf(buf, PAGE_SIZE, "%u\n", sclk * 10 * 1000);
3197 }
3198
3199 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3200                                             struct device_attribute *attr,
3201                                             char *buf)
3202 {
3203         return snprintf(buf, PAGE_SIZE, "sclk\n");
3204 }
3205
3206 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3207                                       struct device_attribute *attr,
3208                                       char *buf)
3209 {
3210         struct amdgpu_device *adev = dev_get_drvdata(dev);
3211         uint32_t mclk;
3212         int r, size = sizeof(mclk);
3213
3214         if (amdgpu_in_reset(adev))
3215                 return -EPERM;
3216
3217         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3218         if (r < 0) {
3219                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3220                 return r;
3221         }
3222
3223         /* get the sclk */
3224         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3225                                    (void *)&mclk, &size);
3226
3227         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3228         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3229
3230         if (r)
3231                 return r;
3232
3233         return snprintf(buf, PAGE_SIZE, "%u\n", mclk * 10 * 1000);
3234 }
3235
3236 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3237                                             struct device_attribute *attr,
3238                                             char *buf)
3239 {
3240         return snprintf(buf, PAGE_SIZE, "mclk\n");
3241 }
3242
3243 /**
3244  * DOC: hwmon
3245  *
3246  * The amdgpu driver exposes the following sensor interfaces:
3247  *
3248  * - GPU temperature (via the on-die sensor)
3249  *
3250  * - GPU voltage
3251  *
3252  * - Northbridge voltage (APUs only)
3253  *
3254  * - GPU power
3255  *
3256  * - GPU fan
3257  *
3258  * - GPU gfx/compute engine clock
3259  *
3260  * - GPU memory clock (dGPU only)
3261  *
3262  * hwmon interfaces for GPU temperature:
3263  *
3264  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3265  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3266  *
3267  * - temp[1-3]_label: temperature channel label
3268  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3269  *
3270  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3271  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3272  *
3273  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3274  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3275  *
3276  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3277  *   - these are supported on SOC15 dGPUs only
3278  *
3279  * hwmon interfaces for GPU voltage:
3280  *
3281  * - in0_input: the voltage on the GPU in millivolts
3282  *
3283  * - in1_input: the voltage on the Northbridge in millivolts
3284  *
3285  * hwmon interfaces for GPU power:
3286  *
3287  * - power1_average: average power used by the GPU in microWatts
3288  *
3289  * - power1_cap_min: minimum cap supported in microWatts
3290  *
3291  * - power1_cap_max: maximum cap supported in microWatts
3292  *
3293  * - power1_cap: selected power cap in microWatts
3294  *
3295  * hwmon interfaces for GPU fan:
3296  *
3297  * - pwm1: pulse width modulation fan level (0-255)
3298  *
3299  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3300  *
3301  * - pwm1_min: pulse width modulation fan control minimum level (0)
3302  *
3303  * - pwm1_max: pulse width modulation fan control maximum level (255)
3304  *
3305  * - fan1_min: an minimum value Unit: revolution/min (RPM)
3306  *
3307  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
3308  *
3309  * - fan1_input: fan speed in RPM
3310  *
3311  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3312  *
3313  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3314  *
3315  * hwmon interfaces for GPU clocks:
3316  *
3317  * - freq1_input: the gfx/compute clock in hertz
3318  *
3319  * - freq2_input: the memory clock in hertz
3320  *
3321  * You can use hwmon tools like sensors to view this information on your system.
3322  *
3323  */
3324
3325 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3326 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3327 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3328 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3329 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3330 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3331 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3332 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3333 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3334 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3335 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3336 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3337 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3338 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3339 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3340 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3341 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3342 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3343 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3344 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3345 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3346 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3347 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3348 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3349 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3350 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3351 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3352 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3353 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3354 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3355 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3356 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3357 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3358 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3359 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3360 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3361
3362 static struct attribute *hwmon_attributes[] = {
3363         &sensor_dev_attr_temp1_input.dev_attr.attr,
3364         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3365         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3366         &sensor_dev_attr_temp2_input.dev_attr.attr,
3367         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3368         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3369         &sensor_dev_attr_temp3_input.dev_attr.attr,
3370         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3371         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3372         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3373         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3374         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3375         &sensor_dev_attr_temp1_label.dev_attr.attr,
3376         &sensor_dev_attr_temp2_label.dev_attr.attr,
3377         &sensor_dev_attr_temp3_label.dev_attr.attr,
3378         &sensor_dev_attr_pwm1.dev_attr.attr,
3379         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3380         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3381         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3382         &sensor_dev_attr_fan1_input.dev_attr.attr,
3383         &sensor_dev_attr_fan1_min.dev_attr.attr,
3384         &sensor_dev_attr_fan1_max.dev_attr.attr,
3385         &sensor_dev_attr_fan1_target.dev_attr.attr,
3386         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3387         &sensor_dev_attr_in0_input.dev_attr.attr,
3388         &sensor_dev_attr_in0_label.dev_attr.attr,
3389         &sensor_dev_attr_in1_input.dev_attr.attr,
3390         &sensor_dev_attr_in1_label.dev_attr.attr,
3391         &sensor_dev_attr_power1_average.dev_attr.attr,
3392         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3393         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3394         &sensor_dev_attr_power1_cap.dev_attr.attr,
3395         &sensor_dev_attr_freq1_input.dev_attr.attr,
3396         &sensor_dev_attr_freq1_label.dev_attr.attr,
3397         &sensor_dev_attr_freq2_input.dev_attr.attr,
3398         &sensor_dev_attr_freq2_label.dev_attr.attr,
3399         NULL
3400 };
3401
3402 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3403                                         struct attribute *attr, int index)
3404 {
3405         struct device *dev = kobj_to_dev(kobj);
3406         struct amdgpu_device *adev = dev_get_drvdata(dev);
3407         umode_t effective_mode = attr->mode;
3408
3409         /* under multi-vf mode, the hwmon attributes are all not supported */
3410         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3411                 return 0;
3412
3413         /* there is no fan under pp one vf mode */
3414         if (amdgpu_sriov_is_pp_one_vf(adev) &&
3415             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3416              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3417              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3418              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3419              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3420              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3421              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3422              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3423              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3424                 return 0;
3425
3426         /* Skip fan attributes if fan is not present */
3427         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3428             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3429             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3430             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3431             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3432             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3433             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3434             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3435             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3436                 return 0;
3437
3438         /* Skip fan attributes on APU */
3439         if ((adev->flags & AMD_IS_APU) &&
3440             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3441              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3442              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3443              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3444              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3445              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3446              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3447              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3448              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3449                 return 0;
3450
3451         /* Skip crit temp on APU */
3452         if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&
3453             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3454              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3455                 return 0;
3456
3457         /* Skip limit attributes if DPM is not enabled */
3458         if (!adev->pm.dpm_enabled &&
3459             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3460              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3461              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3462              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3463              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3464              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3465              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3466              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3467              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3468              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3469              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3470                 return 0;
3471
3472         if (!is_support_sw_smu(adev)) {
3473                 /* mask fan attributes if we have no bindings for this asic to expose */
3474                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
3475                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3476                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
3477                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3478                         effective_mode &= ~S_IRUGO;
3479
3480                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3481                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3482                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
3483                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3484                         effective_mode &= ~S_IWUSR;
3485         }
3486
3487         if (((adev->flags & AMD_IS_APU) ||
3488              adev->family == AMDGPU_FAMILY_SI) &&       /* not implemented yet */
3489             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3490              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3491              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
3492                 return 0;
3493
3494         if (((adev->family == AMDGPU_FAMILY_SI) ||
3495              ((adev->flags & AMD_IS_APU) &&
3496               (adev->asic_type < CHIP_RENOIR))) &&      /* not implemented yet */
3497             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3498                 return 0;
3499
3500         if (!is_support_sw_smu(adev)) {
3501                 /* hide max/min values if we can't both query and manage the fan */
3502                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3503                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
3504                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3505                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3506                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3507                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3508                         return 0;
3509
3510                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3511                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3512                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3513                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3514                         return 0;
3515         }
3516
3517         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3518              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3519             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3520              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3521                 return 0;
3522
3523         /* only APUs have vddnb */
3524         if (!(adev->flags & AMD_IS_APU) &&
3525             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3526              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3527                 return 0;
3528
3529         /* no mclk on APUs */
3530         if ((adev->flags & AMD_IS_APU) &&
3531             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3532              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3533                 return 0;
3534
3535         /* only SOC15 dGPUs support hotspot and mem temperatures */
3536         if (((adev->flags & AMD_IS_APU) ||
3537              adev->asic_type < CHIP_VEGA10) &&
3538             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3539              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3540              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3541              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3542              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3543              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3544              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3545              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3546              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3547              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3548              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3549                 return 0;
3550
3551         return effective_mode;
3552 }
3553
3554 static const struct attribute_group hwmon_attrgroup = {
3555         .attrs = hwmon_attributes,
3556         .is_visible = hwmon_attributes_visible,
3557 };
3558
3559 static const struct attribute_group *hwmon_groups[] = {
3560         &hwmon_attrgroup,
3561         NULL
3562 };
3563
3564 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3565 {
3566         int ret;
3567         uint32_t mask = 0;
3568
3569         if (adev->pm.sysfs_initialized)
3570                 return 0;
3571
3572         if (adev->pm.dpm_enabled == 0)
3573                 return 0;
3574
3575         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3576
3577         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3578                                                                    DRIVER_NAME, adev,
3579                                                                    hwmon_groups);
3580         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3581                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3582                 dev_err(adev->dev,
3583                         "Unable to register hwmon device: %d\n", ret);
3584                 return ret;
3585         }
3586
3587         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3588         case SRIOV_VF_MODE_ONE_VF:
3589                 mask = ATTR_FLAG_ONEVF;
3590                 break;
3591         case SRIOV_VF_MODE_MULTI_VF:
3592                 mask = 0;
3593                 break;
3594         case SRIOV_VF_MODE_BARE_METAL:
3595         default:
3596                 mask = ATTR_FLAG_MASK_ALL;
3597                 break;
3598         }
3599
3600         ret = amdgpu_device_attr_create_groups(adev,
3601                                                amdgpu_device_attrs,
3602                                                ARRAY_SIZE(amdgpu_device_attrs),
3603                                                mask,
3604                                                &adev->pm.pm_attr_list);
3605         if (ret)
3606                 return ret;
3607
3608         adev->pm.sysfs_initialized = true;
3609
3610         return 0;
3611 }
3612
3613 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3614 {
3615         if (adev->pm.dpm_enabled == 0)
3616                 return;
3617
3618         if (adev->pm.int_hwmon_dev)
3619                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3620
3621         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3622 }
3623
3624 /*
3625  * Debugfs info
3626  */
3627 #if defined(CONFIG_DEBUG_FS)
3628
3629 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3630                                            struct amdgpu_device *adev) {
3631         uint16_t *p_val;
3632         uint32_t size;
3633         int i;
3634
3635         if (is_support_cclk_dpm(adev)) {
3636                 p_val = kcalloc(adev->smu.cpu_core_num, sizeof(uint16_t),
3637                                 GFP_KERNEL);
3638
3639                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3640                                             (void *)p_val, &size)) {
3641                         for (i = 0; i < adev->smu.cpu_core_num; i++)
3642                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
3643                                            *(p_val + i), i);
3644                 }
3645
3646                 kfree(p_val);
3647         }
3648 }
3649
3650 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3651 {
3652         uint32_t value;
3653         uint64_t value64 = 0;
3654         uint32_t query = 0;
3655         int size;
3656
3657         /* GPU Clocks */
3658         size = sizeof(value);
3659         seq_printf(m, "GFX Clocks and Power:\n");
3660
3661         amdgpu_debugfs_prints_cpu_info(m, adev);
3662
3663         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3664                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3665         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3666                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3667         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3668                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3669         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3670                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3671         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3672                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3673         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3674                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3675         size = sizeof(uint32_t);
3676         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3677                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3678         size = sizeof(value);
3679         seq_printf(m, "\n");
3680
3681         /* GPU Temp */
3682         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3683                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3684
3685         /* GPU Load */
3686         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3687                 seq_printf(m, "GPU Load: %u %%\n", value);
3688         /* MEM Load */
3689         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3690                 seq_printf(m, "MEM Load: %u %%\n", value);
3691
3692         seq_printf(m, "\n");
3693
3694         /* SMC feature mask */
3695         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3696                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3697
3698         if (adev->asic_type > CHIP_VEGA20) {
3699                 /* VCN clocks */
3700                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3701                         if (!value) {
3702                                 seq_printf(m, "VCN: Disabled\n");
3703                         } else {
3704                                 seq_printf(m, "VCN: Enabled\n");
3705                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3706                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3707                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3708                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3709                         }
3710                 }
3711                 seq_printf(m, "\n");
3712         } else {
3713                 /* UVD clocks */
3714                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3715                         if (!value) {
3716                                 seq_printf(m, "UVD: Disabled\n");
3717                         } else {
3718                                 seq_printf(m, "UVD: Enabled\n");
3719                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3720                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3721                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3722                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3723                         }
3724                 }
3725                 seq_printf(m, "\n");
3726
3727                 /* VCE clocks */
3728                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3729                         if (!value) {
3730                                 seq_printf(m, "VCE: Disabled\n");
3731                         } else {
3732                                 seq_printf(m, "VCE: Enabled\n");
3733                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3734                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3735                         }
3736                 }
3737         }
3738
3739         return 0;
3740 }
3741
3742 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3743 {
3744         int i;
3745
3746         for (i = 0; clocks[i].flag; i++)
3747                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3748                            (flags & clocks[i].flag) ? "On" : "Off");
3749 }
3750
3751 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3752 {
3753         struct drm_info_node *node = (struct drm_info_node *) m->private;
3754         struct drm_device *dev = node->minor->dev;
3755         struct amdgpu_device *adev = drm_to_adev(dev);
3756         u32 flags = 0;
3757         int r;
3758
3759         if (amdgpu_in_reset(adev))
3760                 return -EPERM;
3761
3762         r = pm_runtime_get_sync(dev->dev);
3763         if (r < 0) {
3764                 pm_runtime_put_autosuspend(dev->dev);
3765                 return r;
3766         }
3767
3768         if (!adev->pm.dpm_enabled) {
3769                 seq_printf(m, "dpm not enabled\n");
3770                 pm_runtime_mark_last_busy(dev->dev);
3771                 pm_runtime_put_autosuspend(dev->dev);
3772                 return 0;
3773         }
3774
3775         if (!is_support_sw_smu(adev) &&
3776             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3777                 mutex_lock(&adev->pm.mutex);
3778                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3779                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3780                 else
3781                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3782                 mutex_unlock(&adev->pm.mutex);
3783                 r = 0;
3784         } else {
3785                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3786         }
3787         if (r)
3788                 goto out;
3789
3790         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3791
3792         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3793         amdgpu_parse_cg_state(m, flags);
3794         seq_printf(m, "\n");
3795
3796 out:
3797         pm_runtime_mark_last_busy(dev->dev);
3798         pm_runtime_put_autosuspend(dev->dev);
3799
3800         return r;
3801 }
3802
3803 static const struct drm_info_list amdgpu_pm_info_list[] = {
3804         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3805 };
3806 #endif
3807
3808 int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3809 {
3810 #if defined(CONFIG_DEBUG_FS)
3811         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3812 #else
3813         return 0;
3814 #endif
3815 }