drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109
 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
 114
 115 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 121 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 123 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 125 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 127 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 129 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 131 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 134
 135 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 137 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 139 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 141 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 143 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 145 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 147
 148 #define mmCPG_PSP_DEBUG                         0x5c10
 149 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 150 #define mmCPC_PSP_DEBUG                         0x5c11
 151 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 154
 155 //CC_GC_SA_UNIT_DISABLE
 156 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 160 //GC_USER_SA_UNIT_DISABLE
 161 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 165 //PA_SC_ENHANCE_3
 166 #define mmPA_SC_ENHANCE_3                       0x1085
 167 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 170
 171 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 173
 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 178
 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 181
 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 184
 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 191
 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 203
 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 210
 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 217
 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 224
 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 231
 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 238
 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 245
 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 252
 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 259
 260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
 261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
 262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
 263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
 264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
 266
 267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
 270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 273
 274 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 275 {
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 316 };
 317
 318 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 319 {
 320         /* Pending on emulation bring up */
 321 };
 322
 323 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 324 {
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1377 };
1378
1379 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1380 {
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1419 };
1420
1421 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1422 {
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 };
1466
1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1468 {
1469         /* Pending on emulation bring up */
1470 };
1471
1472 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1473 {
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2094 };
2095
2096 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2097 {
2098         /* Pending on emulation bring up */
2099 };
2100
2101 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2102 {
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3155 };
3156
3157 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3158 {
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3202 };
3203
3204 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3205 {
3206         /* Pending on emulation bring up */
3207 };
3208
3209 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3210 {
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3252
3253         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3255 };
3256
3257 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3258 {
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3283
3284         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3286 };
3287
3288 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3289 {
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3310 };
3311
3312 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3313 {
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3350 };
3351
3352 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3385 };
3386
3387 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3422 };
3423
3424 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
3425 {
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3448 };
3449
3450 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3473 };
3474
3475 #define DEFAULT_SH_MEM_CONFIG \
3476         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3477          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3478          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3479          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3480
3481 /* TODO: pending on golden setting value of gb address config */
3482 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3483
3484 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3485 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3486 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3487 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3488 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3489                                  struct amdgpu_cu_info *cu_info);
3490 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3491 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3492                                    u32 sh_num, u32 instance);
3493 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3494
3495 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3496 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3497 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3498 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3499 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3500 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3501 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3502 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3503 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3504 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3505
3506 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3507 {
3508         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3509         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3510                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3511         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3512         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3513         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3514         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3515         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3516         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3517 }
3518
3519 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3520                                  struct amdgpu_ring *ring)
3521 {
3522         struct amdgpu_device *adev = kiq_ring->adev;
3523         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3524         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3525         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3526
3527         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3528         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3529         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3530                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3531                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3532                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3533                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3534                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3535                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3536                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3537                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3538                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3539         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3540         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3541         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3542         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3543         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3544 }
3545
3546 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3547                                    struct amdgpu_ring *ring,
3548                                    enum amdgpu_unmap_queues_action action,
3549                                    u64 gpu_addr, u64 seq)
3550 {
3551         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3552
3553         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3554         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3555                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3556                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3557                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3558                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3559         amdgpu_ring_write(kiq_ring,
3560                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3561
3562         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3563                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3564                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3565                 amdgpu_ring_write(kiq_ring, seq);
3566         } else {
3567                 amdgpu_ring_write(kiq_ring, 0);
3568                 amdgpu_ring_write(kiq_ring, 0);
3569                 amdgpu_ring_write(kiq_ring, 0);
3570         }
3571 }
3572
3573 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3574                                    struct amdgpu_ring *ring,
3575                                    u64 addr,
3576                                    u64 seq)
3577 {
3578         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3579
3580         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3581         amdgpu_ring_write(kiq_ring,
3582                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3583                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3584                           PACKET3_QUERY_STATUS_COMMAND(2));
3585         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3586                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3587                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3588         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3589         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3590         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3591         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3592 }
3593
3594 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3595                                 uint16_t pasid, uint32_t flush_type,
3596                                 bool all_hub)
3597 {
3598         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3599         amdgpu_ring_write(kiq_ring,
3600                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3601                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3602                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3603                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3604 }
3605
3606 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3607         .kiq_set_resources = gfx10_kiq_set_resources,
3608         .kiq_map_queues = gfx10_kiq_map_queues,
3609         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3610         .kiq_query_status = gfx10_kiq_query_status,
3611         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3612         .set_resources_size = 8,
3613         .map_queues_size = 7,
3614         .unmap_queues_size = 6,
3615         .query_status_size = 7,
3616         .invalidate_tlbs_size = 2,
3617 };
3618
3619 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3620 {
3621         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3622 }
3623
3624 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3625 {
3626         switch (adev->ip_versions[GC_HWIP][0]) {
3627         case IP_VERSION(10, 1, 10):
3628                 soc15_program_register_sequence(adev,
3629                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3630                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3631                 break;
3632         case IP_VERSION(10, 1, 1):
3633                 soc15_program_register_sequence(adev,
3634                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3635                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3636                 break;
3637         case IP_VERSION(10, 1, 2):
3638                 soc15_program_register_sequence(adev,
3639                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3640                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3641                 break;
3642         default:
3643                 break;
3644         }
3645 }
3646
3647 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3648 {
3649         switch (adev->ip_versions[GC_HWIP][0]) {
3650         case IP_VERSION(10, 1, 10):
3651                 soc15_program_register_sequence(adev,
3652                                                 golden_settings_gc_10_1,
3653                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3654                 soc15_program_register_sequence(adev,
3655                                                 golden_settings_gc_10_0_nv10,
3656                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3657                 break;
3658         case IP_VERSION(10, 1, 1):
3659                 soc15_program_register_sequence(adev,
3660                                                 golden_settings_gc_10_1_1,
3661                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3662                 soc15_program_register_sequence(adev,
3663                                                 golden_settings_gc_10_1_nv14,
3664                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3665                 break;
3666         case IP_VERSION(10, 1, 2):
3667                 soc15_program_register_sequence(adev,
3668                                                 golden_settings_gc_10_1_2,
3669                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3670                 soc15_program_register_sequence(adev,
3671                                                 golden_settings_gc_10_1_2_nv12,
3672                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3673                 break;
3674         case IP_VERSION(10, 3, 0):
3675                 soc15_program_register_sequence(adev,
3676                                                 golden_settings_gc_10_3,
3677                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3678                 soc15_program_register_sequence(adev,
3679                                                 golden_settings_gc_10_3_sienna_cichlid,
3680                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3681                 break;
3682         case IP_VERSION(10, 3, 2):
3683                 soc15_program_register_sequence(adev,
3684                                                 golden_settings_gc_10_3_2,
3685                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3686                 break;
3687         case IP_VERSION(10, 3, 1):
3688                 soc15_program_register_sequence(adev,
3689                                                 golden_settings_gc_10_3_vangogh,
3690                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3691                 break;
3692         case IP_VERSION(10, 3, 3):
3693                 soc15_program_register_sequence(adev,
3694                                                 golden_settings_gc_10_3_3,
3695                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3696                 break;
3697         case IP_VERSION(10, 3, 4):
3698                 soc15_program_register_sequence(adev,
3699                                                 golden_settings_gc_10_3_4,
3700                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3701                 break;
3702         case IP_VERSION(10, 3, 5):
3703                 soc15_program_register_sequence(adev,
3704                                                 golden_settings_gc_10_3_5,
3705                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3706                 break;
3707         case IP_VERSION(10, 1, 3):
3708         case IP_VERSION(10, 1, 4):
3709                 soc15_program_register_sequence(adev,
3710                                                 golden_settings_gc_10_0_cyan_skillfish,
3711                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3712                 break;
3713         case IP_VERSION(10, 3, 6):
3714                 soc15_program_register_sequence(adev,
3715                                                 golden_settings_gc_10_3_6,
3716                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3717                 break;
3718         case IP_VERSION(10, 3, 7):
3719                 soc15_program_register_sequence(adev,
3720                                                 golden_settings_gc_10_3_7,
3721                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3722                 break;
3723         default:
3724                 break;
3725         }
3726         gfx_v10_0_init_spm_golden_registers(adev);
3727 }
3728
3729 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3730 {
3731         adev->gfx.scratch.num_reg = 8;
3732         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3733         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3734 }
3735
3736 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3737                                        bool wc, uint32_t reg, uint32_t val)
3738 {
3739         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3740         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3741                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3742         amdgpu_ring_write(ring, reg);
3743         amdgpu_ring_write(ring, 0);
3744         amdgpu_ring_write(ring, val);
3745 }
3746
3747 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3748                                   int mem_space, int opt, uint32_t addr0,
3749                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3750                                   uint32_t inv)
3751 {
3752         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3753         amdgpu_ring_write(ring,
3754                           /* memory (1) or register (0) */
3755                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3756                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3757                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3758                            WAIT_REG_MEM_ENGINE(eng_sel)));
3759
3760         if (mem_space)
3761                 BUG_ON(addr0 & 0x3); /* Dword align */
3762         amdgpu_ring_write(ring, addr0);
3763         amdgpu_ring_write(ring, addr1);
3764         amdgpu_ring_write(ring, ref);
3765         amdgpu_ring_write(ring, mask);
3766         amdgpu_ring_write(ring, inv); /* poll interval */
3767 }
3768
3769 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3770 {
3771         struct amdgpu_device *adev = ring->adev;
3772         uint32_t scratch;
3773         uint32_t tmp = 0;
3774         unsigned i;
3775         int r;
3776
3777         r = amdgpu_gfx_scratch_get(adev, &scratch);
3778         if (r) {
3779                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3780                 return r;
3781         }
3782
3783         WREG32(scratch, 0xCAFEDEAD);
3784
3785         r = amdgpu_ring_alloc(ring, 3);
3786         if (r) {
3787                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3788                           ring->idx, r);
3789                 amdgpu_gfx_scratch_free(adev, scratch);
3790                 return r;
3791         }
3792
3793         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3794         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3795         amdgpu_ring_write(ring, 0xDEADBEEF);
3796         amdgpu_ring_commit(ring);
3797
3798         for (i = 0; i < adev->usec_timeout; i++) {
3799                 tmp = RREG32(scratch);
3800                 if (tmp == 0xDEADBEEF)
3801                         break;
3802                 if (amdgpu_emu_mode == 1)
3803                         msleep(1);
3804                 else
3805                         udelay(1);
3806         }
3807
3808         if (i >= adev->usec_timeout)
3809                 r = -ETIMEDOUT;
3810
3811         amdgpu_gfx_scratch_free(adev, scratch);
3812
3813         return r;
3814 }
3815
3816 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3817 {
3818         struct amdgpu_device *adev = ring->adev;
3819         struct amdgpu_ib ib;
3820         struct dma_fence *f = NULL;
3821         unsigned index;
3822         uint64_t gpu_addr;
3823         uint32_t tmp;
3824         long r;
3825
3826         r = amdgpu_device_wb_get(adev, &index);
3827         if (r)
3828                 return r;
3829
3830         gpu_addr = adev->wb.gpu_addr + (index * 4);
3831         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3832         memset(&ib, 0, sizeof(ib));
3833         r = amdgpu_ib_get(adev, NULL, 16,
3834                                         AMDGPU_IB_POOL_DIRECT, &ib);
3835         if (r)
3836                 goto err1;
3837
3838         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3839         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3840         ib.ptr[2] = lower_32_bits(gpu_addr);
3841         ib.ptr[3] = upper_32_bits(gpu_addr);
3842         ib.ptr[4] = 0xDEADBEEF;
3843         ib.length_dw = 5;
3844
3845         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3846         if (r)
3847                 goto err2;
3848
3849         r = dma_fence_wait_timeout(f, false, timeout);
3850         if (r == 0) {
3851                 r = -ETIMEDOUT;
3852                 goto err2;
3853         } else if (r < 0) {
3854                 goto err2;
3855         }
3856
3857         tmp = adev->wb.wb[index];
3858         if (tmp == 0xDEADBEEF)
3859                 r = 0;
3860         else
3861                 r = -EINVAL;
3862 err2:
3863         amdgpu_ib_free(adev, &ib, NULL);
3864         dma_fence_put(f);
3865 err1:
3866         amdgpu_device_wb_free(adev, index);
3867         return r;
3868 }
3869
3870 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3871 {
3872         release_firmware(adev->gfx.pfp_fw);
3873         adev->gfx.pfp_fw = NULL;
3874         release_firmware(adev->gfx.me_fw);
3875         adev->gfx.me_fw = NULL;
3876         release_firmware(adev->gfx.ce_fw);
3877         adev->gfx.ce_fw = NULL;
3878         release_firmware(adev->gfx.rlc_fw);
3879         adev->gfx.rlc_fw = NULL;
3880         release_firmware(adev->gfx.mec_fw);
3881         adev->gfx.mec_fw = NULL;
3882         release_firmware(adev->gfx.mec2_fw);
3883         adev->gfx.mec2_fw = NULL;
3884
3885         kfree(adev->gfx.rlc.register_list_format);
3886 }
3887
3888 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3889 {
3890         adev->gfx.cp_fw_write_wait = false;
3891
3892         switch (adev->ip_versions[GC_HWIP][0]) {
3893         case IP_VERSION(10, 1, 10):
3894         case IP_VERSION(10, 1, 2):
3895         case IP_VERSION(10, 1, 1):
3896         case IP_VERSION(10, 1, 3):
3897         case IP_VERSION(10, 1, 4):
3898                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3899                     (adev->gfx.me_feature_version >= 27) &&
3900                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3901                     (adev->gfx.pfp_feature_version >= 27) &&
3902                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3903                     (adev->gfx.mec_feature_version >= 27))
3904                         adev->gfx.cp_fw_write_wait = true;
3905                 break;
3906         case IP_VERSION(10, 3, 0):
3907         case IP_VERSION(10, 3, 2):
3908         case IP_VERSION(10, 3, 1):
3909         case IP_VERSION(10, 3, 4):
3910         case IP_VERSION(10, 3, 5):
3911         case IP_VERSION(10, 3, 6):
3912         case IP_VERSION(10, 3, 3):
3913         case IP_VERSION(10, 3, 7):
3914                 adev->gfx.cp_fw_write_wait = true;
3915                 break;
3916         default:
3917                 break;
3918         }
3919
3920         if (!adev->gfx.cp_fw_write_wait)
3921                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3922 }
3923
3924
3925 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3926 {
3927         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3928
3929         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3930         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3931         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3932         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3933         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3934         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3935         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3936         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3937         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3938         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3939         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3940         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3941         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3942         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3943                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3944 }
3945
3946 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3947 {
3948         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3949
3950         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3951         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3952         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3953         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3954         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3955 }
3956
3957 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3958 {
3959         bool ret = false;
3960
3961         switch (adev->pdev->revision) {
3962         case 0xc2:
3963         case 0xc3:
3964                 ret = true;
3965                 break;
3966         default:
3967                 ret = false;
3968                 break;
3969         }
3970
3971         return ret ;
3972 }
3973
3974 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3975 {
3976         switch (adev->ip_versions[GC_HWIP][0]) {
3977         case IP_VERSION(10, 1, 10):
3978                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3979                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3980                 break;
3981         default:
3982                 break;
3983         }
3984 }
3985
3986 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3987 {
3988         const char *chip_name;
3989         char fw_name[40];
3990         char *wks = "";
3991         int err;
3992         struct amdgpu_firmware_info *info = NULL;
3993         const struct common_firmware_header *header = NULL;
3994         const struct gfx_firmware_header_v1_0 *cp_hdr;
3995         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3996         unsigned int *tmp = NULL;
3997         unsigned int i = 0;
3998         uint16_t version_major;
3999         uint16_t version_minor;
4000
4001         DRM_DEBUG("\n");
4002
4003         switch (adev->ip_versions[GC_HWIP][0]) {
4004         case IP_VERSION(10, 1, 10):
4005                 chip_name = "navi10";
4006                 break;
4007         case IP_VERSION(10, 1, 1):
4008                 chip_name = "navi14";
4009                 if (!(adev->pdev->device == 0x7340 &&
4010                       adev->pdev->revision != 0x00))
4011                         wks = "_wks";
4012                 break;
4013         case IP_VERSION(10, 1, 2):
4014                 chip_name = "navi12";
4015                 break;
4016         case IP_VERSION(10, 3, 0):
4017                 chip_name = "sienna_cichlid";
4018                 break;
4019         case IP_VERSION(10, 3, 2):
4020                 chip_name = "navy_flounder";
4021                 break;
4022         case IP_VERSION(10, 3, 1):
4023                 chip_name = "vangogh";
4024                 break;
4025         case IP_VERSION(10, 3, 4):
4026                 chip_name = "dimgrey_cavefish";
4027                 break;
4028         case IP_VERSION(10, 3, 5):
4029                 chip_name = "beige_goby";
4030                 break;
4031         case IP_VERSION(10, 3, 3):
4032                 chip_name = "yellow_carp";
4033                 break;
4034         case IP_VERSION(10, 3, 6):
4035                 chip_name = "gc_10_3_6";
4036                 break;
4037         case IP_VERSION(10, 1, 3):
4038         case IP_VERSION(10, 1, 4):
4039                 chip_name = "cyan_skillfish2";
4040                 break;
4041         case IP_VERSION(10, 3, 7):
4042                 chip_name = "gc_10_3_7";
4043                 break;
4044         default:
4045                 BUG();
4046         }
4047
4048         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4049         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4050         if (err)
4051                 goto out;
4052         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4053         if (err)
4054                 goto out;
4055         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4056         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4057         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4058
4059         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4060         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4061         if (err)
4062                 goto out;
4063         err = amdgpu_ucode_validate(adev->gfx.me_fw);
4064         if (err)
4065                 goto out;
4066         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4067         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4068         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4069
4070         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4071         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4072         if (err)
4073                 goto out;
4074         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4075         if (err)
4076                 goto out;
4077         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4078         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4079         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4080
4081         if (!amdgpu_sriov_vf(adev)) {
4082                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4083                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4084                 if (err)
4085                         goto out;
4086                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4087                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4088                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4089                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4090
4091                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4092                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4093                 adev->gfx.rlc.save_and_restore_offset =
4094                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
4095                 adev->gfx.rlc.clear_state_descriptor_offset =
4096                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4097                 adev->gfx.rlc.avail_scratch_ram_locations =
4098                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4099                 adev->gfx.rlc.reg_restore_list_size =
4100                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
4101                 adev->gfx.rlc.reg_list_format_start =
4102                         le32_to_cpu(rlc_hdr->reg_list_format_start);
4103                 adev->gfx.rlc.reg_list_format_separate_start =
4104                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4105                 adev->gfx.rlc.starting_offsets_start =
4106                         le32_to_cpu(rlc_hdr->starting_offsets_start);
4107                 adev->gfx.rlc.reg_list_format_size_bytes =
4108                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4109                 adev->gfx.rlc.reg_list_size_bytes =
4110                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4111                 adev->gfx.rlc.register_list_format =
4112                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4113                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4114                 if (!adev->gfx.rlc.register_list_format) {
4115                         err = -ENOMEM;
4116                         goto out;
4117                 }
4118
4119                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4120                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4121                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4122                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4123
4124                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4125
4126                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4127                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4128                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4129                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4130
4131                 if (version_major == 2) {
4132                         if (version_minor >= 1)
4133                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4134                         if (version_minor == 2)
4135                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4136                 }
4137         }
4138
4139         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4140         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4141         if (err)
4142                 goto out;
4143         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4144         if (err)
4145                 goto out;
4146         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4147         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4148         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4149
4150         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4151         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4152         if (!err) {
4153                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4154                 if (err)
4155                         goto out;
4156                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4157                 adev->gfx.mec2_fw->data;
4158                 adev->gfx.mec2_fw_version =
4159                 le32_to_cpu(cp_hdr->header.ucode_version);
4160                 adev->gfx.mec2_feature_version =
4161                 le32_to_cpu(cp_hdr->ucode_feature_version);
4162         } else {
4163                 err = 0;
4164                 adev->gfx.mec2_fw = NULL;
4165         }
4166
4167         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4168                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4169                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4170                 info->fw = adev->gfx.pfp_fw;
4171                 header = (const struct common_firmware_header *)info->fw->data;
4172                 adev->firmware.fw_size +=
4173                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4174
4175                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4176                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4177                 info->fw = adev->gfx.me_fw;
4178                 header = (const struct common_firmware_header *)info->fw->data;
4179                 adev->firmware.fw_size +=
4180                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4181
4182                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4183                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4184                 info->fw = adev->gfx.ce_fw;
4185                 header = (const struct common_firmware_header *)info->fw->data;
4186                 adev->firmware.fw_size +=
4187                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4188
4189                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4190                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4191                 info->fw = adev->gfx.rlc_fw;
4192                 if (info->fw) {
4193                         header = (const struct common_firmware_header *)info->fw->data;
4194                         adev->firmware.fw_size +=
4195                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4196                 }
4197                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4198                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4199                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4200                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4201                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4202                         info->fw = adev->gfx.rlc_fw;
4203                         adev->firmware.fw_size +=
4204                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4205
4206                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4207                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4208                         info->fw = adev->gfx.rlc_fw;
4209                         adev->firmware.fw_size +=
4210                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4211
4212                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4213                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4214                         info->fw = adev->gfx.rlc_fw;
4215                         adev->firmware.fw_size +=
4216                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4217
4218                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4219                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4220                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4221                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4222                                 info->fw = adev->gfx.rlc_fw;
4223                                 adev->firmware.fw_size +=
4224                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4225
4226                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4227                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4228                                 info->fw = adev->gfx.rlc_fw;
4229                                 adev->firmware.fw_size +=
4230                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4231                         }
4232                 }
4233
4234                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4235                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4236                 info->fw = adev->gfx.mec_fw;
4237                 header = (const struct common_firmware_header *)info->fw->data;
4238                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4239                 adev->firmware.fw_size +=
4240                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4241                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4242
4243                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4244                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4245                 info->fw = adev->gfx.mec_fw;
4246                 adev->firmware.fw_size +=
4247                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4248
4249                 if (adev->gfx.mec2_fw) {
4250                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4251                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4252                         info->fw = adev->gfx.mec2_fw;
4253                         header = (const struct common_firmware_header *)info->fw->data;
4254                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4255                         adev->firmware.fw_size +=
4256                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4257                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4258                                       PAGE_SIZE);
4259                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4260                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4261                         info->fw = adev->gfx.mec2_fw;
4262                         adev->firmware.fw_size +=
4263                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4264                                       PAGE_SIZE);
4265                 }
4266         }
4267
4268         gfx_v10_0_check_fw_write_wait(adev);
4269 out:
4270         if (err) {
4271                 dev_err(adev->dev,
4272                         "gfx10: Failed to load firmware \"%s\"\n",
4273                         fw_name);
4274                 release_firmware(adev->gfx.pfp_fw);
4275                 adev->gfx.pfp_fw = NULL;
4276                 release_firmware(adev->gfx.me_fw);
4277                 adev->gfx.me_fw = NULL;
4278                 release_firmware(adev->gfx.ce_fw);
4279                 adev->gfx.ce_fw = NULL;
4280                 release_firmware(adev->gfx.rlc_fw);
4281                 adev->gfx.rlc_fw = NULL;
4282                 release_firmware(adev->gfx.mec_fw);
4283                 adev->gfx.mec_fw = NULL;
4284                 release_firmware(adev->gfx.mec2_fw);
4285                 adev->gfx.mec2_fw = NULL;
4286         }
4287
4288         gfx_v10_0_check_gfxoff_flag(adev);
4289
4290         return err;
4291 }
4292
4293 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4294 {
4295         u32 count = 0;
4296         const struct cs_section_def *sect = NULL;
4297         const struct cs_extent_def *ext = NULL;
4298
4299         /* begin clear state */
4300         count += 2;
4301         /* context control state */
4302         count += 3;
4303
4304         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4305                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4306                         if (sect->id == SECT_CONTEXT)
4307                                 count += 2 + ext->reg_count;
4308                         else
4309                                 return 0;
4310                 }
4311         }
4312
4313         /* set PA_SC_TILE_STEERING_OVERRIDE */
4314         count += 3;
4315         /* end clear state */
4316         count += 2;
4317         /* clear state */
4318         count += 2;
4319
4320         return count;
4321 }
4322
4323 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4324                                     volatile u32 *buffer)
4325 {
4326         u32 count = 0, i;
4327         const struct cs_section_def *sect = NULL;
4328         const struct cs_extent_def *ext = NULL;
4329         int ctx_reg_offset;
4330
4331         if (adev->gfx.rlc.cs_data == NULL)
4332                 return;
4333         if (buffer == NULL)
4334                 return;
4335
4336         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4337         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4338
4339         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4340         buffer[count++] = cpu_to_le32(0x80000000);
4341         buffer[count++] = cpu_to_le32(0x80000000);
4342
4343         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4344                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4345                         if (sect->id == SECT_CONTEXT) {
4346                                 buffer[count++] =
4347                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4348                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4349                                                 PACKET3_SET_CONTEXT_REG_START);
4350                                 for (i = 0; i < ext->reg_count; i++)
4351                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4352                         } else {
4353                                 return;
4354                         }
4355                 }
4356         }
4357
4358         ctx_reg_offset =
4359                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4360         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4361         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4362         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4363
4364         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4365         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4366
4367         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4368         buffer[count++] = cpu_to_le32(0);
4369 }
4370
4371 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4372 {
4373         /* clear state block */
4374         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4375                         &adev->gfx.rlc.clear_state_gpu_addr,
4376                         (void **)&adev->gfx.rlc.cs_ptr);
4377
4378         /* jump table block */
4379         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4380                         &adev->gfx.rlc.cp_table_gpu_addr,
4381                         (void **)&adev->gfx.rlc.cp_table_ptr);
4382 }
4383
4384 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4385 {
4386         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4387
4388         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4389         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4390         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4391         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4392         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4393         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4394         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4395         switch (adev->ip_versions[GC_HWIP][0]) {
4396                 case IP_VERSION(10, 3, 0):
4397                         reg_access_ctrl->spare_int =
4398                                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4399                         break;
4400                 default:
4401                         reg_access_ctrl->spare_int =
4402                                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4403                         break;
4404         }
4405         adev->gfx.rlc.rlcg_reg_access_supported = true;
4406 }
4407
4408 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4409 {
4410         const struct cs_section_def *cs_data;
4411         int r;
4412
4413         adev->gfx.rlc.cs_data = gfx10_cs_data;
4414
4415         cs_data = adev->gfx.rlc.cs_data;
4416
4417         if (cs_data) {
4418                 /* init clear state block */
4419                 r = amdgpu_gfx_rlc_init_csb(adev);
4420                 if (r)
4421                         return r;
4422         }
4423
4424         /* init spm vmid with 0xf */
4425         if (adev->gfx.rlc.funcs->update_spm_vmid)
4426                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4427
4428
4429         return 0;
4430 }
4431
4432 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4433 {
4434         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4435         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4436 }
4437
4438 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4439 {
4440         int r;
4441
4442         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4443
4444         amdgpu_gfx_graphics_queue_acquire(adev);
4445
4446         r = gfx_v10_0_init_microcode(adev);
4447         if (r)
4448                 DRM_ERROR("Failed to load gfx firmware!\n");
4449
4450         return r;
4451 }
4452
4453 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4454 {
4455         int r;
4456         u32 *hpd;
4457         const __le32 *fw_data = NULL;
4458         unsigned fw_size;
4459         u32 *fw = NULL;
4460         size_t mec_hpd_size;
4461
4462         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4463
4464         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4465
4466         /* take ownership of the relevant compute queues */
4467         amdgpu_gfx_compute_queue_acquire(adev);
4468         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4469
4470         if (mec_hpd_size) {
4471                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4472                                               AMDGPU_GEM_DOMAIN_GTT,
4473                                               &adev->gfx.mec.hpd_eop_obj,
4474                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4475                                               (void **)&hpd);
4476                 if (r) {
4477                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4478                         gfx_v10_0_mec_fini(adev);
4479                         return r;
4480                 }
4481
4482                 memset(hpd, 0, mec_hpd_size);
4483
4484                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4485                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4486         }
4487
4488         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4489                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4490
4491                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4492                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4493                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4494
4495                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4496                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4497                                               &adev->gfx.mec.mec_fw_obj,
4498                                               &adev->gfx.mec.mec_fw_gpu_addr,
4499                                               (void **)&fw);
4500                 if (r) {
4501                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4502                         gfx_v10_0_mec_fini(adev);
4503                         return r;
4504                 }
4505
4506                 memcpy(fw, fw_data, fw_size);
4507
4508                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4509                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4510         }
4511
4512         return 0;
4513 }
4514
4515 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4516 {
4517         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4518                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4519                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4520         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4521 }
4522
4523 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4524                            uint32_t thread, uint32_t regno,
4525                            uint32_t num, uint32_t *out)
4526 {
4527         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4528                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4529                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4530                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4531                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4532         while (num--)
4533                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4534 }
4535
4536 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4537 {
4538         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4539          * field when performing a select_se_sh so it should be
4540          * zero here */
4541         WARN_ON(simd != 0);
4542
4543         /* type 2 wave data */
4544         dst[(*no_fields)++] = 2;
4545         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4546         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4547         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4548         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4549         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4550         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4551         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4552         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4553         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4554         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4555         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4556         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4557         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4558         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4559         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4560         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4561 }
4562
4563 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4564                                      uint32_t wave, uint32_t start,
4565                                      uint32_t size, uint32_t *dst)
4566 {
4567         WARN_ON(simd != 0);
4568
4569         wave_read_regs(
4570                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4571                 dst);
4572 }
4573
4574 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4575                                       uint32_t wave, uint32_t thread,
4576                                       uint32_t start, uint32_t size,
4577                                       uint32_t *dst)
4578 {
4579         wave_read_regs(
4580                 adev, wave, thread,
4581                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4582 }
4583
4584 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4585                                        u32 me, u32 pipe, u32 q, u32 vm)
4586 {
4587         nv_grbm_select(adev, me, pipe, q, vm);
4588 }
4589
4590 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4591                                           bool enable)
4592 {
4593         uint32_t data, def;
4594
4595         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4596
4597         if (enable)
4598                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4599         else
4600                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4601
4602         if (data != def)
4603                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4604 }
4605
4606 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4607         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4608         .select_se_sh = &gfx_v10_0_select_se_sh,
4609         .read_wave_data = &gfx_v10_0_read_wave_data,
4610         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4611         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4612         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4613         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4614         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4615 };
4616
4617 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4618 {
4619         u32 gb_addr_config;
4620
4621         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4622
4623         switch (adev->ip_versions[GC_HWIP][0]) {
4624         case IP_VERSION(10, 1, 10):
4625         case IP_VERSION(10, 1, 1):
4626         case IP_VERSION(10, 1, 2):
4627                 adev->gfx.config.max_hw_contexts = 8;
4628                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4629                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4630                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4631                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4632                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4633                 break;
4634         case IP_VERSION(10, 3, 0):
4635         case IP_VERSION(10, 3, 2):
4636         case IP_VERSION(10, 3, 1):
4637         case IP_VERSION(10, 3, 4):
4638         case IP_VERSION(10, 3, 5):
4639         case IP_VERSION(10, 3, 6):
4640         case IP_VERSION(10, 3, 3):
4641         case IP_VERSION(10, 3, 7):
4642                 adev->gfx.config.max_hw_contexts = 8;
4643                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4644                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4645                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4646                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4647                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4648                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4649                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4650                 break;
4651         case IP_VERSION(10, 1, 3):
4652         case IP_VERSION(10, 1, 4):
4653                 adev->gfx.config.max_hw_contexts = 8;
4654                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4655                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4656                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4657                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4658                 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4659                 break;
4660         default:
4661                 BUG();
4662                 break;
4663         }
4664
4665         adev->gfx.config.gb_addr_config = gb_addr_config;
4666
4667         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4668                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4669                                       GB_ADDR_CONFIG, NUM_PIPES);
4670
4671         adev->gfx.config.max_tile_pipes =
4672                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4673
4674         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4675                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4676                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4677         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4678                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4679                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4680         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4681                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4682                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4683         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4684                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4685                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4686 }
4687
4688 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4689                                    int me, int pipe, int queue)
4690 {
4691         int r;
4692         struct amdgpu_ring *ring;
4693         unsigned int irq_type;
4694
4695         ring = &adev->gfx.gfx_ring[ring_id];
4696
4697         ring->me = me;
4698         ring->pipe = pipe;
4699         ring->queue = queue;
4700
4701         ring->ring_obj = NULL;
4702         ring->use_doorbell = true;
4703
4704         if (!ring_id)
4705                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4706         else
4707                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4708         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4709
4710         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4711         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4712                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4713         if (r)
4714                 return r;
4715         return 0;
4716 }
4717
4718 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4719                                        int mec, int pipe, int queue)
4720 {
4721         int r;
4722         unsigned irq_type;
4723         struct amdgpu_ring *ring;
4724         unsigned int hw_prio;
4725
4726         ring = &adev->gfx.compute_ring[ring_id];
4727
4728         /* mec0 is me1 */
4729         ring->me = mec + 1;
4730         ring->pipe = pipe;
4731         ring->queue = queue;
4732
4733         ring->ring_obj = NULL;
4734         ring->use_doorbell = true;
4735         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4736         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4737                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4738         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4739
4740         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4741                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4742                 + ring->pipe;
4743         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4744                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4745         /* type-2 packets are deprecated on MEC, use type-3 instead */
4746         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4747                              hw_prio, NULL);
4748         if (r)
4749                 return r;
4750
4751         return 0;
4752 }
4753
4754 static int gfx_v10_0_sw_init(void *handle)
4755 {
4756         int i, j, k, r, ring_id = 0;
4757         struct amdgpu_kiq *kiq;
4758         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4759
4760         switch (adev->ip_versions[GC_HWIP][0]) {
4761         case IP_VERSION(10, 1, 10):
4762         case IP_VERSION(10, 1, 1):
4763         case IP_VERSION(10, 1, 2):
4764         case IP_VERSION(10, 1, 3):
4765         case IP_VERSION(10, 1, 4):
4766                 adev->gfx.me.num_me = 1;
4767                 adev->gfx.me.num_pipe_per_me = 1;
4768                 adev->gfx.me.num_queue_per_pipe = 1;
4769                 adev->gfx.mec.num_mec = 2;
4770                 adev->gfx.mec.num_pipe_per_mec = 4;
4771                 adev->gfx.mec.num_queue_per_pipe = 8;
4772                 break;
4773         case IP_VERSION(10, 3, 0):
4774         case IP_VERSION(10, 3, 2):
4775         case IP_VERSION(10, 3, 1):
4776         case IP_VERSION(10, 3, 4):
4777         case IP_VERSION(10, 3, 5):
4778         case IP_VERSION(10, 3, 6):
4779         case IP_VERSION(10, 3, 3):
4780         case IP_VERSION(10, 3, 7):
4781                 adev->gfx.me.num_me = 1;
4782                 adev->gfx.me.num_pipe_per_me = 1;
4783                 adev->gfx.me.num_queue_per_pipe = 1;
4784                 adev->gfx.mec.num_mec = 2;
4785                 adev->gfx.mec.num_pipe_per_mec = 4;
4786                 adev->gfx.mec.num_queue_per_pipe = 4;
4787                 break;
4788         default:
4789                 adev->gfx.me.num_me = 1;
4790                 adev->gfx.me.num_pipe_per_me = 1;
4791                 adev->gfx.me.num_queue_per_pipe = 1;
4792                 adev->gfx.mec.num_mec = 1;
4793                 adev->gfx.mec.num_pipe_per_mec = 4;
4794                 adev->gfx.mec.num_queue_per_pipe = 8;
4795                 break;
4796         }
4797
4798         /* KIQ event */
4799         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4800                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4801                               &adev->gfx.kiq.irq);
4802         if (r)
4803                 return r;
4804
4805         /* EOP Event */
4806         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4807                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4808                               &adev->gfx.eop_irq);
4809         if (r)
4810                 return r;
4811
4812         /* Privileged reg */
4813         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4814                               &adev->gfx.priv_reg_irq);
4815         if (r)
4816                 return r;
4817
4818         /* Privileged inst */
4819         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4820                               &adev->gfx.priv_inst_irq);
4821         if (r)
4822                 return r;
4823
4824         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4825
4826         gfx_v10_0_scratch_init(adev);
4827
4828         r = gfx_v10_0_me_init(adev);
4829         if (r)
4830                 return r;
4831
4832         if (adev->gfx.rlc.funcs) {
4833                 if (adev->gfx.rlc.funcs->init) {
4834                         r = adev->gfx.rlc.funcs->init(adev);
4835                         if (r) {
4836                                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4837                                 return r;
4838                         }
4839                 }
4840         }
4841
4842         r = gfx_v10_0_mec_init(adev);
4843         if (r) {
4844                 DRM_ERROR("Failed to init MEC BOs!\n");
4845                 return r;
4846         }
4847
4848         /* set up the gfx ring */
4849         for (i = 0; i < adev->gfx.me.num_me; i++) {
4850                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4851                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4852                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4853                                         continue;
4854
4855                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4856                                                             i, k, j);
4857                                 if (r)
4858                                         return r;
4859                                 ring_id++;
4860                         }
4861                 }
4862         }
4863
4864         ring_id = 0;
4865         /* set up the compute queues - allocate horizontally across pipes */
4866         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4867                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4868                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4869                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4870                                                                      j))
4871                                         continue;
4872
4873                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4874                                                                 i, k, j);
4875                                 if (r)
4876                                         return r;
4877
4878                                 ring_id++;
4879                         }
4880                 }
4881         }
4882
4883         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4884         if (r) {
4885                 DRM_ERROR("Failed to init KIQ BOs!\n");
4886                 return r;
4887         }
4888
4889         kiq = &adev->gfx.kiq;
4890         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4891         if (r)
4892                 return r;
4893
4894         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4895         if (r)
4896                 return r;
4897
4898         /* allocate visible FB for rlc auto-loading fw */
4899         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4900                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4901                 if (r)
4902                         return r;
4903         }
4904
4905         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4906
4907         gfx_v10_0_gpu_early_init(adev);
4908
4909         return 0;
4910 }
4911
4912 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4913 {
4914         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4915                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4916                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4917 }
4918
4919 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4920 {
4921         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4922                               &adev->gfx.ce.ce_fw_gpu_addr,
4923                               (void **)&adev->gfx.ce.ce_fw_ptr);
4924 }
4925
4926 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4927 {
4928         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4929                               &adev->gfx.me.me_fw_gpu_addr,
4930                               (void **)&adev->gfx.me.me_fw_ptr);
4931 }
4932
4933 static int gfx_v10_0_sw_fini(void *handle)
4934 {
4935         int i;
4936         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4937
4938         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4939                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4940         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4941                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4942
4943         amdgpu_gfx_mqd_sw_fini(adev);
4944         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4945         amdgpu_gfx_kiq_fini(adev);
4946
4947         gfx_v10_0_pfp_fini(adev);
4948         gfx_v10_0_ce_fini(adev);
4949         gfx_v10_0_me_fini(adev);
4950         gfx_v10_0_rlc_fini(adev);
4951         gfx_v10_0_mec_fini(adev);
4952
4953         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4954                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4955
4956         gfx_v10_0_free_microcode(adev);
4957
4958         return 0;
4959 }
4960
4961 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4962                                    u32 sh_num, u32 instance)
4963 {
4964         u32 data;
4965
4966         if (instance == 0xffffffff)
4967                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4968                                      INSTANCE_BROADCAST_WRITES, 1);
4969         else
4970                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4971                                      instance);
4972
4973         if (se_num == 0xffffffff)
4974                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4975                                      1);
4976         else
4977                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4978
4979         if (sh_num == 0xffffffff)
4980                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4981                                      1);
4982         else
4983                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4984
4985         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4986 }
4987
4988 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4989 {
4990         u32 data, mask;
4991
4992         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4993         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4994
4995         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4996         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4997
4998         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4999                                          adev->gfx.config.max_sh_per_se);
5000
5001         return (~data) & mask;
5002 }
5003
5004 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5005 {
5006         int i, j;
5007         u32 data;
5008         u32 active_rbs = 0;
5009         u32 bitmap;
5010         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5011                                         adev->gfx.config.max_sh_per_se;
5012
5013         mutex_lock(&adev->grbm_idx_mutex);
5014         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5015                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5016                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
5017                         if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
5018                                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
5019                                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
5020                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5021                                 continue;
5022                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5023                         data = gfx_v10_0_get_rb_active_bitmap(adev);
5024                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5025                                                rb_bitmap_width_per_sh);
5026                 }
5027         }
5028         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5029         mutex_unlock(&adev->grbm_idx_mutex);
5030
5031         adev->gfx.config.backend_enable_mask = active_rbs;
5032         adev->gfx.config.num_rbs = hweight32(active_rbs);
5033 }
5034
5035 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5036 {
5037         uint32_t num_sc;
5038         uint32_t enabled_rb_per_sh;
5039         uint32_t active_rb_bitmap;
5040         uint32_t num_rb_per_sc;
5041         uint32_t num_packer_per_sc;
5042         uint32_t pa_sc_tile_steering_override;
5043
5044         /* for ASICs that integrates GFX v10.3
5045          * pa_sc_tile_steering_override should be set to 0 */
5046         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
5047                 return 0;
5048
5049         /* init num_sc */
5050         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5051                         adev->gfx.config.num_sc_per_sh;
5052         /* init num_rb_per_sc */
5053         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5054         enabled_rb_per_sh = hweight32(active_rb_bitmap);
5055         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5056         /* init num_packer_per_sc */
5057         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5058
5059         pa_sc_tile_steering_override = 0;
5060         pa_sc_tile_steering_override |=
5061                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5062                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5063         pa_sc_tile_steering_override |=
5064                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5065                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5066         pa_sc_tile_steering_override |=
5067                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5068                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5069
5070         return pa_sc_tile_steering_override;
5071 }
5072
5073 #define DEFAULT_SH_MEM_BASES    (0x6000)
5074
5075 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5076 {
5077         int i;
5078         uint32_t sh_mem_bases;
5079
5080         /*
5081          * Configure apertures:
5082          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5083          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5084          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5085          */
5086         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5087
5088         mutex_lock(&adev->srbm_mutex);
5089         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5090                 nv_grbm_select(adev, 0, 0, 0, i);
5091                 /* CP and shaders */
5092                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5093                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5094         }
5095         nv_grbm_select(adev, 0, 0, 0, 0);
5096         mutex_unlock(&adev->srbm_mutex);
5097
5098         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
5099            acccess. These should be enabled by FW for target VMIDs. */
5100         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5101                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5102                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5103                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5104                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5105         }
5106 }
5107
5108 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5109 {
5110         int vmid;
5111
5112         /*
5113          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5114          * access. Compute VMIDs should be enabled by FW for target VMIDs,
5115          * the driver can enable them for graphics. VMID0 should maintain
5116          * access so that HWS firmware can save/restore entries.
5117          */
5118         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5119                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5120                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5121                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5122                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5123         }
5124 }
5125
5126
5127 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5128 {
5129         int i, j, k;
5130         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5131         u32 tmp, wgp_active_bitmap = 0;
5132         u32 gcrd_targets_disable_tcp = 0;
5133         u32 utcl_invreq_disable = 0;
5134         /*
5135          * GCRD_TARGETS_DISABLE field contains
5136          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5137          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5138          */
5139         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5140                 2 * max_wgp_per_sh + /* TCP */
5141                 max_wgp_per_sh + /* SQC */
5142                 4); /* GL1C */
5143         /*
5144          * UTCL1_UTCL0_INVREQ_DISABLE field contains
5145          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5146          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5147          */
5148         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5149                 2 * max_wgp_per_sh + /* TCP */
5150                 2 * max_wgp_per_sh + /* SQC */
5151                 4 + /* RMI */
5152                 1); /* SQG */
5153
5154         mutex_lock(&adev->grbm_idx_mutex);
5155         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5156                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5157                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5158                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5159                         /*
5160                          * Set corresponding TCP bits for the inactive WGPs in
5161                          * GCRD_SA_TARGETS_DISABLE
5162                          */
5163                         gcrd_targets_disable_tcp = 0;
5164                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5165                         utcl_invreq_disable = 0;
5166
5167                         for (k = 0; k < max_wgp_per_sh; k++) {
5168                                 if (!(wgp_active_bitmap & (1 << k))) {
5169                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
5170                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5171                                         utcl_invreq_disable |= (3 << (2 * k)) |
5172                                                 (3 << (2 * (max_wgp_per_sh + k)));
5173                                 }
5174                         }
5175
5176                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5177                         /* only override TCP & SQC bits */
5178                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5179                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5180                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5181
5182                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5183                         /* only override TCP & SQC bits */
5184                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5185                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5186                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5187                 }
5188         }
5189
5190         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5191         mutex_unlock(&adev->grbm_idx_mutex);
5192 }
5193
5194 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5195 {
5196         /* TCCs are global (not instanced). */
5197         uint32_t tcc_disable;
5198
5199         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
5200                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5201                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5202         } else {
5203                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5204                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5205         }
5206
5207         adev->gfx.config.tcc_disabled_mask =
5208                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5209                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5210 }
5211
5212 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5213 {
5214         u32 tmp;
5215         int i;
5216
5217         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5218
5219         gfx_v10_0_setup_rb(adev);
5220         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5221         gfx_v10_0_get_tcc_info(adev);
5222         adev->gfx.config.pa_sc_tile_steering_override =
5223                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5224
5225         /* XXX SH_MEM regs */
5226         /* where to put LDS, scratch, GPUVM in FSA64 space */
5227         mutex_lock(&adev->srbm_mutex);
5228         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5229                 nv_grbm_select(adev, 0, 0, 0, i);
5230                 /* CP and shaders */
5231                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5232                 if (i != 0) {
5233                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5234                                 (adev->gmc.private_aperture_start >> 48));
5235                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5236                                 (adev->gmc.shared_aperture_start >> 48));
5237                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5238                 }
5239         }
5240         nv_grbm_select(adev, 0, 0, 0, 0);
5241
5242         mutex_unlock(&adev->srbm_mutex);
5243
5244         gfx_v10_0_init_compute_vmid(adev);
5245         gfx_v10_0_init_gds_vmid(adev);
5246
5247 }
5248
5249 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5250                                                bool enable)
5251 {
5252         u32 tmp;
5253
5254         if (amdgpu_sriov_vf(adev))
5255                 return;
5256
5257         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5258
5259         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5260                             enable ? 1 : 0);
5261         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5262                             enable ? 1 : 0);
5263         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5264                             enable ? 1 : 0);
5265         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5266                             enable ? 1 : 0);
5267
5268         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5269 }
5270
5271 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5272 {
5273         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5274
5275         /* csib */
5276         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5277                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5278                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5279                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5280                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5281                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5282         } else {
5283                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5284                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5285                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5286                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5287                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5288         }
5289         return 0;
5290 }
5291
5292 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5293 {
5294         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5295
5296         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5297         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5298 }
5299
5300 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5301 {
5302         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5303         udelay(50);
5304         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5305         udelay(50);
5306 }
5307
5308 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5309                                              bool enable)
5310 {
5311         uint32_t rlc_pg_cntl;
5312
5313         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5314
5315         if (!enable) {
5316                 /* RLC_PG_CNTL[23] = 0 (default)
5317                  * RLC will wait for handshake acks with SMU
5318                  * GFXOFF will be enabled
5319                  * RLC_PG_CNTL[23] = 1
5320                  * RLC will not issue any message to SMU
5321                  * hence no handshake between SMU & RLC
5322                  * GFXOFF will be disabled
5323                  */
5324                 rlc_pg_cntl |= 0x800000;
5325         } else
5326                 rlc_pg_cntl &= ~0x800000;
5327         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5328 }
5329
5330 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5331 {
5332         /* TODO: enable rlc & smu handshake until smu
5333          * and gfxoff feature works as expected */
5334         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5335                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5336
5337         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5338         udelay(50);
5339 }
5340
5341 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5342 {
5343         uint32_t tmp;
5344
5345         /* enable Save Restore Machine */
5346         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5347         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5348         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5349         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5350 }
5351
5352 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5353 {
5354         const struct rlc_firmware_header_v2_0 *hdr;
5355         const __le32 *fw_data;
5356         unsigned i, fw_size;
5357
5358         if (!adev->gfx.rlc_fw)
5359                 return -EINVAL;
5360
5361         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5362         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5363
5364         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5365                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5366         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5367
5368         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5369                      RLCG_UCODE_LOADING_START_ADDRESS);
5370
5371         for (i = 0; i < fw_size; i++)
5372                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5373                              le32_to_cpup(fw_data++));
5374
5375         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5376
5377         return 0;
5378 }
5379
5380 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5381 {
5382         int r;
5383
5384         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5385                 adev->psp.autoload_supported) {
5386
5387                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5388                 if (r)
5389                         return r;
5390
5391                 gfx_v10_0_init_csb(adev);
5392
5393                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5394                         gfx_v10_0_rlc_enable_srm(adev);
5395         } else {
5396                 if (amdgpu_sriov_vf(adev)) {
5397                         gfx_v10_0_init_csb(adev);
5398                         return 0;
5399                 }
5400
5401                 adev->gfx.rlc.funcs->stop(adev);
5402
5403                 /* disable CG */
5404                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5405
5406                 /* disable PG */
5407                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5408
5409                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5410                         /* legacy rlc firmware loading */
5411                         r = gfx_v10_0_rlc_load_microcode(adev);
5412                         if (r)
5413                                 return r;
5414                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5415                         /* rlc backdoor autoload firmware */
5416                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5417                         if (r)
5418                                 return r;
5419                 }
5420
5421                 gfx_v10_0_init_csb(adev);
5422
5423                 adev->gfx.rlc.funcs->start(adev);
5424
5425                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5426                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5427                         if (r)
5428                                 return r;
5429                 }
5430         }
5431         return 0;
5432 }
5433
5434 static struct {
5435         FIRMWARE_ID     id;
5436         unsigned int    offset;
5437         unsigned int    size;
5438 } rlc_autoload_info[FIRMWARE_ID_MAX];
5439
5440 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5441 {
5442         int ret;
5443         RLC_TABLE_OF_CONTENT *rlc_toc;
5444
5445         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5446                                         AMDGPU_GEM_DOMAIN_GTT,
5447                                         &adev->gfx.rlc.rlc_toc_bo,
5448                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5449                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5450         if (ret) {
5451                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5452                 return ret;
5453         }
5454
5455         /* Copy toc from psp sos fw to rlc toc buffer */
5456         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5457
5458         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5459         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5460                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5461                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5462                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5463                         /* Offset needs 4KB alignment */
5464                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5465                 }
5466
5467                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5468                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5469                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5470
5471                 rlc_toc++;
5472         }
5473
5474         return 0;
5475 }
5476
5477 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5478 {
5479         uint32_t total_size = 0;
5480         FIRMWARE_ID id;
5481         int ret;
5482
5483         ret = gfx_v10_0_parse_rlc_toc(adev);
5484         if (ret) {
5485                 dev_err(adev->dev, "failed to parse rlc toc\n");
5486                 return 0;
5487         }
5488
5489         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5490                 total_size += rlc_autoload_info[id].size;
5491
5492         /* In case the offset in rlc toc ucode is aligned */
5493         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5494                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5495                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5496
5497         return total_size;
5498 }
5499
5500 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5501 {
5502         int r;
5503         uint32_t total_size;
5504
5505         total_size = gfx_v10_0_calc_toc_total_size(adev);
5506
5507         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5508                                       AMDGPU_GEM_DOMAIN_GTT,
5509                                       &adev->gfx.rlc.rlc_autoload_bo,
5510                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5511                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5512         if (r) {
5513                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5514                 return r;
5515         }
5516
5517         return 0;
5518 }
5519
5520 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5521 {
5522         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5523                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5524                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5525         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5526                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5527                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5528 }
5529
5530 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5531                                                        FIRMWARE_ID id,
5532                                                        const void *fw_data,
5533                                                        uint32_t fw_size)
5534 {
5535         uint32_t toc_offset;
5536         uint32_t toc_fw_size;
5537         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5538
5539         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5540                 return;
5541
5542         toc_offset = rlc_autoload_info[id].offset;
5543         toc_fw_size = rlc_autoload_info[id].size;
5544
5545         if (fw_size == 0)
5546                 fw_size = toc_fw_size;
5547
5548         if (fw_size > toc_fw_size)
5549                 fw_size = toc_fw_size;
5550
5551         memcpy(ptr + toc_offset, fw_data, fw_size);
5552
5553         if (fw_size < toc_fw_size)
5554                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5555 }
5556
5557 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5558 {
5559         void *data;
5560         uint32_t size;
5561
5562         data = adev->gfx.rlc.rlc_toc_buf;
5563         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5564
5565         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5566                                                    FIRMWARE_ID_RLC_TOC,
5567                                                    data, size);
5568 }
5569
5570 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5571 {
5572         const __le32 *fw_data;
5573         uint32_t fw_size;
5574         const struct gfx_firmware_header_v1_0 *cp_hdr;
5575         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5576
5577         /* pfp ucode */
5578         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5579                 adev->gfx.pfp_fw->data;
5580         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5581                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5582         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5583         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5584                                                    FIRMWARE_ID_CP_PFP,
5585                                                    fw_data, fw_size);
5586
5587         /* ce ucode */
5588         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5589                 adev->gfx.ce_fw->data;
5590         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5591                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5592         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5593         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5594                                                    FIRMWARE_ID_CP_CE,
5595                                                    fw_data, fw_size);
5596
5597         /* me ucode */
5598         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5599                 adev->gfx.me_fw->data;
5600         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5601                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5602         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5603         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5604                                                    FIRMWARE_ID_CP_ME,
5605                                                    fw_data, fw_size);
5606
5607         /* rlc ucode */
5608         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5609                 adev->gfx.rlc_fw->data;
5610         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5611                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5612         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5613         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5614                                                    FIRMWARE_ID_RLC_G_UCODE,
5615                                                    fw_data, fw_size);
5616
5617         /* mec1 ucode */
5618         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5619                 adev->gfx.mec_fw->data;
5620         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5621                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5622         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5623                 cp_hdr->jt_size * 4;
5624         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5625                                                    FIRMWARE_ID_CP_MEC,
5626                                                    fw_data, fw_size);
5627         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5628 }
5629
5630 /* Temporarily put sdma part here */
5631 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5632 {
5633         const __le32 *fw_data;
5634         uint32_t fw_size;
5635         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5636         int i;
5637
5638         for (i = 0; i < adev->sdma.num_instances; i++) {
5639                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5640                         adev->sdma.instance[i].fw->data;
5641                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5642                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5643                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5644
5645                 if (i == 0) {
5646                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5647                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5648                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5649                                 FIRMWARE_ID_SDMA0_JT,
5650                                 (uint32_t *)fw_data +
5651                                 sdma_hdr->jt_offset,
5652                                 sdma_hdr->jt_size * 4);
5653                 } else if (i == 1) {
5654                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5655                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5656                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5657                                 FIRMWARE_ID_SDMA1_JT,
5658                                 (uint32_t *)fw_data +
5659                                 sdma_hdr->jt_offset,
5660                                 sdma_hdr->jt_size * 4);
5661                 }
5662         }
5663 }
5664
5665 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5666 {
5667         uint32_t rlc_g_offset, rlc_g_size, tmp;
5668         uint64_t gpu_addr;
5669
5670         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5671         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5672         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5673
5674         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5675         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5676         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5677
5678         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5679         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5680         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5681
5682         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5683         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5684                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5685                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5686                 return -EINVAL;
5687         }
5688
5689         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5690         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5691                 DRM_ERROR("RLC ROM should halt itself\n");
5692                 return -EINVAL;
5693         }
5694
5695         return 0;
5696 }
5697
5698 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5699 {
5700         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5701         uint32_t tmp;
5702         int i;
5703         uint64_t addr;
5704
5705         /* Trigger an invalidation of the L1 instruction caches */
5706         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5707         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5708         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5709
5710         /* Wait for invalidation complete */
5711         for (i = 0; i < usec_timeout; i++) {
5712                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5713                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5714                         INVALIDATE_CACHE_COMPLETE))
5715                         break;
5716                 udelay(1);
5717         }
5718
5719         if (i >= usec_timeout) {
5720                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5721                 return -EINVAL;
5722         }
5723
5724         /* Program me ucode address into intruction cache address register */
5725         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5726                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5727         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5728                         lower_32_bits(addr) & 0xFFFFF000);
5729         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5730                         upper_32_bits(addr));
5731
5732         return 0;
5733 }
5734
5735 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5736 {
5737         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5738         uint32_t tmp;
5739         int i;
5740         uint64_t addr;
5741
5742         /* Trigger an invalidation of the L1 instruction caches */
5743         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5744         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5745         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5746
5747         /* Wait for invalidation complete */
5748         for (i = 0; i < usec_timeout; i++) {
5749                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5750                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5751                         INVALIDATE_CACHE_COMPLETE))
5752                         break;
5753                 udelay(1);
5754         }
5755
5756         if (i >= usec_timeout) {
5757                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5758                 return -EINVAL;
5759         }
5760
5761         /* Program ce ucode address into intruction cache address register */
5762         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5763                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5764         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5765                         lower_32_bits(addr) & 0xFFFFF000);
5766         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5767                         upper_32_bits(addr));
5768
5769         return 0;
5770 }
5771
5772 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5773 {
5774         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5775         uint32_t tmp;
5776         int i;
5777         uint64_t addr;
5778
5779         /* Trigger an invalidation of the L1 instruction caches */
5780         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5781         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5782         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5783
5784         /* Wait for invalidation complete */
5785         for (i = 0; i < usec_timeout; i++) {
5786                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5787                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5788                         INVALIDATE_CACHE_COMPLETE))
5789                         break;
5790                 udelay(1);
5791         }
5792
5793         if (i >= usec_timeout) {
5794                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5795                 return -EINVAL;
5796         }
5797
5798         /* Program pfp ucode address into intruction cache address register */
5799         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5800                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5801         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5802                         lower_32_bits(addr) & 0xFFFFF000);
5803         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5804                         upper_32_bits(addr));
5805
5806         return 0;
5807 }
5808
5809 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5810 {
5811         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5812         uint32_t tmp;
5813         int i;
5814         uint64_t addr;
5815
5816         /* Trigger an invalidation of the L1 instruction caches */
5817         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5818         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5819         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5820
5821         /* Wait for invalidation complete */
5822         for (i = 0; i < usec_timeout; i++) {
5823                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5824                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5825                         INVALIDATE_CACHE_COMPLETE))
5826                         break;
5827                 udelay(1);
5828         }
5829
5830         if (i >= usec_timeout) {
5831                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5832                 return -EINVAL;
5833         }
5834
5835         /* Program mec1 ucode address into intruction cache address register */
5836         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5837                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5838         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5839                         lower_32_bits(addr) & 0xFFFFF000);
5840         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5841                         upper_32_bits(addr));
5842
5843         return 0;
5844 }
5845
5846 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5847 {
5848         uint32_t cp_status;
5849         uint32_t bootload_status;
5850         int i, r;
5851
5852         for (i = 0; i < adev->usec_timeout; i++) {
5853                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5854                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5855                 if ((cp_status == 0) &&
5856                     (REG_GET_FIELD(bootload_status,
5857                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5858                         break;
5859                 }
5860                 udelay(1);
5861         }
5862
5863         if (i >= adev->usec_timeout) {
5864                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5865                 return -ETIMEDOUT;
5866         }
5867
5868         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5869                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5870                 if (r)
5871                         return r;
5872
5873                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5874                 if (r)
5875                         return r;
5876
5877                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5878                 if (r)
5879                         return r;
5880
5881                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5882                 if (r)
5883                         return r;
5884         }
5885
5886         return 0;
5887 }
5888
5889 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5890 {
5891         int i;
5892         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5893
5894         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5895         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5896         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5897
5898         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5899                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5900         } else {
5901                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5902         }
5903
5904         for (i = 0; i < adev->usec_timeout; i++) {
5905                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5906                         break;
5907                 udelay(1);
5908         }
5909
5910         if (i >= adev->usec_timeout)
5911                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5912
5913         return 0;
5914 }
5915
5916 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5917 {
5918         int r;
5919         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5920         const __le32 *fw_data;
5921         unsigned i, fw_size;
5922         uint32_t tmp;
5923         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5924
5925         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5926                 adev->gfx.pfp_fw->data;
5927
5928         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5929
5930         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5931                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5932         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5933
5934         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5935                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5936                                       &adev->gfx.pfp.pfp_fw_obj,
5937                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5938                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5939         if (r) {
5940                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5941                 gfx_v10_0_pfp_fini(adev);
5942                 return r;
5943         }
5944
5945         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5946
5947         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5948         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5949
5950         /* Trigger an invalidation of the L1 instruction caches */
5951         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5952         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5953         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5954
5955         /* Wait for invalidation complete */
5956         for (i = 0; i < usec_timeout; i++) {
5957                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5958                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5959                         INVALIDATE_CACHE_COMPLETE))
5960                         break;
5961                 udelay(1);
5962         }
5963
5964         if (i >= usec_timeout) {
5965                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5966                 return -EINVAL;
5967         }
5968
5969         if (amdgpu_emu_mode == 1)
5970                 adev->hdp.funcs->flush_hdp(adev, NULL);
5971
5972         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5973         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5974         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5975         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5976         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5977         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5978         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5979                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5980         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5981                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5982
5983         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5984
5985         for (i = 0; i < pfp_hdr->jt_size; i++)
5986                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5987                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5988
5989         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5990
5991         return 0;
5992 }
5993
5994 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5995 {
5996         int r;
5997         const struct gfx_firmware_header_v1_0 *ce_hdr;
5998         const __le32 *fw_data;
5999         unsigned i, fw_size;
6000         uint32_t tmp;
6001         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6002
6003         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6004                 adev->gfx.ce_fw->data;
6005
6006         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6007
6008         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6009                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6010         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6011
6012         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6013                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6014                                       &adev->gfx.ce.ce_fw_obj,
6015                                       &adev->gfx.ce.ce_fw_gpu_addr,
6016                                       (void **)&adev->gfx.ce.ce_fw_ptr);
6017         if (r) {
6018                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6019                 gfx_v10_0_ce_fini(adev);
6020                 return r;
6021         }
6022
6023         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6024
6025         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6026         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6027
6028         /* Trigger an invalidation of the L1 instruction caches */
6029         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6030         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6031         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6032
6033         /* Wait for invalidation complete */
6034         for (i = 0; i < usec_timeout; i++) {
6035                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6036                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6037                         INVALIDATE_CACHE_COMPLETE))
6038                         break;
6039                 udelay(1);
6040         }
6041
6042         if (i >= usec_timeout) {
6043                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6044                 return -EINVAL;
6045         }
6046
6047         if (amdgpu_emu_mode == 1)
6048                 adev->hdp.funcs->flush_hdp(adev, NULL);
6049
6050         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6051         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6052         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6053         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6054         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6055         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6056                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6057         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6058                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6059
6060         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6061
6062         for (i = 0; i < ce_hdr->jt_size; i++)
6063                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6064                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6065
6066         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6067
6068         return 0;
6069 }
6070
6071 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6072 {
6073         int r;
6074         const struct gfx_firmware_header_v1_0 *me_hdr;
6075         const __le32 *fw_data;
6076         unsigned i, fw_size;
6077         uint32_t tmp;
6078         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6079
6080         me_hdr = (const struct gfx_firmware_header_v1_0 *)
6081                 adev->gfx.me_fw->data;
6082
6083         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6084
6085         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6086                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6087         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6088
6089         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6090                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6091                                       &adev->gfx.me.me_fw_obj,
6092                                       &adev->gfx.me.me_fw_gpu_addr,
6093                                       (void **)&adev->gfx.me.me_fw_ptr);
6094         if (r) {
6095                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6096                 gfx_v10_0_me_fini(adev);
6097                 return r;
6098         }
6099
6100         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6101
6102         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6103         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6104
6105         /* Trigger an invalidation of the L1 instruction caches */
6106         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6107         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6108         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6109
6110         /* Wait for invalidation complete */
6111         for (i = 0; i < usec_timeout; i++) {
6112                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6113                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6114                         INVALIDATE_CACHE_COMPLETE))
6115                         break;
6116                 udelay(1);
6117         }
6118
6119         if (i >= usec_timeout) {
6120                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6121                 return -EINVAL;
6122         }
6123
6124         if (amdgpu_emu_mode == 1)
6125                 adev->hdp.funcs->flush_hdp(adev, NULL);
6126
6127         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6128         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6129         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6130         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6131         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6132         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6133                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6134         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6135                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6136
6137         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6138
6139         for (i = 0; i < me_hdr->jt_size; i++)
6140                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6141                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6142
6143         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6144
6145         return 0;
6146 }
6147
6148 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6149 {
6150         int r;
6151
6152         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6153                 return -EINVAL;
6154
6155         gfx_v10_0_cp_gfx_enable(adev, false);
6156
6157         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6158         if (r) {
6159                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6160                 return r;
6161         }
6162
6163         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6164         if (r) {
6165                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6166                 return r;
6167         }
6168
6169         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6170         if (r) {
6171                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6172                 return r;
6173         }
6174
6175         return 0;
6176 }
6177
6178 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6179 {
6180         struct amdgpu_ring *ring;
6181         const struct cs_section_def *sect = NULL;
6182         const struct cs_extent_def *ext = NULL;
6183         int r, i;
6184         int ctx_reg_offset;
6185
6186         /* init the CP */
6187         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6188                      adev->gfx.config.max_hw_contexts - 1);
6189         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6190
6191         gfx_v10_0_cp_gfx_enable(adev, true);
6192
6193         ring = &adev->gfx.gfx_ring[0];
6194         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6195         if (r) {
6196                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6197                 return r;
6198         }
6199
6200         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6201         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6202
6203         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6204         amdgpu_ring_write(ring, 0x80000000);
6205         amdgpu_ring_write(ring, 0x80000000);
6206
6207         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6208                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6209                         if (sect->id == SECT_CONTEXT) {
6210                                 amdgpu_ring_write(ring,
6211                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6212                                                           ext->reg_count));
6213                                 amdgpu_ring_write(ring, ext->reg_index -
6214                                                   PACKET3_SET_CONTEXT_REG_START);
6215                                 for (i = 0; i < ext->reg_count; i++)
6216                                         amdgpu_ring_write(ring, ext->extent[i]);
6217                         }
6218                 }
6219         }
6220
6221         ctx_reg_offset =
6222                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6223         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6224         amdgpu_ring_write(ring, ctx_reg_offset);
6225         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6226
6227         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6228         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6229
6230         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6231         amdgpu_ring_write(ring, 0);
6232
6233         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6234         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6235         amdgpu_ring_write(ring, 0x8000);
6236         amdgpu_ring_write(ring, 0x8000);
6237
6238         amdgpu_ring_commit(ring);
6239
6240         /* submit cs packet to copy state 0 to next available state */
6241         if (adev->gfx.num_gfx_rings > 1) {
6242                 /* maximum supported gfx ring is 2 */
6243                 ring = &adev->gfx.gfx_ring[1];
6244                 r = amdgpu_ring_alloc(ring, 2);
6245                 if (r) {
6246                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6247                         return r;
6248                 }
6249
6250                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6251                 amdgpu_ring_write(ring, 0);
6252
6253                 amdgpu_ring_commit(ring);
6254         }
6255         return 0;
6256 }
6257
6258 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6259                                          CP_PIPE_ID pipe)
6260 {
6261         u32 tmp;
6262
6263         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6264         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6265
6266         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6267 }
6268
6269 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6270                                           struct amdgpu_ring *ring)
6271 {
6272         u32 tmp;
6273
6274         if (!amdgpu_async_gfx_ring) {
6275                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6276                 if (ring->use_doorbell) {
6277                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6278                                                 DOORBELL_OFFSET, ring->doorbell_index);
6279                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6280                                                 DOORBELL_EN, 1);
6281                 } else {
6282                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6283                                                 DOORBELL_EN, 0);
6284                 }
6285                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6286         }
6287         switch (adev->ip_versions[GC_HWIP][0]) {
6288         case IP_VERSION(10, 3, 0):
6289         case IP_VERSION(10, 3, 2):
6290         case IP_VERSION(10, 3, 1):
6291         case IP_VERSION(10, 3, 4):
6292         case IP_VERSION(10, 3, 5):
6293         case IP_VERSION(10, 3, 6):
6294         case IP_VERSION(10, 3, 3):
6295         case IP_VERSION(10, 3, 7):
6296                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6297                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6298                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6299
6300                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6301                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6302                 break;
6303         default:
6304                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6305                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6306                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6307
6308                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6309                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6310                 break;
6311         }
6312 }
6313
6314 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6315 {
6316         struct amdgpu_ring *ring;
6317         u32 tmp;
6318         u32 rb_bufsz;
6319         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6320         u32 i;
6321
6322         /* Set the write pointer delay */
6323         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6324
6325         /* set the RB to use vmid 0 */
6326         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6327
6328         /* Init gfx ring 0 for pipe 0 */
6329         mutex_lock(&adev->srbm_mutex);
6330         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6331
6332         /* Set ring buffer size */
6333         ring = &adev->gfx.gfx_ring[0];
6334         rb_bufsz = order_base_2(ring->ring_size / 8);
6335         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6336         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6337 #ifdef __BIG_ENDIAN
6338         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6339 #endif
6340         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6341
6342         /* Initialize the ring buffer's write pointers */
6343         ring->wptr = 0;
6344         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6345         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6346
6347         /* set the wb address wether it's enabled or not */
6348         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6349         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6350         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6351                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6352
6353         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6354         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6355                      lower_32_bits(wptr_gpu_addr));
6356         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6357                      upper_32_bits(wptr_gpu_addr));
6358
6359         mdelay(1);
6360         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6361
6362         rb_addr = ring->gpu_addr >> 8;
6363         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6364         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6365
6366         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6367
6368         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6369         mutex_unlock(&adev->srbm_mutex);
6370
6371         /* Init gfx ring 1 for pipe 1 */
6372         if (adev->gfx.num_gfx_rings > 1) {
6373                 mutex_lock(&adev->srbm_mutex);
6374                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6375                 /* maximum supported gfx ring is 2 */
6376                 ring = &adev->gfx.gfx_ring[1];
6377                 rb_bufsz = order_base_2(ring->ring_size / 8);
6378                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6379                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6380                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6381                 /* Initialize the ring buffer's write pointers */
6382                 ring->wptr = 0;
6383                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6384                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6385                 /* Set the wb address wether it's enabled or not */
6386                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6387                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6388                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6389                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6390                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6391                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6392                              lower_32_bits(wptr_gpu_addr));
6393                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6394                              upper_32_bits(wptr_gpu_addr));
6395
6396                 mdelay(1);
6397                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6398
6399                 rb_addr = ring->gpu_addr >> 8;
6400                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6401                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6402                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6403
6404                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6405                 mutex_unlock(&adev->srbm_mutex);
6406         }
6407         /* Switch to pipe 0 */
6408         mutex_lock(&adev->srbm_mutex);
6409         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6410         mutex_unlock(&adev->srbm_mutex);
6411
6412         /* start the ring */
6413         gfx_v10_0_cp_gfx_start(adev);
6414
6415         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6416                 ring = &adev->gfx.gfx_ring[i];
6417                 ring->sched.ready = true;
6418         }
6419
6420         return 0;
6421 }
6422
6423 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6424 {
6425         if (enable) {
6426                 switch (adev->ip_versions[GC_HWIP][0]) {
6427                 case IP_VERSION(10, 3, 0):
6428                 case IP_VERSION(10, 3, 2):
6429                 case IP_VERSION(10, 3, 1):
6430                 case IP_VERSION(10, 3, 4):
6431                 case IP_VERSION(10, 3, 5):
6432                 case IP_VERSION(10, 3, 6):
6433                 case IP_VERSION(10, 3, 3):
6434                 case IP_VERSION(10, 3, 7):
6435                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6436                         break;
6437                 default:
6438                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6439                         break;
6440                 }
6441         } else {
6442                 switch (adev->ip_versions[GC_HWIP][0]) {
6443                 case IP_VERSION(10, 3, 0):
6444                 case IP_VERSION(10, 3, 2):
6445                 case IP_VERSION(10, 3, 1):
6446                 case IP_VERSION(10, 3, 4):
6447                 case IP_VERSION(10, 3, 5):
6448                 case IP_VERSION(10, 3, 6):
6449                 case IP_VERSION(10, 3, 3):
6450                 case IP_VERSION(10, 3, 7):
6451                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6452                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6453                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6454                         break;
6455                 default:
6456                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6457                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6458                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6459                         break;
6460                 }
6461                 adev->gfx.kiq.ring.sched.ready = false;
6462         }
6463         udelay(50);
6464 }
6465
6466 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6467 {
6468         const struct gfx_firmware_header_v1_0 *mec_hdr;
6469         const __le32 *fw_data;
6470         unsigned i;
6471         u32 tmp;
6472         u32 usec_timeout = 50000; /* Wait for 50 ms */
6473
6474         if (!adev->gfx.mec_fw)
6475                 return -EINVAL;
6476
6477         gfx_v10_0_cp_compute_enable(adev, false);
6478
6479         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6480         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6481
6482         fw_data = (const __le32 *)
6483                 (adev->gfx.mec_fw->data +
6484                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6485
6486         /* Trigger an invalidation of the L1 instruction caches */
6487         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6488         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6489         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6490
6491         /* Wait for invalidation complete */
6492         for (i = 0; i < usec_timeout; i++) {
6493                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6494                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6495                                        INVALIDATE_CACHE_COMPLETE))
6496                         break;
6497                 udelay(1);
6498         }
6499
6500         if (i >= usec_timeout) {
6501                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6502                 return -EINVAL;
6503         }
6504
6505         if (amdgpu_emu_mode == 1)
6506                 adev->hdp.funcs->flush_hdp(adev, NULL);
6507
6508         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6509         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6510         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6511         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6512         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6513
6514         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6515                      0xFFFFF000);
6516         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6517                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6518
6519         /* MEC1 */
6520         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6521
6522         for (i = 0; i < mec_hdr->jt_size; i++)
6523                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6524                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6525
6526         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6527
6528         /*
6529          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6530          * different microcode than MEC1.
6531          */
6532
6533         return 0;
6534 }
6535
6536 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6537 {
6538         uint32_t tmp;
6539         struct amdgpu_device *adev = ring->adev;
6540
6541         /* tell RLC which is KIQ queue */
6542         switch (adev->ip_versions[GC_HWIP][0]) {
6543         case IP_VERSION(10, 3, 0):
6544         case IP_VERSION(10, 3, 2):
6545         case IP_VERSION(10, 3, 1):
6546         case IP_VERSION(10, 3, 4):
6547         case IP_VERSION(10, 3, 5):
6548         case IP_VERSION(10, 3, 6):
6549         case IP_VERSION(10, 3, 3):
6550         case IP_VERSION(10, 3, 7):
6551                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6552                 tmp &= 0xffffff00;
6553                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6554                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6555                 tmp |= 0x80;
6556                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6557                 break;
6558         default:
6559                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6560                 tmp &= 0xffffff00;
6561                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6562                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6563                 tmp |= 0x80;
6564                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6565                 break;
6566         }
6567 }
6568
6569 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6570 {
6571         struct amdgpu_device *adev = ring->adev;
6572         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6573         uint64_t hqd_gpu_addr, wb_gpu_addr;
6574         uint32_t tmp;
6575         uint32_t rb_bufsz;
6576
6577         /* set up gfx hqd wptr */
6578         mqd->cp_gfx_hqd_wptr = 0;
6579         mqd->cp_gfx_hqd_wptr_hi = 0;
6580
6581         /* set the pointer to the MQD */
6582         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6583         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6584
6585         /* set up mqd control */
6586         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6587         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6588         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6589         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6590         mqd->cp_gfx_mqd_control = tmp;
6591
6592         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6593         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6594         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6595         mqd->cp_gfx_hqd_vmid = 0;
6596
6597         /* set up default queue priority level
6598          * 0x0 = low priority, 0x1 = high priority */
6599         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6600         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6601         mqd->cp_gfx_hqd_queue_priority = tmp;
6602
6603         /* set up time quantum */
6604         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6605         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6606         mqd->cp_gfx_hqd_quantum = tmp;
6607
6608         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6609         hqd_gpu_addr = ring->gpu_addr >> 8;
6610         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6611         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6612
6613         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6614         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6615         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6616         mqd->cp_gfx_hqd_rptr_addr_hi =
6617                 upper_32_bits(wb_gpu_addr) & 0xffff;
6618
6619         /* set up rb_wptr_poll addr */
6620         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6621         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6622         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6623
6624         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6625         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6626         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6627         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6628         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6629 #ifdef __BIG_ENDIAN
6630         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6631 #endif
6632         mqd->cp_gfx_hqd_cntl = tmp;
6633
6634         /* set up cp_doorbell_control */
6635         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6636         if (ring->use_doorbell) {
6637                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6638                                     DOORBELL_OFFSET, ring->doorbell_index);
6639                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6640                                     DOORBELL_EN, 1);
6641         } else
6642                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6643                                     DOORBELL_EN, 0);
6644         mqd->cp_rb_doorbell_control = tmp;
6645
6646         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6647          *otherwise the range of the second ring will override the first ring */
6648         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6649                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6650
6651         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6652         ring->wptr = 0;
6653         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6654
6655         /* active the queue */
6656         mqd->cp_gfx_hqd_active = 1;
6657
6658         return 0;
6659 }
6660
6661 #ifdef BRING_UP_DEBUG
6662 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6663 {
6664         struct amdgpu_device *adev = ring->adev;
6665         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6666
6667         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6668         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6669         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6670
6671         /* set GFX_MQD_BASE */
6672         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6673         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6674
6675         /* set GFX_MQD_CONTROL */
6676         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6677
6678         /* set GFX_HQD_VMID to 0 */
6679         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6680
6681         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6682                         mqd->cp_gfx_hqd_queue_priority);
6683         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6684
6685         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6686         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6687         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6688
6689         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6690         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6691         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6692
6693         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6694         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6695
6696         /* set RB_WPTR_POLL_ADDR */
6697         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6698         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6699
6700         /* set RB_DOORBELL_CONTROL */
6701         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6702
6703         /* active the queue */
6704         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6705
6706         return 0;
6707 }
6708 #endif
6709
6710 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6711 {
6712         struct amdgpu_device *adev = ring->adev;
6713         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6714         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6715
6716         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6717                 memset((void *)mqd, 0, sizeof(*mqd));
6718                 mutex_lock(&adev->srbm_mutex);
6719                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6720                 gfx_v10_0_gfx_mqd_init(ring);
6721 #ifdef BRING_UP_DEBUG
6722                 gfx_v10_0_gfx_queue_init_register(ring);
6723 #endif
6724                 nv_grbm_select(adev, 0, 0, 0, 0);
6725                 mutex_unlock(&adev->srbm_mutex);
6726                 if (adev->gfx.me.mqd_backup[mqd_idx])
6727                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6728         } else if (amdgpu_in_reset(adev)) {
6729                 /* reset mqd with the backup copy */
6730                 if (adev->gfx.me.mqd_backup[mqd_idx])
6731                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6732                 /* reset the ring */
6733                 ring->wptr = 0;
6734                 adev->wb.wb[ring->wptr_offs] = 0;
6735                 amdgpu_ring_clear_ring(ring);
6736 #ifdef BRING_UP_DEBUG
6737                 mutex_lock(&adev->srbm_mutex);
6738                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6739                 gfx_v10_0_gfx_queue_init_register(ring);
6740                 nv_grbm_select(adev, 0, 0, 0, 0);
6741                 mutex_unlock(&adev->srbm_mutex);
6742 #endif
6743         } else {
6744                 amdgpu_ring_clear_ring(ring);
6745         }
6746
6747         return 0;
6748 }
6749
6750 #ifndef BRING_UP_DEBUG
6751 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6752 {
6753         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6754         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6755         int r, i;
6756
6757         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6758                 return -EINVAL;
6759
6760         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6761                                         adev->gfx.num_gfx_rings);
6762         if (r) {
6763                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6764                 return r;
6765         }
6766
6767         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6768                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6769
6770         return amdgpu_ring_test_helper(kiq_ring);
6771 }
6772 #endif
6773
6774 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6775 {
6776         int r, i;
6777         struct amdgpu_ring *ring;
6778
6779         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6780                 ring = &adev->gfx.gfx_ring[i];
6781
6782                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6783                 if (unlikely(r != 0))
6784                         goto done;
6785
6786                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6787                 if (!r) {
6788                         r = gfx_v10_0_gfx_init_queue(ring);
6789                         amdgpu_bo_kunmap(ring->mqd_obj);
6790                         ring->mqd_ptr = NULL;
6791                 }
6792                 amdgpu_bo_unreserve(ring->mqd_obj);
6793                 if (r)
6794                         goto done;
6795         }
6796 #ifndef BRING_UP_DEBUG
6797         r = gfx_v10_0_kiq_enable_kgq(adev);
6798         if (r)
6799                 goto done;
6800 #endif
6801         r = gfx_v10_0_cp_gfx_start(adev);
6802         if (r)
6803                 goto done;
6804
6805         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6806                 ring = &adev->gfx.gfx_ring[i];
6807                 ring->sched.ready = true;
6808         }
6809 done:
6810         return r;
6811 }
6812
6813 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6814 {
6815         struct amdgpu_device *adev = ring->adev;
6816
6817         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6818                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6819                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6820                         mqd->cp_hqd_queue_priority =
6821                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6822                 }
6823         }
6824 }
6825
6826 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6827 {
6828         struct amdgpu_device *adev = ring->adev;
6829         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6830         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6831         uint32_t tmp;
6832
6833         mqd->header = 0xC0310800;
6834         mqd->compute_pipelinestat_enable = 0x00000001;
6835         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6836         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6837         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6838         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6839         mqd->compute_misc_reserved = 0x00000003;
6840
6841         eop_base_addr = ring->eop_gpu_addr >> 8;
6842         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6843         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6844
6845         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6846         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6847         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6848                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6849
6850         mqd->cp_hqd_eop_control = tmp;
6851
6852         /* enable doorbell? */
6853         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6854
6855         if (ring->use_doorbell) {
6856                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6857                                     DOORBELL_OFFSET, ring->doorbell_index);
6858                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6859                                     DOORBELL_EN, 1);
6860                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6861                                     DOORBELL_SOURCE, 0);
6862                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6863                                     DOORBELL_HIT, 0);
6864         } else {
6865                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6866                                     DOORBELL_EN, 0);
6867         }
6868
6869         mqd->cp_hqd_pq_doorbell_control = tmp;
6870
6871         /* disable the queue if it's active */
6872         ring->wptr = 0;
6873         mqd->cp_hqd_dequeue_request = 0;
6874         mqd->cp_hqd_pq_rptr = 0;
6875         mqd->cp_hqd_pq_wptr_lo = 0;
6876         mqd->cp_hqd_pq_wptr_hi = 0;
6877
6878         /* set the pointer to the MQD */
6879         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6880         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6881
6882         /* set MQD vmid to 0 */
6883         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6884         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6885         mqd->cp_mqd_control = tmp;
6886
6887         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6888         hqd_gpu_addr = ring->gpu_addr >> 8;
6889         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6890         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6891
6892         /* set up the HQD, this is similar to CP_RB0_CNTL */
6893         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6894         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6895                             (order_base_2(ring->ring_size / 4) - 1));
6896         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6897                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6898 #ifdef __BIG_ENDIAN
6899         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6900 #endif
6901         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6902         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6903         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6904         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6905         mqd->cp_hqd_pq_control = tmp;
6906
6907         /* set the wb address whether it's enabled or not */
6908         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6909         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6910         mqd->cp_hqd_pq_rptr_report_addr_hi =
6911                 upper_32_bits(wb_gpu_addr) & 0xffff;
6912
6913         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6914         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6915         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6916         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6917
6918         tmp = 0;
6919         /* enable the doorbell if requested */
6920         if (ring->use_doorbell) {
6921                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6922                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6923                                 DOORBELL_OFFSET, ring->doorbell_index);
6924
6925                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6926                                     DOORBELL_EN, 1);
6927                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6928                                     DOORBELL_SOURCE, 0);
6929                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6930                                     DOORBELL_HIT, 0);
6931         }
6932
6933         mqd->cp_hqd_pq_doorbell_control = tmp;
6934
6935         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6936         ring->wptr = 0;
6937         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6938
6939         /* set the vmid for the queue */
6940         mqd->cp_hqd_vmid = 0;
6941
6942         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6943         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6944         mqd->cp_hqd_persistent_state = tmp;
6945
6946         /* set MIN_IB_AVAIL_SIZE */
6947         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6948         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6949         mqd->cp_hqd_ib_control = tmp;
6950
6951         /* set static priority for a compute queue/ring */
6952         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6953
6954         /* map_queues packet doesn't need activate the queue,
6955          * so only kiq need set this field.
6956          */
6957         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6958                 mqd->cp_hqd_active = 1;
6959
6960         return 0;
6961 }
6962
6963 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6964 {
6965         struct amdgpu_device *adev = ring->adev;
6966         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6967         int j;
6968
6969         /* inactivate the queue */
6970         if (amdgpu_sriov_vf(adev))
6971                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6972
6973         /* disable wptr polling */
6974         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6975
6976         /* write the EOP addr */
6977         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6978                mqd->cp_hqd_eop_base_addr_lo);
6979         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6980                mqd->cp_hqd_eop_base_addr_hi);
6981
6982         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6983         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6984                mqd->cp_hqd_eop_control);
6985
6986         /* enable doorbell? */
6987         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6988                mqd->cp_hqd_pq_doorbell_control);
6989
6990         /* disable the queue if it's active */
6991         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6992                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6993                 for (j = 0; j < adev->usec_timeout; j++) {
6994                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6995                                 break;
6996                         udelay(1);
6997                 }
6998                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6999                        mqd->cp_hqd_dequeue_request);
7000                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
7001                        mqd->cp_hqd_pq_rptr);
7002                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7003                        mqd->cp_hqd_pq_wptr_lo);
7004                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7005                        mqd->cp_hqd_pq_wptr_hi);
7006         }
7007
7008         /* set the pointer to the MQD */
7009         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7010                mqd->cp_mqd_base_addr_lo);
7011         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7012                mqd->cp_mqd_base_addr_hi);
7013
7014         /* set MQD vmid to 0 */
7015         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7016                mqd->cp_mqd_control);
7017
7018         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7019         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7020                mqd->cp_hqd_pq_base_lo);
7021         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7022                mqd->cp_hqd_pq_base_hi);
7023
7024         /* set up the HQD, this is similar to CP_RB0_CNTL */
7025         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7026                mqd->cp_hqd_pq_control);
7027
7028         /* set the wb address whether it's enabled or not */
7029         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7030                 mqd->cp_hqd_pq_rptr_report_addr_lo);
7031         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7032                 mqd->cp_hqd_pq_rptr_report_addr_hi);
7033
7034         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7035         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7036                mqd->cp_hqd_pq_wptr_poll_addr_lo);
7037         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7038                mqd->cp_hqd_pq_wptr_poll_addr_hi);
7039
7040         /* enable the doorbell if requested */
7041         if (ring->use_doorbell) {
7042                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7043                         (adev->doorbell_index.kiq * 2) << 2);
7044                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7045                         (adev->doorbell_index.userqueue_end * 2) << 2);
7046         }
7047
7048         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7049                mqd->cp_hqd_pq_doorbell_control);
7050
7051         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7052         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7053                mqd->cp_hqd_pq_wptr_lo);
7054         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7055                mqd->cp_hqd_pq_wptr_hi);
7056
7057         /* set the vmid for the queue */
7058         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7059
7060         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7061                mqd->cp_hqd_persistent_state);
7062
7063         /* activate the queue */
7064         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7065                mqd->cp_hqd_active);
7066
7067         if (ring->use_doorbell)
7068                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7069
7070         return 0;
7071 }
7072
7073 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7074 {
7075         struct amdgpu_device *adev = ring->adev;
7076         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7077         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7078
7079         gfx_v10_0_kiq_setting(ring);
7080
7081         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7082                 /* reset MQD to a clean status */
7083                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7084                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7085
7086                 /* reset ring buffer */
7087                 ring->wptr = 0;
7088                 amdgpu_ring_clear_ring(ring);
7089
7090                 mutex_lock(&adev->srbm_mutex);
7091                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7092                 gfx_v10_0_kiq_init_register(ring);
7093                 nv_grbm_select(adev, 0, 0, 0, 0);
7094                 mutex_unlock(&adev->srbm_mutex);
7095         } else {
7096                 memset((void *)mqd, 0, sizeof(*mqd));
7097                 mutex_lock(&adev->srbm_mutex);
7098                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7099                 gfx_v10_0_compute_mqd_init(ring);
7100                 gfx_v10_0_kiq_init_register(ring);
7101                 nv_grbm_select(adev, 0, 0, 0, 0);
7102                 mutex_unlock(&adev->srbm_mutex);
7103
7104                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7105                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7106         }
7107
7108         return 0;
7109 }
7110
7111 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7112 {
7113         struct amdgpu_device *adev = ring->adev;
7114         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7115         int mqd_idx = ring - &adev->gfx.compute_ring[0];
7116
7117         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7118                 memset((void *)mqd, 0, sizeof(*mqd));
7119                 mutex_lock(&adev->srbm_mutex);
7120                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7121                 gfx_v10_0_compute_mqd_init(ring);
7122                 nv_grbm_select(adev, 0, 0, 0, 0);
7123                 mutex_unlock(&adev->srbm_mutex);
7124
7125                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7126                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7127         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7128                 /* reset MQD to a clean status */
7129                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7130                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7131
7132                 /* reset ring buffer */
7133                 ring->wptr = 0;
7134                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
7135                 amdgpu_ring_clear_ring(ring);
7136         } else {
7137                 amdgpu_ring_clear_ring(ring);
7138         }
7139
7140         return 0;
7141 }
7142
7143 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7144 {
7145         struct amdgpu_ring *ring;
7146         int r;
7147
7148         ring = &adev->gfx.kiq.ring;
7149
7150         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7151         if (unlikely(r != 0))
7152                 return r;
7153
7154         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7155         if (unlikely(r != 0))
7156                 return r;
7157
7158         gfx_v10_0_kiq_init_queue(ring);
7159         amdgpu_bo_kunmap(ring->mqd_obj);
7160         ring->mqd_ptr = NULL;
7161         amdgpu_bo_unreserve(ring->mqd_obj);
7162         ring->sched.ready = true;
7163         return 0;
7164 }
7165
7166 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7167 {
7168         struct amdgpu_ring *ring = NULL;
7169         int r = 0, i;
7170
7171         gfx_v10_0_cp_compute_enable(adev, true);
7172
7173         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7174                 ring = &adev->gfx.compute_ring[i];
7175
7176                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7177                 if (unlikely(r != 0))
7178                         goto done;
7179                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7180                 if (!r) {
7181                         r = gfx_v10_0_kcq_init_queue(ring);
7182                         amdgpu_bo_kunmap(ring->mqd_obj);
7183                         ring->mqd_ptr = NULL;
7184                 }
7185                 amdgpu_bo_unreserve(ring->mqd_obj);
7186                 if (r)
7187                         goto done;
7188         }
7189
7190         r = amdgpu_gfx_enable_kcq(adev);
7191 done:
7192         return r;
7193 }
7194
7195 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7196 {
7197         int r, i;
7198         struct amdgpu_ring *ring;
7199
7200         if (!(adev->flags & AMD_IS_APU))
7201                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7202
7203         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7204                 /* legacy firmware loading */
7205                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7206                 if (r)
7207                         return r;
7208
7209                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7210                 if (r)
7211                         return r;
7212         }
7213
7214         r = gfx_v10_0_kiq_resume(adev);
7215         if (r)
7216                 return r;
7217
7218         r = gfx_v10_0_kcq_resume(adev);
7219         if (r)
7220                 return r;
7221
7222         if (!amdgpu_async_gfx_ring) {
7223                 r = gfx_v10_0_cp_gfx_resume(adev);
7224                 if (r)
7225                         return r;
7226         } else {
7227                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7228                 if (r)
7229                         return r;
7230         }
7231
7232         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7233                 ring = &adev->gfx.gfx_ring[i];
7234                 r = amdgpu_ring_test_helper(ring);
7235                 if (r)
7236                         return r;
7237         }
7238
7239         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7240                 ring = &adev->gfx.compute_ring[i];
7241                 r = amdgpu_ring_test_helper(ring);
7242                 if (r)
7243                         return r;
7244         }
7245
7246         return 0;
7247 }
7248
7249 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7250 {
7251         gfx_v10_0_cp_gfx_enable(adev, enable);
7252         gfx_v10_0_cp_compute_enable(adev, enable);
7253 }
7254
7255 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7256 {
7257         uint32_t data, pattern = 0xDEADBEEF;
7258
7259         /* check if mmVGT_ESGS_RING_SIZE_UMD
7260          * has been remapped to mmVGT_ESGS_RING_SIZE */
7261         switch (adev->ip_versions[GC_HWIP][0]) {
7262         case IP_VERSION(10, 3, 0):
7263         case IP_VERSION(10, 3, 2):
7264         case IP_VERSION(10, 3, 4):
7265         case IP_VERSION(10, 3, 5):
7266                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7267                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7268                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7269
7270                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7271                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7272                         return true;
7273                 } else {
7274                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7275                         return false;
7276                 }
7277                 break;
7278         case IP_VERSION(10, 3, 1):
7279         case IP_VERSION(10, 3, 3):
7280         case IP_VERSION(10, 3, 6):
7281         case IP_VERSION(10, 3, 7):
7282                 return true;
7283         default:
7284                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7285                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7286                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7287
7288                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7289                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7290                         return true;
7291                 } else {
7292                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7293                         return false;
7294                 }
7295                 break;
7296         }
7297 }
7298
7299 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7300 {
7301         uint32_t data;
7302
7303         if (amdgpu_sriov_vf(adev))
7304                 return;
7305
7306         /* initialize cam_index to 0
7307          * index will auto-inc after each data writting */
7308         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7309
7310         switch (adev->ip_versions[GC_HWIP][0]) {
7311         case IP_VERSION(10, 3, 0):
7312         case IP_VERSION(10, 3, 2):
7313         case IP_VERSION(10, 3, 1):
7314         case IP_VERSION(10, 3, 4):
7315         case IP_VERSION(10, 3, 5):
7316         case IP_VERSION(10, 3, 6):
7317         case IP_VERSION(10, 3, 3):
7318         case IP_VERSION(10, 3, 7):
7319                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7320                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7321                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7322                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7323                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7324                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7325                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7326
7327                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7328                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7329                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7330                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7331                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7332                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7333                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7334
7335                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7336                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7337                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7338                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7339                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7340                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7341                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7342
7343                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7344                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7345                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7346                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7347                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7348                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7349                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7350
7351                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7352                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7353                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7354                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7355                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7356                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7357                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7358
7359                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7360                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7361                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7362                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7363                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7364                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7365                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7366
7367                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7368                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7369                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7370                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7371                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7372                 break;
7373         default:
7374                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7375                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7376                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7377                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7378                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7379                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7380                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7381
7382                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7383                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7384                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7385                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7386                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7387                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7388                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7389
7390                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7391                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7392                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7393                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7394                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7395                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7396                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7397
7398                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7399                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7400                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7401                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7402                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7403                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7404                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7405
7406                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7407                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7408                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7409                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7410                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7411                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7412                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7413
7414                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7415                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7416                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7417                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7418                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7419                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7420                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7421
7422                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7423                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7424                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7425                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7426                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7427                 break;
7428         }
7429
7430         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7431         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7432 }
7433
7434 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7435 {
7436         uint32_t data;
7437         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7438         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7439         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7440
7441         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7442         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7443         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7444 }
7445
7446 static int gfx_v10_0_hw_init(void *handle)
7447 {
7448         int r;
7449         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7450
7451         if (!amdgpu_emu_mode)
7452                 gfx_v10_0_init_golden_registers(adev);
7453
7454         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7455                 /**
7456                  * For gfx 10, rlc firmware loading relies on smu firmware is
7457                  * loaded firstly, so in direct type, it has to load smc ucode
7458                  * here before rlc.
7459                  */
7460                 if (!(adev->flags & AMD_IS_APU)) {
7461                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7462                         if (r)
7463                                 return r;
7464                 }
7465                 gfx_v10_0_disable_gpa_mode(adev);
7466         }
7467
7468         /* if GRBM CAM not remapped, set up the remapping */
7469         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7470                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7471
7472         gfx_v10_0_constants_init(adev);
7473
7474         r = gfx_v10_0_rlc_resume(adev);
7475         if (r)
7476                 return r;
7477
7478         /*
7479          * init golden registers and rlc resume may override some registers,
7480          * reconfig them here
7481          */
7482         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
7483             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
7484             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
7485                 gfx_v10_0_tcp_harvest(adev);
7486
7487         r = gfx_v10_0_cp_resume(adev);
7488         if (r)
7489                 return r;
7490
7491         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
7492                 gfx_v10_3_program_pbb_mode(adev);
7493
7494         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
7495                 gfx_v10_3_set_power_brake_sequence(adev);
7496
7497         return r;
7498 }
7499
7500 #ifndef BRING_UP_DEBUG
7501 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7502 {
7503         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7504         struct amdgpu_ring *kiq_ring = &kiq->ring;
7505         int i;
7506
7507         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7508                 return -EINVAL;
7509
7510         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7511                                         adev->gfx.num_gfx_rings))
7512                 return -ENOMEM;
7513
7514         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7515                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7516                                            PREEMPT_QUEUES, 0, 0);
7517
7518         return amdgpu_ring_test_helper(kiq_ring);
7519 }
7520 #endif
7521
7522 static int gfx_v10_0_hw_fini(void *handle)
7523 {
7524         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7525         int r;
7526         uint32_t tmp;
7527
7528         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7529         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7530
7531         if (!adev->no_hw_access) {
7532 #ifndef BRING_UP_DEBUG
7533                 if (amdgpu_async_gfx_ring) {
7534                         r = gfx_v10_0_kiq_disable_kgq(adev);
7535                         if (r)
7536                                 DRM_ERROR("KGQ disable failed\n");
7537                 }
7538 #endif
7539                 if (amdgpu_gfx_disable_kcq(adev))
7540                         DRM_ERROR("KCQ disable failed\n");
7541         }
7542
7543         if (amdgpu_sriov_vf(adev)) {
7544                 gfx_v10_0_cp_gfx_enable(adev, false);
7545                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7546                 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
7547                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7548                         tmp &= 0xffffff00;
7549                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7550                 } else {
7551                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7552                         tmp &= 0xffffff00;
7553                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7554                 }
7555
7556                 return 0;
7557         }
7558         gfx_v10_0_cp_enable(adev, false);
7559         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7560
7561         return 0;
7562 }
7563
7564 static int gfx_v10_0_suspend(void *handle)
7565 {
7566         return gfx_v10_0_hw_fini(handle);
7567 }
7568
7569 static int gfx_v10_0_resume(void *handle)
7570 {
7571         return gfx_v10_0_hw_init(handle);
7572 }
7573
7574 static bool gfx_v10_0_is_idle(void *handle)
7575 {
7576         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7577
7578         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7579                                 GRBM_STATUS, GUI_ACTIVE))
7580                 return false;
7581         else
7582                 return true;
7583 }
7584
7585 static int gfx_v10_0_wait_for_idle(void *handle)
7586 {
7587         unsigned i;
7588         u32 tmp;
7589         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7590
7591         for (i = 0; i < adev->usec_timeout; i++) {
7592                 /* read MC_STATUS */
7593                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7594                         GRBM_STATUS__GUI_ACTIVE_MASK;
7595
7596                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7597                         return 0;
7598                 udelay(1);
7599         }
7600         return -ETIMEDOUT;
7601 }
7602
7603 static int gfx_v10_0_soft_reset(void *handle)
7604 {
7605         u32 grbm_soft_reset = 0;
7606         u32 tmp;
7607         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7608
7609         /* GRBM_STATUS */
7610         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7611         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7612                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7613                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7614                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7615                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7616                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7617                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7618                                                 1);
7619                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7620                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7621                                                 1);
7622         }
7623
7624         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7625                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7626                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7627                                                 1);
7628         }
7629
7630         /* GRBM_STATUS2 */
7631         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7632         switch (adev->ip_versions[GC_HWIP][0]) {
7633         case IP_VERSION(10, 3, 0):
7634         case IP_VERSION(10, 3, 2):
7635         case IP_VERSION(10, 3, 1):
7636         case IP_VERSION(10, 3, 4):
7637         case IP_VERSION(10, 3, 5):
7638         case IP_VERSION(10, 3, 6):
7639         case IP_VERSION(10, 3, 3):
7640                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7641                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7642                                                         GRBM_SOFT_RESET,
7643                                                         SOFT_RESET_RLC,
7644                                                         1);
7645                 break;
7646         default:
7647                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7648                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7649                                                         GRBM_SOFT_RESET,
7650                                                         SOFT_RESET_RLC,
7651                                                         1);
7652                 break;
7653         }
7654
7655         if (grbm_soft_reset) {
7656                 /* stop the rlc */
7657                 gfx_v10_0_rlc_stop(adev);
7658
7659                 /* Disable GFX parsing/prefetching */
7660                 gfx_v10_0_cp_gfx_enable(adev, false);
7661
7662                 /* Disable MEC parsing/prefetching */
7663                 gfx_v10_0_cp_compute_enable(adev, false);
7664
7665                 if (grbm_soft_reset) {
7666                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7667                         tmp |= grbm_soft_reset;
7668                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7669                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7670                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7671
7672                         udelay(50);
7673
7674                         tmp &= ~grbm_soft_reset;
7675                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7676                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7677                 }
7678
7679                 /* Wait a little for things to settle down */
7680                 udelay(50);
7681         }
7682         return 0;
7683 }
7684
7685 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7686 {
7687         uint64_t clock, clock_lo, clock_hi, hi_check;
7688
7689         switch (adev->ip_versions[GC_HWIP][0]) {
7690         case IP_VERSION(10, 3, 1):
7691         case IP_VERSION(10, 3, 3):
7692                 preempt_disable();
7693                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7694                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7695                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7696                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7697                  * roughly every 42 seconds.
7698                  */
7699                 if (hi_check != clock_hi) {
7700                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7701                         clock_hi = hi_check;
7702                 }
7703                 preempt_enable();
7704                 clock = clock_lo | (clock_hi << 32ULL);
7705                 break;
7706         case IP_VERSION(10, 3, 6):
7707                 preempt_disable();
7708                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7709                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7710                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7711                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7712                  * roughly every 42 seconds.
7713                  */
7714                 if (hi_check != clock_hi) {
7715                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7716                         clock_hi = hi_check;
7717                 }
7718                 preempt_enable();
7719                 clock = clock_lo | (clock_hi << 32ULL);
7720                 break;
7721         default:
7722                 preempt_disable();
7723                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7724                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7725                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7726                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7727                  * roughly every 42 seconds.
7728                  */
7729                 if (hi_check != clock_hi) {
7730                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7731                         clock_hi = hi_check;
7732                 }
7733                 preempt_enable();
7734                 clock = clock_lo | (clock_hi << 32ULL);
7735                 break;
7736         }
7737         return clock;
7738 }
7739
7740 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7741                                            uint32_t vmid,
7742                                            uint32_t gds_base, uint32_t gds_size,
7743                                            uint32_t gws_base, uint32_t gws_size,
7744                                            uint32_t oa_base, uint32_t oa_size)
7745 {
7746         struct amdgpu_device *adev = ring->adev;
7747
7748         /* GDS Base */
7749         gfx_v10_0_write_data_to_reg(ring, 0, false,
7750                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7751                                     gds_base);
7752
7753         /* GDS Size */
7754         gfx_v10_0_write_data_to_reg(ring, 0, false,
7755                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7756                                     gds_size);
7757
7758         /* GWS */
7759         gfx_v10_0_write_data_to_reg(ring, 0, false,
7760                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7761                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7762
7763         /* OA */
7764         gfx_v10_0_write_data_to_reg(ring, 0, false,
7765                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7766                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7767 }
7768
7769 static int gfx_v10_0_early_init(void *handle)
7770 {
7771         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7772
7773         switch (adev->ip_versions[GC_HWIP][0]) {
7774         case IP_VERSION(10, 1, 10):
7775         case IP_VERSION(10, 1, 1):
7776         case IP_VERSION(10, 1, 2):
7777         case IP_VERSION(10, 1, 3):
7778         case IP_VERSION(10, 1, 4):
7779                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7780                 break;
7781         case IP_VERSION(10, 3, 0):
7782         case IP_VERSION(10, 3, 2):
7783         case IP_VERSION(10, 3, 1):
7784         case IP_VERSION(10, 3, 4):
7785         case IP_VERSION(10, 3, 5):
7786         case IP_VERSION(10, 3, 6):
7787         case IP_VERSION(10, 3, 3):
7788         case IP_VERSION(10, 3, 7):
7789                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7790                 break;
7791         default:
7792                 break;
7793         }
7794
7795         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7796                                           AMDGPU_MAX_COMPUTE_RINGS);
7797
7798         gfx_v10_0_set_kiq_pm4_funcs(adev);
7799         gfx_v10_0_set_ring_funcs(adev);
7800         gfx_v10_0_set_irq_funcs(adev);
7801         gfx_v10_0_set_gds_init(adev);
7802         gfx_v10_0_set_rlc_funcs(adev);
7803
7804         /* init rlcg reg access ctrl */
7805         gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7806
7807         return 0;
7808 }
7809
7810 static int gfx_v10_0_late_init(void *handle)
7811 {
7812         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7813         int r;
7814
7815         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7816         if (r)
7817                 return r;
7818
7819         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7820         if (r)
7821                 return r;
7822
7823         return 0;
7824 }
7825
7826 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7827 {
7828         uint32_t rlc_cntl;
7829
7830         /* if RLC is not enabled, do nothing */
7831         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7832         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7833 }
7834
7835 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7836 {
7837         uint32_t data;
7838         unsigned i;
7839
7840         data = RLC_SAFE_MODE__CMD_MASK;
7841         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7842
7843         switch (adev->ip_versions[GC_HWIP][0]) {
7844         case IP_VERSION(10, 3, 0):
7845         case IP_VERSION(10, 3, 2):
7846         case IP_VERSION(10, 3, 1):
7847         case IP_VERSION(10, 3, 4):
7848         case IP_VERSION(10, 3, 5):
7849         case IP_VERSION(10, 3, 6):
7850         case IP_VERSION(10, 3, 3):
7851         case IP_VERSION(10, 3, 7):
7852                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7853
7854                 /* wait for RLC_SAFE_MODE */
7855                 for (i = 0; i < adev->usec_timeout; i++) {
7856                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7857                                            RLC_SAFE_MODE, CMD))
7858                                 break;
7859                         udelay(1);
7860                 }
7861                 break;
7862         default:
7863                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7864
7865                 /* wait for RLC_SAFE_MODE */
7866                 for (i = 0; i < adev->usec_timeout; i++) {
7867                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7868                                            RLC_SAFE_MODE, CMD))
7869                                 break;
7870                         udelay(1);
7871                 }
7872                 break;
7873         }
7874 }
7875
7876 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7877 {
7878         uint32_t data;
7879
7880         data = RLC_SAFE_MODE__CMD_MASK;
7881         switch (adev->ip_versions[GC_HWIP][0]) {
7882         case IP_VERSION(10, 3, 0):
7883         case IP_VERSION(10, 3, 2):
7884         case IP_VERSION(10, 3, 1):
7885         case IP_VERSION(10, 3, 4):
7886         case IP_VERSION(10, 3, 5):
7887         case IP_VERSION(10, 3, 6):
7888         case IP_VERSION(10, 3, 3):
7889         case IP_VERSION(10, 3, 7):
7890                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7891                 break;
7892         default:
7893                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7894                 break;
7895         }
7896 }
7897
7898 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7899                                                       bool enable)
7900 {
7901         uint32_t data, def;
7902
7903         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7904                 return;
7905
7906         /* It is disabled by HW by default */
7907         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7908                 /* 0 - Disable some blocks' MGCG */
7909                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7910                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7911                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7912                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7913
7914                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7915                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7916                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7917                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7918                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7919                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7920                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7921                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7922
7923                 if (def != data)
7924                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7925
7926                 /* MGLS is a global flag to control all MGLS in GFX */
7927                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7928                         /* 2 - RLC memory Light sleep */
7929                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7930                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7931                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7932                                 if (def != data)
7933                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7934                         }
7935                         /* 3 - CP memory Light sleep */
7936                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7937                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7938                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7939                                 if (def != data)
7940                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7941                         }
7942                 }
7943         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7944                 /* 1 - MGCG_OVERRIDE */
7945                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7946                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7947                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7948                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7949                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7950                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7951                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7952                 if (def != data)
7953                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7954
7955                 /* 2 - disable MGLS in CP */
7956                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7957                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7958                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7959                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7960                 }
7961
7962                 /* 3 - disable MGLS in RLC */
7963                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7964                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7965                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7966                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7967                 }
7968
7969         }
7970 }
7971
7972 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7973                                            bool enable)
7974 {
7975         uint32_t data, def;
7976
7977         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7978                 return;
7979
7980         /* Enable 3D CGCG/CGLS */
7981         if (enable) {
7982                 /* write cmd to clear cgcg/cgls ov */
7983                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7984
7985                 /* unset CGCG override */
7986                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7987                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7988
7989                 /* update CGCG and CGLS override bits */
7990                 if (def != data)
7991                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7992
7993                 /* enable 3Dcgcg FSM(0x0000363f) */
7994                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7995                 data = 0;
7996
7997                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7998                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7999                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8000
8001                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8002                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8003                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8004
8005                 if (def != data)
8006                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8007
8008                 /* set IDLE_POLL_COUNT(0x00900100) */
8009                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8010                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8011                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8012                 if (def != data)
8013                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8014         } else {
8015                 /* Disable CGCG/CGLS */
8016                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8017
8018                 /* disable cgcg, cgls should be disabled */
8019                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8020                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8021
8022                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8023                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8024
8025                 /* disable cgcg and cgls in FSM */
8026                 if (def != data)
8027                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8028         }
8029 }
8030
8031 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8032                                                       bool enable)
8033 {
8034         uint32_t def, data;
8035
8036         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8037                 return;
8038
8039         if (enable) {
8040                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8041
8042                 /* unset CGCG override */
8043                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8044                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8045
8046                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8047                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8048
8049                 /* update CGCG and CGLS override bits */
8050                 if (def != data)
8051                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8052
8053                 /* enable cgcg FSM(0x0000363F) */
8054                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8055                 data = 0;
8056
8057                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8058                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8059                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8060
8061                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8062                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8063                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8064
8065                 if (def != data)
8066                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8067
8068                 /* set IDLE_POLL_COUNT(0x00900100) */
8069                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8070                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8071                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8072                 if (def != data)
8073                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8074         } else {
8075                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8076
8077                 /* reset CGCG/CGLS bits */
8078                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8079                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8080
8081                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8082                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8083
8084                 /* disable cgcg and cgls in FSM */
8085                 if (def != data)
8086                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8087         }
8088 }
8089
8090 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8091                                                       bool enable)
8092 {
8093         uint32_t def, data;
8094
8095         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8096                 return;
8097
8098         if (enable) {
8099                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8100                 /* unset FGCG override */
8101                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8102                 /* update FGCG override bits */
8103                 if (def != data)
8104                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8105
8106                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8107                 /* unset RLC SRAM CLK GATER override */
8108                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8109                 /* update RLC SRAM CLK GATER override bits */
8110                 if (def != data)
8111                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8112         } else {
8113                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8114                 /* reset FGCG bits */
8115                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8116                 /* disable FGCG*/
8117                 if (def != data)
8118                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8119
8120                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8121                 /* reset RLC SRAM CLK GATER bits */
8122                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8123                 /* disable RLC SRAM CLK*/
8124                 if (def != data)
8125                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8126         }
8127 }
8128
8129 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8130 {
8131         uint32_t reg_data = 0;
8132         uint32_t reg_idx = 0;
8133         uint32_t i;
8134
8135         const uint32_t tcp_ctrl_regs[] = {
8136                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8137                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8138                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8139                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8140                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8141                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8142                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8143                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8144                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8145                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8146                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8147                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8148                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8149                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8150                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8151                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8152                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8153                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8154                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8155                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8156                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8157                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8158                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8159                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8160         };
8161
8162         const uint32_t tcp_ctrl_regs_nv12[] = {
8163                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8164                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8165                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8166                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8167                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8168                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8169                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8170                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8171                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8172                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8173                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8174                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8175                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8176                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8177                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8178                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8179                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8180                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8181                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8182                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8183         };
8184
8185         const uint32_t sm_ctlr_regs[] = {
8186                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8187                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8188                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8189                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8190         };
8191
8192         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
8193                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8194                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8195                                   tcp_ctrl_regs_nv12[i];
8196                         reg_data = RREG32(reg_idx);
8197                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8198                         WREG32(reg_idx, reg_data);
8199                 }
8200         } else {
8201                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8202                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8203                                   tcp_ctrl_regs[i];
8204                         reg_data = RREG32(reg_idx);
8205                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8206                         WREG32(reg_idx, reg_data);
8207                 }
8208         }
8209
8210         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8211                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8212                           sm_ctlr_regs[i];
8213                 reg_data = RREG32(reg_idx);
8214                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8215                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8216                 WREG32(reg_idx, reg_data);
8217         }
8218 }
8219
8220 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8221                                             bool enable)
8222 {
8223         amdgpu_gfx_rlc_enter_safe_mode(adev);
8224
8225         if (enable) {
8226                 /* enable FGCG firstly*/
8227                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8228                 /* CGCG/CGLS should be enabled after MGCG/MGLS
8229                  * ===  MGCG + MGLS ===
8230                  */
8231                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8232                 /* ===  CGCG /CGLS for GFX 3D Only === */
8233                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8234                 /* ===  CGCG + CGLS === */
8235                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8236
8237                 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) ||
8238                     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) ||
8239                     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)))
8240                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8241         } else {
8242                 /* CGCG/CGLS should be disabled before MGCG/MGLS
8243                  * ===  CGCG + CGLS ===
8244                  */
8245                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8246                 /* ===  CGCG /CGLS for GFX 3D Only === */
8247                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8248                 /* ===  MGCG + MGLS === */
8249                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8250                 /* disable fgcg at last*/
8251                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8252         }
8253
8254         if (adev->cg_flags &
8255             (AMD_CG_SUPPORT_GFX_MGCG |
8256              AMD_CG_SUPPORT_GFX_CGLS |
8257              AMD_CG_SUPPORT_GFX_CGCG |
8258              AMD_CG_SUPPORT_GFX_3D_CGCG |
8259              AMD_CG_SUPPORT_GFX_3D_CGLS))
8260                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8261
8262         amdgpu_gfx_rlc_exit_safe_mode(adev);
8263
8264         return 0;
8265 }
8266
8267 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8268 {
8269         u32 reg, data;
8270
8271         amdgpu_gfx_off_ctrl(adev, false);
8272
8273         /* not for *_SOC15 */
8274         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8275         if (amdgpu_sriov_is_pp_one_vf(adev))
8276                 data = RREG32_NO_KIQ(reg);
8277         else
8278                 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8279
8280         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8281         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8282
8283         if (amdgpu_sriov_is_pp_one_vf(adev))
8284                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8285         else
8286                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8287
8288         amdgpu_gfx_off_ctrl(adev, true);
8289 }
8290
8291 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8292                                         uint32_t offset,
8293                                         struct soc15_reg_rlcg *entries, int arr_size)
8294 {
8295         int i;
8296         uint32_t reg;
8297
8298         if (!entries)
8299                 return false;
8300
8301         for (i = 0; i < arr_size; i++) {
8302                 const struct soc15_reg_rlcg *entry;
8303
8304                 entry = &entries[i];
8305                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8306                 if (offset == reg)
8307                         return true;
8308         }
8309
8310         return false;
8311 }
8312
8313 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8314 {
8315         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8316 }
8317
8318 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8319 {
8320         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8321
8322         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8323                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8324         else
8325                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8326
8327         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8328
8329         /*
8330          * CGPG enablement required and the register to program the hysteresis value
8331          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8332          * in refclk count. Note that RLC FW is modified to take 16 bits from
8333          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8334          *
8335          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8336          * of CGPG enablement starting point.
8337          * Power/performance team will optimize it and might give a new value later.
8338          */
8339         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8340                 switch (adev->ip_versions[GC_HWIP][0]) {
8341                 case IP_VERSION(10, 3, 1):
8342                 case IP_VERSION(10, 3, 3):
8343                 case IP_VERSION(10, 3, 6):
8344                 case IP_VERSION(10, 3, 7):
8345                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8346                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8347                         break;
8348                 default:
8349                         break;
8350                 }
8351         }
8352 }
8353
8354 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8355 {
8356         amdgpu_gfx_rlc_enter_safe_mode(adev);
8357
8358         gfx_v10_cntl_power_gating(adev, enable);
8359
8360         amdgpu_gfx_rlc_exit_safe_mode(adev);
8361 }
8362
8363 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8364         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8365         .set_safe_mode = gfx_v10_0_set_safe_mode,
8366         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8367         .init = gfx_v10_0_rlc_init,
8368         .get_csb_size = gfx_v10_0_get_csb_size,
8369         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8370         .resume = gfx_v10_0_rlc_resume,
8371         .stop = gfx_v10_0_rlc_stop,
8372         .reset = gfx_v10_0_rlc_reset,
8373         .start = gfx_v10_0_rlc_start,
8374         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8375 };
8376
8377 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8378         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8379         .set_safe_mode = gfx_v10_0_set_safe_mode,
8380         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8381         .init = gfx_v10_0_rlc_init,
8382         .get_csb_size = gfx_v10_0_get_csb_size,
8383         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8384         .resume = gfx_v10_0_rlc_resume,
8385         .stop = gfx_v10_0_rlc_stop,
8386         .reset = gfx_v10_0_rlc_reset,
8387         .start = gfx_v10_0_rlc_start,
8388         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8389         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8390 };
8391
8392 static int gfx_v10_0_set_powergating_state(void *handle,
8393                                           enum amd_powergating_state state)
8394 {
8395         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8396         bool enable = (state == AMD_PG_STATE_GATE);
8397
8398         if (amdgpu_sriov_vf(adev))
8399                 return 0;
8400
8401         switch (adev->ip_versions[GC_HWIP][0]) {
8402         case IP_VERSION(10, 1, 10):
8403         case IP_VERSION(10, 1, 1):
8404         case IP_VERSION(10, 1, 2):
8405         case IP_VERSION(10, 3, 0):
8406         case IP_VERSION(10, 3, 2):
8407         case IP_VERSION(10, 3, 4):
8408         case IP_VERSION(10, 3, 5):
8409                 amdgpu_gfx_off_ctrl(adev, enable);
8410                 break;
8411         case IP_VERSION(10, 3, 1):
8412         case IP_VERSION(10, 3, 3):
8413         case IP_VERSION(10, 3, 6):
8414         case IP_VERSION(10, 3, 7):
8415                 gfx_v10_cntl_pg(adev, enable);
8416                 amdgpu_gfx_off_ctrl(adev, enable);
8417                 break;
8418         default:
8419                 break;
8420         }
8421         return 0;
8422 }
8423
8424 static int gfx_v10_0_set_clockgating_state(void *handle,
8425                                           enum amd_clockgating_state state)
8426 {
8427         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8428
8429         if (amdgpu_sriov_vf(adev))
8430                 return 0;
8431
8432         switch (adev->ip_versions[GC_HWIP][0]) {
8433         case IP_VERSION(10, 1, 10):
8434         case IP_VERSION(10, 1, 1):
8435         case IP_VERSION(10, 1, 2):
8436         case IP_VERSION(10, 3, 0):
8437         case IP_VERSION(10, 3, 2):
8438         case IP_VERSION(10, 3, 1):
8439         case IP_VERSION(10, 3, 4):
8440         case IP_VERSION(10, 3, 5):
8441         case IP_VERSION(10, 3, 6):
8442         case IP_VERSION(10, 3, 3):
8443         case IP_VERSION(10, 3, 7):
8444                 gfx_v10_0_update_gfx_clock_gating(adev,
8445                                                  state == AMD_CG_STATE_GATE);
8446                 break;
8447         default:
8448                 break;
8449         }
8450         return 0;
8451 }
8452
8453 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8454 {
8455         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8456         int data;
8457
8458         /* AMD_CG_SUPPORT_GFX_FGCG */
8459         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8460         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8461                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8462
8463         /* AMD_CG_SUPPORT_GFX_MGCG */
8464         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8465         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8466                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8467
8468         /* AMD_CG_SUPPORT_GFX_CGCG */
8469         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8470         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8471                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8472
8473         /* AMD_CG_SUPPORT_GFX_CGLS */
8474         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8475                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8476
8477         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8478         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8479         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8480                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8481
8482         /* AMD_CG_SUPPORT_GFX_CP_LS */
8483         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8484         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8485                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8486
8487         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8488         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8489         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8490                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8491
8492         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8493         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8494                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8495 }
8496
8497 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8498 {
8499         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8500 }
8501
8502 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8503 {
8504         struct amdgpu_device *adev = ring->adev;
8505         u64 wptr;
8506
8507         /* XXX check if swapping is necessary on BE */
8508         if (ring->use_doorbell) {
8509                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8510         } else {
8511                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8512                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8513         }
8514
8515         return wptr;
8516 }
8517
8518 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8519 {
8520         struct amdgpu_device *adev = ring->adev;
8521
8522         if (ring->use_doorbell) {
8523                 /* XXX check if swapping is necessary on BE */
8524                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8525                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8526         } else {
8527                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8528                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8529         }
8530 }
8531
8532 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8533 {
8534         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8535 }
8536
8537 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8538 {
8539         u64 wptr;
8540
8541         /* XXX check if swapping is necessary on BE */
8542         if (ring->use_doorbell)
8543                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8544         else
8545                 BUG();
8546         return wptr;
8547 }
8548
8549 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8550 {
8551         struct amdgpu_device *adev = ring->adev;
8552
8553         /* XXX check if swapping is necessary on BE */
8554         if (ring->use_doorbell) {
8555                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8556                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8557         } else {
8558                 BUG(); /* only DOORBELL method supported on gfx10 now */
8559         }
8560 }
8561
8562 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8563 {
8564         struct amdgpu_device *adev = ring->adev;
8565         u32 ref_and_mask, reg_mem_engine;
8566         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8567
8568         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8569                 switch (ring->me) {
8570                 case 1:
8571                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8572                         break;
8573                 case 2:
8574                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8575                         break;
8576                 default:
8577                         return;
8578                 }
8579                 reg_mem_engine = 0;
8580         } else {
8581                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8582                 reg_mem_engine = 1; /* pfp */
8583         }
8584
8585         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8586                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8587                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8588                                ref_and_mask, ref_and_mask, 0x20);
8589 }
8590
8591 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8592                                        struct amdgpu_job *job,
8593                                        struct amdgpu_ib *ib,
8594                                        uint32_t flags)
8595 {
8596         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8597         u32 header, control = 0;
8598
8599         if (ib->flags & AMDGPU_IB_FLAG_CE)
8600                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8601         else
8602                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8603
8604         control |= ib->length_dw | (vmid << 24);
8605
8606         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8607                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8608
8609                 if (flags & AMDGPU_IB_PREEMPTED)
8610                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8611
8612                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8613                         gfx_v10_0_ring_emit_de_meta(ring,
8614                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8615         }
8616
8617         amdgpu_ring_write(ring, header);
8618         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8619         amdgpu_ring_write(ring,
8620 #ifdef __BIG_ENDIAN
8621                 (2 << 0) |
8622 #endif
8623                 lower_32_bits(ib->gpu_addr));
8624         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8625         amdgpu_ring_write(ring, control);
8626 }
8627
8628 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8629                                            struct amdgpu_job *job,
8630                                            struct amdgpu_ib *ib,
8631                                            uint32_t flags)
8632 {
8633         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8634         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8635
8636         /* Currently, there is a high possibility to get wave ID mismatch
8637          * between ME and GDS, leading to a hw deadlock, because ME generates
8638          * different wave IDs than the GDS expects. This situation happens
8639          * randomly when at least 5 compute pipes use GDS ordered append.
8640          * The wave IDs generated by ME are also wrong after suspend/resume.
8641          * Those are probably bugs somewhere else in the kernel driver.
8642          *
8643          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8644          * GDS to 0 for this ring (me/pipe).
8645          */
8646         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8647                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8648                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8649                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8650         }
8651
8652         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8653         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8654         amdgpu_ring_write(ring,
8655 #ifdef __BIG_ENDIAN
8656                                 (2 << 0) |
8657 #endif
8658                                 lower_32_bits(ib->gpu_addr));
8659         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8660         amdgpu_ring_write(ring, control);
8661 }
8662
8663 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8664                                      u64 seq, unsigned flags)
8665 {
8666         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8667         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8668
8669         /* RELEASE_MEM - flush caches, send int */
8670         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8671         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8672                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8673                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8674                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8675                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8676                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8677                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8678         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8679                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8680
8681         /*
8682          * the address should be Qword aligned if 64bit write, Dword
8683          * aligned if only send 32bit data low (discard data high)
8684          */
8685         if (write64bit)
8686                 BUG_ON(addr & 0x7);
8687         else
8688                 BUG_ON(addr & 0x3);
8689         amdgpu_ring_write(ring, lower_32_bits(addr));
8690         amdgpu_ring_write(ring, upper_32_bits(addr));
8691         amdgpu_ring_write(ring, lower_32_bits(seq));
8692         amdgpu_ring_write(ring, upper_32_bits(seq));
8693         amdgpu_ring_write(ring, 0);
8694 }
8695
8696 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8697 {
8698         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8699         uint32_t seq = ring->fence_drv.sync_seq;
8700         uint64_t addr = ring->fence_drv.gpu_addr;
8701
8702         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8703                                upper_32_bits(addr), seq, 0xffffffff, 4);
8704 }
8705
8706 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8707                                          unsigned vmid, uint64_t pd_addr)
8708 {
8709         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8710
8711         /* compute doesn't have PFP */
8712         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8713                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8714                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8715                 amdgpu_ring_write(ring, 0x0);
8716         }
8717 }
8718
8719 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8720                                           u64 seq, unsigned int flags)
8721 {
8722         struct amdgpu_device *adev = ring->adev;
8723
8724         /* we only allocate 32bit for each seq wb address */
8725         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8726
8727         /* write fence seq to the "addr" */
8728         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8729         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8730                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8731         amdgpu_ring_write(ring, lower_32_bits(addr));
8732         amdgpu_ring_write(ring, upper_32_bits(addr));
8733         amdgpu_ring_write(ring, lower_32_bits(seq));
8734
8735         if (flags & AMDGPU_FENCE_FLAG_INT) {
8736                 /* set register to trigger INT */
8737                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8738                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8739                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8740                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8741                 amdgpu_ring_write(ring, 0);
8742                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8743         }
8744 }
8745
8746 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8747 {
8748         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8749         amdgpu_ring_write(ring, 0);
8750 }
8751
8752 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8753                                          uint32_t flags)
8754 {
8755         uint32_t dw2 = 0;
8756
8757         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8758                 gfx_v10_0_ring_emit_ce_meta(ring,
8759                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8760
8761         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8762         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8763                 /* set load_global_config & load_global_uconfig */
8764                 dw2 |= 0x8001;
8765                 /* set load_cs_sh_regs */
8766                 dw2 |= 0x01000000;
8767                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8768                 dw2 |= 0x10002;
8769
8770                 /* set load_ce_ram if preamble presented */
8771                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8772                         dw2 |= 0x10000000;
8773         } else {
8774                 /* still load_ce_ram if this is the first time preamble presented
8775                  * although there is no context switch happens.
8776                  */
8777                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8778                         dw2 |= 0x10000000;
8779         }
8780
8781         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8782         amdgpu_ring_write(ring, dw2);
8783         amdgpu_ring_write(ring, 0);
8784 }
8785
8786 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8787 {
8788         unsigned ret;
8789
8790         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8791         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8792         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8793         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8794         ret = ring->wptr & ring->buf_mask;
8795         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8796
8797         return ret;
8798 }
8799
8800 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8801 {
8802         unsigned cur;
8803         BUG_ON(offset > ring->buf_mask);
8804         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8805
8806         cur = (ring->wptr - 1) & ring->buf_mask;
8807         if (likely(cur > offset))
8808                 ring->ring[offset] = cur - offset;
8809         else
8810                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8811 }
8812
8813 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8814 {
8815         int i, r = 0;
8816         struct amdgpu_device *adev = ring->adev;
8817         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8818         struct amdgpu_ring *kiq_ring = &kiq->ring;
8819         unsigned long flags;
8820
8821         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8822                 return -EINVAL;
8823
8824         spin_lock_irqsave(&kiq->ring_lock, flags);
8825
8826         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8827                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8828                 return -ENOMEM;
8829         }
8830
8831         /* assert preemption condition */
8832         amdgpu_ring_set_preempt_cond_exec(ring, false);
8833
8834         /* assert IB preemption, emit the trailing fence */
8835         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8836                                    ring->trail_fence_gpu_addr,
8837                                    ++ring->trail_seq);
8838         amdgpu_ring_commit(kiq_ring);
8839
8840         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8841
8842         /* poll the trailing fence */
8843         for (i = 0; i < adev->usec_timeout; i++) {
8844                 if (ring->trail_seq ==
8845                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8846                         break;
8847                 udelay(1);
8848         }
8849
8850         if (i >= adev->usec_timeout) {
8851                 r = -EINVAL;
8852                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8853         }
8854
8855         /* deassert preemption condition */
8856         amdgpu_ring_set_preempt_cond_exec(ring, true);
8857         return r;
8858 }
8859
8860 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8861 {
8862         struct amdgpu_device *adev = ring->adev;
8863         struct v10_ce_ib_state ce_payload = {0};
8864         uint64_t csa_addr;
8865         int cnt;
8866
8867         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8868         csa_addr = amdgpu_csa_vaddr(ring->adev);
8869
8870         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8871         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8872                                  WRITE_DATA_DST_SEL(8) |
8873                                  WR_CONFIRM) |
8874                                  WRITE_DATA_CACHE_POLICY(0));
8875         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8876                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8877         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8878                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8879
8880         if (resume)
8881                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8882                                            offsetof(struct v10_gfx_meta_data,
8883                                                     ce_payload),
8884                                            sizeof(ce_payload) >> 2);
8885         else
8886                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8887                                            sizeof(ce_payload) >> 2);
8888 }
8889
8890 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8891 {
8892         struct amdgpu_device *adev = ring->adev;
8893         struct v10_de_ib_state de_payload = {0};
8894         uint64_t csa_addr, gds_addr;
8895         int cnt;
8896
8897         csa_addr = amdgpu_csa_vaddr(ring->adev);
8898         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8899                          PAGE_SIZE);
8900         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8901         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8902
8903         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8904         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8905         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8906                                  WRITE_DATA_DST_SEL(8) |
8907                                  WR_CONFIRM) |
8908                                  WRITE_DATA_CACHE_POLICY(0));
8909         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8910                               offsetof(struct v10_gfx_meta_data, de_payload)));
8911         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8912                               offsetof(struct v10_gfx_meta_data, de_payload)));
8913
8914         if (resume)
8915                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8916                                            offsetof(struct v10_gfx_meta_data,
8917                                                     de_payload),
8918                                            sizeof(de_payload) >> 2);
8919         else
8920                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8921                                            sizeof(de_payload) >> 2);
8922 }
8923
8924 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8925                                     bool secure)
8926 {
8927         uint32_t v = secure ? FRAME_TMZ : 0;
8928
8929         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8930         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8931 }
8932
8933 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8934                                      uint32_t reg_val_offs)
8935 {
8936         struct amdgpu_device *adev = ring->adev;
8937
8938         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8939         amdgpu_ring_write(ring, 0 |     /* src: register*/
8940                                 (5 << 8) |      /* dst: memory */
8941                                 (1 << 20));     /* write confirm */
8942         amdgpu_ring_write(ring, reg);
8943         amdgpu_ring_write(ring, 0);
8944         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8945                                 reg_val_offs * 4));
8946         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8947                                 reg_val_offs * 4));
8948 }
8949
8950 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8951                                    uint32_t val)
8952 {
8953         uint32_t cmd = 0;
8954
8955         switch (ring->funcs->type) {
8956         case AMDGPU_RING_TYPE_GFX:
8957                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8958                 break;
8959         case AMDGPU_RING_TYPE_KIQ:
8960                 cmd = (1 << 16); /* no inc addr */
8961                 break;
8962         default:
8963                 cmd = WR_CONFIRM;
8964                 break;
8965         }
8966         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8967         amdgpu_ring_write(ring, cmd);
8968         amdgpu_ring_write(ring, reg);
8969         amdgpu_ring_write(ring, 0);
8970         amdgpu_ring_write(ring, val);
8971 }
8972
8973 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8974                                         uint32_t val, uint32_t mask)
8975 {
8976         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8977 }
8978
8979 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8980                                                    uint32_t reg0, uint32_t reg1,
8981                                                    uint32_t ref, uint32_t mask)
8982 {
8983         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8984         struct amdgpu_device *adev = ring->adev;
8985         bool fw_version_ok = false;
8986
8987         fw_version_ok = adev->gfx.cp_fw_write_wait;
8988
8989         if (fw_version_ok)
8990                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8991                                        ref, mask, 0x20);
8992         else
8993                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8994                                                            ref, mask);
8995 }
8996
8997 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8998                                          unsigned vmid)
8999 {
9000         struct amdgpu_device *adev = ring->adev;
9001         uint32_t value = 0;
9002
9003         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9004         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9005         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9006         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9007         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9008 }
9009
9010 static void
9011 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9012                                       uint32_t me, uint32_t pipe,
9013                                       enum amdgpu_interrupt_state state)
9014 {
9015         uint32_t cp_int_cntl, cp_int_cntl_reg;
9016
9017         if (!me) {
9018                 switch (pipe) {
9019                 case 0:
9020                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9021                         break;
9022                 case 1:
9023                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9024                         break;
9025                 default:
9026                         DRM_DEBUG("invalid pipe %d\n", pipe);
9027                         return;
9028                 }
9029         } else {
9030                 DRM_DEBUG("invalid me %d\n", me);
9031                 return;
9032         }
9033
9034         switch (state) {
9035         case AMDGPU_IRQ_STATE_DISABLE:
9036                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9037                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9038                                             TIME_STAMP_INT_ENABLE, 0);
9039                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9040                 break;
9041         case AMDGPU_IRQ_STATE_ENABLE:
9042                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9043                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9044                                             TIME_STAMP_INT_ENABLE, 1);
9045                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9046                 break;
9047         default:
9048                 break;
9049         }
9050 }
9051
9052 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9053                                                      int me, int pipe,
9054                                                      enum amdgpu_interrupt_state state)
9055 {
9056         u32 mec_int_cntl, mec_int_cntl_reg;
9057
9058         /*
9059          * amdgpu controls only the first MEC. That's why this function only
9060          * handles the setting of interrupts for this specific MEC. All other
9061          * pipes' interrupts are set by amdkfd.
9062          */
9063
9064         if (me == 1) {
9065                 switch (pipe) {
9066                 case 0:
9067                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9068                         break;
9069                 case 1:
9070                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9071                         break;
9072                 case 2:
9073                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9074                         break;
9075                 case 3:
9076                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9077                         break;
9078                 default:
9079                         DRM_DEBUG("invalid pipe %d\n", pipe);
9080                         return;
9081                 }
9082         } else {
9083                 DRM_DEBUG("invalid me %d\n", me);
9084                 return;
9085         }
9086
9087         switch (state) {
9088         case AMDGPU_IRQ_STATE_DISABLE:
9089                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9090                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9091                                              TIME_STAMP_INT_ENABLE, 0);
9092                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9093                 break;
9094         case AMDGPU_IRQ_STATE_ENABLE:
9095                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9096                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9097                                              TIME_STAMP_INT_ENABLE, 1);
9098                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9099                 break;
9100         default:
9101                 break;
9102         }
9103 }
9104
9105 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9106                                             struct amdgpu_irq_src *src,
9107                                             unsigned type,
9108                                             enum amdgpu_interrupt_state state)
9109 {
9110         switch (type) {
9111         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9112                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9113                 break;
9114         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9115                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9116                 break;
9117         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9118                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9119                 break;
9120         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9121                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9122                 break;
9123         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9124                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9125                 break;
9126         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9127                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9128                 break;
9129         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9130                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9131                 break;
9132         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9133                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9134                 break;
9135         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9136                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9137                 break;
9138         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9139                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9140                 break;
9141         default:
9142                 break;
9143         }
9144         return 0;
9145 }
9146
9147 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9148                              struct amdgpu_irq_src *source,
9149                              struct amdgpu_iv_entry *entry)
9150 {
9151         int i;
9152         u8 me_id, pipe_id, queue_id;
9153         struct amdgpu_ring *ring;
9154
9155         DRM_DEBUG("IH: CP EOP\n");
9156         me_id = (entry->ring_id & 0x0c) >> 2;
9157         pipe_id = (entry->ring_id & 0x03) >> 0;
9158         queue_id = (entry->ring_id & 0x70) >> 4;
9159
9160         switch (me_id) {
9161         case 0:
9162                 if (pipe_id == 0)
9163                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9164                 else
9165                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9166                 break;
9167         case 1:
9168         case 2:
9169                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9170                         ring = &adev->gfx.compute_ring[i];
9171                         /* Per-queue interrupt is supported for MEC starting from VI.
9172                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
9173                           */
9174                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
9175                                 amdgpu_fence_process(ring);
9176                 }
9177                 break;
9178         }
9179         return 0;
9180 }
9181
9182 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9183                                               struct amdgpu_irq_src *source,
9184                                               unsigned type,
9185                                               enum amdgpu_interrupt_state state)
9186 {
9187         switch (state) {
9188         case AMDGPU_IRQ_STATE_DISABLE:
9189         case AMDGPU_IRQ_STATE_ENABLE:
9190                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9191                                PRIV_REG_INT_ENABLE,
9192                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9193                 break;
9194         default:
9195                 break;
9196         }
9197
9198         return 0;
9199 }
9200
9201 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9202                                                struct amdgpu_irq_src *source,
9203                                                unsigned type,
9204                                                enum amdgpu_interrupt_state state)
9205 {
9206         switch (state) {
9207         case AMDGPU_IRQ_STATE_DISABLE:
9208         case AMDGPU_IRQ_STATE_ENABLE:
9209                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9210                                PRIV_INSTR_INT_ENABLE,
9211                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9212                 break;
9213         default:
9214                 break;
9215         }
9216
9217         return 0;
9218 }
9219
9220 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9221                                         struct amdgpu_iv_entry *entry)
9222 {
9223         u8 me_id, pipe_id, queue_id;
9224         struct amdgpu_ring *ring;
9225         int i;
9226
9227         me_id = (entry->ring_id & 0x0c) >> 2;
9228         pipe_id = (entry->ring_id & 0x03) >> 0;
9229         queue_id = (entry->ring_id & 0x70) >> 4;
9230
9231         switch (me_id) {
9232         case 0:
9233                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9234                         ring = &adev->gfx.gfx_ring[i];
9235                         /* we only enabled 1 gfx queue per pipe for now */
9236                         if (ring->me == me_id && ring->pipe == pipe_id)
9237                                 drm_sched_fault(&ring->sched);
9238                 }
9239                 break;
9240         case 1:
9241         case 2:
9242                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9243                         ring = &adev->gfx.compute_ring[i];
9244                         if (ring->me == me_id && ring->pipe == pipe_id &&
9245                             ring->queue == queue_id)
9246                                 drm_sched_fault(&ring->sched);
9247                 }
9248                 break;
9249         default:
9250                 BUG();
9251         }
9252 }
9253
9254 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9255                                   struct amdgpu_irq_src *source,
9256                                   struct amdgpu_iv_entry *entry)
9257 {
9258         DRM_ERROR("Illegal register access in command stream\n");
9259         gfx_v10_0_handle_priv_fault(adev, entry);
9260         return 0;
9261 }
9262
9263 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9264                                    struct amdgpu_irq_src *source,
9265                                    struct amdgpu_iv_entry *entry)
9266 {
9267         DRM_ERROR("Illegal instruction in command stream\n");
9268         gfx_v10_0_handle_priv_fault(adev, entry);
9269         return 0;
9270 }
9271
9272 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9273                                              struct amdgpu_irq_src *src,
9274                                              unsigned int type,
9275                                              enum amdgpu_interrupt_state state)
9276 {
9277         uint32_t tmp, target;
9278         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9279
9280         if (ring->me == 1)
9281                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9282         else
9283                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9284         target += ring->pipe;
9285
9286         switch (type) {
9287         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9288                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9289                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9290                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9291                                             GENERIC2_INT_ENABLE, 0);
9292                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9293
9294                         tmp = RREG32_SOC15_IP(GC, target);
9295                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9296                                             GENERIC2_INT_ENABLE, 0);
9297                         WREG32_SOC15_IP(GC, target, tmp);
9298                 } else {
9299                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9300                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9301                                             GENERIC2_INT_ENABLE, 1);
9302                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9303
9304                         tmp = RREG32_SOC15_IP(GC, target);
9305                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9306                                             GENERIC2_INT_ENABLE, 1);
9307                         WREG32_SOC15_IP(GC, target, tmp);
9308                 }
9309                 break;
9310         default:
9311                 BUG(); /* kiq only support GENERIC2_INT now */
9312                 break;
9313         }
9314         return 0;
9315 }
9316
9317 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9318                              struct amdgpu_irq_src *source,
9319                              struct amdgpu_iv_entry *entry)
9320 {
9321         u8 me_id, pipe_id, queue_id;
9322         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9323
9324         me_id = (entry->ring_id & 0x0c) >> 2;
9325         pipe_id = (entry->ring_id & 0x03) >> 0;
9326         queue_id = (entry->ring_id & 0x70) >> 4;
9327         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9328                    me_id, pipe_id, queue_id);
9329
9330         amdgpu_fence_process(ring);
9331         return 0;
9332 }
9333
9334 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9335 {
9336         const unsigned int gcr_cntl =
9337                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9338                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9339                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9340                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9341                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9342                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9343                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9344                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9345
9346         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9347         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9348         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9349         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9350         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9351         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9352         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9353         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9354         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9355 }
9356
9357 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9358         .name = "gfx_v10_0",
9359         .early_init = gfx_v10_0_early_init,
9360         .late_init = gfx_v10_0_late_init,
9361         .sw_init = gfx_v10_0_sw_init,
9362         .sw_fini = gfx_v10_0_sw_fini,
9363         .hw_init = gfx_v10_0_hw_init,
9364         .hw_fini = gfx_v10_0_hw_fini,
9365         .suspend = gfx_v10_0_suspend,
9366         .resume = gfx_v10_0_resume,
9367         .is_idle = gfx_v10_0_is_idle,
9368         .wait_for_idle = gfx_v10_0_wait_for_idle,
9369         .soft_reset = gfx_v10_0_soft_reset,
9370         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9371         .set_powergating_state = gfx_v10_0_set_powergating_state,
9372         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9373 };
9374
9375 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9376         .type = AMDGPU_RING_TYPE_GFX,
9377         .align_mask = 0xff,
9378         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9379         .support_64bit_ptrs = true,
9380         .secure_submission_supported = true,
9381         .vmhub = AMDGPU_GFXHUB_0,
9382         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9383         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9384         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9385         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9386                 5 + /* COND_EXEC */
9387                 7 + /* PIPELINE_SYNC */
9388                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9389                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9390                 2 + /* VM_FLUSH */
9391                 8 + /* FENCE for VM_FLUSH */
9392                 20 + /* GDS switch */
9393                 4 + /* double SWITCH_BUFFER,
9394                      * the first COND_EXEC jump to the place
9395                      * just prior to this double SWITCH_BUFFER
9396                      */
9397                 5 + /* COND_EXEC */
9398                 7 + /* HDP_flush */
9399                 4 + /* VGT_flush */
9400                 14 + /* CE_META */
9401                 31 + /* DE_META */
9402                 3 + /* CNTX_CTRL */
9403                 5 + /* HDP_INVL */
9404                 8 + 8 + /* FENCE x2 */
9405                 2 + /* SWITCH_BUFFER */
9406                 8, /* gfx_v10_0_emit_mem_sync */
9407         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9408         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9409         .emit_fence = gfx_v10_0_ring_emit_fence,
9410         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9411         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9412         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9413         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9414         .test_ring = gfx_v10_0_ring_test_ring,
9415         .test_ib = gfx_v10_0_ring_test_ib,
9416         .insert_nop = amdgpu_ring_insert_nop,
9417         .pad_ib = amdgpu_ring_generic_pad_ib,
9418         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9419         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9420         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9421         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9422         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9423         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9424         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9425         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9426         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9427         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9428         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9429 };
9430
9431 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9432         .type = AMDGPU_RING_TYPE_COMPUTE,
9433         .align_mask = 0xff,
9434         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9435         .support_64bit_ptrs = true,
9436         .vmhub = AMDGPU_GFXHUB_0,
9437         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9438         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9439         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9440         .emit_frame_size =
9441                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9442                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9443                 5 + /* hdp invalidate */
9444                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9445                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9446                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9447                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9448                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9449                 8, /* gfx_v10_0_emit_mem_sync */
9450         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9451         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9452         .emit_fence = gfx_v10_0_ring_emit_fence,
9453         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9454         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9455         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9456         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9457         .test_ring = gfx_v10_0_ring_test_ring,
9458         .test_ib = gfx_v10_0_ring_test_ib,
9459         .insert_nop = amdgpu_ring_insert_nop,
9460         .pad_ib = amdgpu_ring_generic_pad_ib,
9461         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9462         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9463         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9464         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9465 };
9466
9467 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9468         .type = AMDGPU_RING_TYPE_KIQ,
9469         .align_mask = 0xff,
9470         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9471         .support_64bit_ptrs = true,
9472         .vmhub = AMDGPU_GFXHUB_0,
9473         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9474         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9475         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9476         .emit_frame_size =
9477                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9478                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9479                 5 + /*hdp invalidate */
9480                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9481                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9482                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9483                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9484                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9485         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9486         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9487         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9488         .test_ring = gfx_v10_0_ring_test_ring,
9489         .test_ib = gfx_v10_0_ring_test_ib,
9490         .insert_nop = amdgpu_ring_insert_nop,
9491         .pad_ib = amdgpu_ring_generic_pad_ib,
9492         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9493         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9494         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9495         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9496 };
9497
9498 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9499 {
9500         int i;
9501
9502         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9503
9504         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9505                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9506
9507         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9508                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9509 }
9510
9511 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9512         .set = gfx_v10_0_set_eop_interrupt_state,
9513         .process = gfx_v10_0_eop_irq,
9514 };
9515
9516 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9517         .set = gfx_v10_0_set_priv_reg_fault_state,
9518         .process = gfx_v10_0_priv_reg_irq,
9519 };
9520
9521 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9522         .set = gfx_v10_0_set_priv_inst_fault_state,
9523         .process = gfx_v10_0_priv_inst_irq,
9524 };
9525
9526 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9527         .set = gfx_v10_0_kiq_set_interrupt_state,
9528         .process = gfx_v10_0_kiq_irq,
9529 };
9530
9531 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9532 {
9533         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9534         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9535
9536         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9537         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9538
9539         adev->gfx.priv_reg_irq.num_types = 1;
9540         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9541
9542         adev->gfx.priv_inst_irq.num_types = 1;
9543         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9544 }
9545
9546 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9547 {
9548         switch (adev->ip_versions[GC_HWIP][0]) {
9549         case IP_VERSION(10, 1, 10):
9550         case IP_VERSION(10, 1, 1):
9551         case IP_VERSION(10, 1, 3):
9552         case IP_VERSION(10, 1, 4):
9553         case IP_VERSION(10, 3, 2):
9554         case IP_VERSION(10, 3, 1):
9555         case IP_VERSION(10, 3, 4):
9556         case IP_VERSION(10, 3, 5):
9557         case IP_VERSION(10, 3, 6):
9558         case IP_VERSION(10, 3, 3):
9559         case IP_VERSION(10, 3, 7):
9560                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9561                 break;
9562         case IP_VERSION(10, 1, 2):
9563         case IP_VERSION(10, 3, 0):
9564                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9565                 break;
9566         default:
9567                 break;
9568         }
9569 }
9570
9571 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9572 {
9573         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9574                             adev->gfx.config.max_sh_per_se *
9575                             adev->gfx.config.max_shader_engines;
9576
9577         adev->gds.gds_size = 0x10000;
9578         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9579         adev->gds.gws_size = 64;
9580         adev->gds.oa_size = 16;
9581 }
9582
9583 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9584                                                           u32 bitmap)
9585 {
9586         u32 data;
9587
9588         if (!bitmap)
9589                 return;
9590
9591         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9592         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9593
9594         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9595 }
9596
9597 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9598 {
9599         u32 disabled_mask =
9600                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9601         u32 efuse_setting = 0;
9602         u32 vbios_setting = 0;
9603
9604         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9605         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9606         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9607
9608         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9609         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9610         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9611
9612         disabled_mask |= efuse_setting | vbios_setting;
9613
9614         return (~disabled_mask);
9615 }
9616
9617 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9618 {
9619         u32 wgp_idx, wgp_active_bitmap;
9620         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9621
9622         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9623         cu_active_bitmap = 0;
9624
9625         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9626                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9627                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9628                 if (wgp_active_bitmap & (1 << wgp_idx))
9629                         cu_active_bitmap |= cu_bitmap_per_wgp;
9630         }
9631
9632         return cu_active_bitmap;
9633 }
9634
9635 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9636                                  struct amdgpu_cu_info *cu_info)
9637 {
9638         int i, j, k, counter, active_cu_number = 0;
9639         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9640         unsigned disable_masks[4 * 2];
9641
9642         if (!adev || !cu_info)
9643                 return -EINVAL;
9644
9645         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9646
9647         mutex_lock(&adev->grbm_idx_mutex);
9648         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9649                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9650                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9651                         if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
9652                              (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
9653                              (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
9654                              (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
9655                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9656                                 continue;
9657                         mask = 1;
9658                         ao_bitmap = 0;
9659                         counter = 0;
9660                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9661                         if (i < 4 && j < 2)
9662                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9663                                         adev, disable_masks[i * 2 + j]);
9664                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9665                         cu_info->bitmap[i][j] = bitmap;
9666
9667                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9668                                 if (bitmap & mask) {
9669                                         if (counter < adev->gfx.config.max_cu_per_sh)
9670                                                 ao_bitmap |= mask;
9671                                         counter++;
9672                                 }
9673                                 mask <<= 1;
9674                         }
9675                         active_cu_number += counter;
9676                         if (i < 2 && j < 2)
9677                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9678                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9679                 }
9680         }
9681         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9682         mutex_unlock(&adev->grbm_idx_mutex);
9683
9684         cu_info->number = active_cu_number;
9685         cu_info->ao_cu_mask = ao_cu_mask;
9686         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9687
9688         return 0;
9689 }
9690
9691 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9692 {
9693         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9694
9695         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9696         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9697         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9698
9699         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9700         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9701         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9702
9703         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9704                                                 adev->gfx.config.max_shader_engines);
9705         disabled_sa = efuse_setting | vbios_setting;
9706         disabled_sa &= max_sa_mask;
9707
9708         return disabled_sa;
9709 }
9710
9711 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9712 {
9713         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9714         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9715
9716         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9717
9718         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9719         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9720         max_shader_engines = adev->gfx.config.max_shader_engines;
9721
9722         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9723                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9724                 disabled_sa_per_se &= max_sa_per_se_mask;
9725                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9726                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9727                         break;
9728                 }
9729         }
9730 }
9731
9732 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9733 {
9734         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9735                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9736                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9737                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9738
9739         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9740         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9741                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9742                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9743                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9744                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9745
9746         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9747                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9748                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9749                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9750
9751         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9752
9753         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9754                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9755 }
9756
9757 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9758 {
9759         .type = AMD_IP_BLOCK_TYPE_GFX,
9760         .major = 10,
9761         .minor = 0,
9762         .rev = 0,
9763         .funcs = &gfx_v10_0_ip_funcs,
9764 };