drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "si_dpm.h"
  34 #include "cik_dpm.h"
  35 #include "vi_dpm.h"
  36
  37 static int amdgpu_create_pp_handle(struct amdgpu_device *adev)
  38 {
  39         struct amd_pp_init pp_init;
  40         struct amd_powerplay *amd_pp;
  41         int ret;
  42
  43         amd_pp = &(adev->powerplay);
  44         pp_init.chip_family = adev->family;
  45         pp_init.chip_id = adev->asic_type;
  46         pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
  47         pp_init.feature_mask = amdgpu_pp_feature_mask;
  48         pp_init.device = amdgpu_cgs_create_device(adev);
  49         ret = amd_powerplay_create(&pp_init, &(amd_pp->pp_handle));
  50         if (ret)
  51                 return -EINVAL;
  52         return 0;
  53 }
  54
  55 static int amdgpu_pp_early_init(void *handle)
  56 {
  57         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  58         struct amd_powerplay *amd_pp;
  59         int ret = 0;
  60
  61         amd_pp = &(adev->powerplay);
  62         adev->pp_enabled = false;
  63         amd_pp->pp_handle = (void *)adev;
  64
  65         switch (adev->asic_type) {
  66         case CHIP_POLARIS11:
  67         case CHIP_POLARIS10:
  68         case CHIP_POLARIS12:
  69         case CHIP_TONGA:
  70         case CHIP_FIJI:
  71         case CHIP_TOPAZ:
  72         case CHIP_CARRIZO:
  73         case CHIP_STONEY:
  74         case CHIP_VEGA10:
  75                 adev->pp_enabled = true;
  76                 if (amdgpu_create_pp_handle(adev))
  77                         return -EINVAL;
  78                 amd_pp->ip_funcs = &pp_ip_funcs;
  79                 amd_pp->pp_funcs = &pp_dpm_funcs;
  80                 break;
  81         /* These chips don't have powerplay implemenations */
  82 #ifdef CONFIG_DRM_AMDGPU_SI
  83         case CHIP_TAHITI:
  84         case CHIP_PITCAIRN:
  85         case CHIP_VERDE:
  86         case CHIP_OLAND:
  87         case CHIP_HAINAN:
  88                 amd_pp->ip_funcs = &si_dpm_ip_funcs;
  89         break;
  90 #endif
  91 #ifdef CONFIG_DRM_AMDGPU_CIK
  92         case CHIP_BONAIRE:
  93         case CHIP_HAWAII:
  94                 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  95                 break;
  96         case CHIP_KABINI:
  97         case CHIP_MULLINS:
  98         case CHIP_KAVERI:
  99                 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
 100                 break;
 101 #endif
 102         default:
 103                 ret = -EINVAL;
 104                 break;
 105         }
 106
 107         if (adev->powerplay.ip_funcs->early_init)
 108                 ret = adev->powerplay.ip_funcs->early_init(
 109                                         adev->powerplay.pp_handle);
 110
 111         if (ret == PP_DPM_DISABLED) {
 112                 adev->pm.dpm_enabled = false;
 113                 return 0;
 114         }
 115         return ret;
 116 }
 117
 118
 119 static int amdgpu_pp_late_init(void *handle)
 120 {
 121         int ret = 0;
 122         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 123
 124         if (adev->powerplay.ip_funcs->late_init)
 125                 ret = adev->powerplay.ip_funcs->late_init(
 126                                         adev->powerplay.pp_handle);
 127
 128         if (adev->pp_enabled && adev->pm.dpm_enabled) {
 129                 amdgpu_pm_sysfs_init(adev);
 130                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
 131         }
 132
 133         return ret;
 134 }
 135
 136 static int amdgpu_pp_sw_init(void *handle)
 137 {
 138         int ret = 0;
 139         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 140
 141         if (adev->powerplay.ip_funcs->sw_init)
 142                 ret = adev->powerplay.ip_funcs->sw_init(
 143                                         adev->powerplay.pp_handle);
 144
 145         return ret;
 146 }
 147
 148 static int amdgpu_pp_sw_fini(void *handle)
 149 {
 150         int ret = 0;
 151         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 152
 153         if (adev->powerplay.ip_funcs->sw_fini)
 154                 ret = adev->powerplay.ip_funcs->sw_fini(
 155                                         adev->powerplay.pp_handle);
 156         if (ret)
 157                 return ret;
 158
 159         return ret;
 160 }
 161
 162 static int amdgpu_pp_hw_init(void *handle)
 163 {
 164         int ret = 0;
 165         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 166
 167         if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
 168                 amdgpu_ucode_init_bo(adev);
 169
 170         if (adev->powerplay.ip_funcs->hw_init)
 171                 ret = adev->powerplay.ip_funcs->hw_init(
 172                                         adev->powerplay.pp_handle);
 173
 174         if (ret == PP_DPM_DISABLED) {
 175                 adev->pm.dpm_enabled = false;
 176                 return 0;
 177         }
 178
 179         if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
 180                 adev->pm.dpm_enabled = true;
 181
 182         return ret;
 183 }
 184
 185 static int amdgpu_pp_hw_fini(void *handle)
 186 {
 187         int ret = 0;
 188         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 189
 190         if (adev->powerplay.ip_funcs->hw_fini)
 191                 ret = adev->powerplay.ip_funcs->hw_fini(
 192                                         adev->powerplay.pp_handle);
 193
 194         if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
 195                 amdgpu_ucode_fini_bo(adev);
 196
 197         return ret;
 198 }
 199
 200 static void amdgpu_pp_late_fini(void *handle)
 201 {
 202         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 203
 204         if (adev->powerplay.ip_funcs->late_fini)
 205                 adev->powerplay.ip_funcs->late_fini(
 206                           adev->powerplay.pp_handle);
 207
 208         if (adev->pp_enabled && adev->pm.dpm_enabled)
 209                 amdgpu_pm_sysfs_fini(adev);
 210
 211         amd_powerplay_destroy(adev->powerplay.pp_handle);
 212 }
 213
 214 static int amdgpu_pp_suspend(void *handle)
 215 {
 216         int ret = 0;
 217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 218
 219         if (adev->powerplay.ip_funcs->suspend)
 220                 ret = adev->powerplay.ip_funcs->suspend(
 221                                          adev->powerplay.pp_handle);
 222         return ret;
 223 }
 224
 225 static int amdgpu_pp_resume(void *handle)
 226 {
 227         int ret = 0;
 228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 229
 230         if (adev->powerplay.ip_funcs->resume)
 231                 ret = adev->powerplay.ip_funcs->resume(
 232                                         adev->powerplay.pp_handle);
 233         return ret;
 234 }
 235
 236 static int amdgpu_pp_set_clockgating_state(void *handle,
 237                                         enum amd_clockgating_state state)
 238 {
 239         int ret = 0;
 240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 241
 242         if (adev->powerplay.ip_funcs->set_clockgating_state)
 243                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 244                                 adev->powerplay.pp_handle, state);
 245         return ret;
 246 }
 247
 248 static int amdgpu_pp_set_powergating_state(void *handle,
 249                                         enum amd_powergating_state state)
 250 {
 251         int ret = 0;
 252         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 253
 254         if (adev->powerplay.ip_funcs->set_powergating_state)
 255                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 256                                  adev->powerplay.pp_handle, state);
 257         return ret;
 258 }
 259
 260
 261 static bool amdgpu_pp_is_idle(void *handle)
 262 {
 263         bool ret = true;
 264         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 265
 266         if (adev->powerplay.ip_funcs->is_idle)
 267                 ret = adev->powerplay.ip_funcs->is_idle(
 268                                         adev->powerplay.pp_handle);
 269         return ret;
 270 }
 271
 272 static int amdgpu_pp_wait_for_idle(void *handle)
 273 {
 274         int ret = 0;
 275         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 276
 277         if (adev->powerplay.ip_funcs->wait_for_idle)
 278                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 279                                         adev->powerplay.pp_handle);
 280         return ret;
 281 }
 282
 283 static int amdgpu_pp_soft_reset(void *handle)
 284 {
 285         int ret = 0;
 286         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 287
 288         if (adev->powerplay.ip_funcs->soft_reset)
 289                 ret = adev->powerplay.ip_funcs->soft_reset(
 290                                         adev->powerplay.pp_handle);
 291         return ret;
 292 }
 293
 294 static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 295         .name = "amdgpu_powerplay",
 296         .early_init = amdgpu_pp_early_init,
 297         .late_init = amdgpu_pp_late_init,
 298         .sw_init = amdgpu_pp_sw_init,
 299         .sw_fini = amdgpu_pp_sw_fini,
 300         .hw_init = amdgpu_pp_hw_init,
 301         .hw_fini = amdgpu_pp_hw_fini,
 302         .late_fini = amdgpu_pp_late_fini,
 303         .suspend = amdgpu_pp_suspend,
 304         .resume = amdgpu_pp_resume,
 305         .is_idle = amdgpu_pp_is_idle,
 306         .wait_for_idle = amdgpu_pp_wait_for_idle,
 307         .soft_reset = amdgpu_pp_soft_reset,
 308         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 309         .set_powergating_state = amdgpu_pp_set_powergating_state,
 310 };
 311
 312 const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
 313 {
 314         .type = AMD_IP_BLOCK_TYPE_SMC,
 315         .major = 1,
 316         .minor = 0,
 317         .rev = 0,
 318         .funcs = &amdgpu_pp_ip_funcs,
 319 };