drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "si_dpm.h"
  34 #include "cik_dpm.h"
  35 #include "vi_dpm.h"
  36
  37 static int amdgpu_create_pp_handle(struct amdgpu_device *adev)
  38 {
  39         struct amd_pp_init pp_init;
  40         struct amd_powerplay *amd_pp;
  41         int ret;
  42
  43         amd_pp = &(adev->powerplay);
  44         pp_init.chip_family = adev->family;
  45         pp_init.chip_id = adev->asic_type;
  46         pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
  47         pp_init.feature_mask = amdgpu_pp_feature_mask;
  48         pp_init.device = amdgpu_cgs_create_device(adev);
  49         ret = amd_powerplay_create(&pp_init, &(amd_pp->pp_handle));
  50         if (ret)
  51                 return -EINVAL;
  52         return 0;
  53 }
  54
  55 static int amdgpu_pp_early_init(void *handle)
  56 {
  57         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  58         struct amd_powerplay *amd_pp;
  59         int ret = 0;
  60
  61         amd_pp = &(adev->powerplay);
  62         adev->pp_enabled = false;
  63         amd_pp->pp_handle = (void *)adev;
  64
  65         switch (adev->asic_type) {
  66         case CHIP_POLARIS11:
  67         case CHIP_POLARIS10:
  68         case CHIP_POLARIS12:
  69         case CHIP_TONGA:
  70         case CHIP_FIJI:
  71         case CHIP_TOPAZ:
  72         case CHIP_CARRIZO:
  73         case CHIP_STONEY:
  74         case CHIP_VEGA10:
  75         case CHIP_RAVEN:
  76                 adev->pp_enabled = true;
  77                 if (amdgpu_create_pp_handle(adev))
  78                         return -EINVAL;
  79                 amd_pp->ip_funcs = &pp_ip_funcs;
  80                 amd_pp->pp_funcs = &pp_dpm_funcs;
  81                 break;
  82         /* These chips don't have powerplay implemenations */
  83 #ifdef CONFIG_DRM_AMDGPU_SI
  84         case CHIP_TAHITI:
  85         case CHIP_PITCAIRN:
  86         case CHIP_VERDE:
  87         case CHIP_OLAND:
  88         case CHIP_HAINAN:
  89                 amd_pp->ip_funcs = &si_dpm_ip_funcs;
  90                 amd_pp->pp_funcs = &si_dpm_funcs;
  91         break;
  92 #endif
  93 #ifdef CONFIG_DRM_AMDGPU_CIK
  94         case CHIP_BONAIRE:
  95         case CHIP_HAWAII:
  96                 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  97                 amd_pp->pp_funcs = &ci_dpm_funcs;
  98                 break;
  99         case CHIP_KABINI:
 100         case CHIP_MULLINS:
 101         case CHIP_KAVERI:
 102                 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
 103                 amd_pp->pp_funcs = &kv_dpm_funcs;
 104                 break;
 105 #endif
 106         default:
 107                 ret = -EINVAL;
 108                 break;
 109         }
 110
 111         if (adev->powerplay.ip_funcs->early_init)
 112                 ret = adev->powerplay.ip_funcs->early_init(
 113                                         adev->powerplay.pp_handle);
 114
 115         if (ret == PP_DPM_DISABLED) {
 116                 adev->pm.dpm_enabled = false;
 117                 return 0;
 118         }
 119         return ret;
 120 }
 121
 122
 123 static int amdgpu_pp_late_init(void *handle)
 124 {
 125         int ret = 0;
 126         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 127
 128         if (adev->powerplay.ip_funcs->late_init)
 129                 ret = adev->powerplay.ip_funcs->late_init(
 130                                         adev->powerplay.pp_handle);
 131
 132         if (adev->pp_enabled && adev->pm.dpm_enabled) {
 133                 amdgpu_pm_sysfs_init(adev);
 134                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
 135         }
 136
 137         return ret;
 138 }
 139
 140 static int amdgpu_pp_sw_init(void *handle)
 141 {
 142         int ret = 0;
 143         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 144
 145         if (adev->powerplay.ip_funcs->sw_init)
 146                 ret = adev->powerplay.ip_funcs->sw_init(
 147                                         adev->powerplay.pp_handle);
 148
 149         return ret;
 150 }
 151
 152 static int amdgpu_pp_sw_fini(void *handle)
 153 {
 154         int ret = 0;
 155         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 156
 157         if (adev->powerplay.ip_funcs->sw_fini)
 158                 ret = adev->powerplay.ip_funcs->sw_fini(
 159                                         adev->powerplay.pp_handle);
 160         if (ret)
 161                 return ret;
 162
 163         return ret;
 164 }
 165
 166 static int amdgpu_pp_hw_init(void *handle)
 167 {
 168         int ret = 0;
 169         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 170
 171         if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
 172                 amdgpu_ucode_init_bo(adev);
 173
 174         if (adev->powerplay.ip_funcs->hw_init)
 175                 ret = adev->powerplay.ip_funcs->hw_init(
 176                                         adev->powerplay.pp_handle);
 177
 178         if (ret == PP_DPM_DISABLED) {
 179                 adev->pm.dpm_enabled = false;
 180                 return 0;
 181         }
 182
 183         if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
 184                 adev->pm.dpm_enabled = true;
 185
 186         return ret;
 187 }
 188
 189 static int amdgpu_pp_hw_fini(void *handle)
 190 {
 191         int ret = 0;
 192         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 193
 194         if (adev->pp_enabled && adev->pm.dpm_enabled)
 195                 amdgpu_pm_sysfs_fini(adev);
 196
 197         if (adev->powerplay.ip_funcs->hw_fini)
 198                 ret = adev->powerplay.ip_funcs->hw_fini(
 199                                         adev->powerplay.pp_handle);
 200
 201         if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
 202                 amdgpu_ucode_fini_bo(adev);
 203
 204         return ret;
 205 }
 206
 207 static void amdgpu_pp_late_fini(void *handle)
 208 {
 209         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 210
 211         if (adev->powerplay.ip_funcs->late_fini)
 212                 adev->powerplay.ip_funcs->late_fini(
 213                           adev->powerplay.pp_handle);
 214
 215
 216         if (adev->pp_enabled)
 217                 amd_powerplay_destroy(adev->powerplay.pp_handle);
 218 }
 219
 220 static int amdgpu_pp_suspend(void *handle)
 221 {
 222         int ret = 0;
 223         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 224
 225         if (adev->powerplay.ip_funcs->suspend)
 226                 ret = adev->powerplay.ip_funcs->suspend(
 227                                          adev->powerplay.pp_handle);
 228         return ret;
 229 }
 230
 231 static int amdgpu_pp_resume(void *handle)
 232 {
 233         int ret = 0;
 234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 235
 236         if (adev->powerplay.ip_funcs->resume)
 237                 ret = adev->powerplay.ip_funcs->resume(
 238                                         adev->powerplay.pp_handle);
 239         return ret;
 240 }
 241
 242 static int amdgpu_pp_set_clockgating_state(void *handle,
 243                                         enum amd_clockgating_state state)
 244 {
 245         int ret = 0;
 246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 247
 248         if (adev->powerplay.ip_funcs->set_clockgating_state)
 249                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 250                                 adev->powerplay.pp_handle, state);
 251         return ret;
 252 }
 253
 254 static int amdgpu_pp_set_powergating_state(void *handle,
 255                                         enum amd_powergating_state state)
 256 {
 257         int ret = 0;
 258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 259
 260         if (adev->powerplay.ip_funcs->set_powergating_state)
 261                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 262                                  adev->powerplay.pp_handle, state);
 263         return ret;
 264 }
 265
 266
 267 static bool amdgpu_pp_is_idle(void *handle)
 268 {
 269         bool ret = true;
 270         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 271
 272         if (adev->powerplay.ip_funcs->is_idle)
 273                 ret = adev->powerplay.ip_funcs->is_idle(
 274                                         adev->powerplay.pp_handle);
 275         return ret;
 276 }
 277
 278 static int amdgpu_pp_wait_for_idle(void *handle)
 279 {
 280         int ret = 0;
 281         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 282
 283         if (adev->powerplay.ip_funcs->wait_for_idle)
 284                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 285                                         adev->powerplay.pp_handle);
 286         return ret;
 287 }
 288
 289 static int amdgpu_pp_soft_reset(void *handle)
 290 {
 291         int ret = 0;
 292         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 293
 294         if (adev->powerplay.ip_funcs->soft_reset)
 295                 ret = adev->powerplay.ip_funcs->soft_reset(
 296                                         adev->powerplay.pp_handle);
 297         return ret;
 298 }
 299
 300 static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 301         .name = "amdgpu_powerplay",
 302         .early_init = amdgpu_pp_early_init,
 303         .late_init = amdgpu_pp_late_init,
 304         .sw_init = amdgpu_pp_sw_init,
 305         .sw_fini = amdgpu_pp_sw_fini,
 306         .hw_init = amdgpu_pp_hw_init,
 307         .hw_fini = amdgpu_pp_hw_fini,
 308         .late_fini = amdgpu_pp_late_fini,
 309         .suspend = amdgpu_pp_suspend,
 310         .resume = amdgpu_pp_resume,
 311         .is_idle = amdgpu_pp_is_idle,
 312         .wait_for_idle = amdgpu_pp_wait_for_idle,
 313         .soft_reset = amdgpu_pp_soft_reset,
 314         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 315         .set_powergating_state = amdgpu_pp_set_powergating_state,
 316 };
 317
 318 const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
 319 {
 320         .type = AMD_IP_BLOCK_TYPE_SMC,
 321         .major = 1,
 322         .minor = 0,
 323         .rev = 0,
 324         .funcs = &amdgpu_pp_ip_funcs,
 325 };