drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/list.h>
  25 #include <linux/slab.h>
  26 #include <linux/pci.h>
  27 #include <linux/acpi.h>
  28 #include <drm/drmP.h>
  29 #include <linux/firmware.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32 #include "cgs_linux.h"
  33 #include "atom.h"
  34 #include "amdgpu_ucode.h"
  35
  36 struct amdgpu_cgs_device {
  37         struct cgs_device base;
  38         struct amdgpu_device *adev;
  39 };
  40
  41 #define CGS_FUNC_ADEV                                                   \
  42         struct amdgpu_device *adev =                                    \
  43                 ((struct amdgpu_cgs_device *)cgs_device)->adev
  44
  45 static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
  46                                     enum cgs_gpu_mem_type type,
  47                                     uint64_t size, uint64_t align,
  48                                     cgs_handle_t *handle)
  49 {
  50         CGS_FUNC_ADEV;
  51         uint16_t flags = 0;
  52         int ret = 0;
  53         uint32_t domain = 0;
  54         struct amdgpu_bo *obj;
  55
  56         /* fail if the alignment is not a power of 2 */
  57         if (((align != 1) && (align & (align - 1)))
  58             || size == 0 || align == 0)
  59                 return -EINVAL;
  60
  61
  62         switch(type) {
  63         case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
  64         case CGS_GPU_MEM_TYPE__VISIBLE_FB:
  65                 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
  66                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
  67                 domain = AMDGPU_GEM_DOMAIN_VRAM;
  68                 break;
  69         case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
  70         case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
  71                 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
  72                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
  73                 domain = AMDGPU_GEM_DOMAIN_VRAM;
  74                 break;
  75         case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
  76                 domain = AMDGPU_GEM_DOMAIN_GTT;
  77                 break;
  78         case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
  79                 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
  80                 domain = AMDGPU_GEM_DOMAIN_GTT;
  81                 break;
  82         default:
  83                 return -EINVAL;
  84         }
  85
  86
  87         *handle = 0;
  88
  89         ret = amdgpu_bo_create(adev, size, align, true, domain, flags,
  90                                NULL, NULL, 0, &obj);
  91         if (ret) {
  92                 DRM_ERROR("(%d) bo create failed\n", ret);
  93                 return ret;
  94         }
  95         *handle = (cgs_handle_t)obj;
  96
  97         return ret;
  98 }
  99
 100 static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
 101 {
 102         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 103
 104         if (obj) {
 105                 int r = amdgpu_bo_reserve(obj, true);
 106                 if (likely(r == 0)) {
 107                         amdgpu_bo_kunmap(obj);
 108                         amdgpu_bo_unpin(obj);
 109                         amdgpu_bo_unreserve(obj);
 110                 }
 111                 amdgpu_bo_unref(&obj);
 112
 113         }
 114         return 0;
 115 }
 116
 117 static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
 118                                    uint64_t *mcaddr)
 119 {
 120         int r;
 121         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 122
 123         WARN_ON_ONCE(obj->placement.num_placement > 1);
 124
 125         r = amdgpu_bo_reserve(obj, true);
 126         if (unlikely(r != 0))
 127                 return r;
 128         r = amdgpu_bo_pin(obj, obj->preferred_domains, mcaddr);
 129         amdgpu_bo_unreserve(obj);
 130         return r;
 131 }
 132
 133 static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
 134 {
 135         int r;
 136         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 137         r = amdgpu_bo_reserve(obj, true);
 138         if (unlikely(r != 0))
 139                 return r;
 140         r = amdgpu_bo_unpin(obj);
 141         amdgpu_bo_unreserve(obj);
 142         return r;
 143 }
 144
 145 static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
 146                                    void **map)
 147 {
 148         int r;
 149         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 150         r = amdgpu_bo_reserve(obj, true);
 151         if (unlikely(r != 0))
 152                 return r;
 153         r = amdgpu_bo_kmap(obj, map);
 154         amdgpu_bo_unreserve(obj);
 155         return r;
 156 }
 157
 158 static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
 159 {
 160         int r;
 161         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 162         r = amdgpu_bo_reserve(obj, true);
 163         if (unlikely(r != 0))
 164                 return r;
 165         amdgpu_bo_kunmap(obj);
 166         amdgpu_bo_unreserve(obj);
 167         return r;
 168 }
 169
 170 static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
 171 {
 172         CGS_FUNC_ADEV;
 173         return RREG32(offset);
 174 }
 175
 176 static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
 177                                       uint32_t value)
 178 {
 179         CGS_FUNC_ADEV;
 180         WREG32(offset, value);
 181 }
 182
 183 static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
 184                                              enum cgs_ind_reg space,
 185                                              unsigned index)
 186 {
 187         CGS_FUNC_ADEV;
 188         switch (space) {
 189         case CGS_IND_REG__MMIO:
 190                 return RREG32_IDX(index);
 191         case CGS_IND_REG__PCIE:
 192                 return RREG32_PCIE(index);
 193         case CGS_IND_REG__SMC:
 194                 return RREG32_SMC(index);
 195         case CGS_IND_REG__UVD_CTX:
 196                 return RREG32_UVD_CTX(index);
 197         case CGS_IND_REG__DIDT:
 198                 return RREG32_DIDT(index);
 199         case CGS_IND_REG_GC_CAC:
 200                 return RREG32_GC_CAC(index);
 201         case CGS_IND_REG_SE_CAC:
 202                 return RREG32_SE_CAC(index);
 203         case CGS_IND_REG__AUDIO_ENDPT:
 204                 DRM_ERROR("audio endpt register access not implemented.\n");
 205                 return 0;
 206         }
 207         WARN(1, "Invalid indirect register space");
 208         return 0;
 209 }
 210
 211 static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
 212                                           enum cgs_ind_reg space,
 213                                           unsigned index, uint32_t value)
 214 {
 215         CGS_FUNC_ADEV;
 216         switch (space) {
 217         case CGS_IND_REG__MMIO:
 218                 return WREG32_IDX(index, value);
 219         case CGS_IND_REG__PCIE:
 220                 return WREG32_PCIE(index, value);
 221         case CGS_IND_REG__SMC:
 222                 return WREG32_SMC(index, value);
 223         case CGS_IND_REG__UVD_CTX:
 224                 return WREG32_UVD_CTX(index, value);
 225         case CGS_IND_REG__DIDT:
 226                 return WREG32_DIDT(index, value);
 227         case CGS_IND_REG_GC_CAC:
 228                 return WREG32_GC_CAC(index, value);
 229         case CGS_IND_REG_SE_CAC:
 230                 return WREG32_SE_CAC(index, value);
 231         case CGS_IND_REG__AUDIO_ENDPT:
 232                 DRM_ERROR("audio endpt register access not implemented.\n");
 233                 return;
 234         }
 235         WARN(1, "Invalid indirect register space");
 236 }
 237
 238 static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
 239                                        enum cgs_resource_type resource_type,
 240                                        uint64_t size,
 241                                        uint64_t offset,
 242                                        uint64_t *resource_base)
 243 {
 244         CGS_FUNC_ADEV;
 245
 246         if (resource_base == NULL)
 247                 return -EINVAL;
 248
 249         switch (resource_type) {
 250         case CGS_RESOURCE_TYPE_MMIO:
 251                 if (adev->rmmio_size == 0)
 252                         return -ENOENT;
 253                 if ((offset + size) > adev->rmmio_size)
 254                         return -EINVAL;
 255                 *resource_base = adev->rmmio_base;
 256                 return 0;
 257         case CGS_RESOURCE_TYPE_DOORBELL:
 258                 if (adev->doorbell.size == 0)
 259                         return -ENOENT;
 260                 if ((offset + size) > adev->doorbell.size)
 261                         return -EINVAL;
 262                 *resource_base = adev->doorbell.base;
 263                 return 0;
 264         case CGS_RESOURCE_TYPE_FB:
 265         case CGS_RESOURCE_TYPE_IO:
 266         case CGS_RESOURCE_TYPE_ROM:
 267         default:
 268                 return -EINVAL;
 269         }
 270 }
 271
 272 static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
 273                                                   unsigned table, uint16_t *size,
 274                                                   uint8_t *frev, uint8_t *crev)
 275 {
 276         CGS_FUNC_ADEV;
 277         uint16_t data_start;
 278
 279         if (amdgpu_atom_parse_data_header(
 280                     adev->mode_info.atom_context, table, size,
 281                     frev, crev, &data_start))
 282                 return (uint8_t*)adev->mode_info.atom_context->bios +
 283                         data_start;
 284
 285         return NULL;
 286 }
 287
 288 static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
 289                                               uint8_t *frev, uint8_t *crev)
 290 {
 291         CGS_FUNC_ADEV;
 292
 293         if (amdgpu_atom_parse_cmd_header(
 294                     adev->mode_info.atom_context, table,
 295                     frev, crev))
 296                 return 0;
 297
 298         return -EINVAL;
 299 }
 300
 301 static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
 302                                           void *args)
 303 {
 304         CGS_FUNC_ADEV;
 305
 306         return amdgpu_atom_execute_table(
 307                 adev->mode_info.atom_context, table, args);
 308 }
 309
 310 struct cgs_irq_params {
 311         unsigned src_id;
 312         cgs_irq_source_set_func_t set;
 313         cgs_irq_handler_func_t handler;
 314         void *private_data;
 315 };
 316
 317 static int cgs_set_irq_state(struct amdgpu_device *adev,
 318                              struct amdgpu_irq_src *src,
 319                              unsigned type,
 320                              enum amdgpu_interrupt_state state)
 321 {
 322         struct cgs_irq_params *irq_params =
 323                 (struct cgs_irq_params *)src->data;
 324         if (!irq_params)
 325                 return -EINVAL;
 326         if (!irq_params->set)
 327                 return -EINVAL;
 328         return irq_params->set(irq_params->private_data,
 329                                irq_params->src_id,
 330                                type,
 331                                (int)state);
 332 }
 333
 334 static int cgs_process_irq(struct amdgpu_device *adev,
 335                            struct amdgpu_irq_src *source,
 336                            struct amdgpu_iv_entry *entry)
 337 {
 338         struct cgs_irq_params *irq_params =
 339                 (struct cgs_irq_params *)source->data;
 340         if (!irq_params)
 341                 return -EINVAL;
 342         if (!irq_params->handler)
 343                 return -EINVAL;
 344         return irq_params->handler(irq_params->private_data,
 345                                    irq_params->src_id,
 346                                    entry->iv_entry);
 347 }
 348
 349 static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
 350         .set = cgs_set_irq_state,
 351         .process = cgs_process_irq,
 352 };
 353
 354 static int amdgpu_cgs_add_irq_source(void *cgs_device,
 355                                      unsigned client_id,
 356                                      unsigned src_id,
 357                                      unsigned num_types,
 358                                      cgs_irq_source_set_func_t set,
 359                                      cgs_irq_handler_func_t handler,
 360                                      void *private_data)
 361 {
 362         CGS_FUNC_ADEV;
 363         int ret = 0;
 364         struct cgs_irq_params *irq_params;
 365         struct amdgpu_irq_src *source =
 366                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
 367         if (!source)
 368                 return -ENOMEM;
 369         irq_params =
 370                 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
 371         if (!irq_params) {
 372                 kfree(source);
 373                 return -ENOMEM;
 374         }
 375         source->num_types = num_types;
 376         source->funcs = &cgs_irq_funcs;
 377         irq_params->src_id = src_id;
 378         irq_params->set = set;
 379         irq_params->handler = handler;
 380         irq_params->private_data = private_data;
 381         source->data = (void *)irq_params;
 382         ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
 383         if (ret) {
 384                 kfree(irq_params);
 385                 kfree(source);
 386         }
 387
 388         return ret;
 389 }
 390
 391 static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
 392                               unsigned src_id, unsigned type)
 393 {
 394         CGS_FUNC_ADEV;
 395
 396         if (!adev->irq.client[client_id].sources)
 397                 return -EINVAL;
 398
 399         return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type);
 400 }
 401
 402 static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id,
 403                               unsigned src_id, unsigned type)
 404 {
 405         CGS_FUNC_ADEV;
 406
 407         if (!adev->irq.client[client_id].sources)
 408                 return -EINVAL;
 409
 410         return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type);
 411 }
 412
 413 static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
 414                                   enum amd_ip_block_type block_type,
 415                                   enum amd_clockgating_state state)
 416 {
 417         CGS_FUNC_ADEV;
 418         int i, r = -1;
 419
 420         for (i = 0; i < adev->num_ip_blocks; i++) {
 421                 if (!adev->ip_blocks[i].status.valid)
 422                         continue;
 423
 424                 if (adev->ip_blocks[i].version->type == block_type) {
 425                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
 426                                                                 (void *)adev,
 427                                                                         state);
 428                         break;
 429                 }
 430         }
 431         return r;
 432 }
 433
 434 static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
 435                                   enum amd_ip_block_type block_type,
 436                                   enum amd_powergating_state state)
 437 {
 438         CGS_FUNC_ADEV;
 439         int i, r = -1;
 440
 441         for (i = 0; i < adev->num_ip_blocks; i++) {
 442                 if (!adev->ip_blocks[i].status.valid)
 443                         continue;
 444
 445                 if (adev->ip_blocks[i].version->type == block_type) {
 446                         r = adev->ip_blocks[i].version->funcs->set_powergating_state(
 447                                                                 (void *)adev,
 448                                                                         state);
 449                         break;
 450                 }
 451         }
 452         return r;
 453 }
 454
 455
 456 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
 457 {
 458         CGS_FUNC_ADEV;
 459         enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
 460
 461         switch (fw_type) {
 462         case CGS_UCODE_ID_SDMA0:
 463                 result = AMDGPU_UCODE_ID_SDMA0;
 464                 break;
 465         case CGS_UCODE_ID_SDMA1:
 466                 result = AMDGPU_UCODE_ID_SDMA1;
 467                 break;
 468         case CGS_UCODE_ID_CP_CE:
 469                 result = AMDGPU_UCODE_ID_CP_CE;
 470                 break;
 471         case CGS_UCODE_ID_CP_PFP:
 472                 result = AMDGPU_UCODE_ID_CP_PFP;
 473                 break;
 474         case CGS_UCODE_ID_CP_ME:
 475                 result = AMDGPU_UCODE_ID_CP_ME;
 476                 break;
 477         case CGS_UCODE_ID_CP_MEC:
 478         case CGS_UCODE_ID_CP_MEC_JT1:
 479                 result = AMDGPU_UCODE_ID_CP_MEC1;
 480                 break;
 481         case CGS_UCODE_ID_CP_MEC_JT2:
 482                 /* for VI. JT2 should be the same as JT1, because:
 483                         1, MEC2 and MEC1 use exactly same FW.
 484                         2, JT2 is not pached but JT1 is.
 485                 */
 486                 if (adev->asic_type >= CHIP_TOPAZ)
 487                         result = AMDGPU_UCODE_ID_CP_MEC1;
 488                 else
 489                         result = AMDGPU_UCODE_ID_CP_MEC2;
 490                 break;
 491         case CGS_UCODE_ID_RLC_G:
 492                 result = AMDGPU_UCODE_ID_RLC_G;
 493                 break;
 494         case CGS_UCODE_ID_STORAGE:
 495                 result = AMDGPU_UCODE_ID_STORAGE;
 496                 break;
 497         default:
 498                 DRM_ERROR("Firmware type not supported\n");
 499         }
 500         return result;
 501 }
 502
 503 static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
 504 {
 505         CGS_FUNC_ADEV;
 506         if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
 507                 release_firmware(adev->pm.fw);
 508                 adev->pm.fw = NULL;
 509                 return 0;
 510         }
 511         /* cannot release other firmware because they are not created by cgs */
 512         return -EINVAL;
 513 }
 514
 515 static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
 516                                         enum cgs_ucode_id type)
 517 {
 518         CGS_FUNC_ADEV;
 519         uint16_t fw_version = 0;
 520
 521         switch (type) {
 522                 case CGS_UCODE_ID_SDMA0:
 523                         fw_version = adev->sdma.instance[0].fw_version;
 524                         break;
 525                 case CGS_UCODE_ID_SDMA1:
 526                         fw_version = adev->sdma.instance[1].fw_version;
 527                         break;
 528                 case CGS_UCODE_ID_CP_CE:
 529                         fw_version = adev->gfx.ce_fw_version;
 530                         break;
 531                 case CGS_UCODE_ID_CP_PFP:
 532                         fw_version = adev->gfx.pfp_fw_version;
 533                         break;
 534                 case CGS_UCODE_ID_CP_ME:
 535                         fw_version = adev->gfx.me_fw_version;
 536                         break;
 537                 case CGS_UCODE_ID_CP_MEC:
 538                         fw_version = adev->gfx.mec_fw_version;
 539                         break;
 540                 case CGS_UCODE_ID_CP_MEC_JT1:
 541                         fw_version = adev->gfx.mec_fw_version;
 542                         break;
 543                 case CGS_UCODE_ID_CP_MEC_JT2:
 544                         fw_version = adev->gfx.mec_fw_version;
 545                         break;
 546                 case CGS_UCODE_ID_RLC_G:
 547                         fw_version = adev->gfx.rlc_fw_version;
 548                         break;
 549                 case CGS_UCODE_ID_STORAGE:
 550                         break;
 551                 default:
 552                         DRM_ERROR("firmware type %d do not have version\n", type);
 553                         break;
 554         }
 555         return fw_version;
 556 }
 557
 558 static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device,
 559                                         bool en)
 560 {
 561         CGS_FUNC_ADEV;
 562
 563         if (adev->gfx.rlc.funcs->enter_safe_mode == NULL ||
 564                 adev->gfx.rlc.funcs->exit_safe_mode == NULL)
 565                 return 0;
 566
 567         if (en)
 568                 adev->gfx.rlc.funcs->enter_safe_mode(adev);
 569         else
 570                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 571
 572         return 0;
 573 }
 574
 575 static void amdgpu_cgs_lock_grbm_idx(struct cgs_device *cgs_device,
 576                                         bool lock)
 577 {
 578         CGS_FUNC_ADEV;
 579
 580         if (lock)
 581                 mutex_lock(&adev->grbm_idx_mutex);
 582         else
 583                 mutex_unlock(&adev->grbm_idx_mutex);
 584 }
 585
 586 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
 587                                         enum cgs_ucode_id type,
 588                                         struct cgs_firmware_info *info)
 589 {
 590         CGS_FUNC_ADEV;
 591
 592         if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
 593                 uint64_t gpu_addr;
 594                 uint32_t data_size;
 595                 const struct gfx_firmware_header_v1_0 *header;
 596                 enum AMDGPU_UCODE_ID id;
 597                 struct amdgpu_firmware_info *ucode;
 598
 599                 id = fw_type_convert(cgs_device, type);
 600                 ucode = &adev->firmware.ucode[id];
 601                 if (ucode->fw == NULL)
 602                         return -EINVAL;
 603
 604                 gpu_addr  = ucode->mc_addr;
 605                 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 606                 data_size = le32_to_cpu(header->header.ucode_size_bytes);
 607
 608                 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
 609                     (type == CGS_UCODE_ID_CP_MEC_JT2)) {
 610                         gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
 611                         data_size = le32_to_cpu(header->jt_size) << 2;
 612                 }
 613
 614                 info->kptr = ucode->kaddr;
 615                 info->image_size = data_size;
 616                 info->mc_addr = gpu_addr;
 617                 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
 618
 619                 if (CGS_UCODE_ID_CP_MEC == type)
 620                         info->image_size = le32_to_cpu(header->jt_offset) << 2;
 621
 622                 info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
 623                 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
 624         } else {
 625                 char fw_name[30] = {0};
 626                 int err = 0;
 627                 uint32_t ucode_size;
 628                 uint32_t ucode_start_address;
 629                 const uint8_t *src;
 630                 const struct smc_firmware_header_v1_0 *hdr;
 631                 const struct common_firmware_header *header;
 632                 struct amdgpu_firmware_info *ucode = NULL;
 633
 634                 if (!adev->pm.fw) {
 635                         switch (adev->asic_type) {
 636                         case CHIP_TOPAZ:
 637                                 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
 638                                     ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
 639                                     ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) {
 640                                         info->is_kicker = true;
 641                                         strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
 642                                 } else
 643                                         strcpy(fw_name, "amdgpu/topaz_smc.bin");
 644                                 break;
 645                         case CHIP_TONGA:
 646                                 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
 647                                     ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
 648                                         info->is_kicker = true;
 649                                         strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
 650                                 } else
 651                                         strcpy(fw_name, "amdgpu/tonga_smc.bin");
 652                                 break;
 653                         case CHIP_FIJI:
 654                                 strcpy(fw_name, "amdgpu/fiji_smc.bin");
 655                                 break;
 656                         case CHIP_POLARIS11:
 657                                 if (type == CGS_UCODE_ID_SMU) {
 658                                         if (((adev->pdev->device == 0x67ef) &&
 659                                              ((adev->pdev->revision == 0xe0) ||
 660                                               (adev->pdev->revision == 0xe2) ||
 661                                               (adev->pdev->revision == 0xe5))) ||
 662                                             ((adev->pdev->device == 0x67ff) &&
 663                                              ((adev->pdev->revision == 0xcf) ||
 664                                               (adev->pdev->revision == 0xef) ||
 665                                               (adev->pdev->revision == 0xff)))) {
 666                                                 info->is_kicker = true;
 667                                                 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
 668                                         } else
 669                                                 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
 670                                 } else if (type == CGS_UCODE_ID_SMU_SK) {
 671                                         strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
 672                                 }
 673                                 break;
 674                         case CHIP_POLARIS10:
 675                                 if (type == CGS_UCODE_ID_SMU) {
 676                                         if ((adev->pdev->device == 0x67df) &&
 677                                             ((adev->pdev->revision == 0xe0) ||
 678                                              (adev->pdev->revision == 0xe3) ||
 679                                              (adev->pdev->revision == 0xe4) ||
 680                                              (adev->pdev->revision == 0xe5) ||
 681                                              (adev->pdev->revision == 0xe7) ||
 682                                              (adev->pdev->revision == 0xef))) {
 683                                                 info->is_kicker = true;
 684                                                 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
 685                                         } else
 686                                                 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
 687                                 } else if (type == CGS_UCODE_ID_SMU_SK) {
 688                                         strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
 689                                 }
 690                                 break;
 691                         case CHIP_POLARIS12:
 692                                 strcpy(fw_name, "amdgpu/polaris12_smc.bin");
 693                                 break;
 694                         case CHIP_VEGA10:
 695                                 if ((adev->pdev->device == 0x687f) &&
 696                                         ((adev->pdev->revision == 0xc0) ||
 697                                         (adev->pdev->revision == 0xc1) ||
 698                                         (adev->pdev->revision == 0xc3)))
 699                                         strcpy(fw_name, "amdgpu/vega10_acg_smc.bin");
 700                                 else
 701                                         strcpy(fw_name, "amdgpu/vega10_smc.bin");
 702                                 break;
 703                         default:
 704                                 DRM_ERROR("SMC firmware not supported\n");
 705                                 return -EINVAL;
 706                         }
 707
 708                         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 709                         if (err) {
 710                                 DRM_ERROR("Failed to request firmware\n");
 711                                 return err;
 712                         }
 713
 714                         err = amdgpu_ucode_validate(adev->pm.fw);
 715                         if (err) {
 716                                 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
 717                                 release_firmware(adev->pm.fw);
 718                                 adev->pm.fw = NULL;
 719                                 return err;
 720                         }
 721
 722                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 723                                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 724                                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 725                                 ucode->fw = adev->pm.fw;
 726                                 header = (const struct common_firmware_header *)ucode->fw->data;
 727                                 adev->firmware.fw_size +=
 728                                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 729                         }
 730                 }
 731
 732                 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 733                 amdgpu_ucode_print_smc_hdr(&hdr->header);
 734                 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 735                 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 736                 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
 737                 src = (const uint8_t *)(adev->pm.fw->data +
 738                        le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 739
 740                 info->version = adev->pm.fw_version;
 741                 info->image_size = ucode_size;
 742                 info->ucode_start_address = ucode_start_address;
 743                 info->kptr = (void *)src;
 744         }
 745         return 0;
 746 }
 747
 748 static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
 749 {
 750         CGS_FUNC_ADEV;
 751         return amdgpu_sriov_vf(adev);
 752 }
 753
 754 static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
 755                                         struct cgs_system_info *sys_info)
 756 {
 757         CGS_FUNC_ADEV;
 758
 759         if (NULL == sys_info)
 760                 return -ENODEV;
 761
 762         if (sizeof(struct cgs_system_info) != sys_info->size)
 763                 return -ENODEV;
 764
 765         switch (sys_info->info_id) {
 766         case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
 767                 sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
 768                 break;
 769         case CGS_SYSTEM_INFO_PCIE_GEN_INFO:
 770                 sys_info->value = adev->pm.pcie_gen_mask;
 771                 break;
 772         case CGS_SYSTEM_INFO_PCIE_MLW:
 773                 sys_info->value = adev->pm.pcie_mlw_mask;
 774                 break;
 775         case CGS_SYSTEM_INFO_PCIE_DEV:
 776                 sys_info->value = adev->pdev->device;
 777                 break;
 778         case CGS_SYSTEM_INFO_PCIE_REV:
 779                 sys_info->value = adev->pdev->revision;
 780                 break;
 781         case CGS_SYSTEM_INFO_CG_FLAGS:
 782                 sys_info->value = adev->cg_flags;
 783                 break;
 784         case CGS_SYSTEM_INFO_PG_FLAGS:
 785                 sys_info->value = adev->pg_flags;
 786                 break;
 787         case CGS_SYSTEM_INFO_GFX_CU_INFO:
 788                 sys_info->value = adev->gfx.cu_info.number;
 789                 break;
 790         case CGS_SYSTEM_INFO_GFX_SE_INFO:
 791                 sys_info->value = adev->gfx.config.max_shader_engines;
 792                 break;
 793         case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID:
 794                 sys_info->value = adev->pdev->subsystem_device;
 795                 break;
 796         case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:
 797                 sys_info->value = adev->pdev->subsystem_vendor;
 798                 break;
 799         default:
 800                 return -ENODEV;
 801         }
 802
 803         return 0;
 804 }
 805
 806 static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
 807                                           struct cgs_display_info *info)
 808 {
 809         CGS_FUNC_ADEV;
 810         struct amdgpu_crtc *amdgpu_crtc;
 811         struct drm_device *ddev = adev->ddev;
 812         struct drm_crtc *crtc;
 813         uint32_t line_time_us, vblank_lines;
 814         struct cgs_mode_info *mode_info;
 815
 816         if (info == NULL)
 817                 return -EINVAL;
 818
 819         mode_info = info->mode_info;
 820         if (mode_info) {
 821                 /* if the displays are off, vblank time is max */
 822                 mode_info->vblank_time_us = 0xffffffff;
 823                 /* always set the reference clock */
 824                 mode_info->ref_clock = adev->clock.spll.reference_freq;
 825         }
 826
 827         if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
 828                 list_for_each_entry(crtc,
 829                                 &ddev->mode_config.crtc_list, head) {
 830                         amdgpu_crtc = to_amdgpu_crtc(crtc);
 831                         if (crtc->enabled) {
 832                                 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
 833                                 info->display_count++;
 834                         }
 835                         if (mode_info != NULL &&
 836                                 crtc->enabled && amdgpu_crtc->enabled &&
 837                                 amdgpu_crtc->hw_mode.clock) {
 838                                 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
 839                                                         amdgpu_crtc->hw_mode.clock;
 840                                 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
 841                                                         amdgpu_crtc->hw_mode.crtc_vdisplay +
 842                                                         (amdgpu_crtc->v_border * 2);
 843                                 mode_info->vblank_time_us = vblank_lines * line_time_us;
 844                                 mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
 845                                 mode_info->ref_clock = adev->clock.spll.reference_freq;
 846                                 mode_info = NULL;
 847                         }
 848                 }
 849         }
 850
 851         return 0;
 852 }
 853
 854
 855 static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
 856 {
 857         CGS_FUNC_ADEV;
 858
 859         adev->pm.dpm_enabled = enabled;
 860
 861         return 0;
 862 }
 863
 864 /** \brief evaluate acpi namespace object, handle or pathname must be valid
 865  *  \param cgs_device
 866  *  \param info input/output arguments for the control method
 867  *  \return status
 868  */
 869
 870 #if defined(CONFIG_ACPI)
 871 static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
 872                                     struct cgs_acpi_method_info *info)
 873 {
 874         CGS_FUNC_ADEV;
 875         acpi_handle handle;
 876         struct acpi_object_list input;
 877         struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
 878         union acpi_object *params, *obj;
 879         uint8_t name[5] = {'\0'};
 880         struct cgs_acpi_method_argument *argument;
 881         uint32_t i, count;
 882         acpi_status status;
 883         int result;
 884
 885         handle = ACPI_HANDLE(&adev->pdev->dev);
 886         if (!handle)
 887                 return -ENODEV;
 888
 889         memset(&input, 0, sizeof(struct acpi_object_list));
 890
 891         /* validate input info */
 892         if (info->size != sizeof(struct cgs_acpi_method_info))
 893                 return -EINVAL;
 894
 895         input.count = info->input_count;
 896         if (info->input_count > 0) {
 897                 if (info->pinput_argument == NULL)
 898                         return -EINVAL;
 899                 argument = info->pinput_argument;
 900                 for (i = 0; i < info->input_count; i++) {
 901                         if (((argument->type == ACPI_TYPE_STRING) ||
 902                              (argument->type == ACPI_TYPE_BUFFER)) &&
 903                             (argument->pointer == NULL))
 904                                 return -EINVAL;
 905                         argument++;
 906                 }
 907         }
 908
 909         if (info->output_count > 0) {
 910                 if (info->poutput_argument == NULL)
 911                         return -EINVAL;
 912                 argument = info->poutput_argument;
 913                 for (i = 0; i < info->output_count; i++) {
 914                         if (((argument->type == ACPI_TYPE_STRING) ||
 915                                 (argument->type == ACPI_TYPE_BUFFER))
 916                                 && (argument->pointer == NULL))
 917                                 return -EINVAL;
 918                         argument++;
 919                 }
 920         }
 921
 922         /* The path name passed to acpi_evaluate_object should be null terminated */
 923         if ((info->field & CGS_ACPI_FIELD_METHOD_NAME) != 0) {
 924                 strncpy(name, (char *)&(info->name), sizeof(uint32_t));
 925                 name[4] = '\0';
 926         }
 927
 928         /* parse input parameters */
 929         if (input.count > 0) {
 930                 input.pointer = params =
 931                                 kzalloc(sizeof(union acpi_object) * input.count, GFP_KERNEL);
 932                 if (params == NULL)
 933                         return -EINVAL;
 934
 935                 argument = info->pinput_argument;
 936
 937                 for (i = 0; i < input.count; i++) {
 938                         params->type = argument->type;
 939                         switch (params->type) {
 940                         case ACPI_TYPE_INTEGER:
 941                                 params->integer.value = argument->value;
 942                                 break;
 943                         case ACPI_TYPE_STRING:
 944                                 params->string.length = argument->data_length;
 945                                 params->string.pointer = argument->pointer;
 946                                 break;
 947                         case ACPI_TYPE_BUFFER:
 948                                 params->buffer.length = argument->data_length;
 949                                 params->buffer.pointer = argument->pointer;
 950                                 break;
 951                         default:
 952                                 break;
 953                         }
 954                         params++;
 955                         argument++;
 956                 }
 957         }
 958
 959         /* parse output info */
 960         count = info->output_count;
 961         argument = info->poutput_argument;
 962
 963         /* evaluate the acpi method */
 964         status = acpi_evaluate_object(handle, name, &input, &output);
 965
 966         if (ACPI_FAILURE(status)) {
 967                 result = -EIO;
 968                 goto free_input;
 969         }
 970
 971         /* return the output info */
 972         obj = output.pointer;
 973
 974         if (count > 1) {
 975                 if ((obj->type != ACPI_TYPE_PACKAGE) ||
 976                         (obj->package.count != count)) {
 977                         result = -EIO;
 978                         goto free_obj;
 979                 }
 980                 params = obj->package.elements;
 981         } else
 982                 params = obj;
 983
 984         if (params == NULL) {
 985                 result = -EIO;
 986                 goto free_obj;
 987         }
 988
 989         for (i = 0; i < count; i++) {
 990                 if (argument->type != params->type) {
 991                         result = -EIO;
 992                         goto free_obj;
 993                 }
 994                 switch (params->type) {
 995                 case ACPI_TYPE_INTEGER:
 996                         argument->value = params->integer.value;
 997                         break;
 998                 case ACPI_TYPE_STRING:
 999                         if ((params->string.length != argument->data_length) ||
1000                                 (params->string.pointer == NULL)) {
1001                                 result = -EIO;
1002                                 goto free_obj;
1003                         }
1004                         strncpy(argument->pointer,
1005                                 params->string.pointer,
1006                                 params->string.length);
1007                         break;
1008                 case ACPI_TYPE_BUFFER:
1009                         if (params->buffer.pointer == NULL) {
1010                                 result = -EIO;
1011                                 goto free_obj;
1012                         }
1013                         memcpy(argument->pointer,
1014                                 params->buffer.pointer,
1015                                 argument->data_length);
1016                         break;
1017                 default:
1018                         break;
1019                 }
1020                 argument++;
1021                 params++;
1022         }
1023
1024         result = 0;
1025 free_obj:
1026         kfree(obj);
1027 free_input:
1028         kfree((void *)input.pointer);
1029         return result;
1030 }
1031 #else
1032 static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
1033                                 struct cgs_acpi_method_info *info)
1034 {
1035         return -EIO;
1036 }
1037 #endif
1038
1039 static int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
1040                                         uint32_t acpi_method,
1041                                         uint32_t acpi_function,
1042                                         void *pinput, void *poutput,
1043                                         uint32_t output_count,
1044                                         uint32_t input_size,
1045                                         uint32_t output_size)
1046 {
1047         struct cgs_acpi_method_argument acpi_input[2] = { {0}, {0} };
1048         struct cgs_acpi_method_argument acpi_output = {0};
1049         struct cgs_acpi_method_info info = {0};
1050
1051         acpi_input[0].type = CGS_ACPI_TYPE_INTEGER;
1052         acpi_input[0].data_length = sizeof(uint32_t);
1053         acpi_input[0].value = acpi_function;
1054
1055         acpi_input[1].type = CGS_ACPI_TYPE_BUFFER;
1056         acpi_input[1].data_length = input_size;
1057         acpi_input[1].pointer = pinput;
1058
1059         acpi_output.type = CGS_ACPI_TYPE_BUFFER;
1060         acpi_output.data_length = output_size;
1061         acpi_output.pointer = poutput;
1062
1063         info.size = sizeof(struct cgs_acpi_method_info);
1064         info.field = CGS_ACPI_FIELD_METHOD_NAME | CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT;
1065         info.input_count = 2;
1066         info.name = acpi_method;
1067         info.pinput_argument = acpi_input;
1068         info.output_count = output_count;
1069         info.poutput_argument = &acpi_output;
1070
1071         return amdgpu_cgs_acpi_eval_object(cgs_device, &info);
1072 }
1073
1074 static const struct cgs_ops amdgpu_cgs_ops = {
1075         .alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,
1076         .free_gpu_mem = amdgpu_cgs_free_gpu_mem,
1077         .gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,
1078         .gunmap_gpu_mem = amdgpu_cgs_gunmap_gpu_mem,
1079         .kmap_gpu_mem = amdgpu_cgs_kmap_gpu_mem,
1080         .kunmap_gpu_mem = amdgpu_cgs_kunmap_gpu_mem,
1081         .read_register = amdgpu_cgs_read_register,
1082         .write_register = amdgpu_cgs_write_register,
1083         .read_ind_register = amdgpu_cgs_read_ind_register,
1084         .write_ind_register = amdgpu_cgs_write_ind_register,
1085         .get_pci_resource = amdgpu_cgs_get_pci_resource,
1086         .atom_get_data_table = amdgpu_cgs_atom_get_data_table,
1087         .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
1088         .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
1089         .get_firmware_info = amdgpu_cgs_get_firmware_info,
1090         .rel_firmware = amdgpu_cgs_rel_firmware,
1091         .set_powergating_state = amdgpu_cgs_set_powergating_state,
1092         .set_clockgating_state = amdgpu_cgs_set_clockgating_state,
1093         .get_active_displays_info = amdgpu_cgs_get_active_displays_info,
1094         .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
1095         .call_acpi_method = amdgpu_cgs_call_acpi_method,
1096         .query_system_info = amdgpu_cgs_query_system_info,
1097         .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
1098         .enter_safe_mode = amdgpu_cgs_enter_safe_mode,
1099         .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
1100 };
1101
1102 static const struct cgs_os_ops amdgpu_cgs_os_ops = {
1103         .add_irq_source = amdgpu_cgs_add_irq_source,
1104         .irq_get = amdgpu_cgs_irq_get,
1105         .irq_put = amdgpu_cgs_irq_put
1106 };
1107
1108 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
1109 {
1110         struct amdgpu_cgs_device *cgs_device =
1111                 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
1112
1113         if (!cgs_device) {
1114                 DRM_ERROR("Couldn't allocate CGS device structure\n");
1115                 return NULL;
1116         }
1117
1118         cgs_device->base.ops = &amdgpu_cgs_ops;
1119         cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
1120         cgs_device->adev = adev;
1121
1122         return (struct cgs_device *)cgs_device;
1123 }
1124
1125 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
1126 {
1127         kfree(cgs_device);
1128 }