drivers/gpu/drm/amd/amdgpu/soc15d.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef SOC15_H
  24 #define SOC15_H
  25
  26 #define GFX9_NUM_GFX_RINGS     1
  27 #define GFX9_NUM_COMPUTE_RINGS 8
  28
  29 /*
  30  * PM4
  31  */
  32 #define PACKET_TYPE0    0
  33 #define PACKET_TYPE1    1
  34 #define PACKET_TYPE2    2
  35 #define PACKET_TYPE3    3
  36
  37 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
  38 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
  39 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
  40 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
  41 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |                         \
  42                          ((reg) & 0xFFFF) |                     \
  43                          ((n) & 0x3FFF) << 16)
  44 #define CP_PACKET2                      0x80000000
  45 #define         PACKET2_PAD_SHIFT               0
  46 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
  47
  48 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
  49
  50 #define PACKET3(op, n)  ((PACKET_TYPE3 << 30) |                         \
  51                          (((op) & 0xFF) << 8) |                         \
  52                          ((n) & 0x3FFF) << 16)
  53
  54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
  55
  56 #define PACKETJ_CONDITION_CHECK0        0
  57 #define PACKETJ_CONDITION_CHECK1        1
  58 #define PACKETJ_CONDITION_CHECK2        2
  59 #define PACKETJ_CONDITION_CHECK3        3
  60 #define PACKETJ_CONDITION_CHECK4        4
  61 #define PACKETJ_CONDITION_CHECK5        5
  62 #define PACKETJ_CONDITION_CHECK6        6
  63 #define PACKETJ_CONDITION_CHECK7        7
  64
  65 #define PACKETJ_TYPE0   0
  66 #define PACKETJ_TYPE1   1
  67 #define PACKETJ_TYPE2   2
  68 #define PACKETJ_TYPE3   3
  69 #define PACKETJ_TYPE4   4
  70 #define PACKETJ_TYPE5   5
  71 #define PACKETJ_TYPE6   6
  72 #define PACKETJ_TYPE7   7
  73
  74 #define PACKETJ(reg, r, cond, type)     ((reg & 0x3FFFF) |                      \
  75                          ((r & 0x3F) << 18) |                   \
  76                          ((cond & 0xF) << 24) |                         \
  77                          ((type & 0xF) << 28))
  78
  79 #define CP_PACKETJ_NOP          0x60000000
  80 #define CP_PACKETJ_GET_REG(x)  ((x) & 0x3FFFF)
  81 #define CP_PACKETJ_GET_RES(x)  (((x) >> 18) & 0x3F)
  82 #define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF)
  83 #define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF)
  84
  85 /* Packet 3 types */
  86 #define PACKET3_NOP                                     0x10
  87 #define PACKET3_SET_BASE                                0x11
  88 #define         PACKET3_BASE_INDEX(x)                  ((x) << 0)
  89 #define                 CE_PARTITION_BASE               3
  90 #define PACKET3_CLEAR_STATE                             0x12
  91 #define PACKET3_INDEX_BUFFER_SIZE                       0x13
  92 #define PACKET3_DISPATCH_DIRECT                         0x15
  93 #define PACKET3_DISPATCH_INDIRECT                       0x16
  94 #define PACKET3_ATOMIC_GDS                              0x1D
  95 #define PACKET3_ATOMIC_MEM                              0x1E
  96 #define PACKET3_OCCLUSION_QUERY                         0x1F
  97 #define PACKET3_SET_PREDICATION                         0x20
  98 #define PACKET3_REG_RMW                                 0x21
  99 #define PACKET3_COND_EXEC                               0x22
 100 #define PACKET3_PRED_EXEC                               0x23
 101 #define PACKET3_DRAW_INDIRECT                           0x24
 102 #define PACKET3_DRAW_INDEX_INDIRECT                     0x25
 103 #define PACKET3_INDEX_BASE                              0x26
 104 #define PACKET3_DRAW_INDEX_2                            0x27
 105 #define PACKET3_CONTEXT_CONTROL                         0x28
 106 #define PACKET3_INDEX_TYPE                              0x2A
 107 #define PACKET3_DRAW_INDIRECT_MULTI                     0x2C
 108 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
 109 #define PACKET3_NUM_INSTANCES                           0x2F
 110 #define PACKET3_DRAW_INDEX_MULTI_AUTO                   0x30
 111 #define PACKET3_INDIRECT_BUFFER_CONST                   0x33
 112 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
 113 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
 114 #define PACKET3_DRAW_PREAMBLE                           0x36
 115 #define PACKET3_WRITE_DATA                              0x37
 116 #define         WRITE_DATA_DST_SEL(x)                   ((x) << 8)
 117                 /* 0 - register
 118                  * 1 - memory (sync - via GRBM)
 119                  * 2 - gl2
 120                  * 3 - gds
 121                  * 4 - reserved
 122                  * 5 - memory (async - direct)
 123                  */
 124 #define         WR_ONE_ADDR                             (1 << 16)
 125 #define         WR_CONFIRM                              (1 << 20)
 126 #define         WRITE_DATA_CACHE_POLICY(x)              ((x) << 25)
 127                 /* 0 - LRU
 128                  * 1 - Stream
 129                  */
 130 #define         WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
 131                 /* 0 - me
 132                  * 1 - pfp
 133                  * 2 - ce
 134                  */
 135 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI               0x38
 136 #define PACKET3_MEM_SEMAPHORE                           0x39
 137 #              define PACKET3_SEM_USE_MAILBOX       (0x1 << 16)
 138 #              define PACKET3_SEM_SEL_SIGNAL_TYPE   (0x1 << 20) /* 0 = increment, 1 = write 1 */
 139 #              define PACKET3_SEM_SEL_SIGNAL        (0x6 << 29)
 140 #              define PACKET3_SEM_SEL_WAIT          (0x7 << 29)
 141 #define PACKET3_WAIT_REG_MEM                            0x3C
 142 #define         WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
 143                 /* 0 - always
 144                  * 1 - <
 145                  * 2 - <=
 146                  * 3 - ==
 147                  * 4 - !=
 148                  * 5 - >=
 149                  * 6 - >
 150                  */
 151 #define         WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
 152                 /* 0 - reg
 153                  * 1 - mem
 154                  */
 155 #define         WAIT_REG_MEM_OPERATION(x)               ((x) << 6)
 156                 /* 0 - wait_reg_mem
 157                  * 1 - wr_wait_wr_reg
 158                  */
 159 #define         WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
 160                 /* 0 - me
 161                  * 1 - pfp
 162                  */
 163 #define PACKET3_INDIRECT_BUFFER                         0x3F
 164 #define         INDIRECT_BUFFER_VALID                   (1 << 23)
 165 #define         INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) << 28)
 166                 /* 0 - LRU
 167                  * 1 - Stream
 168                  * 2 - Bypass
 169                  */
 170 #define     INDIRECT_BUFFER_PRE_ENB(x)           ((x) << 21)
 171 #define     INDIRECT_BUFFER_PRE_RESUME(x)               ((x) << 30)
 172 #define PACKET3_COPY_DATA                               0x40
 173 #define PACKET3_PFP_SYNC_ME                             0x42
 174 #define PACKET3_COND_WRITE                              0x45
 175 #define PACKET3_EVENT_WRITE                             0x46
 176 #define         EVENT_TYPE(x)                           ((x) << 0)
 177 #define         EVENT_INDEX(x)                          ((x) << 8)
 178                 /* 0 - any non-TS event
 179                  * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
 180                  * 2 - SAMPLE_PIPELINESTAT
 181                  * 3 - SAMPLE_STREAMOUTSTAT*
 182                  * 4 - *S_PARTIAL_FLUSH
 183                  */
 184 #define PACKET3_RELEASE_MEM                             0x49
 185 #define         EVENT_TYPE(x)                           ((x) << 0)
 186 #define         EVENT_INDEX(x)                          ((x) << 8)
 187 #define         EOP_TCL1_VOL_ACTION_EN                  (1 << 12)
 188 #define         EOP_TC_VOL_ACTION_EN                    (1 << 13) /* L2 */
 189 #define         EOP_TC_WB_ACTION_EN                     (1 << 15) /* L2 */
 190 #define         EOP_TCL1_ACTION_EN                      (1 << 16)
 191 #define         EOP_TC_ACTION_EN                        (1 << 17) /* L2 */
 192 #define         EOP_TC_NC_ACTION_EN                     (1 << 19)
 193 #define         EOP_TC_MD_ACTION_EN                     (1 << 21) /* L2 metadata */
 194 #define         EOP_EXEC                                (1 << 28) /* For Trailing Fence */
 195
 196 #define         DATA_SEL(x)                             ((x) << 29)
 197                 /* 0 - discard
 198                  * 1 - send low 32bit data
 199                  * 2 - send 64bit data
 200                  * 3 - send 64bit GPU counter value
 201                  * 4 - send 64bit sys counter value
 202                  */
 203 #define         INT_SEL(x)                              ((x) << 24)
 204                 /* 0 - none
 205                  * 1 - interrupt only (DATA_SEL = 0)
 206                  * 2 - interrupt when data write is confirmed
 207                  */
 208 #define         DST_SEL(x)                              ((x) << 16)
 209                 /* 0 - MC
 210                  * 1 - TC/L2
 211                  */
 212
 213
 214
 215 #define PACKET3_PREAMBLE_CNTL                           0x4A
 216 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
 217 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
 218 #define PACKET3_DMA_DATA                                0x50
 219 /* 1. header
 220  * 2. CONTROL
 221  * 3. SRC_ADDR_LO or DATA [31:0]
 222  * 4. SRC_ADDR_HI [31:0]
 223  * 5. DST_ADDR_LO [31:0]
 224  * 6. DST_ADDR_HI [7:0]
 225  * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
 226  */
 227 /* CONTROL */
 228 #              define PACKET3_DMA_DATA_ENGINE(x)     ((x) << 0)
 229                 /* 0 - ME
 230                  * 1 - PFP
 231                  */
 232 #              define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
 233                 /* 0 - LRU
 234                  * 1 - Stream
 235                  */
 236 #              define PACKET3_DMA_DATA_DST_SEL(x)  ((x) << 20)
 237                 /* 0 - DST_ADDR using DAS
 238                  * 1 - GDS
 239                  * 3 - DST_ADDR using L2
 240                  */
 241 #              define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
 242                 /* 0 - LRU
 243                  * 1 - Stream
 244                  */
 245 #              define PACKET3_DMA_DATA_SRC_SEL(x)  ((x) << 29)
 246                 /* 0 - SRC_ADDR using SAS
 247                  * 1 - GDS
 248                  * 2 - DATA
 249                  * 3 - SRC_ADDR using L2
 250                  */
 251 #              define PACKET3_DMA_DATA_CP_SYNC     (1 << 31)
 252 /* COMMAND */
 253 #              define PACKET3_DMA_DATA_CMD_SAS     (1 << 26)
 254                 /* 0 - memory
 255                  * 1 - register
 256                  */
 257 #              define PACKET3_DMA_DATA_CMD_DAS     (1 << 27)
 258                 /* 0 - memory
 259                  * 1 - register
 260                  */
 261 #              define PACKET3_DMA_DATA_CMD_SAIC    (1 << 28)
 262 #              define PACKET3_DMA_DATA_CMD_DAIC    (1 << 29)
 263 #              define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
 264 #define PACKET3_ACQUIRE_MEM                             0x58
 265 /* 1.  HEADER
 266  * 2.  COHER_CNTL [30:0]
 267  * 2.1 ENGINE_SEL [31:31]
 268  * 3.  COHER_SIZE [31:0]
 269  * 4.  COHER_SIZE_HI [7:0]
 270  * 5.  COHER_BASE_LO [31:0]
 271  * 6.  COHER_BASE_HI [23:0]
 272  * 7.  POLL_INTERVAL [15:0]
 273  */
 274 /* COHER_CNTL fields for CP_COHER_CNTL */
 275 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3)
 276 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4)
 277 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5)
 278 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15)
 279 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18)
 280 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22)
 281 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23)
 282 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25)
 283 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26)
 284 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27)
 285 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28)
 286 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29)
 287 #define         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30)
 288 #define PACKET3_REWIND                                  0x59
 289 #define PACKET3_LOAD_UCONFIG_REG                        0x5E
 290 #define PACKET3_LOAD_SH_REG                             0x5F
 291 #define PACKET3_LOAD_CONFIG_REG                         0x60
 292 #define PACKET3_LOAD_CONTEXT_REG                        0x61
 293 #define PACKET3_SET_CONFIG_REG                          0x68
 294 #define         PACKET3_SET_CONFIG_REG_START                    0x00002000
 295 #define         PACKET3_SET_CONFIG_REG_END                      0x00002c00
 296 #define PACKET3_SET_CONTEXT_REG                         0x69
 297 #define         PACKET3_SET_CONTEXT_REG_START                   0x0000a000
 298 #define         PACKET3_SET_CONTEXT_REG_END                     0x0000a400
 299 #define PACKET3_SET_CONTEXT_REG_INDIRECT                0x73
 300 #define PACKET3_SET_SH_REG                              0x76
 301 #define         PACKET3_SET_SH_REG_START                        0x00002c00
 302 #define         PACKET3_SET_SH_REG_END                          0x00003000
 303 #define PACKET3_SET_SH_REG_OFFSET                       0x77
 304 #define PACKET3_SET_QUEUE_REG                           0x78
 305 #define PACKET3_SET_UCONFIG_REG                         0x79
 306 #define         PACKET3_SET_UCONFIG_REG_START                   0x0000c000
 307 #define         PACKET3_SET_UCONFIG_REG_END                     0x0000c400
 308 #define         PACKET3_SET_UCONFIG_REG_INDEX_TYPE              (2 << 28)
 309 #define PACKET3_SCRATCH_RAM_WRITE                       0x7D
 310 #define PACKET3_SCRATCH_RAM_READ                        0x7E
 311 #define PACKET3_LOAD_CONST_RAM                          0x80
 312 #define PACKET3_WRITE_CONST_RAM                         0x81
 313 #define PACKET3_DUMP_CONST_RAM                          0x83
 314 #define PACKET3_INCREMENT_CE_COUNTER                    0x84
 315 #define PACKET3_INCREMENT_DE_COUNTER                    0x85
 316 #define PACKET3_WAIT_ON_CE_COUNTER                      0x86
 317 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF                 0x88
 318 #define PACKET3_SWITCH_BUFFER                           0x8B
 319 #define PACKET3_FRAME_CONTROL                           0x90
 320 #                       define FRAME_TMZ        (1 << 0)
 321 #                       define FRAME_CMD(x) ((x) << 28)
 322                         /*
 323                          * x=0: tmz_begin
 324                          * x=1: tmz_end
 325                          */
 326
 327 #define PACKET3_INVALIDATE_TLBS                         0x98
 328 #              define PACKET3_INVALIDATE_TLBS_DST_SEL(x)     ((x) << 0)
 329 #              define PACKET3_INVALIDATE_TLBS_ALL_HUB(x)     ((x) << 4)
 330 #              define PACKET3_INVALIDATE_TLBS_PASID(x)       ((x) << 5)
 331 #              define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x)  ((x) << 29)
 332 #define PACKET3_SET_RESOURCES                           0xA0
 333 /* 1. header
 334  * 2. CONTROL
 335  * 3. QUEUE_MASK_LO [31:0]
 336  * 4. QUEUE_MASK_HI [31:0]
 337  * 5. GWS_MASK_LO [31:0]
 338  * 6. GWS_MASK_HI [31:0]
 339  * 7. OAC_MASK [15:0]
 340  * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
 341  */
 342 #              define PACKET3_SET_RESOURCES_VMID_MASK(x)     ((x) << 0)
 343 #              define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
 344 #              define PACKET3_SET_RESOURCES_QUEUE_TYPE(x)    ((x) << 29)
 345 #define PACKET3_MAP_QUEUES                              0xA2
 346 /* 1. header
 347  * 2. CONTROL
 348  * 3. CONTROL2
 349  * 4. MQD_ADDR_LO [31:0]
 350  * 5. MQD_ADDR_HI [31:0]
 351  * 6. WPTR_ADDR_LO [31:0]
 352  * 7. WPTR_ADDR_HI [31:0]
 353  */
 354 /* CONTROL */
 355 #              define PACKET3_MAP_QUEUES_QUEUE_SEL(x)       ((x) << 4)
 356 #              define PACKET3_MAP_QUEUES_VMID(x)            ((x) << 8)
 357 #              define PACKET3_MAP_QUEUES_QUEUE(x)           ((x) << 13)
 358 #              define PACKET3_MAP_QUEUES_PIPE(x)            ((x) << 16)
 359 #              define PACKET3_MAP_QUEUES_ME(x)              ((x) << 18)
 360 #              define PACKET3_MAP_QUEUES_QUEUE_TYPE(x)      ((x) << 21)
 361 #              define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x)    ((x) << 24)
 362 #              define PACKET3_MAP_QUEUES_ENGINE_SEL(x)      ((x) << 26)
 363 #              define PACKET3_MAP_QUEUES_NUM_QUEUES(x)      ((x) << 29)
 364 /* CONTROL2 */
 365 #              define PACKET3_MAP_QUEUES_CHECK_DISABLE(x)   ((x) << 1)
 366 #              define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
 367 #define PACKET3_UNMAP_QUEUES                            0xA3
 368 /* 1. header
 369  * 2. CONTROL
 370  * 3. CONTROL2
 371  * 4. CONTROL3
 372  * 5. CONTROL4
 373  * 6. CONTROL5
 374  */
 375 /* CONTROL */
 376 #              define PACKET3_UNMAP_QUEUES_ACTION(x)           ((x) << 0)
 377                 /* 0 - PREEMPT_QUEUES
 378                  * 1 - RESET_QUEUES
 379                  * 2 - DISABLE_PROCESS_QUEUES
 380                  * 3 - PREEMPT_QUEUES_NO_UNMAP
 381                  */
 382 #              define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x)        ((x) << 4)
 383 #              define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x)       ((x) << 26)
 384 #              define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x)       ((x) << 29)
 385 /* CONTROL2a */
 386 #              define PACKET3_UNMAP_QUEUES_PASID(x)            ((x) << 0)
 387 /* CONTROL2b */
 388 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
 389 /* CONTROL3a */
 390 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
 391 /* CONTROL3b */
 392 #              define PACKET3_UNMAP_QUEUES_RB_WPTR(x)          ((x) << 0)
 393 /* CONTROL4 */
 394 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
 395 /* CONTROL5 */
 396 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
 397 #define PACKET3_QUERY_STATUS                            0xA4
 398 /* 1. header
 399  * 2. CONTROL
 400  * 3. CONTROL2
 401  * 4. ADDR_LO [31:0]
 402  * 5. ADDR_HI [31:0]
 403  * 6. DATA_LO [31:0]
 404  * 7. DATA_HI [31:0]
 405  */
 406 /* CONTROL */
 407 #              define PACKET3_QUERY_STATUS_CONTEXT_ID(x)       ((x) << 0)
 408 #              define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x)    ((x) << 28)
 409 #              define PACKET3_QUERY_STATUS_COMMAND(x)          ((x) << 30)
 410 /* CONTROL2a */
 411 #              define PACKET3_QUERY_STATUS_PASID(x)            ((x) << 0)
 412 /* CONTROL2b */
 413 #              define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x)  ((x) << 2)
 414 #              define PACKET3_QUERY_STATUS_ENG_SEL(x)          ((x) << 25)
 415
 416 #define PACKET3_RUN_CLEANER_SHADER                      0xD2
 417 /* 1. header
 418  * 2. RESERVED [31:0]
 419  */
 420
 421 #define VCE_CMD_NO_OP           0x00000000
 422 #define VCE_CMD_END             0x00000001
 423 #define VCE_CMD_IB              0x00000002
 424 #define VCE_CMD_FENCE           0x00000003
 425 #define VCE_CMD_TRAP            0x00000004
 426 #define VCE_CMD_IB_AUTO         0x00000005
 427 #define VCE_CMD_SEMAPHORE       0x00000006
 428
 429 #define VCE_CMD_IB_VM           0x00000102
 430 #define VCE_CMD_WAIT_GE         0x00000106
 431 #define VCE_CMD_UPDATE_PTB      0x00000107
 432 #define VCE_CMD_FLUSH_TLB       0x00000108
 433 #define VCE_CMD_REG_WRITE       0x00000109
 434 #define VCE_CMD_REG_WAIT        0x0000010a
 435
 436 #define HEVC_ENC_CMD_NO_OP              0x00000000
 437 #define HEVC_ENC_CMD_END                0x00000001
 438 #define HEVC_ENC_CMD_FENCE              0x00000003
 439 #define HEVC_ENC_CMD_TRAP               0x00000004
 440 #define HEVC_ENC_CMD_IB_VM              0x00000102
 441 #define HEVC_ENC_CMD_REG_WRITE          0x00000109
 442 #define HEVC_ENC_CMD_REG_WAIT           0x0000010a
 443
 444 #endif