drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "hdp_v6_0.h"
  26
  27 #include "hdp/hdp_6_0_0_offset.h"
  28 #include "hdp/hdp_6_0_0_sh_mask.h"
  29 #include <uapi/linux/kfd_ioctl.h>
  30
  31 #define regHDP_CLK_CNTL_V6_1    0xd5
  32 #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
  33
  34 static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
  35                                 struct amdgpu_ring *ring)
  36 {
  37         if (!ring || !ring->funcs->emit_wreg) {
  38                 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  39                 RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
  40         } else {
  41                 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  42         }
  43 }
  44
  45 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
  46                                          bool enable)
  47 {
  48         uint32_t hdp_clk_cntl;
  49         uint32_t hdp_mem_pwr_cntl;
  50
  51         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
  52                                 AMD_CG_SUPPORT_HDP_DS |
  53                                 AMD_CG_SUPPORT_HDP_SD)))
  54                 return;
  55
  56         if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
  57                 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1);
  58         else
  59                 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
  60         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
  61
  62         /* Before doing clock/power mode switch,
  63          * forced on IPH & RC clock */
  64         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
  65                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
  66         if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
  67                 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
  68         else
  69                 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
  70
  71         /* disable clock and power gating before any changing */
  72         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  73                                          ATOMIC_MEM_POWER_CTRL_EN, 0);
  74         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  75                                          ATOMIC_MEM_POWER_LS_EN, 0);
  76         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  77                                          ATOMIC_MEM_POWER_DS_EN, 0);
  78         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  79                                          ATOMIC_MEM_POWER_SD_EN, 0);
  80         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  81                                          RC_MEM_POWER_CTRL_EN, 0);
  82         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  83                                          RC_MEM_POWER_LS_EN, 0);
  84         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  85                                          RC_MEM_POWER_DS_EN, 0);
  86         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  87                                          RC_MEM_POWER_SD_EN, 0);
  88         WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
  89
  90         /* Already disabled above. The actions below are for "enabled" only */
  91         if (enable) {
  92                 /* only one clock gating mode (LS/DS/SD) can be enabled */
  93                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
  94                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
  95                                                          HDP_MEM_POWER_CTRL,
  96                                                          ATOMIC_MEM_POWER_SD_EN, 1);
  97                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
  98                                                          HDP_MEM_POWER_CTRL,
  99                                                          RC_MEM_POWER_SD_EN, 1);
 100                 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 101                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 102                                                          HDP_MEM_POWER_CTRL,
 103                                                          ATOMIC_MEM_POWER_LS_EN, 1);
 104                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 105                                                          HDP_MEM_POWER_CTRL,
 106                                                          RC_MEM_POWER_LS_EN, 1);
 107                 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
 108                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 109                                                          HDP_MEM_POWER_CTRL,
 110                                                          ATOMIC_MEM_POWER_DS_EN, 1);
 111                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 112                                                          HDP_MEM_POWER_CTRL,
 113                                                          RC_MEM_POWER_DS_EN, 1);
 114                 }
 115
 116                 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
 117                  * be set for SRAM LS/DS/SD */
 118                 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
 119                                       AMD_CG_SUPPORT_HDP_SD)) {
 120                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 121                                                          ATOMIC_MEM_POWER_CTRL_EN, 1);
 122                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 123                                                          RC_MEM_POWER_CTRL_EN, 1);
 124                         WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 125                 }
 126         }
 127
 128         /* disable IPH & RC clock override after clock/power mode changing */
 129         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 130                                      RC_MEM_CLK_SOFT_OVERRIDE, 0);
 131         if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
 132                 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
 133         else
 134                 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
 135 }
 136
 137 static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
 138                                             u64 *flags)
 139 {
 140         uint32_t tmp;
 141
 142         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
 143         tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
 144         if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
 145                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 146         else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
 147                 *flags |= AMD_CG_SUPPORT_HDP_DS;
 148         else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
 149                 *flags |= AMD_CG_SUPPORT_HDP_SD;
 150 }
 151
 152 const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
 153         .flush_hdp = hdp_v6_0_flush_hdp,
 154         .update_clock_gating = hdp_v6_0_update_clock_gating,
 155         .get_clock_gating_state = hdp_v6_0_get_clockgating_state,
 156 };