drivers/gpu/drm/mediatek/mtk_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Jie Qiu <[email protected]>
   5  */
   6
   7 #include <linux/arm-smccc.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/hdmi.h>
  11 #include <linux/i2c.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/module.h>
  16 #include <linux/mutex.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/of.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/phy/phy.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24
  25 #include <sound/hdmi-codec.h>
  26
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_bridge.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_print.h>
  32 #include <drm/drm_probe_helper.h>
  33
  34 #include "mtk_cec.h"
  35 #include "mtk_hdmi.h"
  36 #include "mtk_hdmi_regs.h"
  37
  38 #define NCTS_BYTES      7
  39
  40 enum mtk_hdmi_clk_id {
  41         MTK_HDMI_CLK_HDMI_PIXEL,
  42         MTK_HDMI_CLK_HDMI_PLL,
  43         MTK_HDMI_CLK_AUD_BCLK,
  44         MTK_HDMI_CLK_AUD_SPDIF,
  45         MTK_HDMI_CLK_COUNT
  46 };
  47
  48 enum hdmi_aud_input_type {
  49         HDMI_AUD_INPUT_I2S = 0,
  50         HDMI_AUD_INPUT_SPDIF,
  51 };
  52
  53 enum hdmi_aud_i2s_fmt {
  54         HDMI_I2S_MODE_RJT_24BIT = 0,
  55         HDMI_I2S_MODE_RJT_16BIT,
  56         HDMI_I2S_MODE_LJT_24BIT,
  57         HDMI_I2S_MODE_LJT_16BIT,
  58         HDMI_I2S_MODE_I2S_24BIT,
  59         HDMI_I2S_MODE_I2S_16BIT
  60 };
  61
  62 enum hdmi_aud_mclk {
  63         HDMI_AUD_MCLK_128FS,
  64         HDMI_AUD_MCLK_192FS,
  65         HDMI_AUD_MCLK_256FS,
  66         HDMI_AUD_MCLK_384FS,
  67         HDMI_AUD_MCLK_512FS,
  68         HDMI_AUD_MCLK_768FS,
  69         HDMI_AUD_MCLK_1152FS,
  70 };
  71
  72 enum hdmi_aud_channel_type {
  73         HDMI_AUD_CHAN_TYPE_1_0 = 0,
  74         HDMI_AUD_CHAN_TYPE_1_1,
  75         HDMI_AUD_CHAN_TYPE_2_0,
  76         HDMI_AUD_CHAN_TYPE_2_1,
  77         HDMI_AUD_CHAN_TYPE_3_0,
  78         HDMI_AUD_CHAN_TYPE_3_1,
  79         HDMI_AUD_CHAN_TYPE_4_0,
  80         HDMI_AUD_CHAN_TYPE_4_1,
  81         HDMI_AUD_CHAN_TYPE_5_0,
  82         HDMI_AUD_CHAN_TYPE_5_1,
  83         HDMI_AUD_CHAN_TYPE_6_0,
  84         HDMI_AUD_CHAN_TYPE_6_1,
  85         HDMI_AUD_CHAN_TYPE_7_0,
  86         HDMI_AUD_CHAN_TYPE_7_1,
  87         HDMI_AUD_CHAN_TYPE_3_0_LRS,
  88         HDMI_AUD_CHAN_TYPE_3_1_LRS,
  89         HDMI_AUD_CHAN_TYPE_4_0_CLRS,
  90         HDMI_AUD_CHAN_TYPE_4_1_CLRS,
  91         HDMI_AUD_CHAN_TYPE_6_1_CS,
  92         HDMI_AUD_CHAN_TYPE_6_1_CH,
  93         HDMI_AUD_CHAN_TYPE_6_1_OH,
  94         HDMI_AUD_CHAN_TYPE_6_1_CHR,
  95         HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
  96         HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
  97         HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
  98         HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
  99         HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
 100         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
 101         HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
 102         HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
 103         HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
 104         HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
 105         HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
 106         HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
 107         HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
 108         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
 109         HDMI_AUD_CHAN_TYPE_6_0_CS,
 110         HDMI_AUD_CHAN_TYPE_6_0_CH,
 111         HDMI_AUD_CHAN_TYPE_6_0_OH,
 112         HDMI_AUD_CHAN_TYPE_6_0_CHR,
 113         HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
 114         HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
 115         HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
 116         HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
 117         HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
 118         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
 119         HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
 120         HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
 121         HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
 122         HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
 123         HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
 124         HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
 125         HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
 126         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
 127         HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
 128         HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
 129 };
 130
 131 enum hdmi_aud_channel_swap_type {
 132         HDMI_AUD_SWAP_LR,
 133         HDMI_AUD_SWAP_LFE_CC,
 134         HDMI_AUD_SWAP_LSRS,
 135         HDMI_AUD_SWAP_RLS_RRS,
 136         HDMI_AUD_SWAP_LR_STATUS,
 137 };
 138
 139 struct hdmi_audio_param {
 140         enum hdmi_audio_coding_type aud_codec;
 141         enum hdmi_audio_sample_size aud_sampe_size;
 142         enum hdmi_aud_input_type aud_input_type;
 143         enum hdmi_aud_i2s_fmt aud_i2s_fmt;
 144         enum hdmi_aud_mclk aud_mclk;
 145         enum hdmi_aud_channel_type aud_input_chan_type;
 146         struct hdmi_codec_params codec_params;
 147 };
 148
 149 struct mtk_hdmi_conf {
 150         bool tz_disabled;
 151 };
 152
 153 struct mtk_hdmi {
 154         struct drm_bridge bridge;
 155         struct drm_bridge *next_bridge;
 156         struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
 157         struct device *dev;
 158         const struct mtk_hdmi_conf *conf;
 159         struct phy *phy;
 160         struct device *cec_dev;
 161         struct i2c_adapter *ddc_adpt;
 162         struct clk *clk[MTK_HDMI_CLK_COUNT];
 163         struct drm_display_mode mode;
 164         bool dvi_mode;
 165         u32 min_clock;
 166         u32 max_clock;
 167         u32 max_hdisplay;
 168         u32 max_vdisplay;
 169         u32 ibias;
 170         u32 ibias_up;
 171         struct regmap *sys_regmap;
 172         unsigned int sys_offset;
 173         void __iomem *regs;
 174         enum hdmi_colorspace csp;
 175         struct hdmi_audio_param aud_param;
 176         bool audio_enable;
 177         bool powered;
 178         bool enabled;
 179         hdmi_codec_plugged_cb plugged_cb;
 180         struct device *codec_dev;
 181         struct mutex update_plugged_status_lock;
 182 };
 183
 184 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 185 {
 186         return container_of(b, struct mtk_hdmi, bridge);
 187 }
 188
 189 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
 190 {
 191         return readl(hdmi->regs + offset);
 192 }
 193
 194 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
 195 {
 196         writel(val, hdmi->regs + offset);
 197 }
 198
 199 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 200 {
 201         void __iomem *reg = hdmi->regs + offset;
 202         u32 tmp;
 203
 204         tmp = readl(reg);
 205         tmp &= ~bits;
 206         writel(tmp, reg);
 207 }
 208
 209 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 210 {
 211         void __iomem *reg = hdmi->regs + offset;
 212         u32 tmp;
 213
 214         tmp = readl(reg);
 215         tmp |= bits;
 216         writel(tmp, reg);
 217 }
 218
 219 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
 220 {
 221         void __iomem *reg = hdmi->regs + offset;
 222         u32 tmp;
 223
 224         tmp = readl(reg);
 225         tmp = (tmp & ~mask) | (val & mask);
 226         writel(tmp, reg);
 227 }
 228
 229 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 230 {
 231         mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
 232                       VIDEO_SOURCE_SEL);
 233 }
 234
 235 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 236 {
 237         struct arm_smccc_res res;
 238
 239         /*
 240          * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
 241          * output. This bit can only be controlled in ARM supervisor mode.
 242          * The ARM trusted firmware provides an API for the HDMI driver to set
 243          * this control bit to enable HDMI output in supervisor mode.
 244          */
 245         if (hdmi->conf && hdmi->conf->tz_disabled)
 246                 regmap_update_bits(hdmi->sys_regmap,
 247                                    hdmi->sys_offset + HDMI_SYS_CFG20,
 248                                    0x80008005, enable ? 0x80000005 : 0x8000);
 249         else
 250                 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
 251                               0x80000000, 0, 0, 0, 0, 0, &res);
 252
 253         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 254                            HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
 255         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 256                            HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
 257 }
 258
 259 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
 260 {
 261         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 262                            HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
 263 }
 264
 265 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
 266 {
 267         mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 268 }
 269
 270 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
 271 {
 272         mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 273 }
 274
 275 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
 276 {
 277         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 278                            HDMI_RST, HDMI_RST);
 279         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 280                            HDMI_RST, 0);
 281         mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
 282         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 283                            ANLG_ON, ANLG_ON);
 284 }
 285
 286 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
 287 {
 288         mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
 289                       CFG2_NOTICE_EN);
 290 }
 291
 292 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
 293 {
 294         mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
 295 }
 296
 297 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
 298 {
 299         mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
 300 }
 301
 302 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
 303                                         u8 len)
 304 {
 305         u32 ctrl_reg = GRL_CTRL;
 306         int i;
 307         u8 *frame_data;
 308         enum hdmi_infoframe_type frame_type;
 309         u8 frame_ver;
 310         u8 frame_len;
 311         u8 checksum;
 312         int ctrl_frame_en = 0;
 313
 314         frame_type = *buffer++;
 315         frame_ver = *buffer++;
 316         frame_len = *buffer++;
 317         checksum = *buffer++;
 318         frame_data = buffer;
 319
 320         dev_dbg(hdmi->dev,
 321                 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
 322                 frame_type, frame_ver, frame_len, checksum);
 323
 324         switch (frame_type) {
 325         case HDMI_INFOFRAME_TYPE_AVI:
 326                 ctrl_frame_en = CTRL_AVI_EN;
 327                 ctrl_reg = GRL_CTRL;
 328                 break;
 329         case HDMI_INFOFRAME_TYPE_SPD:
 330                 ctrl_frame_en = CTRL_SPD_EN;
 331                 ctrl_reg = GRL_CTRL;
 332                 break;
 333         case HDMI_INFOFRAME_TYPE_AUDIO:
 334                 ctrl_frame_en = CTRL_AUDIO_EN;
 335                 ctrl_reg = GRL_CTRL;
 336                 break;
 337         case HDMI_INFOFRAME_TYPE_VENDOR:
 338                 ctrl_frame_en = VS_EN;
 339                 ctrl_reg = GRL_ACP_ISRC_CTRL;
 340                 break;
 341         default:
 342                 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
 343                 return;
 344         }
 345         mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
 346         mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
 347         mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
 348         mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
 349
 350         mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
 351         for (i = 0; i < frame_len; i++)
 352                 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
 353
 354         mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
 355 }
 356
 357 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
 358 {
 359         mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
 360                       AUDIO_PACKET_OFF);
 361 }
 362
 363 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
 364 {
 365         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 366                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
 367         usleep_range(2000, 4000);
 368         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 369                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
 370 }
 371
 372 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
 373 {
 374         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 375                            DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
 376                            COLOR_8BIT_MODE);
 377 }
 378
 379 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
 380 {
 381         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 382         usleep_range(2000, 4000);
 383         mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 384 }
 385
 386 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
 387 {
 388         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
 389                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 390         usleep_range(2000, 4000);
 391         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
 392                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 393 }
 394
 395 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
 396 {
 397         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
 398                       CTS_CTRL_SOFT);
 399 }
 400
 401 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
 402                                                bool enable)
 403 {
 404         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
 405                       NCTS_WRI_ANYTIME);
 406 }
 407
 408 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
 409                                      struct drm_display_mode *mode)
 410 {
 411         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
 412
 413         if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
 414             mode->clock == 74250 &&
 415             mode->vdisplay == 1080)
 416                 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 417         else
 418                 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 419 }
 420
 421 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
 422                                         enum hdmi_aud_channel_swap_type swap)
 423 {
 424         u8 swap_bit;
 425
 426         switch (swap) {
 427         case HDMI_AUD_SWAP_LR:
 428                 swap_bit = LR_SWAP;
 429                 break;
 430         case HDMI_AUD_SWAP_LFE_CC:
 431                 swap_bit = LFE_CC_SWAP;
 432                 break;
 433         case HDMI_AUD_SWAP_LSRS:
 434                 swap_bit = LSRS_SWAP;
 435                 break;
 436         case HDMI_AUD_SWAP_RLS_RRS:
 437                 swap_bit = RLS_RRS_SWAP;
 438                 break;
 439         case HDMI_AUD_SWAP_LR_STATUS:
 440                 swap_bit = LR_STATUS_SWAP;
 441                 break;
 442         default:
 443                 swap_bit = LFE_CC_SWAP;
 444                 break;
 445         }
 446         mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
 447 }
 448
 449 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
 450                                         enum hdmi_audio_sample_size bit_num)
 451 {
 452         u32 val;
 453
 454         switch (bit_num) {
 455         case HDMI_AUDIO_SAMPLE_SIZE_16:
 456                 val = AOUT_16BIT;
 457                 break;
 458         case HDMI_AUDIO_SAMPLE_SIZE_20:
 459                 val = AOUT_20BIT;
 460                 break;
 461         case HDMI_AUDIO_SAMPLE_SIZE_24:
 462         case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
 463                 val = AOUT_24BIT;
 464                 break;
 465         }
 466
 467         mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
 468 }
 469
 470 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 471                                         enum hdmi_aud_i2s_fmt i2s_fmt)
 472 {
 473         u32 val;
 474
 475         val = mtk_hdmi_read(hdmi, GRL_CFG0);
 476         val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 477
 478         switch (i2s_fmt) {
 479         case HDMI_I2S_MODE_RJT_24BIT:
 480                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
 481                 break;
 482         case HDMI_I2S_MODE_RJT_16BIT:
 483                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
 484                 break;
 485         case HDMI_I2S_MODE_LJT_24BIT:
 486         default:
 487                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
 488                 break;
 489         case HDMI_I2S_MODE_LJT_16BIT:
 490                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
 491                 break;
 492         case HDMI_I2S_MODE_I2S_24BIT:
 493                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
 494                 break;
 495         case HDMI_I2S_MODE_I2S_16BIT:
 496                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
 497                 break;
 498         }
 499         mtk_hdmi_write(hdmi, GRL_CFG0, val);
 500 }
 501
 502 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
 503 {
 504         const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
 505         u8 val;
 506
 507         /* Disable high bitrate, set DST packet normal/double */
 508         mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
 509
 510         if (dst)
 511                 val = DST_NORMAL_DOUBLE | SACD_DST;
 512         else
 513                 val = 0;
 514
 515         mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
 516 }
 517
 518 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
 519                                         enum hdmi_aud_channel_type channel_type,
 520                                         u8 channel_count)
 521 {
 522         unsigned int ch_switch;
 523         u8 i2s_uv;
 524
 525         ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
 526                     CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
 527                     CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
 528                     CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
 529
 530         if (channel_count == 2) {
 531                 i2s_uv = I2S_UV_CH_EN(0);
 532         } else if (channel_count == 3 || channel_count == 4) {
 533                 if (channel_count == 4 &&
 534                     (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
 535                     channel_type == HDMI_AUD_CHAN_TYPE_4_0))
 536                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
 537                 else
 538                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
 539         } else if (channel_count == 6 || channel_count == 5) {
 540                 if (channel_count == 6 &&
 541                     channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
 542                     channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
 543                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 544                                  I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 545                 } else {
 546                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
 547                                  I2S_UV_CH_EN(0);
 548                 }
 549         } else if (channel_count == 8 || channel_count == 7) {
 550                 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 551                          I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 552         } else {
 553                 i2s_uv = I2S_UV_CH_EN(0);
 554         }
 555
 556         mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
 557         mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
 558         mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
 559         mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
 560 }
 561
 562 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 563                                            enum hdmi_aud_input_type input_type)
 564 {
 565         u32 val;
 566
 567         val = mtk_hdmi_read(hdmi, GRL_CFG1);
 568         if (input_type == HDMI_AUD_INPUT_I2S &&
 569             (val & CFG1_SPDIF) == CFG1_SPDIF) {
 570                 val &= ~CFG1_SPDIF;
 571         } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
 572                 (val & CFG1_SPDIF) == 0) {
 573                 val |= CFG1_SPDIF;
 574         }
 575         mtk_hdmi_write(hdmi, GRL_CFG1, val);
 576 }
 577
 578 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
 579                                                u8 *channel_status)
 580 {
 581         int i;
 582
 583         for (i = 0; i < 5; i++) {
 584                 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
 585                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
 586                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
 587         }
 588         for (; i < 24; i++) {
 589                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
 590                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
 591         }
 592 }
 593
 594 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 595 {
 596         u32 val;
 597
 598         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 599         if (val & MIX_CTRL_SRC_EN) {
 600                 val &= ~MIX_CTRL_SRC_EN;
 601                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 602                 usleep_range(255, 512);
 603                 val |= MIX_CTRL_SRC_EN;
 604                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 605         }
 606 }
 607
 608 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 609 {
 610         u32 val;
 611
 612         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 613         val &= ~MIX_CTRL_SRC_EN;
 614         mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 615         mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
 616 }
 617
 618 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 619                                      enum hdmi_aud_mclk mclk)
 620 {
 621         u32 val;
 622
 623         val = mtk_hdmi_read(hdmi, GRL_CFG5);
 624         val &= CFG5_CD_RATIO_MASK;
 625
 626         switch (mclk) {
 627         case HDMI_AUD_MCLK_128FS:
 628                 val |= CFG5_FS128;
 629                 break;
 630         case HDMI_AUD_MCLK_256FS:
 631                 val |= CFG5_FS256;
 632                 break;
 633         case HDMI_AUD_MCLK_384FS:
 634                 val |= CFG5_FS384;
 635                 break;
 636         case HDMI_AUD_MCLK_512FS:
 637                 val |= CFG5_FS512;
 638                 break;
 639         case HDMI_AUD_MCLK_768FS:
 640                 val |= CFG5_FS768;
 641                 break;
 642         default:
 643                 val |= CFG5_FS256;
 644                 break;
 645         }
 646         mtk_hdmi_write(hdmi, GRL_CFG5, val);
 647 }
 648
 649 struct hdmi_acr_n {
 650         unsigned int clock;
 651         unsigned int n[3];
 652 };
 653
 654 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
 655 static const struct hdmi_acr_n hdmi_rec_n_table[] = {
 656         /* Clock, N: 32kHz 44.1kHz 48kHz */
 657         {  25175, {  4576,  7007,  6864 } },
 658         {  74176, { 11648, 17836, 11648 } },
 659         { 148352, { 11648,  8918,  5824 } },
 660         { 296703, {  5824,  4459,  5824 } },
 661         { 297000, {  3072,  4704,  5120 } },
 662         {      0, {  4096,  6272,  6144 } }, /* all other TMDS clocks */
 663 };
 664
 665 /**
 666  * hdmi_recommended_n() - Return N value recommended by HDMI specification
 667  * @freq: audio sample rate in Hz
 668  * @clock: rounded TMDS clock in kHz
 669  */
 670 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
 671 {
 672         const struct hdmi_acr_n *recommended;
 673         unsigned int i;
 674
 675         for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
 676                 if (clock == hdmi_rec_n_table[i].clock)
 677                         break;
 678         }
 679         recommended = hdmi_rec_n_table + i;
 680
 681         switch (freq) {
 682         case 32000:
 683                 return recommended->n[0];
 684         case 44100:
 685                 return recommended->n[1];
 686         case 48000:
 687                 return recommended->n[2];
 688         case 88200:
 689                 return recommended->n[1] * 2;
 690         case 96000:
 691                 return recommended->n[2] * 2;
 692         case 176400:
 693                 return recommended->n[1] * 4;
 694         case 192000:
 695                 return recommended->n[2] * 4;
 696         default:
 697                 return (128 * freq) / 1000;
 698         }
 699 }
 700
 701 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
 702 {
 703         switch (clock) {
 704         case 25175:
 705                 return 25174825;        /* 25.2/1.001 MHz */
 706         case 74176:
 707                 return 74175824;        /* 74.25/1.001 MHz */
 708         case 148352:
 709                 return 148351648;       /* 148.5/1.001 MHz */
 710         case 296703:
 711                 return 296703297;       /* 297/1.001 MHz */
 712         default:
 713                 return clock * 1000;
 714         }
 715 }
 716
 717 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
 718                                       unsigned int tmds_clock, unsigned int n)
 719 {
 720         return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
 721                                      128 * audio_sample_rate);
 722 }
 723
 724 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
 725                                     unsigned int cts)
 726 {
 727         unsigned char val[NCTS_BYTES];
 728         int i;
 729
 730         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 731         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 732         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 733         memset(val, 0, sizeof(val));
 734
 735         val[0] = (cts >> 24) & 0xff;
 736         val[1] = (cts >> 16) & 0xff;
 737         val[2] = (cts >> 8) & 0xff;
 738         val[3] = cts & 0xff;
 739
 740         val[4] = (n >> 16) & 0xff;
 741         val[5] = (n >> 8) & 0xff;
 742         val[6] = n & 0xff;
 743
 744         for (i = 0; i < NCTS_BYTES; i++)
 745                 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
 746 }
 747
 748 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
 749                                      unsigned int sample_rate,
 750                                      unsigned int clock)
 751 {
 752         unsigned int n, cts;
 753
 754         n = hdmi_recommended_n(sample_rate, clock);
 755         cts = hdmi_expected_cts(sample_rate, clock, n);
 756
 757         dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
 758                 __func__, sample_rate, clock, n, cts);
 759
 760         mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
 761                       AUDIO_I2S_NCTS_SEL);
 762         do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
 763 }
 764
 765 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
 766 {
 767         switch (channel_type) {
 768         case HDMI_AUD_CHAN_TYPE_1_0:
 769         case HDMI_AUD_CHAN_TYPE_1_1:
 770         case HDMI_AUD_CHAN_TYPE_2_0:
 771                 return 2;
 772         case HDMI_AUD_CHAN_TYPE_2_1:
 773         case HDMI_AUD_CHAN_TYPE_3_0:
 774                 return 3;
 775         case HDMI_AUD_CHAN_TYPE_3_1:
 776         case HDMI_AUD_CHAN_TYPE_4_0:
 777         case HDMI_AUD_CHAN_TYPE_3_0_LRS:
 778                 return 4;
 779         case HDMI_AUD_CHAN_TYPE_4_1:
 780         case HDMI_AUD_CHAN_TYPE_5_0:
 781         case HDMI_AUD_CHAN_TYPE_3_1_LRS:
 782         case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
 783                 return 5;
 784         case HDMI_AUD_CHAN_TYPE_5_1:
 785         case HDMI_AUD_CHAN_TYPE_6_0:
 786         case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
 787         case HDMI_AUD_CHAN_TYPE_6_0_CS:
 788         case HDMI_AUD_CHAN_TYPE_6_0_CH:
 789         case HDMI_AUD_CHAN_TYPE_6_0_OH:
 790         case HDMI_AUD_CHAN_TYPE_6_0_CHR:
 791                 return 6;
 792         case HDMI_AUD_CHAN_TYPE_6_1:
 793         case HDMI_AUD_CHAN_TYPE_6_1_CS:
 794         case HDMI_AUD_CHAN_TYPE_6_1_CH:
 795         case HDMI_AUD_CHAN_TYPE_6_1_OH:
 796         case HDMI_AUD_CHAN_TYPE_6_1_CHR:
 797         case HDMI_AUD_CHAN_TYPE_7_0:
 798         case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
 799         case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
 800         case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
 801         case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
 802         case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
 803         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
 804         case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
 805         case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
 806         case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
 807         case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
 808         case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
 809         case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
 810         case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
 811         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
 812         case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
 813                 return 7;
 814         case HDMI_AUD_CHAN_TYPE_7_1:
 815         case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
 816         case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
 817         case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
 818         case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
 819         case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
 820         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
 821         case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
 822         case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
 823         case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
 824         case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
 825         case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
 826         case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
 827         case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
 828         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
 829                 return 8;
 830         default:
 831                 return 2;
 832         }
 833 }
 834
 835 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
 836 {
 837         unsigned long rate;
 838         int ret;
 839
 840         /* The DPI driver already should have set TVDPLL to the correct rate */
 841         ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
 842         if (ret) {
 843                 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
 844                         ret);
 845                 return ret;
 846         }
 847
 848         rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
 849
 850         if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
 851                 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
 852                          rate);
 853         else
 854                 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
 855
 856         mtk_hdmi_hw_config_sys(hdmi);
 857         mtk_hdmi_hw_set_deep_color_mode(hdmi);
 858         return 0;
 859 }
 860
 861 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
 862                                             struct drm_display_mode *mode)
 863 {
 864         mtk_hdmi_hw_reset(hdmi);
 865         mtk_hdmi_hw_enable_notice(hdmi, true);
 866         mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
 867         mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
 868         mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
 869
 870         mtk_hdmi_hw_msic_setting(hdmi, mode);
 871 }
 872
 873
 874 static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
 875 {
 876         enum hdmi_aud_channel_type chan_type;
 877         u8 chan_count;
 878         bool dst;
 879
 880         mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
 881         mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
 882
 883         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
 884             hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
 885                 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 886         } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
 887                 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
 888         }
 889
 890         mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
 891         mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 892
 893         dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
 894                (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
 895         mtk_hdmi_hw_audio_config(hdmi, dst);
 896
 897         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
 898                 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
 899         else
 900                 chan_type = hdmi->aud_param.aud_input_chan_type;
 901         chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
 902         mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
 903         mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
 904 }
 905
 906 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
 907                                 struct drm_display_mode *display_mode)
 908 {
 909         unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
 910
 911         mtk_hdmi_hw_ncts_enable(hdmi, false);
 912         mtk_hdmi_hw_aud_src_disable(hdmi);
 913         mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
 914
 915         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
 916                 switch (sample_rate) {
 917                 case 32000:
 918                 case 44100:
 919                 case 48000:
 920                 case 88200:
 921                 case 96000:
 922                         break;
 923                 default:
 924                         return -EINVAL;
 925                 }
 926                 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
 927         } else {
 928                 switch (sample_rate) {
 929                 case 32000:
 930                 case 44100:
 931                 case 48000:
 932                         break;
 933                 default:
 934                         return -EINVAL;
 935                 }
 936                 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
 937         }
 938
 939         mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
 940
 941         mtk_hdmi_hw_aud_src_reenable(hdmi);
 942         return 0;
 943 }
 944
 945 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
 946                                       struct drm_display_mode *display_mode)
 947 {
 948         mtk_hdmi_hw_aud_mute(hdmi);
 949         mtk_hdmi_hw_send_aud_packet(hdmi, false);
 950
 951         mtk_hdmi_aud_set_input(hdmi);
 952         mtk_hdmi_aud_set_src(hdmi, display_mode);
 953         mtk_hdmi_hw_aud_set_channel_status(hdmi,
 954                         hdmi->aud_param.codec_params.iec.status);
 955
 956         usleep_range(50, 100);
 957
 958         mtk_hdmi_hw_ncts_enable(hdmi, true);
 959         mtk_hdmi_hw_send_aud_packet(hdmi, true);
 960         mtk_hdmi_hw_aud_unmute(hdmi);
 961         return 0;
 962 }
 963
 964 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
 965                                         struct drm_display_mode *mode)
 966 {
 967         struct hdmi_avi_infoframe frame;
 968         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 969         ssize_t err;
 970
 971         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
 972                                                        hdmi->curr_conn, mode);
 973         if (err < 0) {
 974                 dev_err(hdmi->dev,
 975                         "Failed to get AVI infoframe from mode: %zd\n", err);
 976                 return err;
 977         }
 978
 979         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 980         if (err < 0) {
 981                 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
 982                 return err;
 983         }
 984
 985         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
 986         return 0;
 987 }
 988
 989 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
 990                                         const char *vendor,
 991                                         const char *product)
 992 {
 993         struct hdmi_spd_infoframe frame;
 994         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
 995         ssize_t err;
 996
 997         err = hdmi_spd_infoframe_init(&frame, vendor, product);
 998         if (err < 0) {
 999                 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1000                         err);
1001                 return err;
1002         }
1003
1004         err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1005         if (err < 0) {
1006                 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1007                 return err;
1008         }
1009
1010         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1011         return 0;
1012 }
1013
1014 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1015 {
1016         struct hdmi_audio_infoframe frame;
1017         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
1018         ssize_t err;
1019
1020         err = hdmi_audio_infoframe_init(&frame);
1021         if (err < 0) {
1022                 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1023                         err);
1024                 return err;
1025         }
1026
1027         frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1028         frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1029         frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1030         frame.channels = mtk_hdmi_aud_get_chnl_count(
1031                                         hdmi->aud_param.aud_input_chan_type);
1032
1033         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1034         if (err < 0) {
1035                 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1036                         err);
1037                 return err;
1038         }
1039
1040         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1041         return 0;
1042 }
1043
1044 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1045                                                 struct drm_display_mode *mode)
1046 {
1047         struct hdmi_vendor_infoframe frame;
1048         u8 buffer[10];
1049         ssize_t err;
1050
1051         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1052                                                           hdmi->curr_conn, mode);
1053         if (err) {
1054                 dev_err(hdmi->dev,
1055                         "Failed to get vendor infoframe from mode: %zd\n", err);
1056                 return err;
1057         }
1058
1059         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1060         if (err < 0) {
1061                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1062                         err);
1063                 return err;
1064         }
1065
1066         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1067         return 0;
1068 }
1069
1070 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1071 {
1072         struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1073
1074         hdmi->csp = HDMI_COLORSPACE_RGB;
1075         aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1076         aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1077         aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1078         aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1079         aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1080         aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1081
1082         return 0;
1083 }
1084
1085 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1086 {
1087         mtk_hdmi_hw_send_aud_packet(hdmi, true);
1088         hdmi->audio_enable = true;
1089 }
1090
1091 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1092 {
1093         mtk_hdmi_hw_send_aud_packet(hdmi, false);
1094         hdmi->audio_enable = false;
1095 }
1096
1097 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1098                                     struct hdmi_audio_param *param)
1099 {
1100         if (!hdmi->audio_enable) {
1101                 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1102                 return -EINVAL;
1103         }
1104         dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1105                 param->aud_codec, param->aud_input_type,
1106                 param->aud_input_chan_type, param->codec_params.sample_rate);
1107         memcpy(&hdmi->aud_param, param, sizeof(*param));
1108         return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1109 }
1110
1111 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1112                                             struct drm_display_mode *mode)
1113 {
1114         int ret;
1115
1116         mtk_hdmi_hw_vid_black(hdmi, true);
1117         mtk_hdmi_hw_aud_mute(hdmi);
1118         mtk_hdmi_hw_send_av_mute(hdmi);
1119         phy_power_off(hdmi->phy);
1120
1121         ret = mtk_hdmi_video_change_vpll(hdmi,
1122                                          mode->clock * 1000);
1123         if (ret) {
1124                 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1125                 return ret;
1126         }
1127         mtk_hdmi_video_set_display_mode(hdmi, mode);
1128
1129         phy_power_on(hdmi->phy);
1130         mtk_hdmi_aud_output_config(hdmi, mode);
1131
1132         mtk_hdmi_hw_vid_black(hdmi, false);
1133         mtk_hdmi_hw_aud_unmute(hdmi);
1134         mtk_hdmi_hw_send_av_unmute(hdmi);
1135
1136         return 0;
1137 }
1138
1139 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1140         [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1141         [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1142         [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1143         [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1144 };
1145
1146 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1147                                 struct device_node *np)
1148 {
1149         int i;
1150
1151         for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1152                 hdmi->clk[i] = of_clk_get_by_name(np,
1153                                                   mtk_hdmi_clk_names[i]);
1154                 if (IS_ERR(hdmi->clk[i]))
1155                         return PTR_ERR(hdmi->clk[i]);
1156         }
1157         return 0;
1158 }
1159
1160 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1161 {
1162         int ret;
1163
1164         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1165         if (ret)
1166                 return ret;
1167
1168         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1169         if (ret)
1170                 goto err;
1171
1172         return 0;
1173 err:
1174         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1175         return ret;
1176 }
1177
1178 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1179 {
1180         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1181         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1182 }
1183
1184 static enum drm_connector_status
1185 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
1186 {
1187         bool connected;
1188
1189         mutex_lock(&hdmi->update_plugged_status_lock);
1190         connected = mtk_cec_hpd_high(hdmi->cec_dev);
1191         if (hdmi->plugged_cb && hdmi->codec_dev)
1192                 hdmi->plugged_cb(hdmi->codec_dev, connected);
1193         mutex_unlock(&hdmi->update_plugged_status_lock);
1194
1195         return connected ?
1196                connector_status_connected : connector_status_disconnected;
1197 }
1198
1199 static enum drm_connector_status mtk_hdmi_detect(struct mtk_hdmi *hdmi)
1200 {
1201         return mtk_hdmi_update_plugged_status(hdmi);
1202 }
1203
1204 static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1205                                       const struct drm_display_info *info,
1206                                       const struct drm_display_mode *mode)
1207 {
1208         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1209         struct drm_bridge *next_bridge;
1210
1211         dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1212                 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1213                 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1214
1215         next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge);
1216         if (next_bridge) {
1217                 struct drm_display_mode adjusted_mode;
1218
1219                 drm_mode_copy(&adjusted_mode, mode);
1220                 if (!drm_bridge_chain_mode_fixup(next_bridge, mode,
1221                                                  &adjusted_mode))
1222                         return MODE_BAD;
1223         }
1224
1225         if (mode->clock < 27000)
1226                 return MODE_CLOCK_LOW;
1227         if (mode->clock > 297000)
1228                 return MODE_CLOCK_HIGH;
1229
1230         return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1231 }
1232
1233 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1234 {
1235         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1236
1237         if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) {
1238                 static enum drm_connector_status status;
1239
1240                 status = mtk_hdmi_detect(hdmi);
1241                 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1242                 drm_bridge_hpd_notify(&hdmi->bridge, status);
1243         }
1244 }
1245
1246 /*
1247  * Bridge callbacks
1248  */
1249
1250 static enum drm_connector_status mtk_hdmi_bridge_detect(struct drm_bridge *bridge)
1251 {
1252         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1253
1254         return mtk_hdmi_detect(hdmi);
1255 }
1256
1257 static struct edid *mtk_hdmi_bridge_get_edid(struct drm_bridge *bridge,
1258                                              struct drm_connector *connector)
1259 {
1260         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1261         struct edid *edid;
1262
1263         if (!hdmi->ddc_adpt)
1264                 return NULL;
1265         edid = drm_get_edid(connector, hdmi->ddc_adpt);
1266         if (!edid)
1267                 return NULL;
1268         hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1269         return edid;
1270 }
1271
1272 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
1273                                   enum drm_bridge_attach_flags flags)
1274 {
1275         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1276         int ret;
1277
1278         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
1279                 DRM_ERROR("%s: The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n",
1280                           __func__);
1281                 return -EINVAL;
1282         }
1283
1284         if (hdmi->next_bridge) {
1285                 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1286                                         bridge, flags);
1287                 if (ret) {
1288                         dev_err(hdmi->dev,
1289                                 "Failed to attach external bridge: %d\n", ret);
1290                         return ret;
1291                 }
1292         }
1293
1294         mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1295
1296         return 0;
1297 }
1298
1299 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1300                                        const struct drm_display_mode *mode,
1301                                        struct drm_display_mode *adjusted_mode)
1302 {
1303         return true;
1304 }
1305
1306 static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
1307                                            struct drm_bridge_state *old_bridge_state)
1308 {
1309         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1310
1311         if (!hdmi->enabled)
1312                 return;
1313
1314         phy_power_off(hdmi->phy);
1315         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1316         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1317
1318         hdmi->curr_conn = NULL;
1319
1320         hdmi->enabled = false;
1321 }
1322
1323 static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
1324                                                 struct drm_bridge_state *old_state)
1325 {
1326         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1327
1328         if (!hdmi->powered)
1329                 return;
1330
1331         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1332         mtk_hdmi_hw_make_reg_writable(hdmi, false);
1333
1334         hdmi->powered = false;
1335 }
1336
1337 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1338                                 const struct drm_display_mode *mode,
1339                                 const struct drm_display_mode *adjusted_mode)
1340 {
1341         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1342
1343         dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1344                 adjusted_mode->name, adjusted_mode->hdisplay);
1345         dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1346                 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1347                 adjusted_mode->htotal);
1348         dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1349                 adjusted_mode->hskew, adjusted_mode->vdisplay);
1350         dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1351                 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1352                 adjusted_mode->vtotal);
1353         dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1354                 adjusted_mode->vscan, adjusted_mode->flags);
1355
1356         drm_mode_copy(&hdmi->mode, adjusted_mode);
1357 }
1358
1359 static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1360                                               struct drm_bridge_state *old_state)
1361 {
1362         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1363
1364         mtk_hdmi_hw_make_reg_writable(hdmi, true);
1365         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1366
1367         hdmi->powered = true;
1368 }
1369
1370 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1371                                     struct drm_display_mode *mode)
1372 {
1373         mtk_hdmi_setup_audio_infoframe(hdmi);
1374         mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1375         mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1376         if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1377                 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1378 }
1379
1380 static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
1381                                           struct drm_bridge_state *old_state)
1382 {
1383         struct drm_atomic_state *state = old_state->base.state;
1384         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1385
1386         /* Retrieve the connector through the atomic state. */
1387         hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state,
1388                                                                    bridge->encoder);
1389
1390         mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1391         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1392         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1393         phy_power_on(hdmi->phy);
1394         mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1395
1396         hdmi->enabled = true;
1397 }
1398
1399 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1400         .mode_valid = mtk_hdmi_bridge_mode_valid,
1401         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1402         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1403         .atomic_reset = drm_atomic_helper_bridge_reset,
1404         .attach = mtk_hdmi_bridge_attach,
1405         .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1406         .atomic_disable = mtk_hdmi_bridge_atomic_disable,
1407         .atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable,
1408         .mode_set = mtk_hdmi_bridge_mode_set,
1409         .atomic_pre_enable = mtk_hdmi_bridge_atomic_pre_enable,
1410         .atomic_enable = mtk_hdmi_bridge_atomic_enable,
1411         .detect = mtk_hdmi_bridge_detect,
1412         .get_edid = mtk_hdmi_bridge_get_edid,
1413 };
1414
1415 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1416                                    struct platform_device *pdev)
1417 {
1418         struct device *dev = &pdev->dev;
1419         struct device_node *np = dev->of_node;
1420         struct device_node *cec_np, *remote, *i2c_np;
1421         struct platform_device *cec_pdev;
1422         struct regmap *regmap;
1423         struct resource *mem;
1424         int ret;
1425
1426         ret = mtk_hdmi_get_all_clk(hdmi, np);
1427         if (ret) {
1428                 if (ret != -EPROBE_DEFER)
1429                         dev_err(dev, "Failed to get clocks: %d\n", ret);
1430
1431                 return ret;
1432         }
1433
1434         /* The CEC module handles HDMI hotplug detection */
1435         cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1436         if (!cec_np) {
1437                 dev_err(dev, "Failed to find CEC node\n");
1438                 return -EINVAL;
1439         }
1440
1441         cec_pdev = of_find_device_by_node(cec_np);
1442         if (!cec_pdev) {
1443                 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1444                         cec_np);
1445                 of_node_put(cec_np);
1446                 return -EPROBE_DEFER;
1447         }
1448         of_node_put(cec_np);
1449         hdmi->cec_dev = &cec_pdev->dev;
1450
1451         /*
1452          * The mediatek,syscon-hdmi property contains a phandle link to the
1453          * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1454          * registers it contains.
1455          */
1456         regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1457         ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1458                                          &hdmi->sys_offset);
1459         if (IS_ERR(regmap))
1460                 ret = PTR_ERR(regmap);
1461         if (ret) {
1462                 dev_err(dev,
1463                         "Failed to get system configuration registers: %d\n",
1464                         ret);
1465                 goto put_device;
1466         }
1467         hdmi->sys_regmap = regmap;
1468
1469         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1470         hdmi->regs = devm_ioremap_resource(dev, mem);
1471         if (IS_ERR(hdmi->regs)) {
1472                 ret = PTR_ERR(hdmi->regs);
1473                 goto put_device;
1474         }
1475
1476         remote = of_graph_get_remote_node(np, 1, 0);
1477         if (!remote) {
1478                 ret = -EINVAL;
1479                 goto put_device;
1480         }
1481
1482         if (!of_device_is_compatible(remote, "hdmi-connector")) {
1483                 hdmi->next_bridge = of_drm_find_bridge(remote);
1484                 if (!hdmi->next_bridge) {
1485                         dev_err(dev, "Waiting for external bridge\n");
1486                         of_node_put(remote);
1487                         ret = -EPROBE_DEFER;
1488                         goto put_device;
1489                 }
1490         }
1491
1492         i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1493         if (!i2c_np) {
1494                 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1495                         remote);
1496                 of_node_put(remote);
1497                 ret = -EINVAL;
1498                 goto put_device;
1499         }
1500         of_node_put(remote);
1501
1502         hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1503         of_node_put(i2c_np);
1504         if (!hdmi->ddc_adpt) {
1505                 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1506                 ret = -EINVAL;
1507                 goto put_device;
1508         }
1509
1510         return 0;
1511 put_device:
1512         put_device(hdmi->cec_dev);
1513         return ret;
1514 }
1515
1516 /*
1517  * HDMI audio codec callbacks
1518  */
1519
1520 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1521                                     struct hdmi_codec_daifmt *daifmt,
1522                                     struct hdmi_codec_params *params)
1523 {
1524         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1525         struct hdmi_audio_param hdmi_params;
1526         unsigned int chan = params->cea.channels;
1527
1528         dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1529                 params->sample_rate, params->sample_width, chan);
1530
1531         if (!hdmi->bridge.encoder)
1532                 return -ENODEV;
1533
1534         switch (chan) {
1535         case 2:
1536                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1537                 break;
1538         case 4:
1539                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1540                 break;
1541         case 6:
1542                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1543                 break;
1544         case 8:
1545                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1546                 break;
1547         default:
1548                 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1549                 return -EINVAL;
1550         }
1551
1552         switch (params->sample_rate) {
1553         case 32000:
1554         case 44100:
1555         case 48000:
1556         case 88200:
1557         case 96000:
1558         case 176400:
1559         case 192000:
1560                 break;
1561         default:
1562                 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1563                         params->sample_rate);
1564                 return -EINVAL;
1565         }
1566
1567         switch (daifmt->fmt) {
1568         case HDMI_I2S:
1569                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1570                 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1571                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1572                 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1573                 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1574                 break;
1575         case HDMI_SPDIF:
1576                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1577                 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1578                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1579                 break;
1580         default:
1581                 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1582                         daifmt->fmt);
1583                 return -EINVAL;
1584         }
1585
1586         memcpy(&hdmi_params.codec_params, params,
1587                sizeof(hdmi_params.codec_params));
1588
1589         mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1590
1591         return 0;
1592 }
1593
1594 static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1595 {
1596         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1597
1598         mtk_hdmi_audio_enable(hdmi);
1599
1600         return 0;
1601 }
1602
1603 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1604 {
1605         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1606
1607         mtk_hdmi_audio_disable(hdmi);
1608 }
1609
1610 static int
1611 mtk_hdmi_audio_mute(struct device *dev, void *data,
1612                     bool enable, int direction)
1613 {
1614         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1615
1616         if (enable)
1617                 mtk_hdmi_hw_aud_mute(hdmi);
1618         else
1619                 mtk_hdmi_hw_aud_unmute(hdmi);
1620
1621         return 0;
1622 }
1623
1624 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1625 {
1626         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1627
1628         if (hdmi->enabled)
1629                 memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
1630         else
1631                 memset(buf, 0, len);
1632         return 0;
1633 }
1634
1635 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
1636                                           hdmi_codec_plugged_cb fn,
1637                                           struct device *codec_dev)
1638 {
1639         struct mtk_hdmi *hdmi = data;
1640
1641         mutex_lock(&hdmi->update_plugged_status_lock);
1642         hdmi->plugged_cb = fn;
1643         hdmi->codec_dev = codec_dev;
1644         mutex_unlock(&hdmi->update_plugged_status_lock);
1645
1646         mtk_hdmi_update_plugged_status(hdmi);
1647
1648         return 0;
1649 }
1650
1651 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1652         .hw_params = mtk_hdmi_audio_hw_params,
1653         .audio_startup = mtk_hdmi_audio_startup,
1654         .audio_shutdown = mtk_hdmi_audio_shutdown,
1655         .mute_stream = mtk_hdmi_audio_mute,
1656         .get_eld = mtk_hdmi_audio_get_eld,
1657         .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
1658         .no_capture_mute = 1,
1659 };
1660
1661 static int mtk_hdmi_register_audio_driver(struct device *dev)
1662 {
1663         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1664         struct hdmi_codec_pdata codec_data = {
1665                 .ops = &mtk_hdmi_audio_codec_ops,
1666                 .max_i2s_channels = 2,
1667                 .i2s = 1,
1668                 .data = hdmi,
1669         };
1670         struct platform_device *pdev;
1671
1672         pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1673                                              PLATFORM_DEVID_AUTO, &codec_data,
1674                                              sizeof(codec_data));
1675         if (IS_ERR(pdev))
1676                 return PTR_ERR(pdev);
1677
1678         DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1679         return 0;
1680 }
1681
1682 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1683 {
1684         struct mtk_hdmi *hdmi;
1685         struct device *dev = &pdev->dev;
1686         int ret;
1687
1688         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1689         if (!hdmi)
1690                 return -ENOMEM;
1691
1692         hdmi->dev = dev;
1693         hdmi->conf = of_device_get_match_data(dev);
1694
1695         ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1696         if (ret)
1697                 return ret;
1698
1699         hdmi->phy = devm_phy_get(dev, "hdmi");
1700         if (IS_ERR(hdmi->phy)) {
1701                 ret = PTR_ERR(hdmi->phy);
1702                 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1703                 return ret;
1704         }
1705
1706         mutex_init(&hdmi->update_plugged_status_lock);
1707         platform_set_drvdata(pdev, hdmi);
1708
1709         ret = mtk_hdmi_output_init(hdmi);
1710         if (ret) {
1711                 dev_err(dev, "Failed to initialize hdmi output\n");
1712                 return ret;
1713         }
1714
1715         ret = mtk_hdmi_register_audio_driver(dev);
1716         if (ret) {
1717                 dev_err(dev, "Failed to register audio driver: %d\n", ret);
1718                 return ret;
1719         }
1720
1721         hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1722         hdmi->bridge.of_node = pdev->dev.of_node;
1723         hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
1724                          | DRM_BRIDGE_OP_HPD;
1725         hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1726         drm_bridge_add(&hdmi->bridge);
1727
1728         ret = mtk_hdmi_clk_enable_audio(hdmi);
1729         if (ret) {
1730                 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1731                 goto err_bridge_remove;
1732         }
1733
1734         return 0;
1735
1736 err_bridge_remove:
1737         drm_bridge_remove(&hdmi->bridge);
1738         return ret;
1739 }
1740
1741 static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1742 {
1743         struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1744
1745         drm_bridge_remove(&hdmi->bridge);
1746         mtk_hdmi_clk_disable_audio(hdmi);
1747         return 0;
1748 }
1749
1750 #ifdef CONFIG_PM_SLEEP
1751 static int mtk_hdmi_suspend(struct device *dev)
1752 {
1753         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1754
1755         mtk_hdmi_clk_disable_audio(hdmi);
1756
1757         return 0;
1758 }
1759
1760 static int mtk_hdmi_resume(struct device *dev)
1761 {
1762         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1763         int ret = 0;
1764
1765         ret = mtk_hdmi_clk_enable_audio(hdmi);
1766         if (ret) {
1767                 dev_err(dev, "hdmi resume failed!\n");
1768                 return ret;
1769         }
1770
1771         return 0;
1772 }
1773 #endif
1774 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1775                          mtk_hdmi_suspend, mtk_hdmi_resume);
1776
1777 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
1778         .tz_disabled = true,
1779 };
1780
1781 static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1782         { .compatible = "mediatek,mt2701-hdmi",
1783           .data = &mtk_hdmi_conf_mt2701,
1784         },
1785         { .compatible = "mediatek,mt8173-hdmi",
1786         },
1787         {}
1788 };
1789 MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_of_ids);
1790
1791 static struct platform_driver mtk_hdmi_driver = {
1792         .probe = mtk_drm_hdmi_probe,
1793         .remove = mtk_drm_hdmi_remove,
1794         .driver = {
1795                 .name = "mediatek-drm-hdmi",
1796                 .of_match_table = mtk_drm_hdmi_of_ids,
1797                 .pm = &mtk_hdmi_pm_ops,
1798         },
1799 };
1800
1801 static struct platform_driver * const mtk_hdmi_drivers[] = {
1802         &mtk_hdmi_ddc_driver,
1803         &mtk_cec_driver,
1804         &mtk_hdmi_driver,
1805 };
1806
1807 static int __init mtk_hdmitx_init(void)
1808 {
1809         return platform_register_drivers(mtk_hdmi_drivers,
1810                                          ARRAY_SIZE(mtk_hdmi_drivers));
1811 }
1812
1813 static void __exit mtk_hdmitx_exit(void)
1814 {
1815         platform_unregister_drivers(mtk_hdmi_drivers,
1816                                     ARRAY_SIZE(mtk_hdmi_drivers));
1817 }
1818
1819 module_init(mtk_hdmitx_init);
1820 module_exit(mtk_hdmitx_exit);
1821
1822 MODULE_AUTHOR("Jie Qiu <[email protected]>");
1823 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1824 MODULE_LICENSE("GPL v2");