drivers/gpu/drm/i915/gt/intel_gt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include "debugfs_gt.h"
   7
   8 #include "gem/i915_gem_lmem.h"
   9 #include "i915_drv.h"
  10 #include "intel_context.h"
  11 #include "intel_gt.h"
  12 #include "intel_gt_buffer_pool.h"
  13 #include "intel_gt_clock_utils.h"
  14 #include "intel_gt_pm.h"
  15 #include "intel_gt_requests.h"
  16 #include "intel_mocs.h"
  17 #include "intel_rc6.h"
  18 #include "intel_renderstate.h"
  19 #include "intel_rps.h"
  20 #include "intel_uncore.h"
  21 #include "intel_pm.h"
  22 #include "shmem_utils.h"
  23
  24 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
  25 {
  26         gt->i915 = i915;
  27         gt->uncore = &i915->uncore;
  28
  29         spin_lock_init(&gt->irq_lock);
  30
  31         INIT_LIST_HEAD(&gt->closed_vma);
  32         spin_lock_init(&gt->closed_lock);
  33
  34         init_llist_head(&gt->watchdog.list);
  35         INIT_WORK(&gt->watchdog.work, intel_gt_watchdog_work);
  36
  37         intel_gt_init_buffer_pool(gt);
  38         intel_gt_init_reset(gt);
  39         intel_gt_init_requests(gt);
  40         intel_gt_init_timelines(gt);
  41         intel_gt_pm_init_early(gt);
  42
  43         intel_rps_init_early(&gt->rps);
  44         intel_uc_init_early(&gt->uc);
  45 }
  46
  47 int intel_gt_probe_lmem(struct intel_gt *gt)
  48 {
  49         struct drm_i915_private *i915 = gt->i915;
  50         struct intel_memory_region *mem;
  51         int id;
  52         int err;
  53
  54         mem = intel_gt_setup_lmem(gt);
  55         if (mem == ERR_PTR(-ENODEV))
  56                 mem = intel_gt_setup_fake_lmem(gt);
  57         if (IS_ERR(mem)) {
  58                 err = PTR_ERR(mem);
  59                 if (err == -ENODEV)
  60                         return 0;
  61
  62                 drm_err(&i915->drm,
  63                         "Failed to setup region(%d) type=%d\n",
  64                         err, INTEL_MEMORY_LOCAL);
  65                 return err;
  66         }
  67
  68         id = INTEL_REGION_LMEM;
  69
  70         mem->id = id;
  71         mem->type = INTEL_MEMORY_LOCAL;
  72         mem->instance = 0;
  73
  74         intel_memory_region_set_name(mem, "local%u", mem->instance);
  75
  76         GEM_BUG_ON(!HAS_REGION(i915, id));
  77         GEM_BUG_ON(i915->mm.regions[id]);
  78         i915->mm.regions[id] = mem;
  79
  80         return 0;
  81 }
  82
  83 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
  84 {
  85         gt->ggtt = ggtt;
  86 }
  87
  88 int intel_gt_init_mmio(struct intel_gt *gt)
  89 {
  90         intel_gt_init_clock_frequency(gt);
  91
  92         intel_uc_init_mmio(&gt->uc);
  93         intel_sseu_info_init(gt);
  94
  95         return intel_engines_init_mmio(gt);
  96 }
  97
  98 static void init_unused_ring(struct intel_gt *gt, u32 base)
  99 {
 100         struct intel_uncore *uncore = gt->uncore;
 101
 102         intel_uncore_write(uncore, RING_CTL(base), 0);
 103         intel_uncore_write(uncore, RING_HEAD(base), 0);
 104         intel_uncore_write(uncore, RING_TAIL(base), 0);
 105         intel_uncore_write(uncore, RING_START(base), 0);
 106 }
 107
 108 static void init_unused_rings(struct intel_gt *gt)
 109 {
 110         struct drm_i915_private *i915 = gt->i915;
 111
 112         if (IS_I830(i915)) {
 113                 init_unused_ring(gt, PRB1_BASE);
 114                 init_unused_ring(gt, SRB0_BASE);
 115                 init_unused_ring(gt, SRB1_BASE);
 116                 init_unused_ring(gt, SRB2_BASE);
 117                 init_unused_ring(gt, SRB3_BASE);
 118         } else if (IS_GEN(i915, 2)) {
 119                 init_unused_ring(gt, SRB0_BASE);
 120                 init_unused_ring(gt, SRB1_BASE);
 121         } else if (IS_GEN(i915, 3)) {
 122                 init_unused_ring(gt, PRB1_BASE);
 123                 init_unused_ring(gt, PRB2_BASE);
 124         }
 125 }
 126
 127 int intel_gt_init_hw(struct intel_gt *gt)
 128 {
 129         struct drm_i915_private *i915 = gt->i915;
 130         struct intel_uncore *uncore = gt->uncore;
 131         int ret;
 132
 133         gt->last_init_time = ktime_get();
 134
 135         /* Double layer security blanket, see i915_gem_init() */
 136         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 137
 138         if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
 139                 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 140
 141         if (IS_HASWELL(i915))
 142                 intel_uncore_write(uncore,
 143                                    MI_PREDICATE_RESULT_2,
 144                                    IS_HSW_GT3(i915) ?
 145                                    LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 146
 147         /* Apply the GT workarounds... */
 148         intel_gt_apply_workarounds(gt);
 149         /* ...and determine whether they are sticking. */
 150         intel_gt_verify_workarounds(gt, "init");
 151
 152         intel_gt_init_swizzling(gt);
 153
 154         /*
 155          * At least 830 can leave some of the unused rings
 156          * "active" (ie. head != tail) after resume which
 157          * will prevent c3 entry. Makes sure all unused rings
 158          * are totally idle.
 159          */
 160         init_unused_rings(gt);
 161
 162         ret = i915_ppgtt_init_hw(gt);
 163         if (ret) {
 164                 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 165                 goto out;
 166         }
 167
 168         /* We can't enable contexts until all firmware is loaded */
 169         ret = intel_uc_init_hw(&gt->uc);
 170         if (ret) {
 171                 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
 172                 goto out;
 173         }
 174
 175         intel_mocs_init(gt);
 176
 177 out:
 178         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 179         return ret;
 180 }
 181
 182 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 183 {
 184         intel_uncore_rmw(uncore, reg, 0, set);
 185 }
 186
 187 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
 188 {
 189         intel_uncore_rmw(uncore, reg, clr, 0);
 190 }
 191
 192 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 193 {
 194         intel_uncore_rmw(uncore, reg, 0, 0);
 195 }
 196
 197 static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
 198 {
 199         GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
 200         GEN6_RING_FAULT_REG_POSTING_READ(engine);
 201 }
 202
 203 void
 204 intel_gt_clear_error_registers(struct intel_gt *gt,
 205                                intel_engine_mask_t engine_mask)
 206 {
 207         struct drm_i915_private *i915 = gt->i915;
 208         struct intel_uncore *uncore = gt->uncore;
 209         u32 eir;
 210
 211         if (!IS_GEN(i915, 2))
 212                 clear_register(uncore, PGTBL_ER);
 213
 214         if (INTEL_GEN(i915) < 4)
 215                 clear_register(uncore, IPEIR(RENDER_RING_BASE));
 216         else
 217                 clear_register(uncore, IPEIR_I965);
 218
 219         clear_register(uncore, EIR);
 220         eir = intel_uncore_read(uncore, EIR);
 221         if (eir) {
 222                 /*
 223                  * some errors might have become stuck,
 224                  * mask them.
 225                  */
 226                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
 227                 rmw_set(uncore, EMR, eir);
 228                 intel_uncore_write(uncore, GEN2_IIR,
 229                                    I915_MASTER_ERROR_INTERRUPT);
 230         }
 231
 232         if (INTEL_GEN(i915) >= 12) {
 233                 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
 234                 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
 235         } else if (INTEL_GEN(i915) >= 8) {
 236                 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
 237                 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
 238         } else if (INTEL_GEN(i915) >= 6) {
 239                 struct intel_engine_cs *engine;
 240                 enum intel_engine_id id;
 241
 242                 for_each_engine_masked(engine, gt, engine_mask, id)
 243                         gen8_clear_engine_error_register(engine);
 244         }
 245 }
 246
 247 static void gen6_check_faults(struct intel_gt *gt)
 248 {
 249         struct intel_engine_cs *engine;
 250         enum intel_engine_id id;
 251         u32 fault;
 252
 253         for_each_engine(engine, gt, id) {
 254                 fault = GEN6_RING_FAULT_REG_READ(engine);
 255                 if (fault & RING_FAULT_VALID) {
 256                         drm_dbg(&engine->i915->drm, "Unexpected fault\n"
 257                                 "\tAddr: 0x%08lx\n"
 258                                 "\tAddress space: %s\n"
 259                                 "\tSource ID: %d\n"
 260                                 "\tType: %d\n",
 261                                 fault & PAGE_MASK,
 262                                 fault & RING_FAULT_GTTSEL_MASK ?
 263                                 "GGTT" : "PPGTT",
 264                                 RING_FAULT_SRCID(fault),
 265                                 RING_FAULT_FAULT_TYPE(fault));
 266                 }
 267         }
 268 }
 269
 270 static void gen8_check_faults(struct intel_gt *gt)
 271 {
 272         struct intel_uncore *uncore = gt->uncore;
 273         i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
 274         u32 fault;
 275
 276         if (INTEL_GEN(gt->i915) >= 12) {
 277                 fault_reg = GEN12_RING_FAULT_REG;
 278                 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
 279                 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
 280         } else {
 281                 fault_reg = GEN8_RING_FAULT_REG;
 282                 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
 283                 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
 284         }
 285
 286         fault = intel_uncore_read(uncore, fault_reg);
 287         if (fault & RING_FAULT_VALID) {
 288                 u32 fault_data0, fault_data1;
 289                 u64 fault_addr;
 290
 291                 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
 292                 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
 293
 294                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 295                              ((u64)fault_data0 << 12);
 296
 297                 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
 298                         "\tAddr: 0x%08x_%08x\n"
 299                         "\tAddress space: %s\n"
 300                         "\tEngine ID: %d\n"
 301                         "\tSource ID: %d\n"
 302                         "\tType: %d\n",
 303                         upper_32_bits(fault_addr), lower_32_bits(fault_addr),
 304                         fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 305                         GEN8_RING_FAULT_ENGINE_ID(fault),
 306                         RING_FAULT_SRCID(fault),
 307                         RING_FAULT_FAULT_TYPE(fault));
 308         }
 309 }
 310
 311 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 312 {
 313         struct drm_i915_private *i915 = gt->i915;
 314
 315         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
 316         if (INTEL_GEN(i915) >= 8)
 317                 gen8_check_faults(gt);
 318         else if (INTEL_GEN(i915) >= 6)
 319                 gen6_check_faults(gt);
 320         else
 321                 return;
 322
 323         intel_gt_clear_error_registers(gt, ALL_ENGINES);
 324 }
 325
 326 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 327 {
 328         struct intel_uncore *uncore = gt->uncore;
 329         intel_wakeref_t wakeref;
 330
 331         /*
 332          * No actual flushing is required for the GTT write domain for reads
 333          * from the GTT domain. Writes to it "immediately" go to main memory
 334          * as far as we know, so there's no chipset flush. It also doesn't
 335          * land in the GPU render cache.
 336          *
 337          * However, we do have to enforce the order so that all writes through
 338          * the GTT land before any writes to the device, such as updates to
 339          * the GATT itself.
 340          *
 341          * We also have to wait a bit for the writes to land from the GTT.
 342          * An uncached read (i.e. mmio) seems to be ideal for the round-trip
 343          * timing. This issue has only been observed when switching quickly
 344          * between GTT writes and CPU reads from inside the kernel on recent hw,
 345          * and it appears to only affect discrete GTT blocks (i.e. on LLC
 346          * system agents we cannot reproduce this behaviour, until Cannonlake
 347          * that was!).
 348          */
 349
 350         wmb();
 351
 352         if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 353                 return;
 354
 355         intel_gt_chipset_flush(gt);
 356
 357         with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
 358                 unsigned long flags;
 359
 360                 spin_lock_irqsave(&uncore->lock, flags);
 361                 intel_uncore_posting_read_fw(uncore,
 362                                              RING_HEAD(RENDER_RING_BASE));
 363                 spin_unlock_irqrestore(&uncore->lock, flags);
 364         }
 365 }
 366
 367 void intel_gt_chipset_flush(struct intel_gt *gt)
 368 {
 369         wmb();
 370         if (INTEL_GEN(gt->i915) < 6)
 371                 intel_gtt_chipset_flush();
 372 }
 373
 374 void intel_gt_driver_register(struct intel_gt *gt)
 375 {
 376         intel_rps_driver_register(&gt->rps);
 377
 378         debugfs_gt_register(gt);
 379 }
 380
 381 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 382 {
 383         struct drm_i915_private *i915 = gt->i915;
 384         struct drm_i915_gem_object *obj;
 385         struct i915_vma *vma;
 386         int ret;
 387
 388         obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
 389         if (IS_ERR(obj))
 390                 obj = i915_gem_object_create_stolen(i915, size);
 391         if (IS_ERR(obj))
 392                 obj = i915_gem_object_create_internal(i915, size);
 393         if (IS_ERR(obj)) {
 394                 drm_err(&i915->drm, "Failed to allocate scratch page\n");
 395                 return PTR_ERR(obj);
 396         }
 397
 398         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 399         if (IS_ERR(vma)) {
 400                 ret = PTR_ERR(vma);
 401                 goto err_unref;
 402         }
 403
 404         ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
 405         if (ret)
 406                 goto err_unref;
 407
 408         gt->scratch = i915_vma_make_unshrinkable(vma);
 409
 410         return 0;
 411
 412 err_unref:
 413         i915_gem_object_put(obj);
 414         return ret;
 415 }
 416
 417 static void intel_gt_fini_scratch(struct intel_gt *gt)
 418 {
 419         i915_vma_unpin_and_release(&gt->scratch, 0);
 420 }
 421
 422 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
 423 {
 424         if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
 425                 return &i915_ppgtt_create(gt)->vm;
 426         else
 427                 return i915_vm_get(&gt->ggtt->vm);
 428 }
 429
 430 static int __engines_record_defaults(struct intel_gt *gt)
 431 {
 432         struct i915_request *requests[I915_NUM_ENGINES] = {};
 433         struct intel_engine_cs *engine;
 434         enum intel_engine_id id;
 435         int err = 0;
 436
 437         /*
 438          * As we reset the gpu during very early sanitisation, the current
 439          * register state on the GPU should reflect its defaults values.
 440          * We load a context onto the hw (with restore-inhibit), then switch
 441          * over to a second context to save that default register state. We
 442          * can then prime every new context with that state so they all start
 443          * from the same default HW values.
 444          */
 445
 446         for_each_engine(engine, gt, id) {
 447                 struct intel_renderstate so;
 448                 struct intel_context *ce;
 449                 struct i915_request *rq;
 450
 451                 /* We must be able to switch to something! */
 452                 GEM_BUG_ON(!engine->kernel_context);
 453
 454                 ce = intel_context_create(engine);
 455                 if (IS_ERR(ce)) {
 456                         err = PTR_ERR(ce);
 457                         goto out;
 458                 }
 459
 460                 err = intel_renderstate_init(&so, ce);
 461                 if (err)
 462                         goto err;
 463
 464                 rq = i915_request_create(ce);
 465                 if (IS_ERR(rq)) {
 466                         err = PTR_ERR(rq);
 467                         goto err_fini;
 468                 }
 469
 470                 err = intel_engine_emit_ctx_wa(rq);
 471                 if (err)
 472                         goto err_rq;
 473
 474                 err = intel_renderstate_emit(&so, rq);
 475                 if (err)
 476                         goto err_rq;
 477
 478 err_rq:
 479                 requests[id] = i915_request_get(rq);
 480                 i915_request_add(rq);
 481 err_fini:
 482                 intel_renderstate_fini(&so, ce);
 483 err:
 484                 if (err) {
 485                         intel_context_put(ce);
 486                         goto out;
 487                 }
 488         }
 489
 490         /* Flush the default context image to memory, and enable powersaving. */
 491         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 492                 err = -EIO;
 493                 goto out;
 494         }
 495
 496         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 497                 struct i915_request *rq;
 498                 struct file *state;
 499
 500                 rq = requests[id];
 501                 if (!rq)
 502                         continue;
 503
 504                 if (rq->fence.error) {
 505                         err = -EIO;
 506                         goto out;
 507                 }
 508
 509                 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 510                 if (!rq->context->state)
 511                         continue;
 512
 513                 /* Keep a copy of the state's backing pages; free the obj */
 514                 state = shmem_create_from_object(rq->context->state->obj);
 515                 if (IS_ERR(state)) {
 516                         err = PTR_ERR(state);
 517                         goto out;
 518                 }
 519                 rq->engine->default_state = state;
 520         }
 521
 522 out:
 523         /*
 524          * If we have to abandon now, we expect the engines to be idle
 525          * and ready to be torn-down. The quickest way we can accomplish
 526          * this is by declaring ourselves wedged.
 527          */
 528         if (err)
 529                 intel_gt_set_wedged(gt);
 530
 531         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 532                 struct intel_context *ce;
 533                 struct i915_request *rq;
 534
 535                 rq = requests[id];
 536                 if (!rq)
 537                         continue;
 538
 539                 ce = rq->context;
 540                 i915_request_put(rq);
 541                 intel_context_put(ce);
 542         }
 543         return err;
 544 }
 545
 546 static int __engines_verify_workarounds(struct intel_gt *gt)
 547 {
 548         struct intel_engine_cs *engine;
 549         enum intel_engine_id id;
 550         int err = 0;
 551
 552         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 553                 return 0;
 554
 555         for_each_engine(engine, gt, id) {
 556                 if (intel_engine_verify_workarounds(engine, "load"))
 557                         err = -EIO;
 558         }
 559
 560         /* Flush and restore the kernel context for safety */
 561         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
 562                 err = -EIO;
 563
 564         return err;
 565 }
 566
 567 static void __intel_gt_disable(struct intel_gt *gt)
 568 {
 569         intel_gt_set_wedged_on_fini(gt);
 570
 571         intel_gt_suspend_prepare(gt);
 572         intel_gt_suspend_late(gt);
 573
 574         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 575 }
 576
 577 int intel_gt_init(struct intel_gt *gt)
 578 {
 579         int err;
 580
 581         err = i915_inject_probe_error(gt->i915, -ENODEV);
 582         if (err)
 583                 return err;
 584
 585         /*
 586          * This is just a security blanket to placate dragons.
 587          * On some systems, we very sporadically observe that the first TLBs
 588          * used by the CS may be stale, despite us poking the TLB reset. If
 589          * we hold the forcewake during initialisation these problems
 590          * just magically go away.
 591          */
 592         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 593
 594         err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
 595         if (err)
 596                 goto out_fw;
 597
 598         intel_gt_pm_init(gt);
 599
 600         gt->vm = kernel_vm(gt);
 601         if (!gt->vm) {
 602                 err = -ENOMEM;
 603                 goto err_pm;
 604         }
 605
 606         err = intel_engines_init(gt);
 607         if (err)
 608                 goto err_engines;
 609
 610         err = intel_uc_init(&gt->uc);
 611         if (err)
 612                 goto err_engines;
 613
 614         err = intel_gt_resume(gt);
 615         if (err)
 616                 goto err_uc_init;
 617
 618         err = __engines_record_defaults(gt);
 619         if (err)
 620                 goto err_gt;
 621
 622         err = __engines_verify_workarounds(gt);
 623         if (err)
 624                 goto err_gt;
 625
 626         err = i915_inject_probe_error(gt->i915, -EIO);
 627         if (err)
 628                 goto err_gt;
 629
 630         goto out_fw;
 631 err_gt:
 632         __intel_gt_disable(gt);
 633         intel_uc_fini_hw(&gt->uc);
 634 err_uc_init:
 635         intel_uc_fini(&gt->uc);
 636 err_engines:
 637         intel_engines_release(gt);
 638         i915_vm_put(fetch_and_zero(&gt->vm));
 639 err_pm:
 640         intel_gt_pm_fini(gt);
 641         intel_gt_fini_scratch(gt);
 642 out_fw:
 643         if (err)
 644                 intel_gt_set_wedged_on_init(gt);
 645         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 646         return err;
 647 }
 648
 649 void intel_gt_driver_remove(struct intel_gt *gt)
 650 {
 651         __intel_gt_disable(gt);
 652
 653         intel_uc_driver_remove(&gt->uc);
 654
 655         intel_engines_release(gt);
 656 }
 657
 658 void intel_gt_driver_unregister(struct intel_gt *gt)
 659 {
 660         intel_wakeref_t wakeref;
 661
 662         intel_rps_driver_unregister(&gt->rps);
 663
 664         /*
 665          * Upon unregistering the device to prevent any new users, cancel
 666          * all in-flight requests so that we can quickly unbind the active
 667          * resources.
 668          */
 669         intel_gt_set_wedged(gt);
 670
 671         /* Scrub all HW state upon release */
 672         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
 673                 __intel_gt_reset(gt, ALL_ENGINES);
 674 }
 675
 676 void intel_gt_driver_release(struct intel_gt *gt)
 677 {
 678         struct i915_address_space *vm;
 679
 680         vm = fetch_and_zero(&gt->vm);
 681         if (vm) /* FIXME being called twice on error paths :( */
 682                 i915_vm_put(vm);
 683
 684         intel_gt_pm_fini(gt);
 685         intel_gt_fini_scratch(gt);
 686         intel_gt_fini_buffer_pool(gt);
 687 }
 688
 689 void intel_gt_driver_late_release(struct intel_gt *gt)
 690 {
 691         /* We need to wait for inflight RCU frees to release their grip */
 692         rcu_barrier();
 693
 694         intel_uc_driver_late_release(&gt->uc);
 695         intel_gt_fini_requests(gt);
 696         intel_gt_fini_reset(gt);
 697         intel_gt_fini_timelines(gt);
 698         intel_engines_free(gt);
 699 }
 700
 701 void intel_gt_info_print(const struct intel_gt_info *info,
 702                          struct drm_printer *p)
 703 {
 704         drm_printf(p, "available engines: %x\n", info->engine_mask);
 705
 706         intel_sseu_dump(&info->sseu, p);
 707 }