drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include "amdgpu_display.h"
  33 #include <asm/div64.h>
  34
  35 #include <linux/pci.h>
  36 #include <linux/pm_runtime.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_edid.h>
  39 #include <drm/drm_gem_framebuffer_helper.h>
  40 #include <drm/drm_fb_helper.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_vblank.h>
  43
  44 static void amdgpu_display_flip_callback(struct dma_fence *f,
  45                                          struct dma_fence_cb *cb)
  46 {
  47         struct amdgpu_flip_work *work =
  48                 container_of(cb, struct amdgpu_flip_work, cb);
  49
  50         dma_fence_put(f);
  51         schedule_work(&work->flip_work.work);
  52 }
  53
  54 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
  55                                              struct dma_fence **f)
  56 {
  57         struct dma_fence *fence= *f;
  58
  59         if (fence == NULL)
  60                 return false;
  61
  62         *f = NULL;
  63
  64         if (!dma_fence_add_callback(fence, &work->cb,
  65                                     amdgpu_display_flip_callback))
  66                 return true;
  67
  68         dma_fence_put(fence);
  69         return false;
  70 }
  71
  72 static void amdgpu_display_flip_work_func(struct work_struct *__work)
  73 {
  74         struct delayed_work *delayed_work =
  75                 container_of(__work, struct delayed_work, work);
  76         struct amdgpu_flip_work *work =
  77                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
  78         struct amdgpu_device *adev = work->adev;
  79         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
  80
  81         struct drm_crtc *crtc = &amdgpu_crtc->base;
  82         unsigned long flags;
  83         unsigned i;
  84         int vpos, hpos;
  85
  86         if (amdgpu_display_flip_handle_fence(work, &work->excl))
  87                 return;
  88
  89         for (i = 0; i < work->shared_count; ++i)
  90                 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
  91                         return;
  92
  93         /* Wait until we're out of the vertical blank period before the one
  94          * targeted by the flip
  95          */
  96         if (amdgpu_crtc->enabled &&
  97             (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
  98                                                 &vpos, &hpos, NULL, NULL,
  99                                                 &crtc->hwmode)
 100              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 101             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 102             (int)(work->target_vblank -
 103                   amdgpu_get_vblank_counter_kms(crtc)) > 0) {
 104                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
 105                 return;
 106         }
 107
 108         /* We borrow the event spin lock for protecting flip_status */
 109         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 110
 111         /* Do the flip (mmio) */
 112         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 113
 114         /* Set the flip status */
 115         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 116         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 117
 118
 119         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 120                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 121
 122 }
 123
 124 /*
 125  * Handle unpin events outside the interrupt handler proper.
 126  */
 127 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
 128 {
 129         struct amdgpu_flip_work *work =
 130                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 131         int r;
 132
 133         /* unpin of the old buffer */
 134         r = amdgpu_bo_reserve(work->old_abo, true);
 135         if (likely(r == 0)) {
 136                 amdgpu_bo_unpin(work->old_abo);
 137                 amdgpu_bo_unreserve(work->old_abo);
 138         } else
 139                 DRM_ERROR("failed to reserve buffer after flip\n");
 140
 141         amdgpu_bo_unref(&work->old_abo);
 142         kfree(work->shared);
 143         kfree(work);
 144 }
 145
 146 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 147                                 struct drm_framebuffer *fb,
 148                                 struct drm_pending_vblank_event *event,
 149                                 uint32_t page_flip_flags, uint32_t target,
 150                                 struct drm_modeset_acquire_ctx *ctx)
 151 {
 152         struct drm_device *dev = crtc->dev;
 153         struct amdgpu_device *adev = drm_to_adev(dev);
 154         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 155         struct drm_gem_object *obj;
 156         struct amdgpu_flip_work *work;
 157         struct amdgpu_bo *new_abo;
 158         unsigned long flags;
 159         u64 tiling_flags;
 160         int i, r;
 161
 162         work = kzalloc(sizeof *work, GFP_KERNEL);
 163         if (work == NULL)
 164                 return -ENOMEM;
 165
 166         INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
 167         INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
 168
 169         work->event = event;
 170         work->adev = adev;
 171         work->crtc_id = amdgpu_crtc->crtc_id;
 172         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 173
 174         /* schedule unpin of the old buffer */
 175         obj = crtc->primary->fb->obj[0];
 176
 177         /* take a reference to the old object */
 178         work->old_abo = gem_to_amdgpu_bo(obj);
 179         amdgpu_bo_ref(work->old_abo);
 180
 181         obj = fb->obj[0];
 182         new_abo = gem_to_amdgpu_bo(obj);
 183
 184         /* pin the new buffer */
 185         r = amdgpu_bo_reserve(new_abo, false);
 186         if (unlikely(r != 0)) {
 187                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
 188                 goto cleanup;
 189         }
 190
 191         if (!adev->enable_virtual_display) {
 192                 r = amdgpu_bo_pin(new_abo,
 193                                   amdgpu_display_supported_domains(adev, new_abo->flags));
 194                 if (unlikely(r != 0)) {
 195                         DRM_ERROR("failed to pin new abo buffer before flip\n");
 196                         goto unreserve;
 197                 }
 198         }
 199
 200         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
 201         if (unlikely(r != 0)) {
 202                 DRM_ERROR("%p bind failed\n", new_abo);
 203                 goto unpin;
 204         }
 205
 206         r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl,
 207                                               &work->shared_count,
 208                                               &work->shared);
 209         if (unlikely(r != 0)) {
 210                 DRM_ERROR("failed to get fences for buffer\n");
 211                 goto unpin;
 212         }
 213
 214         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 215         amdgpu_bo_unreserve(new_abo);
 216
 217         if (!adev->enable_virtual_display)
 218                 work->base = amdgpu_bo_gpu_offset(new_abo);
 219         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 220                 amdgpu_get_vblank_counter_kms(crtc);
 221
 222         /* we borrow the event spin lock for protecting flip_wrok */
 223         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 224         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 225                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 226                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 227                 r = -EBUSY;
 228                 goto pflip_cleanup;
 229         }
 230
 231         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 232         amdgpu_crtc->pflip_works = work;
 233
 234
 235         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 236                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 237         /* update crtc fb */
 238         crtc->primary->fb = fb;
 239         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 240         amdgpu_display_flip_work_func(&work->flip_work.work);
 241         return 0;
 242
 243 pflip_cleanup:
 244         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 245                 DRM_ERROR("failed to reserve new abo in error path\n");
 246                 goto cleanup;
 247         }
 248 unpin:
 249         if (!adev->enable_virtual_display)
 250                 amdgpu_bo_unpin(new_abo);
 251
 252 unreserve:
 253         amdgpu_bo_unreserve(new_abo);
 254
 255 cleanup:
 256         amdgpu_bo_unref(&work->old_abo);
 257         dma_fence_put(work->excl);
 258         for (i = 0; i < work->shared_count; ++i)
 259                 dma_fence_put(work->shared[i]);
 260         kfree(work->shared);
 261         kfree(work);
 262
 263         return r;
 264 }
 265
 266 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 267                                    struct drm_modeset_acquire_ctx *ctx)
 268 {
 269         struct drm_device *dev;
 270         struct amdgpu_device *adev;
 271         struct drm_crtc *crtc;
 272         bool active = false;
 273         int ret;
 274
 275         if (!set || !set->crtc)
 276                 return -EINVAL;
 277
 278         dev = set->crtc->dev;
 279
 280         ret = pm_runtime_get_sync(dev->dev);
 281         if (ret < 0)
 282                 goto out;
 283
 284         ret = drm_crtc_helper_set_config(set, ctx);
 285
 286         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 287                 if (crtc->enabled)
 288                         active = true;
 289
 290         pm_runtime_mark_last_busy(dev->dev);
 291
 292         adev = drm_to_adev(dev);
 293         /* if we have active crtcs and we don't have a power ref,
 294            take the current one */
 295         if (active && !adev->have_disp_power_ref) {
 296                 adev->have_disp_power_ref = true;
 297                 return ret;
 298         }
 299         /* if we have no active crtcs, then drop the power ref
 300            we got before */
 301         if (!active && adev->have_disp_power_ref) {
 302                 pm_runtime_put_autosuspend(dev->dev);
 303                 adev->have_disp_power_ref = false;
 304         }
 305
 306 out:
 307         /* drop the power reference we got coming in here */
 308         pm_runtime_put_autosuspend(dev->dev);
 309         return ret;
 310 }
 311
 312 static const char *encoder_names[41] = {
 313         "NONE",
 314         "INTERNAL_LVDS",
 315         "INTERNAL_TMDS1",
 316         "INTERNAL_TMDS2",
 317         "INTERNAL_DAC1",
 318         "INTERNAL_DAC2",
 319         "INTERNAL_SDVOA",
 320         "INTERNAL_SDVOB",
 321         "SI170B",
 322         "CH7303",
 323         "CH7301",
 324         "INTERNAL_DVO1",
 325         "EXTERNAL_SDVOA",
 326         "EXTERNAL_SDVOB",
 327         "TITFP513",
 328         "INTERNAL_LVTM1",
 329         "VT1623",
 330         "HDMI_SI1930",
 331         "HDMI_INTERNAL",
 332         "INTERNAL_KLDSCP_TMDS1",
 333         "INTERNAL_KLDSCP_DVO1",
 334         "INTERNAL_KLDSCP_DAC1",
 335         "INTERNAL_KLDSCP_DAC2",
 336         "SI178",
 337         "MVPU_FPGA",
 338         "INTERNAL_DDI",
 339         "VT1625",
 340         "HDMI_SI1932",
 341         "DP_AN9801",
 342         "DP_DP501",
 343         "INTERNAL_UNIPHY",
 344         "INTERNAL_KLDSCP_LVTMA",
 345         "INTERNAL_UNIPHY1",
 346         "INTERNAL_UNIPHY2",
 347         "NUTMEG",
 348         "TRAVIS",
 349         "INTERNAL_VCE",
 350         "INTERNAL_UNIPHY3",
 351         "HDMI_ANX9805",
 352         "INTERNAL_AMCLK",
 353         "VIRTUAL",
 354 };
 355
 356 static const char *hpd_names[6] = {
 357         "HPD1",
 358         "HPD2",
 359         "HPD3",
 360         "HPD4",
 361         "HPD5",
 362         "HPD6",
 363 };
 364
 365 void amdgpu_display_print_display_setup(struct drm_device *dev)
 366 {
 367         struct drm_connector *connector;
 368         struct amdgpu_connector *amdgpu_connector;
 369         struct drm_encoder *encoder;
 370         struct amdgpu_encoder *amdgpu_encoder;
 371         struct drm_connector_list_iter iter;
 372         uint32_t devices;
 373         int i = 0;
 374
 375         drm_connector_list_iter_begin(dev, &iter);
 376         DRM_INFO("AMDGPU Display Connectors\n");
 377         drm_for_each_connector_iter(connector, &iter) {
 378                 amdgpu_connector = to_amdgpu_connector(connector);
 379                 DRM_INFO("Connector %d:\n", i);
 380                 DRM_INFO("  %s\n", connector->name);
 381                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 382                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 383                 if (amdgpu_connector->ddc_bus) {
 384                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 385                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 386                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 387                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 388                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 389                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 390                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 391                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 392                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 393                         if (amdgpu_connector->router.ddc_valid)
 394                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 395                                          amdgpu_connector->router.ddc_mux_control_pin,
 396                                          amdgpu_connector->router.ddc_mux_state);
 397                         if (amdgpu_connector->router.cd_valid)
 398                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 399                                          amdgpu_connector->router.cd_mux_control_pin,
 400                                          amdgpu_connector->router.cd_mux_state);
 401                 } else {
 402                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 403                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 404                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 405                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 406                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 407                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 408                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n");
 409                 }
 410                 DRM_INFO("  Encoders:\n");
 411                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 412                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 413                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 414                         if (devices) {
 415                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 416                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 417                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 418                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 419                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 420                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 421                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 422                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 423                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 424                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 425                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 426                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 427                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 428                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 429                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 430                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 431                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 432                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 433                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 434                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 435                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 436                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 437                         }
 438                 }
 439                 i++;
 440         }
 441         drm_connector_list_iter_end(&iter);
 442 }
 443
 444 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 445                               bool use_aux)
 446 {
 447         u8 out = 0x0;
 448         u8 buf[8];
 449         int ret;
 450         struct i2c_msg msgs[] = {
 451                 {
 452                         .addr = DDC_ADDR,
 453                         .flags = 0,
 454                         .len = 1,
 455                         .buf = &out,
 456                 },
 457                 {
 458                         .addr = DDC_ADDR,
 459                         .flags = I2C_M_RD,
 460                         .len = 8,
 461                         .buf = buf,
 462                 }
 463         };
 464
 465         /* on hw with routers, select right port */
 466         if (amdgpu_connector->router.ddc_valid)
 467                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 468
 469         if (use_aux) {
 470                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 471         } else {
 472                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 473         }
 474
 475         if (ret != 2)
 476                 /* Couldn't find an accessible DDC on this connector */
 477                 return false;
 478         /* Probe also for valid EDID header
 479          * EDID header starts with:
 480          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 481          * Only the first 6 bytes must be valid as
 482          * drm_edid_block_valid() can fix the last 2 bytes */
 483         if (drm_edid_header_is_valid(buf) < 6) {
 484                 /* Couldn't find an accessible EDID on this
 485                  * connector */
 486                 return false;
 487         }
 488         return true;
 489 }
 490
 491 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 492         .destroy = drm_gem_fb_destroy,
 493         .create_handle = drm_gem_fb_create_handle,
 494 };
 495
 496 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 497                                           uint64_t bo_flags)
 498 {
 499         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 500
 501 #if defined(CONFIG_DRM_AMD_DC)
 502         /*
 503          * if amdgpu_bo_support_uswc returns false it means that USWC mappings
 504          * is not supported for this board. But this mapping is required
 505          * to avoid hang caused by placement of scanout BO in GTT on certain
 506          * APUs. So force the BO placement to VRAM in case this architecture
 507          * will not allow USWC mappings.
 508          * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
 509          */
 510         if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 511             amdgpu_bo_support_uswc(bo_flags) &&
 512             amdgpu_device_asic_has_dc_support(adev->asic_type)) {
 513                 switch (adev->asic_type) {
 514                 case CHIP_CARRIZO:
 515                 case CHIP_STONEY:
 516                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 517                         break;
 518                 case CHIP_RAVEN:
 519                         /* enable S/G on PCO and RV2 */
 520                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
 521                             (adev->apu_flags & AMD_APU_IS_PICASSO))
 522                                 domain |= AMDGPU_GEM_DOMAIN_GTT;
 523                         break;
 524                 case CHIP_RENOIR:
 525                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 526                         break;
 527
 528                 default:
 529                         break;
 530                 }
 531         }
 532 #endif
 533
 534         return domain;
 535 }
 536
 537 static const struct drm_format_info dcc_formats[] = {
 538         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 539           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 540          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 541           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 542         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 543           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 544            .has_alpha = true, },
 545         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 546           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 547           .has_alpha = true, },
 548         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
 549           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 550           .has_alpha = true, },
 551         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
 552           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 553         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
 554           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 555         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
 556           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 557           .has_alpha = true, },
 558         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
 559           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 560           .has_alpha = true, },
 561         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
 562           .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 563 };
 564
 565 static const struct drm_format_info dcc_retile_formats[] = {
 566         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
 567           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 568          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 569           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 570         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 571           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 572            .has_alpha = true, },
 573         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 574           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 575           .has_alpha = true, },
 576         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
 577           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 578           .has_alpha = true, },
 579         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
 580           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 581         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
 582           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 583         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
 584           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 585           .has_alpha = true, },
 586         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
 587           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 588           .has_alpha = true, },
 589         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
 590           .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 591 };
 592
 593 static const struct drm_format_info *
 594 lookup_format_info(const struct drm_format_info formats[],
 595                   int num_formats, u32 format)
 596 {
 597         int i;
 598
 599         for (i = 0; i < num_formats; i++) {
 600                 if (formats[i].format == format)
 601                         return &formats[i];
 602         }
 603
 604         return NULL;
 605 }
 606
 607 const struct drm_format_info *
 608 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
 609 {
 610         if (!IS_AMD_FMT_MOD(modifier))
 611                 return NULL;
 612
 613         if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
 614                 return lookup_format_info(dcc_retile_formats,
 615                                           ARRAY_SIZE(dcc_retile_formats),
 616                                           format);
 617
 618         if (AMD_FMT_MOD_GET(DCC, modifier))
 619                 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
 620                                           format);
 621
 622         /* returning NULL will cause the default format structs to be used. */
 623         return NULL;
 624 }
 625
 626
 627 /*
 628  * Tries to extract the renderable DCC offset from the opaque metadata attached
 629  * to the buffer.
 630  */
 631 static int
 632 extract_render_dcc_offset(struct amdgpu_device *adev,
 633                           struct drm_gem_object *obj,
 634                           uint64_t *offset)
 635 {
 636         struct amdgpu_bo *rbo;
 637         int r = 0;
 638         uint32_t metadata[10]; /* Something that fits a descriptor + header. */
 639         uint32_t size;
 640
 641         rbo = gem_to_amdgpu_bo(obj);
 642         r = amdgpu_bo_reserve(rbo, false);
 643
 644         if (unlikely(r)) {
 645                 /* Don't show error message when returning -ERESTARTSYS */
 646                 if (r != -ERESTARTSYS)
 647                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 648                 return r;
 649         }
 650
 651         r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
 652         amdgpu_bo_unreserve(rbo);
 653
 654         if (r)
 655                 return r;
 656
 657         /*
 658          * The first word is the metadata version, and we need space for at least
 659          * the version + pci vendor+device id + 8 words for a descriptor.
 660          */
 661         if (size < 40  || metadata[0] != 1)
 662                 return -EINVAL;
 663
 664         if (adev->family >= AMDGPU_FAMILY_NV) {
 665                 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
 666                 *offset = ((u64)metadata[9] << 16u) |
 667                           ((metadata[8] & 0xFF000000u) >> 16);
 668         } else {
 669                 /* resource word 5/7 META_DATA_ADDRESS */
 670                 *offset = ((u64)metadata[9] << 8u) |
 671                           ((u64)(metadata[7] & 0x1FE0000u) << 23);
 672         }
 673
 674         return 0;
 675 }
 676
 677 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 678 {
 679         struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 680         uint64_t modifier = 0;
 681
 682         if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 683                 modifier = DRM_FORMAT_MOD_LINEAR;
 684         } else {
 685                 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
 686                 bool has_xor = swizzle >= 16;
 687                 int block_size_bits;
 688                 int version;
 689                 int pipe_xor_bits = 0;
 690                 int bank_xor_bits = 0;
 691                 int packers = 0;
 692                 int rb = 0;
 693                 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
 694                 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 695
 696                 switch (swizzle >> 2) {
 697                 case 0: /* 256B */
 698                         block_size_bits = 8;
 699                         break;
 700                 case 1: /* 4KiB */
 701                 case 5: /* 4KiB _X */
 702                         block_size_bits = 12;
 703                         break;
 704                 case 2: /* 64KiB */
 705                 case 4: /* 64 KiB _T */
 706                 case 6: /* 64 KiB _X */
 707                         block_size_bits = 16;
 708                         break;
 709                 default:
 710                         /* RESERVED or VAR */
 711                         return -EINVAL;
 712                 }
 713
 714                 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 715                         version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 716                 else if (adev->family == AMDGPU_FAMILY_NV)
 717                         version = AMD_FMT_MOD_TILE_VER_GFX10;
 718                 else
 719                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 720
 721                 switch (swizzle & 3) {
 722                 case 0: /* Z microtiling */
 723                         return -EINVAL;
 724                 case 1: /* S microtiling */
 725                         if (!has_xor)
 726                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 727                         break;
 728                 case 2:
 729                         if (!has_xor && afb->base.format->cpp[0] != 4)
 730                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 731                         break;
 732                 case 3:
 733                         break;
 734                 }
 735
 736                 if (has_xor) {
 737                         switch (version) {
 738                         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 739                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 740                                 packers = min(block_size_bits - 8 - pipe_xor_bits,
 741                                               ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
 742                                 break;
 743                         case AMD_FMT_MOD_TILE_VER_GFX10:
 744                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 745                                 break;
 746                         case AMD_FMT_MOD_TILE_VER_GFX9:
 747                                 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
 748                                      ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
 749                                 pipe_xor_bits = min(block_size_bits - 8, pipes +
 750                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
 751                                 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
 752                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
 753                                 break;
 754                         }
 755                 }
 756
 757                 modifier = AMD_FMT_MOD |
 758                            AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
 759                            AMD_FMT_MOD_SET(TILE_VERSION, version) |
 760                            AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
 761                            AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
 762                            AMD_FMT_MOD_SET(PACKERS, packers);
 763
 764                 if (dcc_offset != 0) {
 765                         bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
 766                         bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 767                         const struct drm_format_info *format_info;
 768                         u64 render_dcc_offset;
 769
 770                         /* Enable constant encode on RAVEN2 and later. */
 771                         bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
 772                                                    (adev->asic_type == CHIP_RAVEN &&
 773                                                     adev->external_rev_id >= 0x81);
 774
 775                         int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 776                                               dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
 777                                               AMD_FMT_MOD_DCC_BLOCK_256B;
 778
 779                         modifier |= AMD_FMT_MOD_SET(DCC, 1) |
 780                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
 781                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
 782                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
 783                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
 784
 785                         afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
 786                         afb->base.pitches[1] =
 787                                 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
 788
 789                         /*
 790                          * If the userspace driver uses retiling the tiling flags do not contain
 791                          * info on the renderable DCC buffer. Luckily the opaque metadata contains
 792                          * the info so we can try to extract it. The kernel does not use this info
 793                          * but we should convert it to a modifier plane for getfb2, so the
 794                          * userspace driver that gets it doesn't have to juggle around another DCC
 795                          * plane internally.
 796                          */
 797                         if (extract_render_dcc_offset(adev, afb->base.obj[0],
 798                                                       &render_dcc_offset) == 0 &&
 799                             render_dcc_offset != 0 &&
 800                             render_dcc_offset != afb->base.offsets[1] &&
 801                             render_dcc_offset < UINT_MAX) {
 802                                 uint32_t dcc_block_bits;  /* of base surface data */
 803
 804                                 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
 805                                 afb->base.offsets[2] = render_dcc_offset;
 806
 807                                 if (adev->family >= AMDGPU_FAMILY_NV) {
 808                                         int extra_pipe = 0;
 809
 810                                         if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
 811                                             pipes == packers && pipes > 1)
 812                                                 extra_pipe = 1;
 813
 814                                         dcc_block_bits = max(20, 16 + pipes + extra_pipe);
 815                                 } else {
 816                                         modifier |= AMD_FMT_MOD_SET(RB, rb) |
 817                                                     AMD_FMT_MOD_SET(PIPE, pipes);
 818                                         dcc_block_bits = max(20, 18 + rb);
 819                                 }
 820
 821                                 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
 822                                 afb->base.pitches[2] = ALIGN(afb->base.width,
 823                                                              1u << ((dcc_block_bits + 1) / 2));
 824                         }
 825                         format_info = amdgpu_lookup_format_info(afb->base.format->format,
 826                                                                 modifier);
 827                         if (!format_info)
 828                                 return -EINVAL;
 829
 830                         afb->base.format = format_info;
 831                 }
 832         }
 833
 834         afb->base.modifier = modifier;
 835         afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 836         return 0;
 837 }
 838
 839 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
 840                                       uint64_t *tiling_flags, bool *tmz_surface)
 841 {
 842         struct amdgpu_bo *rbo;
 843         int r;
 844
 845         if (!amdgpu_fb) {
 846                 *tiling_flags = 0;
 847                 *tmz_surface = false;
 848                 return 0;
 849         }
 850
 851         rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
 852         r = amdgpu_bo_reserve(rbo, false);
 853
 854         if (unlikely(r)) {
 855                 /* Don't show error message when returning -ERESTARTSYS */
 856                 if (r != -ERESTARTSYS)
 857                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 858                 return r;
 859         }
 860
 861         if (tiling_flags)
 862                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
 863
 864         if (tmz_surface)
 865                 *tmz_surface = amdgpu_bo_encrypted(rbo);
 866
 867         amdgpu_bo_unreserve(rbo);
 868
 869         return r;
 870 }
 871
 872 int amdgpu_display_framebuffer_init(struct drm_device *dev,
 873                                     struct amdgpu_framebuffer *rfb,
 874                                     const struct drm_mode_fb_cmd2 *mode_cmd,
 875                                     struct drm_gem_object *obj)
 876 {
 877         int ret, i;
 878         rfb->base.obj[0] = obj;
 879         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
 880         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
 881         if (ret)
 882                 goto fail;
 883
 884         /*
 885          * This needs to happen before modifier conversion as that might change
 886          * the number of planes.
 887          */
 888         for (i = 1; i < rfb->base.format->num_planes; ++i) {
 889                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
 890                         drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
 891                                     i, mode_cmd->handles[0], mode_cmd->handles[i]);
 892                         ret = -EINVAL;
 893                         goto fail;
 894                 }
 895         }
 896
 897         ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
 898         if (ret)
 899                 goto fail;
 900
 901         if (dev->mode_config.allow_fb_modifiers &&
 902             !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
 903                 ret = convert_tiling_flags_to_modifier(rfb);
 904                 if (ret)
 905                         goto fail;
 906         }
 907
 908         for (i = 1; i < rfb->base.format->num_planes; ++i) {
 909                 rfb->base.obj[i] = rfb->base.obj[0];
 910                 drm_gem_object_get(rfb->base.obj[i]);
 911         }
 912
 913         return 0;
 914
 915 fail:
 916         rfb->base.obj[0] = NULL;
 917         return ret;
 918 }
 919
 920 struct drm_framebuffer *
 921 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
 922                                        struct drm_file *file_priv,
 923                                        const struct drm_mode_fb_cmd2 *mode_cmd)
 924 {
 925         struct drm_gem_object *obj;
 926         struct amdgpu_framebuffer *amdgpu_fb;
 927         int ret;
 928
 929         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
 930         if (obj ==  NULL) {
 931                 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
 932                             "can't create framebuffer\n", mode_cmd->handles[0]);
 933                 return ERR_PTR(-ENOENT);
 934         }
 935
 936         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
 937         if (obj->import_attach) {
 938                 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
 939                 return ERR_PTR(-EINVAL);
 940         }
 941
 942         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
 943         if (amdgpu_fb == NULL) {
 944                 drm_gem_object_put(obj);
 945                 return ERR_PTR(-ENOMEM);
 946         }
 947
 948         ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
 949         if (ret) {
 950                 kfree(amdgpu_fb);
 951                 drm_gem_object_put(obj);
 952                 return ERR_PTR(ret);
 953         }
 954
 955         return &amdgpu_fb->base;
 956 }
 957
 958 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
 959         .fb_create = amdgpu_display_user_framebuffer_create,
 960         .output_poll_changed = drm_fb_helper_output_poll_changed,
 961 };
 962
 963 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
 964 {       { UNDERSCAN_OFF, "off" },
 965         { UNDERSCAN_ON, "on" },
 966         { UNDERSCAN_AUTO, "auto" },
 967 };
 968
 969 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
 970 {       { AMDGPU_AUDIO_DISABLE, "off" },
 971         { AMDGPU_AUDIO_ENABLE, "on" },
 972         { AMDGPU_AUDIO_AUTO, "auto" },
 973 };
 974
 975 /* XXX support different dither options? spatial, temporal, both, etc. */
 976 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
 977 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
 978         { AMDGPU_FMT_DITHER_ENABLE, "on" },
 979 };
 980
 981 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
 982 {
 983         int sz;
 984
 985         adev->mode_info.coherent_mode_property =
 986                 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
 987         if (!adev->mode_info.coherent_mode_property)
 988                 return -ENOMEM;
 989
 990         adev->mode_info.load_detect_property =
 991                 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
 992         if (!adev->mode_info.load_detect_property)
 993                 return -ENOMEM;
 994
 995         drm_mode_create_scaling_mode_property(adev_to_drm(adev));
 996
 997         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
 998         adev->mode_info.underscan_property =
 999                 drm_property_create_enum(adev_to_drm(adev), 0,
1000                                          "underscan",
1001                                          amdgpu_underscan_enum_list, sz);
1002
1003         adev->mode_info.underscan_hborder_property =
1004                 drm_property_create_range(adev_to_drm(adev), 0,
1005                                           "underscan hborder", 0, 128);
1006         if (!adev->mode_info.underscan_hborder_property)
1007                 return -ENOMEM;
1008
1009         adev->mode_info.underscan_vborder_property =
1010                 drm_property_create_range(adev_to_drm(adev), 0,
1011                                           "underscan vborder", 0, 128);
1012         if (!adev->mode_info.underscan_vborder_property)
1013                 return -ENOMEM;
1014
1015         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1016         adev->mode_info.audio_property =
1017                 drm_property_create_enum(adev_to_drm(adev), 0,
1018                                          "audio",
1019                                          amdgpu_audio_enum_list, sz);
1020
1021         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1022         adev->mode_info.dither_property =
1023                 drm_property_create_enum(adev_to_drm(adev), 0,
1024                                          "dither",
1025                                          amdgpu_dither_enum_list, sz);
1026
1027         if (amdgpu_device_has_dc_support(adev)) {
1028                 adev->mode_info.abm_level_property =
1029                         drm_property_create_range(adev_to_drm(adev), 0,
1030                                                   "abm level", 0, 4);
1031                 if (!adev->mode_info.abm_level_property)
1032                         return -ENOMEM;
1033         }
1034
1035         return 0;
1036 }
1037
1038 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1039 {
1040         /* adjustment options for the display watermarks */
1041         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1042                 adev->mode_info.disp_priority = 0;
1043         else
1044                 adev->mode_info.disp_priority = amdgpu_disp_priority;
1045
1046 }
1047
1048 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1049 {
1050         /* try and guess if this is a tv or a monitor */
1051         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1052             (mode->vdisplay == 576) || /* 576p */
1053             (mode->vdisplay == 720) || /* 720p */
1054             (mode->vdisplay == 1080)) /* 1080p */
1055                 return true;
1056         else
1057                 return false;
1058 }
1059
1060 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1061                                         const struct drm_display_mode *mode,
1062                                         struct drm_display_mode *adjusted_mode)
1063 {
1064         struct drm_device *dev = crtc->dev;
1065         struct drm_encoder *encoder;
1066         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1067         struct amdgpu_encoder *amdgpu_encoder;
1068         struct drm_connector *connector;
1069         u32 src_v = 1, dst_v = 1;
1070         u32 src_h = 1, dst_h = 1;
1071
1072         amdgpu_crtc->h_border = 0;
1073         amdgpu_crtc->v_border = 0;
1074
1075         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1076                 if (encoder->crtc != crtc)
1077                         continue;
1078                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1079                 connector = amdgpu_get_connector_for_encoder(encoder);
1080
1081                 /* set scaling */
1082                 if (amdgpu_encoder->rmx_type == RMX_OFF)
1083                         amdgpu_crtc->rmx_type = RMX_OFF;
1084                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1085                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1086                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1087                 else
1088                         amdgpu_crtc->rmx_type = RMX_OFF;
1089                 /* copy native mode */
1090                 memcpy(&amdgpu_crtc->native_mode,
1091                        &amdgpu_encoder->native_mode,
1092                        sizeof(struct drm_display_mode));
1093                 src_v = crtc->mode.vdisplay;
1094                 dst_v = amdgpu_crtc->native_mode.vdisplay;
1095                 src_h = crtc->mode.hdisplay;
1096                 dst_h = amdgpu_crtc->native_mode.hdisplay;
1097
1098                 /* fix up for overscan on hdmi */
1099                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1100                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1101                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1102                       drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
1103                       amdgpu_display_is_hdtv_mode(mode)))) {
1104                         if (amdgpu_encoder->underscan_hborder != 0)
1105                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1106                         else
1107                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1108                         if (amdgpu_encoder->underscan_vborder != 0)
1109                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1110                         else
1111                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1112                         amdgpu_crtc->rmx_type = RMX_FULL;
1113                         src_v = crtc->mode.vdisplay;
1114                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1115                         src_h = crtc->mode.hdisplay;
1116                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1117                 }
1118         }
1119         if (amdgpu_crtc->rmx_type != RMX_OFF) {
1120                 fixed20_12 a, b;
1121                 a.full = dfixed_const(src_v);
1122                 b.full = dfixed_const(dst_v);
1123                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1124                 a.full = dfixed_const(src_h);
1125                 b.full = dfixed_const(dst_h);
1126                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1127         } else {
1128                 amdgpu_crtc->vsc.full = dfixed_const(1);
1129                 amdgpu_crtc->hsc.full = dfixed_const(1);
1130         }
1131         return true;
1132 }
1133
1134 /*
1135  * Retrieve current video scanout position of crtc on a given gpu, and
1136  * an optional accurate timestamp of when query happened.
1137  *
1138  * \param dev Device to query.
1139  * \param pipe Crtc to query.
1140  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1141  *              For driver internal use only also supports these flags:
1142  *
1143  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1144  *              of a fudged earlier start of vblank.
1145  *
1146  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1147  *              fudged earlier start of vblank in *vpos and the distance
1148  *              to true start of vblank in *hpos.
1149  *
1150  * \param *vpos Location where vertical scanout position should be stored.
1151  * \param *hpos Location where horizontal scanout position should go.
1152  * \param *stime Target location for timestamp taken immediately before
1153  *               scanout position query. Can be NULL to skip timestamp.
1154  * \param *etime Target location for timestamp taken immediately after
1155  *               scanout position query. Can be NULL to skip timestamp.
1156  *
1157  * Returns vpos as a positive number while in active scanout area.
1158  * Returns vpos as a negative number inside vblank, counting the number
1159  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1160  * until start of active scanout / end of vblank."
1161  *
1162  * \return Flags, or'ed together as follows:
1163  *
1164  * DRM_SCANOUTPOS_VALID = Query successful.
1165  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1166  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1167  * this flag means that returned position may be offset by a constant but
1168  * unknown small number of scanlines wrt. real scanout position.
1169  *
1170  */
1171 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1172                         unsigned int pipe, unsigned int flags, int *vpos,
1173                         int *hpos, ktime_t *stime, ktime_t *etime,
1174                         const struct drm_display_mode *mode)
1175 {
1176         u32 vbl = 0, position = 0;
1177         int vbl_start, vbl_end, vtotal, ret = 0;
1178         bool in_vbl = true;
1179
1180         struct amdgpu_device *adev = drm_to_adev(dev);
1181
1182         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1183
1184         /* Get optional system timestamp before query. */
1185         if (stime)
1186                 *stime = ktime_get();
1187
1188         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1189                 ret |= DRM_SCANOUTPOS_VALID;
1190
1191         /* Get optional system timestamp after query. */
1192         if (etime)
1193                 *etime = ktime_get();
1194
1195         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1196
1197         /* Decode into vertical and horizontal scanout position. */
1198         *vpos = position & 0x1fff;
1199         *hpos = (position >> 16) & 0x1fff;
1200
1201         /* Valid vblank area boundaries from gpu retrieved? */
1202         if (vbl > 0) {
1203                 /* Yes: Decode. */
1204                 ret |= DRM_SCANOUTPOS_ACCURATE;
1205                 vbl_start = vbl & 0x1fff;
1206                 vbl_end = (vbl >> 16) & 0x1fff;
1207         }
1208         else {
1209                 /* No: Fake something reasonable which gives at least ok results. */
1210                 vbl_start = mode->crtc_vdisplay;
1211                 vbl_end = 0;
1212         }
1213
1214         /* Called from driver internal vblank counter query code? */
1215         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1216             /* Caller wants distance from real vbl_start in *hpos */
1217             *hpos = *vpos - vbl_start;
1218         }
1219
1220         /* Fudge vblank to start a few scanlines earlier to handle the
1221          * problem that vblank irqs fire a few scanlines before start
1222          * of vblank. Some driver internal callers need the true vblank
1223          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1224          *
1225          * The cause of the "early" vblank irq is that the irq is triggered
1226          * by the line buffer logic when the line buffer read position enters
1227          * the vblank, whereas our crtc scanout position naturally lags the
1228          * line buffer read position.
1229          */
1230         if (!(flags & USE_REAL_VBLANKSTART))
1231                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1232
1233         /* Test scanout position against vblank region. */
1234         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1235                 in_vbl = false;
1236
1237         /* In vblank? */
1238         if (in_vbl)
1239             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1240
1241         /* Called from driver internal vblank counter query code? */
1242         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1243                 /* Caller wants distance from fudged earlier vbl_start */
1244                 *vpos -= vbl_start;
1245                 return ret;
1246         }
1247
1248         /* Check if inside vblank area and apply corrective offsets:
1249          * vpos will then be >=0 in video scanout area, but negative
1250          * within vblank area, counting down the number of lines until
1251          * start of scanout.
1252          */
1253
1254         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1255         if (in_vbl && (*vpos >= vbl_start)) {
1256                 vtotal = mode->crtc_vtotal;
1257
1258                 /* With variable refresh rate displays the vpos can exceed
1259                  * the vtotal value. Clamp to 0 to return -vbl_end instead
1260                  * of guessing the remaining number of lines until scanout.
1261                  */
1262                 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1263         }
1264
1265         /* Correct for shifted end of vbl at vbl_end. */
1266         *vpos = *vpos - vbl_end;
1267
1268         return ret;
1269 }
1270
1271 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1272 {
1273         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1274                 return AMDGPU_CRTC_IRQ_NONE;
1275
1276         switch (crtc) {
1277         case 0:
1278                 return AMDGPU_CRTC_IRQ_VBLANK1;
1279         case 1:
1280                 return AMDGPU_CRTC_IRQ_VBLANK2;
1281         case 2:
1282                 return AMDGPU_CRTC_IRQ_VBLANK3;
1283         case 3:
1284                 return AMDGPU_CRTC_IRQ_VBLANK4;
1285         case 4:
1286                 return AMDGPU_CRTC_IRQ_VBLANK5;
1287         case 5:
1288                 return AMDGPU_CRTC_IRQ_VBLANK6;
1289         default:
1290                 return AMDGPU_CRTC_IRQ_NONE;
1291         }
1292 }
1293
1294 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1295                         bool in_vblank_irq, int *vpos,
1296                         int *hpos, ktime_t *stime, ktime_t *etime,
1297                         const struct drm_display_mode *mode)
1298 {
1299         struct drm_device *dev = crtc->dev;
1300         unsigned int pipe = crtc->index;
1301
1302         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1303                                                   stime, etime, mode);
1304 }