drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  34                        u32 ip_instance, u32 ring,
  35                        struct amdgpu_ring **out_ring)
  36 {
  37         /* Right now all IPs have only one instance - multiple rings. */
  38         if (ip_instance != 0) {
  39                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  40                 return -EINVAL;
  41         }
  42
  43         switch (ip_type) {
  44         default:
  45                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  46                 return -EINVAL;
  47         case AMDGPU_HW_IP_GFX:
  48                 if (ring < adev->gfx.num_gfx_rings) {
  49                         *out_ring = &adev->gfx.gfx_ring[ring];
  50                 } else {
  51                         DRM_ERROR("only %d gfx rings are supported now\n",
  52                                   adev->gfx.num_gfx_rings);
  53                         return -EINVAL;
  54                 }
  55                 break;
  56         case AMDGPU_HW_IP_COMPUTE:
  57                 if (ring < adev->gfx.num_compute_rings) {
  58                         *out_ring = &adev->gfx.compute_ring[ring];
  59                 } else {
  60                         DRM_ERROR("only %d compute rings are supported now\n",
  61                                   adev->gfx.num_compute_rings);
  62                         return -EINVAL;
  63                 }
  64                 break;
  65         case AMDGPU_HW_IP_DMA:
  66                 if (ring < adev->sdma.num_instances) {
  67                         *out_ring = &adev->sdma.instance[ring].ring;
  68                 } else {
  69                         DRM_ERROR("only %d SDMA rings are supported\n",
  70                                   adev->sdma.num_instances);
  71                         return -EINVAL;
  72                 }
  73                 break;
  74         case AMDGPU_HW_IP_UVD:
  75                 *out_ring = &adev->uvd.ring;
  76                 break;
  77         case AMDGPU_HW_IP_VCE:
  78                 if (ring < 2){
  79                         *out_ring = &adev->vce.ring[ring];
  80                 } else {
  81                         DRM_ERROR("only two VCE rings are supported\n");
  82                         return -EINVAL;
  83                 }
  84                 break;
  85         }
  86         return 0;
  87 }
  88
  89 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  90                                       struct drm_amdgpu_cs_chunk_fence *fence_data)
  91 {
  92         struct drm_gem_object *gobj;
  93         uint32_t handle;
  94
  95         handle = fence_data->handle;
  96         gobj = drm_gem_object_lookup(p->adev->ddev, p->filp,
  97                                      fence_data->handle);
  98         if (gobj == NULL)
  99                 return -EINVAL;
 100
 101         p->uf.bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
 102         p->uf.offset = fence_data->offset;
 103
 104         if (amdgpu_ttm_tt_get_usermm(p->uf.bo->tbo.ttm)) {
 105                 drm_gem_object_unreference_unlocked(gobj);
 106                 return -EINVAL;
 107         }
 108
 109         p->uf_entry.robj = amdgpu_bo_ref(p->uf.bo);
 110         p->uf_entry.priority = 0;
 111         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
 112         p->uf_entry.tv.shared = true;
 113
 114         drm_gem_object_unreference_unlocked(gobj);
 115         return 0;
 116 }
 117
 118 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 119 {
 120         union drm_amdgpu_cs *cs = data;
 121         uint64_t *chunk_array_user;
 122         uint64_t *chunk_array;
 123         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 124         unsigned size;
 125         int i;
 126         int ret;
 127
 128         if (cs->in.num_chunks == 0)
 129                 return 0;
 130
 131         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 132         if (!chunk_array)
 133                 return -ENOMEM;
 134
 135         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 136         if (!p->ctx) {
 137                 ret = -EINVAL;
 138                 goto free_chunk;
 139         }
 140
 141         /* get chunks */
 142         chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
 143         if (copy_from_user(chunk_array, chunk_array_user,
 144                            sizeof(uint64_t)*cs->in.num_chunks)) {
 145                 ret = -EFAULT;
 146                 goto put_ctx;
 147         }
 148
 149         p->nchunks = cs->in.num_chunks;
 150         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 151                             GFP_KERNEL);
 152         if (!p->chunks) {
 153                 ret = -ENOMEM;
 154                 goto put_ctx;
 155         }
 156
 157         for (i = 0; i < p->nchunks; i++) {
 158                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 159                 struct drm_amdgpu_cs_chunk user_chunk;
 160                 uint32_t __user *cdata;
 161
 162                 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
 163                 if (copy_from_user(&user_chunk, chunk_ptr,
 164                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 165                         ret = -EFAULT;
 166                         i--;
 167                         goto free_partial_kdata;
 168                 }
 169                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 170                 p->chunks[i].length_dw = user_chunk.length_dw;
 171
 172                 size = p->chunks[i].length_dw;
 173                 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 174
 175                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 176                 if (p->chunks[i].kdata == NULL) {
 177                         ret = -ENOMEM;
 178                         i--;
 179                         goto free_partial_kdata;
 180                 }
 181                 size *= sizeof(uint32_t);
 182                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 183                         ret = -EFAULT;
 184                         goto free_partial_kdata;
 185                 }
 186
 187                 switch (p->chunks[i].chunk_id) {
 188                 case AMDGPU_CHUNK_ID_IB:
 189                         p->num_ibs++;
 190                         break;
 191
 192                 case AMDGPU_CHUNK_ID_FENCE:
 193                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 194                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 195                                 ret = -EINVAL;
 196                                 goto free_partial_kdata;
 197                         }
 198
 199                         ret = amdgpu_cs_user_fence_chunk(p, (void *)p->chunks[i].kdata);
 200                         if (ret)
 201                                 goto free_partial_kdata;
 202
 203                         break;
 204
 205                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 206                         break;
 207
 208                 default:
 209                         ret = -EINVAL;
 210                         goto free_partial_kdata;
 211                 }
 212         }
 213
 214
 215         p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 216         if (!p->ibs) {
 217                 ret = -ENOMEM;
 218                 goto free_all_kdata;
 219         }
 220
 221         kfree(chunk_array);
 222         return 0;
 223
 224 free_all_kdata:
 225         i = p->nchunks - 1;
 226 free_partial_kdata:
 227         for (; i >= 0; i--)
 228                 drm_free_large(p->chunks[i].kdata);
 229         kfree(p->chunks);
 230 put_ctx:
 231         amdgpu_ctx_put(p->ctx);
 232 free_chunk:
 233         kfree(chunk_array);
 234
 235         return ret;
 236 }
 237
 238 /* Returns how many bytes TTM can move per IB.
 239  */
 240 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 241 {
 242         u64 real_vram_size = adev->mc.real_vram_size;
 243         u64 vram_usage = atomic64_read(&adev->vram_usage);
 244
 245         /* This function is based on the current VRAM usage.
 246          *
 247          * - If all of VRAM is free, allow relocating the number of bytes that
 248          *   is equal to 1/4 of the size of VRAM for this IB.
 249
 250          * - If more than one half of VRAM is occupied, only allow relocating
 251          *   1 MB of data for this IB.
 252          *
 253          * - From 0 to one half of used VRAM, the threshold decreases
 254          *   linearly.
 255          *         __________________
 256          * 1/4 of -|\               |
 257          * VRAM    | \              |
 258          *         |  \             |
 259          *         |   \            |
 260          *         |    \           |
 261          *         |     \          |
 262          *         |      \         |
 263          *         |       \________|1 MB
 264          *         |----------------|
 265          *    VRAM 0 %             100 %
 266          *         used            used
 267          *
 268          * Note: It's a threshold, not a limit. The threshold must be crossed
 269          * for buffer relocations to stop, so any buffer of an arbitrary size
 270          * can be moved as long as the threshold isn't crossed before
 271          * the relocation takes place. We don't want to disable buffer
 272          * relocations completely.
 273          *
 274          * The idea is that buffers should be placed in VRAM at creation time
 275          * and TTM should only do a minimum number of relocations during
 276          * command submission. In practice, you need to submit at least
 277          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 278          *
 279          * Also, things can get pretty crazy under memory pressure and actual
 280          * VRAM usage can change a lot, so playing safe even at 50% does
 281          * consistently increase performance.
 282          */
 283
 284         u64 half_vram = real_vram_size >> 1;
 285         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 286         u64 bytes_moved_threshold = half_free_vram >> 1;
 287         return max(bytes_moved_threshold, 1024*1024ull);
 288 }
 289
 290 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 291                             struct list_head *validated)
 292 {
 293         struct amdgpu_bo_list_entry *lobj;
 294         u64 initial_bytes_moved;
 295         int r;
 296
 297         list_for_each_entry(lobj, validated, tv.head) {
 298                 struct amdgpu_bo *bo = lobj->robj;
 299                 struct mm_struct *usermm;
 300                 uint32_t domain;
 301
 302                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 303                 if (usermm && usermm != current->mm)
 304                         return -EPERM;
 305
 306                 if (bo->pin_count)
 307                         continue;
 308
 309                 /* Avoid moving this one if we have moved too many buffers
 310                  * for this IB already.
 311                  *
 312                  * Note that this allows moving at least one buffer of
 313                  * any size, because it doesn't take the current "bo"
 314                  * into account. We don't want to disallow buffer moves
 315                  * completely.
 316                  */
 317                 if (p->bytes_moved <= p->bytes_moved_threshold)
 318                         domain = bo->prefered_domains;
 319                 else
 320                         domain = bo->allowed_domains;
 321
 322         retry:
 323                 amdgpu_ttm_placement_from_domain(bo, domain);
 324                 initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
 325                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 326                 p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
 327                                initial_bytes_moved;
 328
 329                 if (unlikely(r)) {
 330                         if (r != -ERESTARTSYS && domain != bo->allowed_domains) {
 331                                 domain = bo->allowed_domains;
 332                                 goto retry;
 333                         }
 334                         return r;
 335                 }
 336         }
 337         return 0;
 338 }
 339
 340 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 341                                 union drm_amdgpu_cs *cs)
 342 {
 343         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 344         struct list_head duplicates;
 345         bool need_mmap_lock = false;
 346         int r;
 347
 348         INIT_LIST_HEAD(&p->validated);
 349
 350         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 351         if (p->bo_list) {
 352                 need_mmap_lock = p->bo_list->has_userptr;
 353                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 354         }
 355
 356         INIT_LIST_HEAD(&duplicates);
 357         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 358
 359         if (p->uf.bo)
 360                 list_add(&p->uf_entry.tv.head, &p->validated);
 361
 362         if (need_mmap_lock)
 363                 down_read(&current->mm->mmap_sem);
 364
 365         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 366         if (unlikely(r != 0))
 367                 goto error_reserve;
 368
 369         amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
 370
 371         p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
 372         p->bytes_moved = 0;
 373
 374         r = amdgpu_cs_list_validate(p, &duplicates);
 375         if (r)
 376                 goto error_validate;
 377
 378         r = amdgpu_cs_list_validate(p, &p->validated);
 379         if (r)
 380                 goto error_validate;
 381
 382         if (p->bo_list) {
 383                 struct amdgpu_vm *vm = &fpriv->vm;
 384                 unsigned i;
 385
 386                 for (i = 0; i < p->bo_list->num_entries; i++) {
 387                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 388
 389                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 390                 }
 391         }
 392
 393 error_validate:
 394         if (r) {
 395                 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
 396                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 397         }
 398
 399 error_reserve:
 400         if (need_mmap_lock)
 401                 up_read(&current->mm->mmap_sem);
 402
 403         return r;
 404 }
 405
 406 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 407 {
 408         struct amdgpu_bo_list_entry *e;
 409         int r;
 410
 411         list_for_each_entry(e, &p->validated, tv.head) {
 412                 struct reservation_object *resv = e->robj->tbo.resv;
 413                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 414
 415                 if (r)
 416                         return r;
 417         }
 418         return 0;
 419 }
 420
 421 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 422                                   struct list_head *b)
 423 {
 424         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 425         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 426
 427         /* Sort A before B if A is smaller. */
 428         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 429 }
 430
 431 /**
 432  * cs_parser_fini() - clean parser states
 433  * @parser:     parser structure holding parsing context.
 434  * @error:      error number
 435  *
 436  * If error is set than unvalidate buffer, otherwise just free memory
 437  * used by parsing context.
 438  **/
 439 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 440 {
 441         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 442         unsigned i;
 443
 444         if (!error) {
 445                 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
 446
 447                 /* Sort the buffer list from the smallest to largest buffer,
 448                  * which affects the order of buffers in the LRU list.
 449                  * This assures that the smallest buffers are added first
 450                  * to the LRU list, so they are likely to be later evicted
 451                  * first, instead of large buffers whose eviction is more
 452                  * expensive.
 453                  *
 454                  * This slightly lowers the number of bytes moved by TTM
 455                  * per frame under memory pressure.
 456                  */
 457                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 458
 459                 ttm_eu_fence_buffer_objects(&parser->ticket,
 460                                             &parser->validated,
 461                                             parser->fence);
 462         } else if (backoff) {
 463                 ttm_eu_backoff_reservation(&parser->ticket,
 464                                            &parser->validated);
 465         }
 466         fence_put(parser->fence);
 467
 468         if (parser->ctx)
 469                 amdgpu_ctx_put(parser->ctx);
 470         if (parser->bo_list)
 471                 amdgpu_bo_list_put(parser->bo_list);
 472
 473         for (i = 0; i < parser->nchunks; i++)
 474                 drm_free_large(parser->chunks[i].kdata);
 475         kfree(parser->chunks);
 476         if (parser->ibs)
 477                 for (i = 0; i < parser->num_ibs; i++)
 478                         amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 479         kfree(parser->ibs);
 480         amdgpu_bo_unref(&parser->uf.bo);
 481         amdgpu_bo_unref(&parser->uf_entry.robj);
 482 }
 483
 484 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 485                                    struct amdgpu_vm *vm)
 486 {
 487         struct amdgpu_device *adev = p->adev;
 488         struct amdgpu_bo_va *bo_va;
 489         struct amdgpu_bo *bo;
 490         int i, r;
 491
 492         r = amdgpu_vm_update_page_directory(adev, vm);
 493         if (r)
 494                 return r;
 495
 496         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence);
 497         if (r)
 498                 return r;
 499
 500         r = amdgpu_vm_clear_freed(adev, vm);
 501         if (r)
 502                 return r;
 503
 504         if (p->bo_list) {
 505                 for (i = 0; i < p->bo_list->num_entries; i++) {
 506                         struct fence *f;
 507
 508                         /* ignore duplicates */
 509                         bo = p->bo_list->array[i].robj;
 510                         if (!bo)
 511                                 continue;
 512
 513                         bo_va = p->bo_list->array[i].bo_va;
 514                         if (bo_va == NULL)
 515                                 continue;
 516
 517                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 518                         if (r)
 519                                 return r;
 520
 521                         f = bo_va->last_pt_update;
 522                         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
 523                         if (r)
 524                                 return r;
 525                 }
 526
 527         }
 528
 529         r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
 530
 531         if (amdgpu_vm_debug && p->bo_list) {
 532                 /* Invalidate all BOs to test for userspace bugs */
 533                 for (i = 0; i < p->bo_list->num_entries; i++) {
 534                         /* ignore duplicates */
 535                         bo = p->bo_list->array[i].robj;
 536                         if (!bo)
 537                                 continue;
 538
 539                         amdgpu_vm_bo_invalidate(adev, bo);
 540                 }
 541         }
 542
 543         return r;
 544 }
 545
 546 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 547                                  struct amdgpu_cs_parser *parser)
 548 {
 549         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 550         struct amdgpu_vm *vm = &fpriv->vm;
 551         struct amdgpu_ring *ring;
 552         int i, r;
 553
 554         if (parser->num_ibs == 0)
 555                 return 0;
 556
 557         /* Only for UVD/VCE VM emulation */
 558         for (i = 0; i < parser->num_ibs; i++) {
 559                 ring = parser->ibs[i].ring;
 560                 if (ring->funcs->parse_cs) {
 561                         r = amdgpu_ring_parse_cs(ring, parser, i);
 562                         if (r)
 563                                 return r;
 564                 }
 565         }
 566
 567         r = amdgpu_bo_vm_update_pte(parser, vm);
 568         if (!r)
 569                 amdgpu_cs_sync_rings(parser);
 570
 571         return r;
 572 }
 573
 574 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 575 {
 576         if (r == -EDEADLK) {
 577                 r = amdgpu_gpu_reset(adev);
 578                 if (!r)
 579                         r = -EAGAIN;
 580         }
 581         return r;
 582 }
 583
 584 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 585                              struct amdgpu_cs_parser *parser)
 586 {
 587         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 588         struct amdgpu_vm *vm = &fpriv->vm;
 589         int i, j;
 590         int r;
 591
 592         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 593                 struct amdgpu_cs_chunk *chunk;
 594                 struct amdgpu_ib *ib;
 595                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 596                 struct amdgpu_ring *ring;
 597
 598                 chunk = &parser->chunks[i];
 599                 ib = &parser->ibs[j];
 600                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 601
 602                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 603                         continue;
 604
 605                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 606                                        chunk_ib->ip_instance, chunk_ib->ring,
 607                                        &ring);
 608                 if (r)
 609                         return r;
 610
 611                 if (ring->funcs->parse_cs) {
 612                         struct amdgpu_bo_va_mapping *m;
 613                         struct amdgpu_bo *aobj = NULL;
 614                         uint64_t offset;
 615                         uint8_t *kptr;
 616
 617                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 618                                                    &aobj);
 619                         if (!aobj) {
 620                                 DRM_ERROR("IB va_start is invalid\n");
 621                                 return -EINVAL;
 622                         }
 623
 624                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 625                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 626                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 627                                 return -EINVAL;
 628                         }
 629
 630                         /* the IB should be reserved at this point */
 631                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 632                         if (r) {
 633                                 return r;
 634                         }
 635
 636                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 637                         kptr += chunk_ib->va_start - offset;
 638
 639                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 640                         if (r) {
 641                                 DRM_ERROR("Failed to get ib !\n");
 642                                 return r;
 643                         }
 644
 645                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 646                         amdgpu_bo_kunmap(aobj);
 647                 } else {
 648                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 649                         if (r) {
 650                                 DRM_ERROR("Failed to get ib !\n");
 651                                 return r;
 652                         }
 653
 654                         ib->gpu_addr = chunk_ib->va_start;
 655                 }
 656
 657                 ib->length_dw = chunk_ib->ib_bytes / 4;
 658                 ib->flags = chunk_ib->flags;
 659                 ib->ctx = parser->ctx;
 660                 j++;
 661         }
 662
 663         if (!parser->num_ibs)
 664                 return 0;
 665
 666         /* add GDS resources to first IB */
 667         if (parser->bo_list) {
 668                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 669                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 670                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 671                 struct amdgpu_ib *ib = &parser->ibs[0];
 672
 673                 if (gds) {
 674                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 675                         ib->gds_size = amdgpu_bo_size(gds);
 676                 }
 677                 if (gws) {
 678                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 679                         ib->gws_size = amdgpu_bo_size(gws);
 680                 }
 681                 if (oa) {
 682                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 683                         ib->oa_size = amdgpu_bo_size(oa);
 684                 }
 685         }
 686         /* wrap the last IB with user fence */
 687         if (parser->uf.bo) {
 688                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 689
 690                 /* UVD & VCE fw doesn't support user fences */
 691                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 692                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 693                         return -EINVAL;
 694
 695                 ib->user = &parser->uf;
 696         }
 697
 698         return 0;
 699 }
 700
 701 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 702                                   struct amdgpu_cs_parser *p)
 703 {
 704         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 705         struct amdgpu_ib *ib;
 706         int i, j, r;
 707
 708         if (!p->num_ibs)
 709                 return 0;
 710
 711         /* Add dependencies to first IB */
 712         ib = &p->ibs[0];
 713         for (i = 0; i < p->nchunks; ++i) {
 714                 struct drm_amdgpu_cs_chunk_dep *deps;
 715                 struct amdgpu_cs_chunk *chunk;
 716                 unsigned num_deps;
 717
 718                 chunk = &p->chunks[i];
 719
 720                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 721                         continue;
 722
 723                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 724                 num_deps = chunk->length_dw * 4 /
 725                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 726
 727                 for (j = 0; j < num_deps; ++j) {
 728                         struct amdgpu_ring *ring;
 729                         struct amdgpu_ctx *ctx;
 730                         struct fence *fence;
 731
 732                         r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
 733                                                deps[j].ip_instance,
 734                                                deps[j].ring, &ring);
 735                         if (r)
 736                                 return r;
 737
 738                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 739                         if (ctx == NULL)
 740                                 return -EINVAL;
 741
 742                         fence = amdgpu_ctx_get_fence(ctx, ring,
 743                                                      deps[j].handle);
 744                         if (IS_ERR(fence)) {
 745                                 r = PTR_ERR(fence);
 746                                 amdgpu_ctx_put(ctx);
 747                                 return r;
 748
 749                         } else if (fence) {
 750                                 r = amdgpu_sync_fence(adev, &ib->sync, fence);
 751                                 fence_put(fence);
 752                                 amdgpu_ctx_put(ctx);
 753                                 if (r)
 754                                         return r;
 755                         }
 756                 }
 757         }
 758
 759         return 0;
 760 }
 761
 762 static int amdgpu_cs_free_job(struct amdgpu_job *job)
 763 {
 764         int i;
 765         if (job->ibs)
 766                 for (i = 0; i < job->num_ibs; i++)
 767                         amdgpu_ib_free(job->adev, &job->ibs[i]);
 768         kfree(job->ibs);
 769         if (job->uf.bo)
 770                 amdgpu_bo_unref(&job->uf.bo);
 771         return 0;
 772 }
 773
 774 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 775                             union drm_amdgpu_cs *cs)
 776 {
 777         struct amdgpu_ring * ring = p->ibs->ring;
 778         struct amd_sched_fence *fence;
 779         struct amdgpu_job *job;
 780
 781         job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
 782         if (!job)
 783                 return -ENOMEM;
 784
 785         job->base.sched = &ring->sched;
 786         job->base.s_entity = &p->ctx->rings[ring->idx].entity;
 787         job->adev = p->adev;
 788         job->owner = p->filp;
 789         job->free_job = amdgpu_cs_free_job;
 790
 791         job->ibs = p->ibs;
 792         job->num_ibs = p->num_ibs;
 793         p->ibs = NULL;
 794         p->num_ibs = 0;
 795
 796         if (job->ibs[job->num_ibs - 1].user) {
 797                 job->uf = p->uf;
 798                 job->ibs[job->num_ibs - 1].user = &job->uf;
 799                 p->uf.bo = NULL;
 800         }
 801
 802         fence = amd_sched_fence_create(job->base.s_entity, p->filp);
 803         if (!fence) {
 804                 amdgpu_cs_free_job(job);
 805                 kfree(job);
 806                 return -ENOMEM;
 807         }
 808
 809         job->base.s_fence = fence;
 810         p->fence = fence_get(&fence->base);
 811
 812         cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring,
 813                                               &fence->base);
 814         job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
 815
 816         trace_amdgpu_cs_ioctl(job);
 817         amd_sched_entity_push_job(&job->base);
 818
 819         return 0;
 820 }
 821
 822 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 823 {
 824         struct amdgpu_device *adev = dev->dev_private;
 825         union drm_amdgpu_cs *cs = data;
 826         struct amdgpu_cs_parser parser = {};
 827         bool reserved_buffers = false;
 828         int i, r;
 829
 830         if (!adev->accel_working)
 831                 return -EBUSY;
 832
 833         parser.adev = adev;
 834         parser.filp = filp;
 835
 836         r = amdgpu_cs_parser_init(&parser, data);
 837         if (r) {
 838                 DRM_ERROR("Failed to initialize parser !\n");
 839                 amdgpu_cs_parser_fini(&parser, r, false);
 840                 r = amdgpu_cs_handle_lockup(adev, r);
 841                 return r;
 842         }
 843         r = amdgpu_cs_parser_bos(&parser, data);
 844         if (r == -ENOMEM)
 845                 DRM_ERROR("Not enough memory for command submission!\n");
 846         else if (r && r != -ERESTARTSYS)
 847                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 848         else if (!r) {
 849                 reserved_buffers = true;
 850                 r = amdgpu_cs_ib_fill(adev, &parser);
 851         }
 852
 853         if (!r) {
 854                 r = amdgpu_cs_dependencies(adev, &parser);
 855                 if (r)
 856                         DRM_ERROR("Failed in the dependencies handling %d!\n", r);
 857         }
 858
 859         if (r)
 860                 goto out;
 861
 862         for (i = 0; i < parser.num_ibs; i++)
 863                 trace_amdgpu_cs(&parser, i);
 864
 865         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
 866         if (r)
 867                 goto out;
 868
 869         if (parser.num_ibs)
 870                 r = amdgpu_cs_submit(&parser, cs);
 871
 872 out:
 873         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
 874         r = amdgpu_cs_handle_lockup(adev, r);
 875         return r;
 876 }
 877
 878 /**
 879  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 880  *
 881  * @dev: drm device
 882  * @data: data from userspace
 883  * @filp: file private
 884  *
 885  * Wait for the command submission identified by handle to finish.
 886  */
 887 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 888                          struct drm_file *filp)
 889 {
 890         union drm_amdgpu_wait_cs *wait = data;
 891         struct amdgpu_device *adev = dev->dev_private;
 892         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 893         struct amdgpu_ring *ring = NULL;
 894         struct amdgpu_ctx *ctx;
 895         struct fence *fence;
 896         long r;
 897
 898         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 899                                wait->in.ring, &ring);
 900         if (r)
 901                 return r;
 902
 903         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 904         if (ctx == NULL)
 905                 return -EINVAL;
 906
 907         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
 908         if (IS_ERR(fence))
 909                 r = PTR_ERR(fence);
 910         else if (fence) {
 911                 r = fence_wait_timeout(fence, true, timeout);
 912                 fence_put(fence);
 913         } else
 914                 r = 1;
 915
 916         amdgpu_ctx_put(ctx);
 917         if (r < 0)
 918                 return r;
 919
 920         memset(wait, 0, sizeof(*wait));
 921         wait->out.status = (r == 0);
 922
 923         return 0;
 924 }
 925
 926 /**
 927  * amdgpu_cs_find_bo_va - find bo_va for VM address
 928  *
 929  * @parser: command submission parser context
 930  * @addr: VM address
 931  * @bo: resulting BO of the mapping found
 932  *
 933  * Search the buffer objects in the command submission context for a certain
 934  * virtual memory address. Returns allocation structure when found, NULL
 935  * otherwise.
 936  */
 937 struct amdgpu_bo_va_mapping *
 938 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
 939                        uint64_t addr, struct amdgpu_bo **bo)
 940 {
 941         struct amdgpu_bo_va_mapping *mapping;
 942         unsigned i;
 943
 944         if (!parser->bo_list)
 945                 return NULL;
 946
 947         addr /= AMDGPU_GPU_PAGE_SIZE;
 948
 949         for (i = 0; i < parser->bo_list->num_entries; i++) {
 950                 struct amdgpu_bo_list_entry *lobj;
 951
 952                 lobj = &parser->bo_list->array[i];
 953                 if (!lobj->bo_va)
 954                         continue;
 955
 956                 list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
 957                         if (mapping->it.start > addr ||
 958                             addr > mapping->it.last)
 959                                 continue;
 960
 961                         *bo = lobj->bo_va->bo;
 962                         return mapping;
 963                 }
 964
 965                 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
 966                         if (mapping->it.start > addr ||
 967                             addr > mapping->it.last)
 968                                 continue;
 969
 970                         *bo = lobj->bo_va->bo;
 971                         return mapping;
 972                 }
 973         }
 974
 975         return NULL;
 976 }