drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68 #include "amdgpu_dm_replay.h"
  69
  70 #include "ivsrcid/ivsrcid_vislands30.h"
  71
  72 #include <linux/backlight.h>
  73 #include <linux/module.h>
  74 #include <linux/moduleparam.h>
  75 #include <linux/types.h>
  76 #include <linux/pm_runtime.h>
  77 #include <linux/pci.h>
  78 #include <linux/firmware.h>
  79 #include <linux/component.h>
  80 #include <linux/dmi.h>
  81
  82 #include <drm/display/drm_dp_mst_helper.h>
  83 #include <drm/display/drm_hdmi_helper.h>
  84 #include <drm/drm_atomic.h>
  85 #include <drm/drm_atomic_uapi.h>
  86 #include <drm/drm_atomic_helper.h>
  87 #include <drm/drm_blend.h>
  88 #include <drm/drm_fixed.h>
  89 #include <drm/drm_fourcc.h>
  90 #include <drm/drm_edid.h>
  91 #include <drm/drm_eld.h>
  92 #include <drm/drm_vblank.h>
  93 #include <drm/drm_audio_component.h>
  94 #include <drm/drm_gem_atomic_helper.h>
  95
  96 #include <acpi/video.h>
  97
  98 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  99
 100 #include "dcn/dcn_1_0_offset.h"
 101 #include "dcn/dcn_1_0_sh_mask.h"
 102 #include "soc15_hw_ip.h"
 103 #include "soc15_common.h"
 104 #include "vega10_ip_offset.h"
 105
 106 #include "gc/gc_11_0_0_offset.h"
 107 #include "gc/gc_11_0_0_sh_mask.h"
 108
 109 #include "modules/inc/mod_freesync.h"
 110 #include "modules/power/power_helpers.h"
 111
 112 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 114 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 116 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 118 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 120 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 122 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 124 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 126 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 128 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 130 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 132 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 133 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 134
 135 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 137 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 138 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 139
 140 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 141 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 142
 143 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 144 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 145
 146 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
 147 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
 148
 149 /* Number of bytes in PSP header for firmware. */
 150 #define PSP_HEADER_BYTES 0x100
 151
 152 /* Number of bytes in PSP footer for firmware. */
 153 #define PSP_FOOTER_BYTES 0x100
 154
 155 /**
 156  * DOC: overview
 157  *
 158  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 159  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 160  * requests into DC requests, and DC responses into DRM responses.
 161  *
 162  * The root control structure is &struct amdgpu_display_manager.
 163  */
 164
 165 /* basic init/fini API */
 166 static int amdgpu_dm_init(struct amdgpu_device *adev);
 167 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 168 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 169
 170 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 171 {
 172         switch (link->dpcd_caps.dongle_type) {
 173         case DISPLAY_DONGLE_NONE:
 174                 return DRM_MODE_SUBCONNECTOR_Native;
 175         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 176                 return DRM_MODE_SUBCONNECTOR_VGA;
 177         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 178         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 179                 return DRM_MODE_SUBCONNECTOR_DVID;
 180         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 181         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 182                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 183         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 184         default:
 185                 return DRM_MODE_SUBCONNECTOR_Unknown;
 186         }
 187 }
 188
 189 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 190 {
 191         struct dc_link *link = aconnector->dc_link;
 192         struct drm_connector *connector = &aconnector->base;
 193         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 194
 195         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 196                 return;
 197
 198         if (aconnector->dc_sink)
 199                 subconnector = get_subconnector_type(link);
 200
 201         drm_object_property_set_value(&connector->base,
 202                         connector->dev->mode_config.dp_subconnector_property,
 203                         subconnector);
 204 }
 205
 206 /*
 207  * initializes drm_device display related structures, based on the information
 208  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 209  * drm_encoder, drm_mode_config
 210  *
 211  * Returns 0 on success
 212  */
 213 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 214 /* removes and deallocates the drm structures, created by the above function */
 215 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 216
 217 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 218                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 219                                     u32 link_index,
 220                                     struct amdgpu_encoder *amdgpu_encoder);
 221 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 222                                   struct amdgpu_encoder *aencoder,
 223                                   uint32_t link_index);
 224
 225 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 226
 227 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 228
 229 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 230                                   struct drm_atomic_state *state);
 231
 232 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 233 static void handle_hpd_rx_irq(void *param);
 234
 235 static bool
 236 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 237                                  struct drm_crtc_state *new_crtc_state);
 238 /*
 239  * dm_vblank_get_counter
 240  *
 241  * @brief
 242  * Get counter for number of vertical blanks
 243  *
 244  * @param
 245  * struct amdgpu_device *adev - [in] desired amdgpu device
 246  * int disp_idx - [in] which CRTC to get the counter from
 247  *
 248  * @return
 249  * Counter for vertical blanks
 250  */
 251 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 252 {
 253         struct amdgpu_crtc *acrtc = NULL;
 254
 255         if (crtc >= adev->mode_info.num_crtc)
 256                 return 0;
 257
 258         acrtc = adev->mode_info.crtcs[crtc];
 259
 260         if (!acrtc->dm_irq_params.stream) {
 261                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 262                           crtc);
 263                 return 0;
 264         }
 265
 266         return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 267 }
 268
 269 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 270                                   u32 *vbl, u32 *position)
 271 {
 272         u32 v_blank_start, v_blank_end, h_position, v_position;
 273         struct amdgpu_crtc *acrtc = NULL;
 274
 275         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 276                 return -EINVAL;
 277
 278         acrtc = adev->mode_info.crtcs[crtc];
 279
 280         if (!acrtc->dm_irq_params.stream) {
 281                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 282                           crtc);
 283                 return 0;
 284         }
 285
 286         /*
 287          * TODO rework base driver to use values directly.
 288          * for now parse it back into reg-format
 289          */
 290         dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 291                                  &v_blank_start,
 292                                  &v_blank_end,
 293                                  &h_position,
 294                                  &v_position);
 295
 296         *position = v_position | (h_position << 16);
 297         *vbl = v_blank_start | (v_blank_end << 16);
 298
 299         return 0;
 300 }
 301
 302 static bool dm_is_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return true;
 306 }
 307
 308 static int dm_wait_for_idle(void *handle)
 309 {
 310         /* XXX todo */
 311         return 0;
 312 }
 313
 314 static bool dm_check_soft_reset(void *handle)
 315 {
 316         return false;
 317 }
 318
 319 static int dm_soft_reset(void *handle)
 320 {
 321         /* XXX todo */
 322         return 0;
 323 }
 324
 325 static struct amdgpu_crtc *
 326 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 327                      int otg_inst)
 328 {
 329         struct drm_device *dev = adev_to_drm(adev);
 330         struct drm_crtc *crtc;
 331         struct amdgpu_crtc *amdgpu_crtc;
 332
 333         if (WARN_ON(otg_inst == -1))
 334                 return adev->mode_info.crtcs[0];
 335
 336         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 337                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 338
 339                 if (amdgpu_crtc->otg_inst == otg_inst)
 340                         return amdgpu_crtc;
 341         }
 342
 343         return NULL;
 344 }
 345
 346 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 347                                               struct dm_crtc_state *new_state)
 348 {
 349         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 350                 return true;
 351         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 352                 return true;
 353         else
 354                 return false;
 355 }
 356
 357 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 358                                         int planes_count)
 359 {
 360         int i, j;
 361
 362         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 363                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 364 }
 365
 366 /**
 367  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 368  *
 369  * DC has a generic way to update planes and stream via
 370  * dc_update_planes_and_stream function; however, DM might need some
 371  * adjustments and preparation before calling it. This function is a wrapper
 372  * for the dc_update_planes_and_stream that does any required configuration
 373  * before passing control to DC.
 374  *
 375  * @dc: Display Core control structure
 376  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 377  * @planes_count: planes count to update
 378  * @stream: stream state
 379  * @stream_update: stream update
 380  * @array_of_surface_update: dc surface update pointer
 381  *
 382  */
 383 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 384                                                     int update_type,
 385                                                     int planes_count,
 386                                                     struct dc_stream_state *stream,
 387                                                     struct dc_stream_update *stream_update,
 388                                                     struct dc_surface_update *array_of_surface_update)
 389 {
 390         reverse_planes_order(array_of_surface_update, planes_count);
 391
 392         /*
 393          * Previous frame finished and HW is ready for optimization.
 394          */
 395         if (update_type == UPDATE_TYPE_FAST)
 396                 dc_post_update_surfaces_to_stream(dc);
 397
 398         return dc_update_planes_and_stream(dc,
 399                                            array_of_surface_update,
 400                                            planes_count,
 401                                            stream,
 402                                            stream_update);
 403 }
 404
 405 /**
 406  * dm_pflip_high_irq() - Handle pageflip interrupt
 407  * @interrupt_params: ignored
 408  *
 409  * Handles the pageflip interrupt by notifying all interested parties
 410  * that the pageflip has been completed.
 411  */
 412 static void dm_pflip_high_irq(void *interrupt_params)
 413 {
 414         struct amdgpu_crtc *amdgpu_crtc;
 415         struct common_irq_params *irq_params = interrupt_params;
 416         struct amdgpu_device *adev = irq_params->adev;
 417         struct drm_device *dev = adev_to_drm(adev);
 418         unsigned long flags;
 419         struct drm_pending_vblank_event *e;
 420         u32 vpos, hpos, v_blank_start, v_blank_end;
 421         bool vrr_active;
 422
 423         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 424
 425         /* IRQ could occur when in initial stage */
 426         /* TODO work and BO cleanup */
 427         if (amdgpu_crtc == NULL) {
 428                 drm_dbg_state(dev, "CRTC is null, returning.\n");
 429                 return;
 430         }
 431
 432         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 433
 434         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 435                 drm_dbg_state(dev,
 436                               "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
 437                               amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
 438                               amdgpu_crtc->crtc_id, amdgpu_crtc);
 439                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 440                 return;
 441         }
 442
 443         /* page flip completed. */
 444         e = amdgpu_crtc->event;
 445         amdgpu_crtc->event = NULL;
 446
 447         WARN_ON(!e);
 448
 449         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 450
 451         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 452         if (!vrr_active ||
 453             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 454                                       &v_blank_end, &hpos, &vpos) ||
 455             (vpos < v_blank_start)) {
 456                 /* Update to correct count and vblank timestamp if racing with
 457                  * vblank irq. This also updates to the correct vblank timestamp
 458                  * even in VRR mode, as scanout is past the front-porch atm.
 459                  */
 460                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 461
 462                 /* Wake up userspace by sending the pageflip event with proper
 463                  * count and timestamp of vblank of flip completion.
 464                  */
 465                 if (e) {
 466                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 467
 468                         /* Event sent, so done with vblank for this flip */
 469                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 470                 }
 471         } else if (e) {
 472                 /* VRR active and inside front-porch: vblank count and
 473                  * timestamp for pageflip event will only be up to date after
 474                  * drm_crtc_handle_vblank() has been executed from late vblank
 475                  * irq handler after start of back-porch (vline 0). We queue the
 476                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 477                  * updated timestamp and count, once it runs after us.
 478                  *
 479                  * We need to open-code this instead of using the helper
 480                  * drm_crtc_arm_vblank_event(), as that helper would
 481                  * call drm_crtc_accurate_vblank_count(), which we must
 482                  * not call in VRR mode while we are in front-porch!
 483                  */
 484
 485                 /* sequence will be replaced by real count during send-out. */
 486                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 487                 e->pipe = amdgpu_crtc->crtc_id;
 488
 489                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 490                 e = NULL;
 491         }
 492
 493         /* Keep track of vblank of this flip for flip throttling. We use the
 494          * cooked hw counter, as that one incremented at start of this vblank
 495          * of pageflip completion, so last_flip_vblank is the forbidden count
 496          * for queueing new pageflips if vsync + VRR is enabled.
 497          */
 498         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 499                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 500
 501         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 502         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 503
 504         drm_dbg_state(dev,
 505                       "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 506                       amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
 507 }
 508
 509 static void dm_vupdate_high_irq(void *interrupt_params)
 510 {
 511         struct common_irq_params *irq_params = interrupt_params;
 512         struct amdgpu_device *adev = irq_params->adev;
 513         struct amdgpu_crtc *acrtc;
 514         struct drm_device *drm_dev;
 515         struct drm_vblank_crtc *vblank;
 516         ktime_t frame_duration_ns, previous_timestamp;
 517         unsigned long flags;
 518         int vrr_active;
 519
 520         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 521
 522         if (acrtc) {
 523                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 524                 drm_dev = acrtc->base.dev;
 525                 vblank = &drm_dev->vblank[acrtc->base.index];
 526                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 527                 frame_duration_ns = vblank->time - previous_timestamp;
 528
 529                 if (frame_duration_ns > 0) {
 530                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 531                                                 frame_duration_ns,
 532                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 533                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 534                 }
 535
 536                 drm_dbg_vbl(drm_dev,
 537                             "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 538                             vrr_active);
 539
 540                 /* Core vblank handling is done here after end of front-porch in
 541                  * vrr mode, as vblank timestamping will give valid results
 542                  * while now done after front-porch. This will also deliver
 543                  * page-flip completion events that have been queued to us
 544                  * if a pageflip happened inside front-porch.
 545                  */
 546                 if (vrr_active) {
 547                         amdgpu_dm_crtc_handle_vblank(acrtc);
 548
 549                         /* BTR processing for pre-DCE12 ASICs */
 550                         if (acrtc->dm_irq_params.stream &&
 551                             adev->family < AMDGPU_FAMILY_AI) {
 552                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 553                                 mod_freesync_handle_v_update(
 554                                     adev->dm.freesync_module,
 555                                     acrtc->dm_irq_params.stream,
 556                                     &acrtc->dm_irq_params.vrr_params);
 557
 558                                 dc_stream_adjust_vmin_vmax(
 559                                     adev->dm.dc,
 560                                     acrtc->dm_irq_params.stream,
 561                                     &acrtc->dm_irq_params.vrr_params.adjust);
 562                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 563                         }
 564                 }
 565         }
 566 }
 567
 568 /**
 569  * dm_crtc_high_irq() - Handles CRTC interrupt
 570  * @interrupt_params: used for determining the CRTC instance
 571  *
 572  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 573  * event handler.
 574  */
 575 static void dm_crtc_high_irq(void *interrupt_params)
 576 {
 577         struct common_irq_params *irq_params = interrupt_params;
 578         struct amdgpu_device *adev = irq_params->adev;
 579         struct amdgpu_crtc *acrtc;
 580         unsigned long flags;
 581         int vrr_active;
 582
 583         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 584         if (!acrtc)
 585                 return;
 586
 587         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 588
 589         drm_dbg_vbl(adev_to_drm(adev),
 590                     "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 591                     vrr_active, acrtc->dm_irq_params.active_planes);
 592
 593         /**
 594          * Core vblank handling at start of front-porch is only possible
 595          * in non-vrr mode, as only there vblank timestamping will give
 596          * valid results while done in front-porch. Otherwise defer it
 597          * to dm_vupdate_high_irq after end of front-porch.
 598          */
 599         if (!vrr_active)
 600                 amdgpu_dm_crtc_handle_vblank(acrtc);
 601
 602         /**
 603          * Following stuff must happen at start of vblank, for crc
 604          * computation and below-the-range btr support in vrr mode.
 605          */
 606         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 607
 608         /* BTR updates need to happen before VUPDATE on Vega and above. */
 609         if (adev->family < AMDGPU_FAMILY_AI)
 610                 return;
 611
 612         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 613
 614         if (acrtc->dm_irq_params.stream &&
 615             acrtc->dm_irq_params.vrr_params.supported &&
 616             acrtc->dm_irq_params.freesync_config.state ==
 617                     VRR_STATE_ACTIVE_VARIABLE) {
 618                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 619                                              acrtc->dm_irq_params.stream,
 620                                              &acrtc->dm_irq_params.vrr_params);
 621
 622                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 623                                            &acrtc->dm_irq_params.vrr_params.adjust);
 624         }
 625
 626         /*
 627          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 628          * In that case, pageflip completion interrupts won't fire and pageflip
 629          * completion events won't get delivered. Prevent this by sending
 630          * pending pageflip events from here if a flip is still pending.
 631          *
 632          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 633          * avoid race conditions between flip programming and completion,
 634          * which could cause too early flip completion events.
 635          */
 636         if (adev->family >= AMDGPU_FAMILY_RV &&
 637             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 638             acrtc->dm_irq_params.active_planes == 0) {
 639                 if (acrtc->event) {
 640                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 641                         acrtc->event = NULL;
 642                         drm_crtc_vblank_put(&acrtc->base);
 643                 }
 644                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 645         }
 646
 647         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 648 }
 649
 650 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 651 /**
 652  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 653  * DCN generation ASICs
 654  * @interrupt_params: interrupt parameters
 655  *
 656  * Used to set crc window/read out crc value at vertical line 0 position
 657  */
 658 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 659 {
 660         struct common_irq_params *irq_params = interrupt_params;
 661         struct amdgpu_device *adev = irq_params->adev;
 662         struct amdgpu_crtc *acrtc;
 663
 664         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 665
 666         if (!acrtc)
 667                 return;
 668
 669         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 670 }
 671 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 672
 673 /**
 674  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 675  * @adev: amdgpu_device pointer
 676  * @notify: dmub notification structure
 677  *
 678  * Dmub AUX or SET_CONFIG command completion processing callback
 679  * Copies dmub notification to DM which is to be read by AUX command.
 680  * issuing thread and also signals the event to wake up the thread.
 681  */
 682 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 683                                         struct dmub_notification *notify)
 684 {
 685         if (adev->dm.dmub_notify)
 686                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 687         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 688                 complete(&adev->dm.dmub_aux_transfer_done);
 689 }
 690
 691 /**
 692  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 693  * @adev: amdgpu_device pointer
 694  * @notify: dmub notification structure
 695  *
 696  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 697  * ink index and calls helper to do the processing.
 698  */
 699 static void dmub_hpd_callback(struct amdgpu_device *adev,
 700                               struct dmub_notification *notify)
 701 {
 702         struct amdgpu_dm_connector *aconnector;
 703         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 704         struct drm_connector *connector;
 705         struct drm_connector_list_iter iter;
 706         struct dc_link *link;
 707         u8 link_index = 0;
 708         struct drm_device *dev;
 709
 710         if (adev == NULL)
 711                 return;
 712
 713         if (notify == NULL) {
 714                 DRM_ERROR("DMUB HPD callback notification was NULL");
 715                 return;
 716         }
 717
 718         if (notify->link_index > adev->dm.dc->link_count) {
 719                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 720                 return;
 721         }
 722
 723         link_index = notify->link_index;
 724         link = adev->dm.dc->links[link_index];
 725         dev = adev->dm.ddev;
 726
 727         drm_connector_list_iter_begin(dev, &iter);
 728         drm_for_each_connector_iter(connector, &iter) {
 729                 aconnector = to_amdgpu_dm_connector(connector);
 730                 if (link && aconnector->dc_link == link) {
 731                         if (notify->type == DMUB_NOTIFICATION_HPD)
 732                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 733                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 734                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 735                         else
 736                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 737                                                 notify->type, link_index);
 738
 739                         hpd_aconnector = aconnector;
 740                         break;
 741                 }
 742         }
 743         drm_connector_list_iter_end(&iter);
 744
 745         if (hpd_aconnector) {
 746                 if (notify->type == DMUB_NOTIFICATION_HPD)
 747                         handle_hpd_irq_helper(hpd_aconnector);
 748                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 749                         handle_hpd_rx_irq(hpd_aconnector);
 750         }
 751 }
 752
 753 /**
 754  * register_dmub_notify_callback - Sets callback for DMUB notify
 755  * @adev: amdgpu_device pointer
 756  * @type: Type of dmub notification
 757  * @callback: Dmub interrupt callback function
 758  * @dmub_int_thread_offload: offload indicator
 759  *
 760  * API to register a dmub callback handler for a dmub notification
 761  * Also sets indicator whether callback processing to be offloaded.
 762  * to dmub interrupt handling thread
 763  * Return: true if successfully registered, false if there is existing registration
 764  */
 765 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 766                                           enum dmub_notification_type type,
 767                                           dmub_notify_interrupt_callback_t callback,
 768                                           bool dmub_int_thread_offload)
 769 {
 770         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 771                 adev->dm.dmub_callback[type] = callback;
 772                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 773         } else
 774                 return false;
 775
 776         return true;
 777 }
 778
 779 static void dm_handle_hpd_work(struct work_struct *work)
 780 {
 781         struct dmub_hpd_work *dmub_hpd_wrk;
 782
 783         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 784
 785         if (!dmub_hpd_wrk->dmub_notify) {
 786                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 787                 return;
 788         }
 789
 790         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 791                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 792                 dmub_hpd_wrk->dmub_notify);
 793         }
 794
 795         kfree(dmub_hpd_wrk->dmub_notify);
 796         kfree(dmub_hpd_wrk);
 797
 798 }
 799
 800 #define DMUB_TRACE_MAX_READ 64
 801 /**
 802  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 803  * @interrupt_params: used for determining the Outbox instance
 804  *
 805  * Handles the Outbox Interrupt
 806  * event handler.
 807  */
 808 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 809 {
 810         struct dmub_notification notify;
 811         struct common_irq_params *irq_params = interrupt_params;
 812         struct amdgpu_device *adev = irq_params->adev;
 813         struct amdgpu_display_manager *dm = &adev->dm;
 814         struct dmcub_trace_buf_entry entry = { 0 };
 815         u32 count = 0;
 816         struct dmub_hpd_work *dmub_hpd_wrk;
 817         struct dc_link *plink = NULL;
 818
 819         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 820                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 821
 822                 do {
 823                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 824                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 825                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 826                                 continue;
 827                         }
 828                         if (!dm->dmub_callback[notify.type]) {
 829                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 830                                 continue;
 831                         }
 832                         if (dm->dmub_thread_offload[notify.type] == true) {
 833                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 834                                 if (!dmub_hpd_wrk) {
 835                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 836                                         return;
 837                                 }
 838                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 839                                                                     GFP_ATOMIC);
 840                                 if (!dmub_hpd_wrk->dmub_notify) {
 841                                         kfree(dmub_hpd_wrk);
 842                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 843                                         return;
 844                                 }
 845                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 846                                 dmub_hpd_wrk->adev = adev;
 847                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 848                                         plink = adev->dm.dc->links[notify.link_index];
 849                                         if (plink) {
 850                                                 plink->hpd_status =
 851                                                         notify.hpd_status == DP_HPD_PLUG;
 852                                         }
 853                                 }
 854                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 855                         } else {
 856                                 dm->dmub_callback[notify.type](adev, &notify);
 857                         }
 858                 } while (notify.pending_notification);
 859         }
 860
 861
 862         do {
 863                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 864                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 865                                                         entry.param0, entry.param1);
 866
 867                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 868                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 869                 } else
 870                         break;
 871
 872                 count++;
 873
 874         } while (count <= DMUB_TRACE_MAX_READ);
 875
 876         if (count > DMUB_TRACE_MAX_READ)
 877                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 878 }
 879
 880 static int dm_set_clockgating_state(void *handle,
 881                   enum amd_clockgating_state state)
 882 {
 883         return 0;
 884 }
 885
 886 static int dm_set_powergating_state(void *handle,
 887                   enum amd_powergating_state state)
 888 {
 889         return 0;
 890 }
 891
 892 /* Prototypes of private functions */
 893 static int dm_early_init(void *handle);
 894
 895 /* Allocate memory for FBC compressed data  */
 896 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 897 {
 898         struct drm_device *dev = connector->dev;
 899         struct amdgpu_device *adev = drm_to_adev(dev);
 900         struct dm_compressor_info *compressor = &adev->dm.compressor;
 901         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 902         struct drm_display_mode *mode;
 903         unsigned long max_size = 0;
 904
 905         if (adev->dm.dc->fbc_compressor == NULL)
 906                 return;
 907
 908         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 909                 return;
 910
 911         if (compressor->bo_ptr)
 912                 return;
 913
 914
 915         list_for_each_entry(mode, &connector->modes, head) {
 916                 if (max_size < mode->htotal * mode->vtotal)
 917                         max_size = mode->htotal * mode->vtotal;
 918         }
 919
 920         if (max_size) {
 921                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 922                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 923                             &compressor->gpu_addr, &compressor->cpu_addr);
 924
 925                 if (r)
 926                         DRM_ERROR("DM: Failed to initialize FBC\n");
 927                 else {
 928                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 929                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 930                 }
 931
 932         }
 933
 934 }
 935
 936 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 937                                           int pipe, bool *enabled,
 938                                           unsigned char *buf, int max_bytes)
 939 {
 940         struct drm_device *dev = dev_get_drvdata(kdev);
 941         struct amdgpu_device *adev = drm_to_adev(dev);
 942         struct drm_connector *connector;
 943         struct drm_connector_list_iter conn_iter;
 944         struct amdgpu_dm_connector *aconnector;
 945         int ret = 0;
 946
 947         *enabled = false;
 948
 949         mutex_lock(&adev->dm.audio_lock);
 950
 951         drm_connector_list_iter_begin(dev, &conn_iter);
 952         drm_for_each_connector_iter(connector, &conn_iter) {
 953                 aconnector = to_amdgpu_dm_connector(connector);
 954                 if (aconnector->audio_inst != port)
 955                         continue;
 956
 957                 *enabled = true;
 958                 ret = drm_eld_size(connector->eld);
 959                 memcpy(buf, connector->eld, min(max_bytes, ret));
 960
 961                 break;
 962         }
 963         drm_connector_list_iter_end(&conn_iter);
 964
 965         mutex_unlock(&adev->dm.audio_lock);
 966
 967         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 968
 969         return ret;
 970 }
 971
 972 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 973         .get_eld = amdgpu_dm_audio_component_get_eld,
 974 };
 975
 976 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 977                                        struct device *hda_kdev, void *data)
 978 {
 979         struct drm_device *dev = dev_get_drvdata(kdev);
 980         struct amdgpu_device *adev = drm_to_adev(dev);
 981         struct drm_audio_component *acomp = data;
 982
 983         acomp->ops = &amdgpu_dm_audio_component_ops;
 984         acomp->dev = kdev;
 985         adev->dm.audio_component = acomp;
 986
 987         return 0;
 988 }
 989
 990 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 991                                           struct device *hda_kdev, void *data)
 992 {
 993         struct drm_device *dev = dev_get_drvdata(kdev);
 994         struct amdgpu_device *adev = drm_to_adev(dev);
 995         struct drm_audio_component *acomp = data;
 996
 997         acomp->ops = NULL;
 998         acomp->dev = NULL;
 999         adev->dm.audio_component = NULL;
1000 }
1001
1002 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1003         .bind   = amdgpu_dm_audio_component_bind,
1004         .unbind = amdgpu_dm_audio_component_unbind,
1005 };
1006
1007 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1008 {
1009         int i, ret;
1010
1011         if (!amdgpu_audio)
1012                 return 0;
1013
1014         adev->mode_info.audio.enabled = true;
1015
1016         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1017
1018         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1019                 adev->mode_info.audio.pin[i].channels = -1;
1020                 adev->mode_info.audio.pin[i].rate = -1;
1021                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1022                 adev->mode_info.audio.pin[i].status_bits = 0;
1023                 adev->mode_info.audio.pin[i].category_code = 0;
1024                 adev->mode_info.audio.pin[i].connected = false;
1025                 adev->mode_info.audio.pin[i].id =
1026                         adev->dm.dc->res_pool->audios[i]->inst;
1027                 adev->mode_info.audio.pin[i].offset = 0;
1028         }
1029
1030         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1031         if (ret < 0)
1032                 return ret;
1033
1034         adev->dm.audio_registered = true;
1035
1036         return 0;
1037 }
1038
1039 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1040 {
1041         if (!amdgpu_audio)
1042                 return;
1043
1044         if (!adev->mode_info.audio.enabled)
1045                 return;
1046
1047         if (adev->dm.audio_registered) {
1048                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1049                 adev->dm.audio_registered = false;
1050         }
1051
1052         /* TODO: Disable audio? */
1053
1054         adev->mode_info.audio.enabled = false;
1055 }
1056
1057 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1058 {
1059         struct drm_audio_component *acomp = adev->dm.audio_component;
1060
1061         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1062                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1063
1064                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1065                                                  pin, -1);
1066         }
1067 }
1068
1069 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1070 {
1071         const struct dmcub_firmware_header_v1_0 *hdr;
1072         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1073         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1074         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1075         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1076         struct abm *abm = adev->dm.dc->res_pool->abm;
1077         struct dc_context *ctx = adev->dm.dc->ctx;
1078         struct dmub_srv_hw_params hw_params;
1079         enum dmub_status status;
1080         const unsigned char *fw_inst_const, *fw_bss_data;
1081         u32 i, fw_inst_const_size, fw_bss_data_size;
1082         bool has_hw_support;
1083
1084         if (!dmub_srv)
1085                 /* DMUB isn't supported on the ASIC. */
1086                 return 0;
1087
1088         if (!fb_info) {
1089                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1090                 return -EINVAL;
1091         }
1092
1093         if (!dmub_fw) {
1094                 /* Firmware required for DMUB support. */
1095                 DRM_ERROR("No firmware provided for DMUB.\n");
1096                 return -EINVAL;
1097         }
1098
1099         /* initialize register offsets for ASICs with runtime initialization available */
1100         if (dmub_srv->hw_funcs.init_reg_offsets)
1101                 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1102
1103         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1104         if (status != DMUB_STATUS_OK) {
1105                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1106                 return -EINVAL;
1107         }
1108
1109         if (!has_hw_support) {
1110                 DRM_INFO("DMUB unsupported on ASIC\n");
1111                 return 0;
1112         }
1113
1114         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1115         status = dmub_srv_hw_reset(dmub_srv);
1116         if (status != DMUB_STATUS_OK)
1117                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1118
1119         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1120
1121         fw_inst_const = dmub_fw->data +
1122                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1123                         PSP_HEADER_BYTES;
1124
1125         fw_bss_data = dmub_fw->data +
1126                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1127                       le32_to_cpu(hdr->inst_const_bytes);
1128
1129         /* Copy firmware and bios info into FB memory. */
1130         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1131                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1132
1133         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1134
1135         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1136          * amdgpu_ucode_init_single_fw will load dmub firmware
1137          * fw_inst_const part to cw0; otherwise, the firmware back door load
1138          * will be done by dm_dmub_hw_init
1139          */
1140         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1141                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1142                                 fw_inst_const_size);
1143         }
1144
1145         if (fw_bss_data_size)
1146                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1147                        fw_bss_data, fw_bss_data_size);
1148
1149         /* Copy firmware bios info into FB memory. */
1150         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1151                adev->bios_size);
1152
1153         /* Reset regions that need to be reset. */
1154         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1155         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1156
1157         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1158                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1159
1160         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1161                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1162
1163         /* Initialize hardware. */
1164         memset(&hw_params, 0, sizeof(hw_params));
1165         hw_params.fb_base = adev->gmc.fb_start;
1166         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1167
1168         /* backdoor load firmware and trigger dmub running */
1169         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1170                 hw_params.load_inst_const = true;
1171
1172         if (dmcu)
1173                 hw_params.psp_version = dmcu->psp_version;
1174
1175         for (i = 0; i < fb_info->num_fb; ++i)
1176                 hw_params.fb[i] = &fb_info->fb[i];
1177
1178         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1179         case IP_VERSION(3, 1, 3):
1180         case IP_VERSION(3, 1, 4):
1181         case IP_VERSION(3, 5, 0):
1182                 hw_params.dpia_supported = true;
1183                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1184                 break;
1185         default:
1186                 break;
1187         }
1188
1189         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1190         if (status != DMUB_STATUS_OK) {
1191                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1192                 return -EINVAL;
1193         }
1194
1195         /* Wait for firmware load to finish. */
1196         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1197         if (status != DMUB_STATUS_OK)
1198                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1199
1200         /* Init DMCU and ABM if available. */
1201         if (dmcu && abm) {
1202                 dmcu->funcs->dmcu_init(dmcu);
1203                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1204         }
1205
1206         if (!adev->dm.dc->ctx->dmub_srv)
1207                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1208         if (!adev->dm.dc->ctx->dmub_srv) {
1209                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1210                 return -ENOMEM;
1211         }
1212
1213         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1214                  adev->dm.dmcub_fw_version);
1215
1216         return 0;
1217 }
1218
1219 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1220 {
1221         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1222         enum dmub_status status;
1223         bool init;
1224
1225         if (!dmub_srv) {
1226                 /* DMUB isn't supported on the ASIC. */
1227                 return;
1228         }
1229
1230         status = dmub_srv_is_hw_init(dmub_srv, &init);
1231         if (status != DMUB_STATUS_OK)
1232                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1233
1234         if (status == DMUB_STATUS_OK && init) {
1235                 /* Wait for firmware load to finish. */
1236                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1237                 if (status != DMUB_STATUS_OK)
1238                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1239         } else {
1240                 /* Perform the full hardware initialization. */
1241                 dm_dmub_hw_init(adev);
1242         }
1243 }
1244
1245 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1246 {
1247         u64 pt_base;
1248         u32 logical_addr_low;
1249         u32 logical_addr_high;
1250         u32 agp_base, agp_bot, agp_top;
1251         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1252
1253         memset(pa_config, 0, sizeof(*pa_config));
1254
1255         agp_base = 0;
1256         agp_bot = adev->gmc.agp_start >> 24;
1257         agp_top = adev->gmc.agp_end >> 24;
1258
1259         /* AGP aperture is disabled */
1260         if (agp_bot > agp_top) {
1261                 logical_addr_low = adev->gmc.fb_start >> 18;
1262                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1263                         /*
1264                          * Raven2 has a HW issue that it is unable to use the vram which
1265                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1266                          * workaround that increase system aperture high address (add 1)
1267                          * to get rid of the VM fault and hardware hang.
1268                          */
1269                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1270                 else
1271                         logical_addr_high = adev->gmc.fb_end >> 18;
1272         } else {
1273                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1274                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1275                         /*
1276                          * Raven2 has a HW issue that it is unable to use the vram which
1277                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1278                          * workaround that increase system aperture high address (add 1)
1279                          * to get rid of the VM fault and hardware hang.
1280                          */
1281                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1282                 else
1283                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1284         }
1285
1286         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1287
1288         page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1289                                                    AMDGPU_GPU_PAGE_SHIFT);
1290         page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1291                                                   AMDGPU_GPU_PAGE_SHIFT);
1292         page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1293                                                  AMDGPU_GPU_PAGE_SHIFT);
1294         page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1295                                                 AMDGPU_GPU_PAGE_SHIFT);
1296         page_table_base.high_part = upper_32_bits(pt_base);
1297         page_table_base.low_part = lower_32_bits(pt_base);
1298
1299         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1300         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1301
1302         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1303         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1304         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1305
1306         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1307         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1308         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1309
1310         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1311         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1312         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1313
1314         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1315
1316 }
1317
1318 static void force_connector_state(
1319         struct amdgpu_dm_connector *aconnector,
1320         enum drm_connector_force force_state)
1321 {
1322         struct drm_connector *connector = &aconnector->base;
1323
1324         mutex_lock(&connector->dev->mode_config.mutex);
1325         aconnector->base.force = force_state;
1326         mutex_unlock(&connector->dev->mode_config.mutex);
1327
1328         mutex_lock(&aconnector->hpd_lock);
1329         drm_kms_helper_connector_hotplug_event(connector);
1330         mutex_unlock(&aconnector->hpd_lock);
1331 }
1332
1333 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1334 {
1335         struct hpd_rx_irq_offload_work *offload_work;
1336         struct amdgpu_dm_connector *aconnector;
1337         struct dc_link *dc_link;
1338         struct amdgpu_device *adev;
1339         enum dc_connection_type new_connection_type = dc_connection_none;
1340         unsigned long flags;
1341         union test_response test_response;
1342
1343         memset(&test_response, 0, sizeof(test_response));
1344
1345         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1346         aconnector = offload_work->offload_wq->aconnector;
1347
1348         if (!aconnector) {
1349                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1350                 goto skip;
1351         }
1352
1353         adev = drm_to_adev(aconnector->base.dev);
1354         dc_link = aconnector->dc_link;
1355
1356         mutex_lock(&aconnector->hpd_lock);
1357         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1358                 DRM_ERROR("KMS: Failed to detect connector\n");
1359         mutex_unlock(&aconnector->hpd_lock);
1360
1361         if (new_connection_type == dc_connection_none)
1362                 goto skip;
1363
1364         if (amdgpu_in_reset(adev))
1365                 goto skip;
1366
1367         if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1368                 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1369                 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1370                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1371                 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1372                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1373                 goto skip;
1374         }
1375
1376         mutex_lock(&adev->dm.dc_lock);
1377         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1378                 dc_link_dp_handle_automated_test(dc_link);
1379
1380                 if (aconnector->timing_changed) {
1381                         /* force connector disconnect and reconnect */
1382                         force_connector_state(aconnector, DRM_FORCE_OFF);
1383                         msleep(100);
1384                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1385                 }
1386
1387                 test_response.bits.ACK = 1;
1388
1389                 core_link_write_dpcd(
1390                 dc_link,
1391                 DP_TEST_RESPONSE,
1392                 &test_response.raw,
1393                 sizeof(test_response));
1394         } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1395                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1396                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1397                 /* offload_work->data is from handle_hpd_rx_irq->
1398                  * schedule_hpd_rx_offload_work.this is defer handle
1399                  * for hpd short pulse. upon here, link status may be
1400                  * changed, need get latest link status from dpcd
1401                  * registers. if link status is good, skip run link
1402                  * training again.
1403                  */
1404                 union hpd_irq_data irq_data;
1405
1406                 memset(&irq_data, 0, sizeof(irq_data));
1407
1408                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1409                  * request be added to work queue if link lost at end of dc_link_
1410                  * dp_handle_link_loss
1411                  */
1412                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1413                 offload_work->offload_wq->is_handling_link_loss = false;
1414                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1415
1416                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1417                         dc_link_check_link_loss_status(dc_link, &irq_data))
1418                         dc_link_dp_handle_link_loss(dc_link);
1419         }
1420         mutex_unlock(&adev->dm.dc_lock);
1421
1422 skip:
1423         kfree(offload_work);
1424
1425 }
1426
1427 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1428 {
1429         int max_caps = dc->caps.max_links;
1430         int i = 0;
1431         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1432
1433         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1434
1435         if (!hpd_rx_offload_wq)
1436                 return NULL;
1437
1438
1439         for (i = 0; i < max_caps; i++) {
1440                 hpd_rx_offload_wq[i].wq =
1441                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1442
1443                 if (hpd_rx_offload_wq[i].wq == NULL) {
1444                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1445                         goto out_err;
1446                 }
1447
1448                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1449         }
1450
1451         return hpd_rx_offload_wq;
1452
1453 out_err:
1454         for (i = 0; i < max_caps; i++) {
1455                 if (hpd_rx_offload_wq[i].wq)
1456                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1457         }
1458         kfree(hpd_rx_offload_wq);
1459         return NULL;
1460 }
1461
1462 struct amdgpu_stutter_quirk {
1463         u16 chip_vendor;
1464         u16 chip_device;
1465         u16 subsys_vendor;
1466         u16 subsys_device;
1467         u8 revision;
1468 };
1469
1470 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1471         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1472         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1473         { 0, 0, 0, 0, 0 },
1474 };
1475
1476 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1477 {
1478         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1479
1480         while (p && p->chip_device != 0) {
1481                 if (pdev->vendor == p->chip_vendor &&
1482                     pdev->device == p->chip_device &&
1483                     pdev->subsystem_vendor == p->subsys_vendor &&
1484                     pdev->subsystem_device == p->subsys_device &&
1485                     pdev->revision == p->revision) {
1486                         return true;
1487                 }
1488                 ++p;
1489         }
1490         return false;
1491 }
1492
1493 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1494         {
1495                 .matches = {
1496                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1497                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1498                 },
1499         },
1500         {
1501                 .matches = {
1502                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1503                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1504                 },
1505         },
1506         {
1507                 .matches = {
1508                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1509                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1510                 },
1511         },
1512         {
1513                 .matches = {
1514                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1515                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1516                 },
1517         },
1518         {
1519                 .matches = {
1520                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1521                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1522                 },
1523         },
1524         {
1525                 .matches = {
1526                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1527                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1528                 },
1529         },
1530         {
1531                 .matches = {
1532                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1533                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1534                 },
1535         },
1536         {
1537                 .matches = {
1538                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1539                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1540                 },
1541         },
1542         {
1543                 .matches = {
1544                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1545                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1546                 },
1547         },
1548         {}
1549         /* TODO: refactor this from a fixed table to a dynamic option */
1550 };
1551
1552 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1553 {
1554         const struct dmi_system_id *dmi_id;
1555
1556         dm->aux_hpd_discon_quirk = false;
1557
1558         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1559         if (dmi_id) {
1560                 dm->aux_hpd_discon_quirk = true;
1561                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1562         }
1563 }
1564
1565 static int amdgpu_dm_init(struct amdgpu_device *adev)
1566 {
1567         struct dc_init_data init_data;
1568         struct dc_callback_init init_params;
1569         int r;
1570
1571         adev->dm.ddev = adev_to_drm(adev);
1572         adev->dm.adev = adev;
1573
1574         /* Zero all the fields */
1575         memset(&init_data, 0, sizeof(init_data));
1576         memset(&init_params, 0, sizeof(init_params));
1577
1578         mutex_init(&adev->dm.dpia_aux_lock);
1579         mutex_init(&adev->dm.dc_lock);
1580         mutex_init(&adev->dm.audio_lock);
1581
1582         if (amdgpu_dm_irq_init(adev)) {
1583                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1584                 goto error;
1585         }
1586
1587         init_data.asic_id.chip_family = adev->family;
1588
1589         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1590         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1591         init_data.asic_id.chip_id = adev->pdev->device;
1592
1593         init_data.asic_id.vram_width = adev->gmc.vram_width;
1594         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1595         init_data.asic_id.atombios_base_address =
1596                 adev->mode_info.atom_context->bios;
1597
1598         init_data.driver = adev;
1599
1600         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1601
1602         if (!adev->dm.cgs_device) {
1603                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1604                 goto error;
1605         }
1606
1607         init_data.cgs_device = adev->dm.cgs_device;
1608
1609         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1610
1611         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1612         case IP_VERSION(2, 1, 0):
1613                 switch (adev->dm.dmcub_fw_version) {
1614                 case 0: /* development */
1615                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1616                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1617                         init_data.flags.disable_dmcu = false;
1618                         break;
1619                 default:
1620                         init_data.flags.disable_dmcu = true;
1621                 }
1622                 break;
1623         case IP_VERSION(2, 0, 3):
1624                 init_data.flags.disable_dmcu = true;
1625                 break;
1626         default:
1627                 break;
1628         }
1629
1630         /* APU support S/G display by default except:
1631          * ASICs before Carrizo,
1632          * RAVEN1 (Users reported stability issue)
1633          */
1634
1635         if (adev->asic_type < CHIP_CARRIZO) {
1636                 init_data.flags.gpu_vm_support = false;
1637         } else if (adev->asic_type == CHIP_RAVEN) {
1638                 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1639                         init_data.flags.gpu_vm_support = false;
1640                 else
1641                         init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1642         } else {
1643                 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1644         }
1645
1646         adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1647
1648         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1649                 init_data.flags.fbc_support = true;
1650
1651         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1652                 init_data.flags.multi_mon_pp_mclk_switch = true;
1653
1654         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1655                 init_data.flags.disable_fractional_pwm = true;
1656
1657         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1658                 init_data.flags.edp_no_power_sequencing = true;
1659
1660         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1661                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1662         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1663                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1664
1665         init_data.flags.seamless_boot_edp_requested = false;
1666
1667         if (amdgpu_device_seamless_boot_supported(adev)) {
1668                 init_data.flags.seamless_boot_edp_requested = true;
1669                 init_data.flags.allow_seamless_boot_optimization = true;
1670                 DRM_INFO("Seamless boot condition check passed\n");
1671         }
1672
1673         init_data.flags.enable_mipi_converter_optimization = true;
1674
1675         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1676         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1677         init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1678
1679         INIT_LIST_HEAD(&adev->dm.da_list);
1680
1681         retrieve_dmi_info(&adev->dm);
1682
1683         /* Display Core create. */
1684         adev->dm.dc = dc_create(&init_data);
1685
1686         if (adev->dm.dc) {
1687                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1688                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1689         } else {
1690                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1691                 goto error;
1692         }
1693
1694         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1695                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1696                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1697         }
1698
1699         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1700                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1701         if (dm_should_disable_stutter(adev->pdev))
1702                 adev->dm.dc->debug.disable_stutter = true;
1703
1704         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1705                 adev->dm.dc->debug.disable_stutter = true;
1706
1707         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1708                 adev->dm.dc->debug.disable_dsc = true;
1709
1710         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1711                 adev->dm.dc->debug.disable_clock_gate = true;
1712
1713         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1714                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1715
1716         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1717
1718         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1719         adev->dm.dc->debug.ignore_cable_id = true;
1720
1721         /* TODO: There is a new drm mst change where the freedom of
1722          * vc_next_start_slot update is revoked/moved into drm, instead of in
1723          * driver. This forces us to make sure to get vc_next_start_slot updated
1724          * in drm function each time without considering if mst_state is active
1725          * or not. Otherwise, next time hotplug will give wrong start_slot
1726          * number. We are implementing a temporary solution to even notify drm
1727          * mst deallocation when link is no longer of MST type when uncommitting
1728          * the stream so we will have more time to work on a proper solution.
1729          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1730          * should notify drm to do a complete "reset" of its states and stop
1731          * calling further drm mst functions when link is no longer of an MST
1732          * type. This could happen when we unplug an MST hubs/displays. When
1733          * uncommit stream comes later after unplug, we should just reset
1734          * hardware states only.
1735          */
1736         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1737
1738         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1739                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1740
1741         r = dm_dmub_hw_init(adev);
1742         if (r) {
1743                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1744                 goto error;
1745         }
1746
1747         dc_hardware_init(adev->dm.dc);
1748
1749         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1750         if (!adev->dm.hpd_rx_offload_wq) {
1751                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1752                 goto error;
1753         }
1754
1755         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1756                 struct dc_phy_addr_space_config pa_config;
1757
1758                 mmhub_read_system_context(adev, &pa_config);
1759
1760                 // Call the DC init_memory func
1761                 dc_setup_system_context(adev->dm.dc, &pa_config);
1762         }
1763
1764         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1765         if (!adev->dm.freesync_module) {
1766                 DRM_ERROR(
1767                 "amdgpu: failed to initialize freesync_module.\n");
1768         } else
1769                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1770                                 adev->dm.freesync_module);
1771
1772         amdgpu_dm_init_color_mod();
1773
1774         if (adev->dm.dc->caps.max_links > 0) {
1775                 adev->dm.vblank_control_workqueue =
1776                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1777                 if (!adev->dm.vblank_control_workqueue)
1778                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1779         }
1780
1781         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1782                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1783
1784                 if (!adev->dm.hdcp_workqueue)
1785                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1786                 else
1787                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1788
1789                 dc_init_callbacks(adev->dm.dc, &init_params);
1790         }
1791         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1792                 init_completion(&adev->dm.dmub_aux_transfer_done);
1793                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1794                 if (!adev->dm.dmub_notify) {
1795                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1796                         goto error;
1797                 }
1798
1799                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1800                 if (!adev->dm.delayed_hpd_wq) {
1801                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1802                         goto error;
1803                 }
1804
1805                 amdgpu_dm_outbox_init(adev);
1806                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1807                         dmub_aux_setconfig_callback, false)) {
1808                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1809                         goto error;
1810                 }
1811                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1812                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1813                         goto error;
1814                 }
1815                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1816                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1817                         goto error;
1818                 }
1819         }
1820
1821         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1822          * It is expected that DMUB will resend any pending notifications at this point, for
1823          * example HPD from DPIA.
1824          */
1825         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1826                 dc_enable_dmub_outbox(adev->dm.dc);
1827
1828                 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1829                 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1830                         dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1831         }
1832
1833         if (amdgpu_dm_initialize_drm_device(adev)) {
1834                 DRM_ERROR(
1835                 "amdgpu: failed to initialize sw for display support.\n");
1836                 goto error;
1837         }
1838
1839         /* create fake encoders for MST */
1840         dm_dp_create_fake_mst_encoders(adev);
1841
1842         /* TODO: Add_display_info? */
1843
1844         /* TODO use dynamic cursor width */
1845         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1846         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1847
1848         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1849                 DRM_ERROR(
1850                 "amdgpu: failed to initialize sw for display support.\n");
1851                 goto error;
1852         }
1853
1854 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1855         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1856         if (!adev->dm.secure_display_ctxs)
1857                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1858 #endif
1859
1860         DRM_DEBUG_DRIVER("KMS initialized.\n");
1861
1862         return 0;
1863 error:
1864         amdgpu_dm_fini(adev);
1865
1866         return -EINVAL;
1867 }
1868
1869 static int amdgpu_dm_early_fini(void *handle)
1870 {
1871         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1872
1873         amdgpu_dm_audio_fini(adev);
1874
1875         return 0;
1876 }
1877
1878 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1879 {
1880         int i;
1881
1882         if (adev->dm.vblank_control_workqueue) {
1883                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1884                 adev->dm.vblank_control_workqueue = NULL;
1885         }
1886
1887         amdgpu_dm_destroy_drm_device(&adev->dm);
1888
1889 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1890         if (adev->dm.secure_display_ctxs) {
1891                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1892                         if (adev->dm.secure_display_ctxs[i].crtc) {
1893                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1894                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1895                         }
1896                 }
1897                 kfree(adev->dm.secure_display_ctxs);
1898                 adev->dm.secure_display_ctxs = NULL;
1899         }
1900 #endif
1901         if (adev->dm.hdcp_workqueue) {
1902                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1903                 adev->dm.hdcp_workqueue = NULL;
1904         }
1905
1906         if (adev->dm.dc)
1907                 dc_deinit_callbacks(adev->dm.dc);
1908
1909         if (adev->dm.dc)
1910                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1911
1912         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1913                 kfree(adev->dm.dmub_notify);
1914                 adev->dm.dmub_notify = NULL;
1915                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1916                 adev->dm.delayed_hpd_wq = NULL;
1917         }
1918
1919         if (adev->dm.dmub_bo)
1920                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1921                                       &adev->dm.dmub_bo_gpu_addr,
1922                                       &adev->dm.dmub_bo_cpu_addr);
1923
1924         if (adev->dm.hpd_rx_offload_wq) {
1925                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1926                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1927                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1928                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1929                         }
1930                 }
1931
1932                 kfree(adev->dm.hpd_rx_offload_wq);
1933                 adev->dm.hpd_rx_offload_wq = NULL;
1934         }
1935
1936         /* DC Destroy TODO: Replace destroy DAL */
1937         if (adev->dm.dc)
1938                 dc_destroy(&adev->dm.dc);
1939         /*
1940          * TODO: pageflip, vlank interrupt
1941          *
1942          * amdgpu_dm_irq_fini(adev);
1943          */
1944
1945         if (adev->dm.cgs_device) {
1946                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1947                 adev->dm.cgs_device = NULL;
1948         }
1949         if (adev->dm.freesync_module) {
1950                 mod_freesync_destroy(adev->dm.freesync_module);
1951                 adev->dm.freesync_module = NULL;
1952         }
1953
1954         mutex_destroy(&adev->dm.audio_lock);
1955         mutex_destroy(&adev->dm.dc_lock);
1956         mutex_destroy(&adev->dm.dpia_aux_lock);
1957 }
1958
1959 static int load_dmcu_fw(struct amdgpu_device *adev)
1960 {
1961         const char *fw_name_dmcu = NULL;
1962         int r;
1963         const struct dmcu_firmware_header_v1_0 *hdr;
1964
1965         switch (adev->asic_type) {
1966 #if defined(CONFIG_DRM_AMD_DC_SI)
1967         case CHIP_TAHITI:
1968         case CHIP_PITCAIRN:
1969         case CHIP_VERDE:
1970         case CHIP_OLAND:
1971 #endif
1972         case CHIP_BONAIRE:
1973         case CHIP_HAWAII:
1974         case CHIP_KAVERI:
1975         case CHIP_KABINI:
1976         case CHIP_MULLINS:
1977         case CHIP_TONGA:
1978         case CHIP_FIJI:
1979         case CHIP_CARRIZO:
1980         case CHIP_STONEY:
1981         case CHIP_POLARIS11:
1982         case CHIP_POLARIS10:
1983         case CHIP_POLARIS12:
1984         case CHIP_VEGAM:
1985         case CHIP_VEGA10:
1986         case CHIP_VEGA12:
1987         case CHIP_VEGA20:
1988                 return 0;
1989         case CHIP_NAVI12:
1990                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1991                 break;
1992         case CHIP_RAVEN:
1993                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1994                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1995                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1996                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1997                 else
1998                         return 0;
1999                 break;
2000         default:
2001                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2002                 case IP_VERSION(2, 0, 2):
2003                 case IP_VERSION(2, 0, 3):
2004                 case IP_VERSION(2, 0, 0):
2005                 case IP_VERSION(2, 1, 0):
2006                 case IP_VERSION(3, 0, 0):
2007                 case IP_VERSION(3, 0, 2):
2008                 case IP_VERSION(3, 0, 3):
2009                 case IP_VERSION(3, 0, 1):
2010                 case IP_VERSION(3, 1, 2):
2011                 case IP_VERSION(3, 1, 3):
2012                 case IP_VERSION(3, 1, 4):
2013                 case IP_VERSION(3, 1, 5):
2014                 case IP_VERSION(3, 1, 6):
2015                 case IP_VERSION(3, 2, 0):
2016                 case IP_VERSION(3, 2, 1):
2017                 case IP_VERSION(3, 5, 0):
2018                         return 0;
2019                 default:
2020                         break;
2021                 }
2022                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2023                 return -EINVAL;
2024         }
2025
2026         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2027                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2028                 return 0;
2029         }
2030
2031         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2032         if (r == -ENODEV) {
2033                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2034                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2035                 adev->dm.fw_dmcu = NULL;
2036                 return 0;
2037         }
2038         if (r) {
2039                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2040                         fw_name_dmcu);
2041                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2042                 return r;
2043         }
2044
2045         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2046         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2047         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2048         adev->firmware.fw_size +=
2049                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2050
2051         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2052         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2053         adev->firmware.fw_size +=
2054                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2055
2056         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2057
2058         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2059
2060         return 0;
2061 }
2062
2063 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2064 {
2065         struct amdgpu_device *adev = ctx;
2066
2067         return dm_read_reg(adev->dm.dc->ctx, address);
2068 }
2069
2070 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2071                                      uint32_t value)
2072 {
2073         struct amdgpu_device *adev = ctx;
2074
2075         return dm_write_reg(adev->dm.dc->ctx, address, value);
2076 }
2077
2078 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2079 {
2080         struct dmub_srv_create_params create_params;
2081         struct dmub_srv_region_params region_params;
2082         struct dmub_srv_region_info region_info;
2083         struct dmub_srv_memory_params memory_params;
2084         struct dmub_srv_fb_info *fb_info;
2085         struct dmub_srv *dmub_srv;
2086         const struct dmcub_firmware_header_v1_0 *hdr;
2087         enum dmub_asic dmub_asic;
2088         enum dmub_status status;
2089         int r;
2090
2091         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2092         case IP_VERSION(2, 1, 0):
2093                 dmub_asic = DMUB_ASIC_DCN21;
2094                 break;
2095         case IP_VERSION(3, 0, 0):
2096                 dmub_asic = DMUB_ASIC_DCN30;
2097                 break;
2098         case IP_VERSION(3, 0, 1):
2099                 dmub_asic = DMUB_ASIC_DCN301;
2100                 break;
2101         case IP_VERSION(3, 0, 2):
2102                 dmub_asic = DMUB_ASIC_DCN302;
2103                 break;
2104         case IP_VERSION(3, 0, 3):
2105                 dmub_asic = DMUB_ASIC_DCN303;
2106                 break;
2107         case IP_VERSION(3, 1, 2):
2108         case IP_VERSION(3, 1, 3):
2109                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2110                 break;
2111         case IP_VERSION(3, 1, 4):
2112                 dmub_asic = DMUB_ASIC_DCN314;
2113                 break;
2114         case IP_VERSION(3, 1, 5):
2115                 dmub_asic = DMUB_ASIC_DCN315;
2116                 break;
2117         case IP_VERSION(3, 1, 6):
2118                 dmub_asic = DMUB_ASIC_DCN316;
2119                 break;
2120         case IP_VERSION(3, 2, 0):
2121                 dmub_asic = DMUB_ASIC_DCN32;
2122                 break;
2123         case IP_VERSION(3, 2, 1):
2124                 dmub_asic = DMUB_ASIC_DCN321;
2125                 break;
2126         case IP_VERSION(3, 5, 0):
2127                 dmub_asic = DMUB_ASIC_DCN35;
2128                 break;
2129         default:
2130                 /* ASIC doesn't support DMUB. */
2131                 return 0;
2132         }
2133
2134         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2135         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2136
2137         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2138                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2139                         AMDGPU_UCODE_ID_DMCUB;
2140                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2141                         adev->dm.dmub_fw;
2142                 adev->firmware.fw_size +=
2143                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2144
2145                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2146                          adev->dm.dmcub_fw_version);
2147         }
2148
2149
2150         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2151         dmub_srv = adev->dm.dmub_srv;
2152
2153         if (!dmub_srv) {
2154                 DRM_ERROR("Failed to allocate DMUB service!\n");
2155                 return -ENOMEM;
2156         }
2157
2158         memset(&create_params, 0, sizeof(create_params));
2159         create_params.user_ctx = adev;
2160         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2161         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2162         create_params.asic = dmub_asic;
2163
2164         /* Create the DMUB service. */
2165         status = dmub_srv_create(dmub_srv, &create_params);
2166         if (status != DMUB_STATUS_OK) {
2167                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2168                 return -EINVAL;
2169         }
2170
2171         /* Calculate the size of all the regions for the DMUB service. */
2172         memset(&region_params, 0, sizeof(region_params));
2173
2174         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2175                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2176         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2177         region_params.vbios_size = adev->bios_size;
2178         region_params.fw_bss_data = region_params.bss_data_size ?
2179                 adev->dm.dmub_fw->data +
2180                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2181                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2182         region_params.fw_inst_const =
2183                 adev->dm.dmub_fw->data +
2184                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2185                 PSP_HEADER_BYTES;
2186         region_params.is_mailbox_in_inbox = false;
2187
2188         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2189                                            &region_info);
2190
2191         if (status != DMUB_STATUS_OK) {
2192                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2193                 return -EINVAL;
2194         }
2195
2196         /*
2197          * Allocate a framebuffer based on the total size of all the regions.
2198          * TODO: Move this into GART.
2199          */
2200         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2201                                     AMDGPU_GEM_DOMAIN_VRAM |
2202                                     AMDGPU_GEM_DOMAIN_GTT,
2203                                     &adev->dm.dmub_bo,
2204                                     &adev->dm.dmub_bo_gpu_addr,
2205                                     &adev->dm.dmub_bo_cpu_addr);
2206         if (r)
2207                 return r;
2208
2209         /* Rebase the regions on the framebuffer address. */
2210         memset(&memory_params, 0, sizeof(memory_params));
2211         memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
2212         memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
2213         memory_params.region_info = &region_info;
2214
2215         adev->dm.dmub_fb_info =
2216                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2217         fb_info = adev->dm.dmub_fb_info;
2218
2219         if (!fb_info) {
2220                 DRM_ERROR(
2221                         "Failed to allocate framebuffer info for DMUB service!\n");
2222                 return -ENOMEM;
2223         }
2224
2225         status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
2226         if (status != DMUB_STATUS_OK) {
2227                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2228                 return -EINVAL;
2229         }
2230
2231         return 0;
2232 }
2233
2234 static int dm_sw_init(void *handle)
2235 {
2236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2237         int r;
2238
2239         r = dm_dmub_sw_init(adev);
2240         if (r)
2241                 return r;
2242
2243         return load_dmcu_fw(adev);
2244 }
2245
2246 static int dm_sw_fini(void *handle)
2247 {
2248         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2249
2250         kfree(adev->dm.dmub_fb_info);
2251         adev->dm.dmub_fb_info = NULL;
2252
2253         if (adev->dm.dmub_srv) {
2254                 dmub_srv_destroy(adev->dm.dmub_srv);
2255                 adev->dm.dmub_srv = NULL;
2256         }
2257
2258         amdgpu_ucode_release(&adev->dm.dmub_fw);
2259         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2260
2261         return 0;
2262 }
2263
2264 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2265 {
2266         struct amdgpu_dm_connector *aconnector;
2267         struct drm_connector *connector;
2268         struct drm_connector_list_iter iter;
2269         int ret = 0;
2270
2271         drm_connector_list_iter_begin(dev, &iter);
2272         drm_for_each_connector_iter(connector, &iter) {
2273                 aconnector = to_amdgpu_dm_connector(connector);
2274                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2275                     aconnector->mst_mgr.aux) {
2276                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2277                                          aconnector,
2278                                          aconnector->base.base.id);
2279
2280                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2281                         if (ret < 0) {
2282                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2283                                 aconnector->dc_link->type =
2284                                         dc_connection_single;
2285                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2286                                                                      aconnector->dc_link);
2287                                 break;
2288                         }
2289                 }
2290         }
2291         drm_connector_list_iter_end(&iter);
2292
2293         return ret;
2294 }
2295
2296 static int dm_late_init(void *handle)
2297 {
2298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2299
2300         struct dmcu_iram_parameters params;
2301         unsigned int linear_lut[16];
2302         int i;
2303         struct dmcu *dmcu = NULL;
2304
2305         dmcu = adev->dm.dc->res_pool->dmcu;
2306
2307         for (i = 0; i < 16; i++)
2308                 linear_lut[i] = 0xFFFF * i / 15;
2309
2310         params.set = 0;
2311         params.backlight_ramping_override = false;
2312         params.backlight_ramping_start = 0xCCCC;
2313         params.backlight_ramping_reduction = 0xCCCCCCCC;
2314         params.backlight_lut_array_size = 16;
2315         params.backlight_lut_array = linear_lut;
2316
2317         /* Min backlight level after ABM reduction,  Don't allow below 1%
2318          * 0xFFFF x 0.01 = 0x28F
2319          */
2320         params.min_abm_backlight = 0x28F;
2321         /* In the case where abm is implemented on dmcub,
2322          * dmcu object will be null.
2323          * ABM 2.4 and up are implemented on dmcub.
2324          */
2325         if (dmcu) {
2326                 if (!dmcu_load_iram(dmcu, params))
2327                         return -EINVAL;
2328         } else if (adev->dm.dc->ctx->dmub_srv) {
2329                 struct dc_link *edp_links[MAX_NUM_EDP];
2330                 int edp_num;
2331
2332                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2333                 for (i = 0; i < edp_num; i++) {
2334                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2335                                 return -EINVAL;
2336                 }
2337         }
2338
2339         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2340 }
2341
2342 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2343 {
2344         int ret;
2345         u8 guid[16];
2346         u64 tmp64;
2347
2348         mutex_lock(&mgr->lock);
2349         if (!mgr->mst_primary)
2350                 goto out_fail;
2351
2352         if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2353                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2354                 goto out_fail;
2355         }
2356
2357         ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2358                                  DP_MST_EN |
2359                                  DP_UP_REQ_EN |
2360                                  DP_UPSTREAM_IS_SRC);
2361         if (ret < 0) {
2362                 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2363                 goto out_fail;
2364         }
2365
2366         /* Some hubs forget their guids after they resume */
2367         ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2368         if (ret != 16) {
2369                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2370                 goto out_fail;
2371         }
2372
2373         if (memchr_inv(guid, 0, 16) == NULL) {
2374                 tmp64 = get_jiffies_64();
2375                 memcpy(&guid[0], &tmp64, sizeof(u64));
2376                 memcpy(&guid[8], &tmp64, sizeof(u64));
2377
2378                 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2379
2380                 if (ret != 16) {
2381                         drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2382                         goto out_fail;
2383                 }
2384         }
2385
2386         memcpy(mgr->mst_primary->guid, guid, 16);
2387
2388 out_fail:
2389         mutex_unlock(&mgr->lock);
2390 }
2391
2392 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2393 {
2394         struct amdgpu_dm_connector *aconnector;
2395         struct drm_connector *connector;
2396         struct drm_connector_list_iter iter;
2397         struct drm_dp_mst_topology_mgr *mgr;
2398
2399         drm_connector_list_iter_begin(dev, &iter);
2400         drm_for_each_connector_iter(connector, &iter) {
2401                 aconnector = to_amdgpu_dm_connector(connector);
2402                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2403                     aconnector->mst_root)
2404                         continue;
2405
2406                 mgr = &aconnector->mst_mgr;
2407
2408                 if (suspend) {
2409                         drm_dp_mst_topology_mgr_suspend(mgr);
2410                 } else {
2411                         /* if extended timeout is supported in hardware,
2412                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2413                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2414                          */
2415                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2416                         if (!dp_is_lttpr_present(aconnector->dc_link))
2417                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2418
2419                         /* TODO: move resume_mst_branch_status() into drm mst resume again
2420                          * once topology probing work is pulled out from mst resume into mst
2421                          * resume 2nd step. mst resume 2nd step should be called after old
2422                          * state getting restored (i.e. drm_atomic_helper_resume()).
2423                          */
2424                         resume_mst_branch_status(mgr);
2425                 }
2426         }
2427         drm_connector_list_iter_end(&iter);
2428 }
2429
2430 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2431 {
2432         int ret = 0;
2433
2434         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2435          * on window driver dc implementation.
2436          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2437          * should be passed to smu during boot up and resume from s3.
2438          * boot up: dc calculate dcn watermark clock settings within dc_create,
2439          * dcn20_resource_construct
2440          * then call pplib functions below to pass the settings to smu:
2441          * smu_set_watermarks_for_clock_ranges
2442          * smu_set_watermarks_table
2443          * navi10_set_watermarks_table
2444          * smu_write_watermarks_table
2445          *
2446          * For Renoir, clock settings of dcn watermark are also fixed values.
2447          * dc has implemented different flow for window driver:
2448          * dc_hardware_init / dc_set_power_state
2449          * dcn10_init_hw
2450          * notify_wm_ranges
2451          * set_wm_ranges
2452          * -- Linux
2453          * smu_set_watermarks_for_clock_ranges
2454          * renoir_set_watermarks_table
2455          * smu_write_watermarks_table
2456          *
2457          * For Linux,
2458          * dc_hardware_init -> amdgpu_dm_init
2459          * dc_set_power_state --> dm_resume
2460          *
2461          * therefore, this function apply to navi10/12/14 but not Renoir
2462          * *
2463          */
2464         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2465         case IP_VERSION(2, 0, 2):
2466         case IP_VERSION(2, 0, 0):
2467                 break;
2468         default:
2469                 return 0;
2470         }
2471
2472         ret = amdgpu_dpm_write_watermarks_table(adev);
2473         if (ret) {
2474                 DRM_ERROR("Failed to update WMTABLE!\n");
2475                 return ret;
2476         }
2477
2478         return 0;
2479 }
2480
2481 /**
2482  * dm_hw_init() - Initialize DC device
2483  * @handle: The base driver device containing the amdgpu_dm device.
2484  *
2485  * Initialize the &struct amdgpu_display_manager device. This involves calling
2486  * the initializers of each DM component, then populating the struct with them.
2487  *
2488  * Although the function implies hardware initialization, both hardware and
2489  * software are initialized here. Splitting them out to their relevant init
2490  * hooks is a future TODO item.
2491  *
2492  * Some notable things that are initialized here:
2493  *
2494  * - Display Core, both software and hardware
2495  * - DC modules that we need (freesync and color management)
2496  * - DRM software states
2497  * - Interrupt sources and handlers
2498  * - Vblank support
2499  * - Debug FS entries, if enabled
2500  */
2501 static int dm_hw_init(void *handle)
2502 {
2503         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2504         /* Create DAL display manager */
2505         amdgpu_dm_init(adev);
2506         amdgpu_dm_hpd_init(adev);
2507
2508         return 0;
2509 }
2510
2511 /**
2512  * dm_hw_fini() - Teardown DC device
2513  * @handle: The base driver device containing the amdgpu_dm device.
2514  *
2515  * Teardown components within &struct amdgpu_display_manager that require
2516  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2517  * were loaded. Also flush IRQ workqueues and disable them.
2518  */
2519 static int dm_hw_fini(void *handle)
2520 {
2521         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2522
2523         amdgpu_dm_hpd_fini(adev);
2524
2525         amdgpu_dm_irq_fini(adev);
2526         amdgpu_dm_fini(adev);
2527         return 0;
2528 }
2529
2530
2531 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2532                                  struct dc_state *state, bool enable)
2533 {
2534         enum dc_irq_source irq_source;
2535         struct amdgpu_crtc *acrtc;
2536         int rc = -EBUSY;
2537         int i = 0;
2538
2539         for (i = 0; i < state->stream_count; i++) {
2540                 acrtc = get_crtc_by_otg_inst(
2541                                 adev, state->stream_status[i].primary_otg_inst);
2542
2543                 if (acrtc && state->stream_status[i].plane_count != 0) {
2544                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2545                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2546                         if (rc)
2547                                 DRM_WARN("Failed to %s pflip interrupts\n",
2548                                          enable ? "enable" : "disable");
2549
2550                         if (enable) {
2551                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2552                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2553                         } else
2554                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2555
2556                         if (rc)
2557                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2558
2559                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2560                         /* During gpu-reset we disable and then enable vblank irq, so
2561                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2562                          */
2563                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2564                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2565                 }
2566         }
2567
2568 }
2569
2570 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2571 {
2572         struct dc_state *context = NULL;
2573         enum dc_status res = DC_ERROR_UNEXPECTED;
2574         int i;
2575         struct dc_stream_state *del_streams[MAX_PIPES];
2576         int del_streams_count = 0;
2577
2578         memset(del_streams, 0, sizeof(del_streams));
2579
2580         context = dc_create_state(dc);
2581         if (context == NULL)
2582                 goto context_alloc_fail;
2583
2584         dc_resource_state_copy_construct_current(dc, context);
2585
2586         /* First remove from context all streams */
2587         for (i = 0; i < context->stream_count; i++) {
2588                 struct dc_stream_state *stream = context->streams[i];
2589
2590                 del_streams[del_streams_count++] = stream;
2591         }
2592
2593         /* Remove all planes for removed streams and then remove the streams */
2594         for (i = 0; i < del_streams_count; i++) {
2595                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2596                         res = DC_FAIL_DETACH_SURFACES;
2597                         goto fail;
2598                 }
2599
2600                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2601                 if (res != DC_OK)
2602                         goto fail;
2603         }
2604
2605         res = dc_commit_streams(dc, context->streams, context->stream_count);
2606
2607 fail:
2608         dc_release_state(context);
2609
2610 context_alloc_fail:
2611         return res;
2612 }
2613
2614 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2615 {
2616         int i;
2617
2618         if (dm->hpd_rx_offload_wq) {
2619                 for (i = 0; i < dm->dc->caps.max_links; i++)
2620                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2621         }
2622 }
2623
2624 static int dm_suspend(void *handle)
2625 {
2626         struct amdgpu_device *adev = handle;
2627         struct amdgpu_display_manager *dm = &adev->dm;
2628         int ret = 0;
2629
2630         if (amdgpu_in_reset(adev)) {
2631                 mutex_lock(&dm->dc_lock);
2632
2633                 dc_allow_idle_optimizations(adev->dm.dc, false);
2634
2635                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2636
2637                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2638
2639                 amdgpu_dm_commit_zero_streams(dm->dc);
2640
2641                 amdgpu_dm_irq_suspend(adev);
2642
2643                 hpd_rx_irq_work_suspend(dm);
2644
2645                 return ret;
2646         }
2647
2648         WARN_ON(adev->dm.cached_state);
2649         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2650         if (IS_ERR(adev->dm.cached_state))
2651                 return PTR_ERR(adev->dm.cached_state);
2652
2653         s3_handle_mst(adev_to_drm(adev), true);
2654
2655         amdgpu_dm_irq_suspend(adev);
2656
2657         hpd_rx_irq_work_suspend(dm);
2658
2659         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2660
2661         return 0;
2662 }
2663
2664 struct amdgpu_dm_connector *
2665 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2666                                              struct drm_crtc *crtc)
2667 {
2668         u32 i;
2669         struct drm_connector_state *new_con_state;
2670         struct drm_connector *connector;
2671         struct drm_crtc *crtc_from_state;
2672
2673         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2674                 crtc_from_state = new_con_state->crtc;
2675
2676                 if (crtc_from_state == crtc)
2677                         return to_amdgpu_dm_connector(connector);
2678         }
2679
2680         return NULL;
2681 }
2682
2683 static void emulated_link_detect(struct dc_link *link)
2684 {
2685         struct dc_sink_init_data sink_init_data = { 0 };
2686         struct display_sink_capability sink_caps = { 0 };
2687         enum dc_edid_status edid_status;
2688         struct dc_context *dc_ctx = link->ctx;
2689         struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
2690         struct dc_sink *sink = NULL;
2691         struct dc_sink *prev_sink = NULL;
2692
2693         link->type = dc_connection_none;
2694         prev_sink = link->local_sink;
2695
2696         if (prev_sink)
2697                 dc_sink_release(prev_sink);
2698
2699         switch (link->connector_signal) {
2700         case SIGNAL_TYPE_HDMI_TYPE_A: {
2701                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2702                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2703                 break;
2704         }
2705
2706         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2707                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2708                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2709                 break;
2710         }
2711
2712         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2713                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2714                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2715                 break;
2716         }
2717
2718         case SIGNAL_TYPE_LVDS: {
2719                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2720                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2721                 break;
2722         }
2723
2724         case SIGNAL_TYPE_EDP: {
2725                 sink_caps.transaction_type =
2726                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2727                 sink_caps.signal = SIGNAL_TYPE_EDP;
2728                 break;
2729         }
2730
2731         case SIGNAL_TYPE_DISPLAY_PORT: {
2732                 sink_caps.transaction_type =
2733                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2734                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2735                 break;
2736         }
2737
2738         default:
2739                 drm_err(dev, "Invalid connector type! signal:%d\n",
2740                         link->connector_signal);
2741                 return;
2742         }
2743
2744         sink_init_data.link = link;
2745         sink_init_data.sink_signal = sink_caps.signal;
2746
2747         sink = dc_sink_create(&sink_init_data);
2748         if (!sink) {
2749                 drm_err(dev, "Failed to create sink!\n");
2750                 return;
2751         }
2752
2753         /* dc_sink_create returns a new reference */
2754         link->local_sink = sink;
2755
2756         edid_status = dm_helpers_read_local_edid(
2757                         link->ctx,
2758                         link,
2759                         sink);
2760
2761         if (edid_status != EDID_OK)
2762                 drm_err(dev, "Failed to read EDID\n");
2763
2764 }
2765
2766 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2767                                      struct amdgpu_display_manager *dm)
2768 {
2769         struct {
2770                 struct dc_surface_update surface_updates[MAX_SURFACES];
2771                 struct dc_plane_info plane_infos[MAX_SURFACES];
2772                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2773                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2774                 struct dc_stream_update stream_update;
2775         } *bundle;
2776         int k, m;
2777
2778         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2779
2780         if (!bundle) {
2781                 drm_err(dm->ddev, "Failed to allocate update bundle\n");
2782                 goto cleanup;
2783         }
2784
2785         for (k = 0; k < dc_state->stream_count; k++) {
2786                 bundle->stream_update.stream = dc_state->streams[k];
2787
2788                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2789                         bundle->surface_updates[m].surface =
2790                                 dc_state->stream_status->plane_states[m];
2791                         bundle->surface_updates[m].surface->force_full_update =
2792                                 true;
2793                 }
2794
2795                 update_planes_and_stream_adapter(dm->dc,
2796                                          UPDATE_TYPE_FULL,
2797                                          dc_state->stream_status->plane_count,
2798                                          dc_state->streams[k],
2799                                          &bundle->stream_update,
2800                                          bundle->surface_updates);
2801         }
2802
2803 cleanup:
2804         kfree(bundle);
2805 }
2806
2807 static int dm_resume(void *handle)
2808 {
2809         struct amdgpu_device *adev = handle;
2810         struct drm_device *ddev = adev_to_drm(adev);
2811         struct amdgpu_display_manager *dm = &adev->dm;
2812         struct amdgpu_dm_connector *aconnector;
2813         struct drm_connector *connector;
2814         struct drm_connector_list_iter iter;
2815         struct drm_crtc *crtc;
2816         struct drm_crtc_state *new_crtc_state;
2817         struct dm_crtc_state *dm_new_crtc_state;
2818         struct drm_plane *plane;
2819         struct drm_plane_state *new_plane_state;
2820         struct dm_plane_state *dm_new_plane_state;
2821         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2822         enum dc_connection_type new_connection_type = dc_connection_none;
2823         struct dc_state *dc_state;
2824         int i, r, j, ret;
2825         bool need_hotplug = false;
2826
2827         if (dm->dc->caps.ips_support) {
2828                 dc_dmub_srv_exit_low_power_state(dm->dc);
2829         }
2830
2831         if (amdgpu_in_reset(adev)) {
2832                 dc_state = dm->cached_dc_state;
2833
2834                 /*
2835                  * The dc->current_state is backed up into dm->cached_dc_state
2836                  * before we commit 0 streams.
2837                  *
2838                  * DC will clear link encoder assignments on the real state
2839                  * but the changes won't propagate over to the copy we made
2840                  * before the 0 streams commit.
2841                  *
2842                  * DC expects that link encoder assignments are *not* valid
2843                  * when committing a state, so as a workaround we can copy
2844                  * off of the current state.
2845                  *
2846                  * We lose the previous assignments, but we had already
2847                  * commit 0 streams anyway.
2848                  */
2849                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2850
2851                 r = dm_dmub_hw_init(adev);
2852                 if (r)
2853                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2854
2855                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2856
2857                 dc_resume(dm->dc);
2858
2859                 amdgpu_dm_irq_resume_early(adev);
2860
2861                 for (i = 0; i < dc_state->stream_count; i++) {
2862                         dc_state->streams[i]->mode_changed = true;
2863                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2864                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2865                                         = 0xffffffff;
2866                         }
2867                 }
2868
2869                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2870                         amdgpu_dm_outbox_init(adev);
2871                         dc_enable_dmub_outbox(adev->dm.dc);
2872                 }
2873
2874                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2875
2876                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2877
2878                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2879
2880                 dc_release_state(dm->cached_dc_state);
2881                 dm->cached_dc_state = NULL;
2882
2883                 amdgpu_dm_irq_resume_late(adev);
2884
2885                 mutex_unlock(&dm->dc_lock);
2886
2887                 return 0;
2888         }
2889         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2890         dc_release_state(dm_state->context);
2891         dm_state->context = dc_create_state(dm->dc);
2892         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2893         dc_resource_state_construct(dm->dc, dm_state->context);
2894
2895         /* Before powering on DC we need to re-initialize DMUB. */
2896         dm_dmub_hw_resume(adev);
2897
2898         /* Re-enable outbox interrupts for DPIA. */
2899         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2900                 amdgpu_dm_outbox_init(adev);
2901                 dc_enable_dmub_outbox(adev->dm.dc);
2902         }
2903
2904         /* power on hardware */
2905         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2906
2907         /* program HPD filter */
2908         dc_resume(dm->dc);
2909
2910         /*
2911          * early enable HPD Rx IRQ, should be done before set mode as short
2912          * pulse interrupts are used for MST
2913          */
2914         amdgpu_dm_irq_resume_early(adev);
2915
2916         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2917         s3_handle_mst(ddev, false);
2918
2919         /* Do detection*/
2920         drm_connector_list_iter_begin(ddev, &iter);
2921         drm_for_each_connector_iter(connector, &iter) {
2922                 aconnector = to_amdgpu_dm_connector(connector);
2923
2924                 if (!aconnector->dc_link)
2925                         continue;
2926
2927                 /*
2928                  * this is the case when traversing through already created end sink
2929                  * MST connectors, should be skipped
2930                  */
2931                 if (aconnector && aconnector->mst_root)
2932                         continue;
2933
2934                 mutex_lock(&aconnector->hpd_lock);
2935                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2936                         DRM_ERROR("KMS: Failed to detect connector\n");
2937
2938                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2939                         emulated_link_detect(aconnector->dc_link);
2940                 } else {
2941                         mutex_lock(&dm->dc_lock);
2942                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2943                         mutex_unlock(&dm->dc_lock);
2944                 }
2945
2946                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2947                         aconnector->fake_enable = false;
2948
2949                 if (aconnector->dc_sink)
2950                         dc_sink_release(aconnector->dc_sink);
2951                 aconnector->dc_sink = NULL;
2952                 amdgpu_dm_update_connector_after_detect(aconnector);
2953                 mutex_unlock(&aconnector->hpd_lock);
2954         }
2955         drm_connector_list_iter_end(&iter);
2956
2957         /* Force mode set in atomic commit */
2958         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2959                 new_crtc_state->active_changed = true;
2960
2961         /*
2962          * atomic_check is expected to create the dc states. We need to release
2963          * them here, since they were duplicated as part of the suspend
2964          * procedure.
2965          */
2966         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2967                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2968                 if (dm_new_crtc_state->stream) {
2969                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2970                         dc_stream_release(dm_new_crtc_state->stream);
2971                         dm_new_crtc_state->stream = NULL;
2972                 }
2973         }
2974
2975         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2976                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2977                 if (dm_new_plane_state->dc_state) {
2978                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2979                         dc_plane_state_release(dm_new_plane_state->dc_state);
2980                         dm_new_plane_state->dc_state = NULL;
2981                 }
2982         }
2983
2984         drm_atomic_helper_resume(ddev, dm->cached_state);
2985
2986         dm->cached_state = NULL;
2987
2988         /* Do mst topology probing after resuming cached state*/
2989         drm_connector_list_iter_begin(ddev, &iter);
2990         drm_for_each_connector_iter(connector, &iter) {
2991                 aconnector = to_amdgpu_dm_connector(connector);
2992                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2993                     aconnector->mst_root)
2994                         continue;
2995
2996                 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2997
2998                 if (ret < 0) {
2999                         dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
3000                                         aconnector->dc_link);
3001                         need_hotplug = true;
3002                 }
3003         }
3004         drm_connector_list_iter_end(&iter);
3005
3006         if (need_hotplug)
3007                 drm_kms_helper_hotplug_event(ddev);
3008
3009         amdgpu_dm_irq_resume_late(adev);
3010
3011         amdgpu_dm_smu_write_watermarks_table(adev);
3012
3013         return 0;
3014 }
3015
3016 /**
3017  * DOC: DM Lifecycle
3018  *
3019  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3020  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3021  * the base driver's device list to be initialized and torn down accordingly.
3022  *
3023  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3024  */
3025
3026 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3027         .name = "dm",
3028         .early_init = dm_early_init,
3029         .late_init = dm_late_init,
3030         .sw_init = dm_sw_init,
3031         .sw_fini = dm_sw_fini,
3032         .early_fini = amdgpu_dm_early_fini,
3033         .hw_init = dm_hw_init,
3034         .hw_fini = dm_hw_fini,
3035         .suspend = dm_suspend,
3036         .resume = dm_resume,
3037         .is_idle = dm_is_idle,
3038         .wait_for_idle = dm_wait_for_idle,
3039         .check_soft_reset = dm_check_soft_reset,
3040         .soft_reset = dm_soft_reset,
3041         .set_clockgating_state = dm_set_clockgating_state,
3042         .set_powergating_state = dm_set_powergating_state,
3043 };
3044
3045 const struct amdgpu_ip_block_version dm_ip_block = {
3046         .type = AMD_IP_BLOCK_TYPE_DCE,
3047         .major = 1,
3048         .minor = 0,
3049         .rev = 0,
3050         .funcs = &amdgpu_dm_funcs,
3051 };
3052
3053
3054 /**
3055  * DOC: atomic
3056  *
3057  * *WIP*
3058  */
3059
3060 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3061         .fb_create = amdgpu_display_user_framebuffer_create,
3062         .get_format_info = amdgpu_dm_plane_get_format_info,
3063         .atomic_check = amdgpu_dm_atomic_check,
3064         .atomic_commit = drm_atomic_helper_commit,
3065 };
3066
3067 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3068         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3069         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3070 };
3071
3072 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3073 {
3074         struct amdgpu_dm_backlight_caps *caps;
3075         struct drm_connector *conn_base;
3076         struct amdgpu_device *adev;
3077         struct drm_luminance_range_info *luminance_range;
3078
3079         if (aconnector->bl_idx == -1 ||
3080             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3081                 return;
3082
3083         conn_base = &aconnector->base;
3084         adev = drm_to_adev(conn_base->dev);
3085
3086         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3087         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3088         caps->aux_support = false;
3089
3090         if (caps->ext_caps->bits.oled == 1
3091             /*
3092              * ||
3093              * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3094              * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3095              */)
3096                 caps->aux_support = true;
3097
3098         if (amdgpu_backlight == 0)
3099                 caps->aux_support = false;
3100         else if (amdgpu_backlight == 1)
3101                 caps->aux_support = true;
3102
3103         luminance_range = &conn_base->display_info.luminance_range;
3104
3105         if (luminance_range->max_luminance) {
3106                 caps->aux_min_input_signal = luminance_range->min_luminance;
3107                 caps->aux_max_input_signal = luminance_range->max_luminance;
3108         } else {
3109                 caps->aux_min_input_signal = 0;
3110                 caps->aux_max_input_signal = 512;
3111         }
3112 }
3113
3114 void amdgpu_dm_update_connector_after_detect(
3115                 struct amdgpu_dm_connector *aconnector)
3116 {
3117         struct drm_connector *connector = &aconnector->base;
3118         struct drm_device *dev = connector->dev;
3119         struct dc_sink *sink;
3120
3121         /* MST handled by drm_mst framework */
3122         if (aconnector->mst_mgr.mst_state == true)
3123                 return;
3124
3125         sink = aconnector->dc_link->local_sink;
3126         if (sink)
3127                 dc_sink_retain(sink);
3128
3129         /*
3130          * Edid mgmt connector gets first update only in mode_valid hook and then
3131          * the connector sink is set to either fake or physical sink depends on link status.
3132          * Skip if already done during boot.
3133          */
3134         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3135                         && aconnector->dc_em_sink) {
3136
3137                 /*
3138                  * For S3 resume with headless use eml_sink to fake stream
3139                  * because on resume connector->sink is set to NULL
3140                  */
3141                 mutex_lock(&dev->mode_config.mutex);
3142
3143                 if (sink) {
3144                         if (aconnector->dc_sink) {
3145                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3146                                 /*
3147                                  * retain and release below are used to
3148                                  * bump up refcount for sink because the link doesn't point
3149                                  * to it anymore after disconnect, so on next crtc to connector
3150                                  * reshuffle by UMD we will get into unwanted dc_sink release
3151                                  */
3152                                 dc_sink_release(aconnector->dc_sink);
3153                         }
3154                         aconnector->dc_sink = sink;
3155                         dc_sink_retain(aconnector->dc_sink);
3156                         amdgpu_dm_update_freesync_caps(connector,
3157                                         aconnector->edid);
3158                 } else {
3159                         amdgpu_dm_update_freesync_caps(connector, NULL);
3160                         if (!aconnector->dc_sink) {
3161                                 aconnector->dc_sink = aconnector->dc_em_sink;
3162                                 dc_sink_retain(aconnector->dc_sink);
3163                         }
3164                 }
3165
3166                 mutex_unlock(&dev->mode_config.mutex);
3167
3168                 if (sink)
3169                         dc_sink_release(sink);
3170                 return;
3171         }
3172
3173         /*
3174          * TODO: temporary guard to look for proper fix
3175          * if this sink is MST sink, we should not do anything
3176          */
3177         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3178                 dc_sink_release(sink);
3179                 return;
3180         }
3181
3182         if (aconnector->dc_sink == sink) {
3183                 /*
3184                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3185                  * Do nothing!!
3186                  */
3187                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3188                                 aconnector->connector_id);
3189                 if (sink)
3190                         dc_sink_release(sink);
3191                 return;
3192         }
3193
3194         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3195                 aconnector->connector_id, aconnector->dc_sink, sink);
3196
3197         mutex_lock(&dev->mode_config.mutex);
3198
3199         /*
3200          * 1. Update status of the drm connector
3201          * 2. Send an event and let userspace tell us what to do
3202          */
3203         if (sink) {
3204                 /*
3205                  * TODO: check if we still need the S3 mode update workaround.
3206                  * If yes, put it here.
3207                  */
3208                 if (aconnector->dc_sink) {
3209                         amdgpu_dm_update_freesync_caps(connector, NULL);
3210                         dc_sink_release(aconnector->dc_sink);
3211                 }
3212
3213                 aconnector->dc_sink = sink;
3214                 dc_sink_retain(aconnector->dc_sink);
3215                 if (sink->dc_edid.length == 0) {
3216                         aconnector->edid = NULL;
3217                         if (aconnector->dc_link->aux_mode) {
3218                                 drm_dp_cec_unset_edid(
3219                                         &aconnector->dm_dp_aux.aux);
3220                         }
3221                 } else {
3222                         aconnector->edid =
3223                                 (struct edid *)sink->dc_edid.raw_edid;
3224
3225                         if (aconnector->dc_link->aux_mode)
3226                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3227                                                     aconnector->edid);
3228                 }
3229
3230                 if (!aconnector->timing_requested) {
3231                         aconnector->timing_requested =
3232                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3233                         if (!aconnector->timing_requested)
3234                                 drm_err(dev,
3235                                         "failed to create aconnector->requested_timing\n");
3236                 }
3237
3238                 drm_connector_update_edid_property(connector, aconnector->edid);
3239                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3240                 update_connector_ext_caps(aconnector);
3241         } else {
3242                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3243                 amdgpu_dm_update_freesync_caps(connector, NULL);
3244                 drm_connector_update_edid_property(connector, NULL);
3245                 aconnector->num_modes = 0;
3246                 dc_sink_release(aconnector->dc_sink);
3247                 aconnector->dc_sink = NULL;
3248                 aconnector->edid = NULL;
3249                 kfree(aconnector->timing_requested);
3250                 aconnector->timing_requested = NULL;
3251                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3252                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3253                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3254         }
3255
3256         mutex_unlock(&dev->mode_config.mutex);
3257
3258         update_subconnector_property(aconnector);
3259
3260         if (sink)
3261                 dc_sink_release(sink);
3262 }
3263
3264 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3265 {
3266         struct drm_connector *connector = &aconnector->base;
3267         struct drm_device *dev = connector->dev;
3268         enum dc_connection_type new_connection_type = dc_connection_none;
3269         struct amdgpu_device *adev = drm_to_adev(dev);
3270         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3271         bool ret = false;
3272
3273         if (adev->dm.disable_hpd_irq)
3274                 return;
3275
3276         /*
3277          * In case of failure or MST no need to update connector status or notify the OS
3278          * since (for MST case) MST does this in its own context.
3279          */
3280         mutex_lock(&aconnector->hpd_lock);
3281
3282         if (adev->dm.hdcp_workqueue) {
3283                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3284                 dm_con_state->update_hdcp = true;
3285         }
3286         if (aconnector->fake_enable)
3287                 aconnector->fake_enable = false;
3288
3289         aconnector->timing_changed = false;
3290
3291         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3292                 DRM_ERROR("KMS: Failed to detect connector\n");
3293
3294         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3295                 emulated_link_detect(aconnector->dc_link);
3296
3297                 drm_modeset_lock_all(dev);
3298                 dm_restore_drm_connector_state(dev, connector);
3299                 drm_modeset_unlock_all(dev);
3300
3301                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3302                         drm_kms_helper_connector_hotplug_event(connector);
3303         } else {
3304                 mutex_lock(&adev->dm.dc_lock);
3305                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3306                 mutex_unlock(&adev->dm.dc_lock);
3307                 if (ret) {
3308                         amdgpu_dm_update_connector_after_detect(aconnector);
3309
3310                         drm_modeset_lock_all(dev);
3311                         dm_restore_drm_connector_state(dev, connector);
3312                         drm_modeset_unlock_all(dev);
3313
3314                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3315                                 drm_kms_helper_connector_hotplug_event(connector);
3316                 }
3317         }
3318         mutex_unlock(&aconnector->hpd_lock);
3319
3320 }
3321
3322 static void handle_hpd_irq(void *param)
3323 {
3324         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3325
3326         handle_hpd_irq_helper(aconnector);
3327
3328 }
3329
3330 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3331                                                         union hpd_irq_data hpd_irq_data)
3332 {
3333         struct hpd_rx_irq_offload_work *offload_work =
3334                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3335
3336         if (!offload_work) {
3337                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3338                 return;
3339         }
3340
3341         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3342         offload_work->data = hpd_irq_data;
3343         offload_work->offload_wq = offload_wq;
3344
3345         queue_work(offload_wq->wq, &offload_work->work);
3346         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3347 }
3348
3349 static void handle_hpd_rx_irq(void *param)
3350 {
3351         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3352         struct drm_connector *connector = &aconnector->base;
3353         struct drm_device *dev = connector->dev;
3354         struct dc_link *dc_link = aconnector->dc_link;
3355         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3356         bool result = false;
3357         enum dc_connection_type new_connection_type = dc_connection_none;
3358         struct amdgpu_device *adev = drm_to_adev(dev);
3359         union hpd_irq_data hpd_irq_data;
3360         bool link_loss = false;
3361         bool has_left_work = false;
3362         int idx = dc_link->link_index;
3363         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3364
3365         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3366
3367         if (adev->dm.disable_hpd_irq)
3368                 return;
3369
3370         /*
3371          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3372          * conflict, after implement i2c helper, this mutex should be
3373          * retired.
3374          */
3375         mutex_lock(&aconnector->hpd_lock);
3376
3377         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3378                                                 &link_loss, true, &has_left_work);
3379
3380         if (!has_left_work)
3381                 goto out;
3382
3383         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3384                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3385                 goto out;
3386         }
3387
3388         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3389                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3390                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3391                         bool skip = false;
3392
3393                         /*
3394                          * DOWN_REP_MSG_RDY is also handled by polling method
3395                          * mgr->cbs->poll_hpd_irq()
3396                          */
3397                         spin_lock(&offload_wq->offload_lock);
3398                         skip = offload_wq->is_handling_mst_msg_rdy_event;
3399
3400                         if (!skip)
3401                                 offload_wq->is_handling_mst_msg_rdy_event = true;
3402
3403                         spin_unlock(&offload_wq->offload_lock);
3404
3405                         if (!skip)
3406                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3407
3408                         goto out;
3409                 }
3410
3411                 if (link_loss) {
3412                         bool skip = false;
3413
3414                         spin_lock(&offload_wq->offload_lock);
3415                         skip = offload_wq->is_handling_link_loss;
3416
3417                         if (!skip)
3418                                 offload_wq->is_handling_link_loss = true;
3419
3420                         spin_unlock(&offload_wq->offload_lock);
3421
3422                         if (!skip)
3423                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3424
3425                         goto out;
3426                 }
3427         }
3428
3429 out:
3430         if (result && !is_mst_root_connector) {
3431                 /* Downstream Port status changed. */
3432                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3433                         DRM_ERROR("KMS: Failed to detect connector\n");
3434
3435                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3436                         emulated_link_detect(dc_link);
3437
3438                         if (aconnector->fake_enable)
3439                                 aconnector->fake_enable = false;
3440
3441                         amdgpu_dm_update_connector_after_detect(aconnector);
3442
3443
3444                         drm_modeset_lock_all(dev);
3445                         dm_restore_drm_connector_state(dev, connector);
3446                         drm_modeset_unlock_all(dev);
3447
3448                         drm_kms_helper_connector_hotplug_event(connector);
3449                 } else {
3450                         bool ret = false;
3451
3452                         mutex_lock(&adev->dm.dc_lock);
3453                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3454                         mutex_unlock(&adev->dm.dc_lock);
3455
3456                         if (ret) {
3457                                 if (aconnector->fake_enable)
3458                                         aconnector->fake_enable = false;
3459
3460                                 amdgpu_dm_update_connector_after_detect(aconnector);
3461
3462                                 drm_modeset_lock_all(dev);
3463                                 dm_restore_drm_connector_state(dev, connector);
3464                                 drm_modeset_unlock_all(dev);
3465
3466                                 drm_kms_helper_connector_hotplug_event(connector);
3467                         }
3468                 }
3469         }
3470         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3471                 if (adev->dm.hdcp_workqueue)
3472                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3473         }
3474
3475         if (dc_link->type != dc_connection_mst_branch)
3476                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3477
3478         mutex_unlock(&aconnector->hpd_lock);
3479 }
3480
3481 static void register_hpd_handlers(struct amdgpu_device *adev)
3482 {
3483         struct drm_device *dev = adev_to_drm(adev);
3484         struct drm_connector *connector;
3485         struct amdgpu_dm_connector *aconnector;
3486         const struct dc_link *dc_link;
3487         struct dc_interrupt_params int_params = {0};
3488
3489         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3490         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3491
3492         list_for_each_entry(connector,
3493                         &dev->mode_config.connector_list, head) {
3494
3495                 aconnector = to_amdgpu_dm_connector(connector);
3496                 dc_link = aconnector->dc_link;
3497
3498                 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3499                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3500                         int_params.irq_source = dc_link->irq_source_hpd;
3501
3502                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3503                                         handle_hpd_irq,
3504                                         (void *) aconnector);
3505                 }
3506
3507                 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3508
3509                         /* Also register for DP short pulse (hpd_rx). */
3510                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3511                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3512
3513                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3514                                         handle_hpd_rx_irq,
3515                                         (void *) aconnector);
3516                 }
3517
3518                 if (adev->dm.hpd_rx_offload_wq)
3519                         adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3520                                 aconnector;
3521         }
3522 }
3523
3524 #if defined(CONFIG_DRM_AMD_DC_SI)
3525 /* Register IRQ sources and initialize IRQ callbacks */
3526 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3527 {
3528         struct dc *dc = adev->dm.dc;
3529         struct common_irq_params *c_irq_params;
3530         struct dc_interrupt_params int_params = {0};
3531         int r;
3532         int i;
3533         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3534
3535         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3536         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3537
3538         /*
3539          * Actions of amdgpu_irq_add_id():
3540          * 1. Register a set() function with base driver.
3541          *    Base driver will call set() function to enable/disable an
3542          *    interrupt in DC hardware.
3543          * 2. Register amdgpu_dm_irq_handler().
3544          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3545          *    coming from DC hardware.
3546          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3547          *    for acknowledging and handling.
3548          */
3549
3550         /* Use VBLANK interrupt */
3551         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3552                 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3553                 if (r) {
3554                         DRM_ERROR("Failed to add crtc irq id!\n");
3555                         return r;
3556                 }
3557
3558                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3559                 int_params.irq_source =
3560                         dc_interrupt_to_irq_source(dc, i + 1, 0);
3561
3562                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3563
3564                 c_irq_params->adev = adev;
3565                 c_irq_params->irq_src = int_params.irq_source;
3566
3567                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3568                                 dm_crtc_high_irq, c_irq_params);
3569         }
3570
3571         /* Use GRPH_PFLIP interrupt */
3572         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3573                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3574                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3575                 if (r) {
3576                         DRM_ERROR("Failed to add page flip irq id!\n");
3577                         return r;
3578                 }
3579
3580                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3581                 int_params.irq_source =
3582                         dc_interrupt_to_irq_source(dc, i, 0);
3583
3584                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3585
3586                 c_irq_params->adev = adev;
3587                 c_irq_params->irq_src = int_params.irq_source;
3588
3589                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3590                                 dm_pflip_high_irq, c_irq_params);
3591
3592         }
3593
3594         /* HPD */
3595         r = amdgpu_irq_add_id(adev, client_id,
3596                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3597         if (r) {
3598                 DRM_ERROR("Failed to add hpd irq id!\n");
3599                 return r;
3600         }
3601
3602         register_hpd_handlers(adev);
3603
3604         return 0;
3605 }
3606 #endif
3607
3608 /* Register IRQ sources and initialize IRQ callbacks */
3609 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3610 {
3611         struct dc *dc = adev->dm.dc;
3612         struct common_irq_params *c_irq_params;
3613         struct dc_interrupt_params int_params = {0};
3614         int r;
3615         int i;
3616         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3617
3618         if (adev->family >= AMDGPU_FAMILY_AI)
3619                 client_id = SOC15_IH_CLIENTID_DCE;
3620
3621         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3622         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3623
3624         /*
3625          * Actions of amdgpu_irq_add_id():
3626          * 1. Register a set() function with base driver.
3627          *    Base driver will call set() function to enable/disable an
3628          *    interrupt in DC hardware.
3629          * 2. Register amdgpu_dm_irq_handler().
3630          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3631          *    coming from DC hardware.
3632          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3633          *    for acknowledging and handling.
3634          */
3635
3636         /* Use VBLANK interrupt */
3637         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3638                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3639                 if (r) {
3640                         DRM_ERROR("Failed to add crtc irq id!\n");
3641                         return r;
3642                 }
3643
3644                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3645                 int_params.irq_source =
3646                         dc_interrupt_to_irq_source(dc, i, 0);
3647
3648                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3649
3650                 c_irq_params->adev = adev;
3651                 c_irq_params->irq_src = int_params.irq_source;
3652
3653                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3654                                 dm_crtc_high_irq, c_irq_params);
3655         }
3656
3657         /* Use VUPDATE interrupt */
3658         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3659                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3660                 if (r) {
3661                         DRM_ERROR("Failed to add vupdate irq id!\n");
3662                         return r;
3663                 }
3664
3665                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3666                 int_params.irq_source =
3667                         dc_interrupt_to_irq_source(dc, i, 0);
3668
3669                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3670
3671                 c_irq_params->adev = adev;
3672                 c_irq_params->irq_src = int_params.irq_source;
3673
3674                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3675                                 dm_vupdate_high_irq, c_irq_params);
3676         }
3677
3678         /* Use GRPH_PFLIP interrupt */
3679         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3680                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3681                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3682                 if (r) {
3683                         DRM_ERROR("Failed to add page flip irq id!\n");
3684                         return r;
3685                 }
3686
3687                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3688                 int_params.irq_source =
3689                         dc_interrupt_to_irq_source(dc, i, 0);
3690
3691                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3692
3693                 c_irq_params->adev = adev;
3694                 c_irq_params->irq_src = int_params.irq_source;
3695
3696                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3697                                 dm_pflip_high_irq, c_irq_params);
3698
3699         }
3700
3701         /* HPD */
3702         r = amdgpu_irq_add_id(adev, client_id,
3703                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3704         if (r) {
3705                 DRM_ERROR("Failed to add hpd irq id!\n");
3706                 return r;
3707         }
3708
3709         register_hpd_handlers(adev);
3710
3711         return 0;
3712 }
3713
3714 /* Register IRQ sources and initialize IRQ callbacks */
3715 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3716 {
3717         struct dc *dc = adev->dm.dc;
3718         struct common_irq_params *c_irq_params;
3719         struct dc_interrupt_params int_params = {0};
3720         int r;
3721         int i;
3722 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3723         static const unsigned int vrtl_int_srcid[] = {
3724                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3725                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3726                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3727                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3728                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3729                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3730         };
3731 #endif
3732
3733         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3734         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3735
3736         /*
3737          * Actions of amdgpu_irq_add_id():
3738          * 1. Register a set() function with base driver.
3739          *    Base driver will call set() function to enable/disable an
3740          *    interrupt in DC hardware.
3741          * 2. Register amdgpu_dm_irq_handler().
3742          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3743          *    coming from DC hardware.
3744          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3745          *    for acknowledging and handling.
3746          */
3747
3748         /* Use VSTARTUP interrupt */
3749         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3750                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3751                         i++) {
3752                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3753
3754                 if (r) {
3755                         DRM_ERROR("Failed to add crtc irq id!\n");
3756                         return r;
3757                 }
3758
3759                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3760                 int_params.irq_source =
3761                         dc_interrupt_to_irq_source(dc, i, 0);
3762
3763                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3764
3765                 c_irq_params->adev = adev;
3766                 c_irq_params->irq_src = int_params.irq_source;
3767
3768                 amdgpu_dm_irq_register_interrupt(
3769                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3770         }
3771
3772         /* Use otg vertical line interrupt */
3773 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3774         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3775                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3776                                 vrtl_int_srcid[i], &adev->vline0_irq);
3777
3778                 if (r) {
3779                         DRM_ERROR("Failed to add vline0 irq id!\n");
3780                         return r;
3781                 }
3782
3783                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3784                 int_params.irq_source =
3785                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3786
3787                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3788                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3789                         break;
3790                 }
3791
3792                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3793                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3794
3795                 c_irq_params->adev = adev;
3796                 c_irq_params->irq_src = int_params.irq_source;
3797
3798                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3799                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3800         }
3801 #endif
3802
3803         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3804          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3805          * to trigger at end of each vblank, regardless of state of the lock,
3806          * matching DCE behaviour.
3807          */
3808         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3809              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3810              i++) {
3811                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3812
3813                 if (r) {
3814                         DRM_ERROR("Failed to add vupdate irq id!\n");
3815                         return r;
3816                 }
3817
3818                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3819                 int_params.irq_source =
3820                         dc_interrupt_to_irq_source(dc, i, 0);
3821
3822                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3823
3824                 c_irq_params->adev = adev;
3825                 c_irq_params->irq_src = int_params.irq_source;
3826
3827                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3828                                 dm_vupdate_high_irq, c_irq_params);
3829         }
3830
3831         /* Use GRPH_PFLIP interrupt */
3832         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3833                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3834                         i++) {
3835                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3836                 if (r) {
3837                         DRM_ERROR("Failed to add page flip irq id!\n");
3838                         return r;
3839                 }
3840
3841                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3842                 int_params.irq_source =
3843                         dc_interrupt_to_irq_source(dc, i, 0);
3844
3845                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3846
3847                 c_irq_params->adev = adev;
3848                 c_irq_params->irq_src = int_params.irq_source;
3849
3850                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3851                                 dm_pflip_high_irq, c_irq_params);
3852
3853         }
3854
3855         /* HPD */
3856         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3857                         &adev->hpd_irq);
3858         if (r) {
3859                 DRM_ERROR("Failed to add hpd irq id!\n");
3860                 return r;
3861         }
3862
3863         register_hpd_handlers(adev);
3864
3865         return 0;
3866 }
3867 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3868 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3869 {
3870         struct dc *dc = adev->dm.dc;
3871         struct common_irq_params *c_irq_params;
3872         struct dc_interrupt_params int_params = {0};
3873         int r, i;
3874
3875         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3876         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3877
3878         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3879                         &adev->dmub_outbox_irq);
3880         if (r) {
3881                 DRM_ERROR("Failed to add outbox irq id!\n");
3882                 return r;
3883         }
3884
3885         if (dc->ctx->dmub_srv) {
3886                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3887                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3888                 int_params.irq_source =
3889                 dc_interrupt_to_irq_source(dc, i, 0);
3890
3891                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3892
3893                 c_irq_params->adev = adev;
3894                 c_irq_params->irq_src = int_params.irq_source;
3895
3896                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3897                                 dm_dmub_outbox1_low_irq, c_irq_params);
3898         }
3899
3900         return 0;
3901 }
3902
3903 /*
3904  * Acquires the lock for the atomic state object and returns
3905  * the new atomic state.
3906  *
3907  * This should only be called during atomic check.
3908  */
3909 int dm_atomic_get_state(struct drm_atomic_state *state,
3910                         struct dm_atomic_state **dm_state)
3911 {
3912         struct drm_device *dev = state->dev;
3913         struct amdgpu_device *adev = drm_to_adev(dev);
3914         struct amdgpu_display_manager *dm = &adev->dm;
3915         struct drm_private_state *priv_state;
3916
3917         if (*dm_state)
3918                 return 0;
3919
3920         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3921         if (IS_ERR(priv_state))
3922                 return PTR_ERR(priv_state);
3923
3924         *dm_state = to_dm_atomic_state(priv_state);
3925
3926         return 0;
3927 }
3928
3929 static struct dm_atomic_state *
3930 dm_atomic_get_new_state(struct drm_atomic_state *state)
3931 {
3932         struct drm_device *dev = state->dev;
3933         struct amdgpu_device *adev = drm_to_adev(dev);
3934         struct amdgpu_display_manager *dm = &adev->dm;
3935         struct drm_private_obj *obj;
3936         struct drm_private_state *new_obj_state;
3937         int i;
3938
3939         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3940                 if (obj->funcs == dm->atomic_obj.funcs)
3941                         return to_dm_atomic_state(new_obj_state);
3942         }
3943
3944         return NULL;
3945 }
3946
3947 static struct drm_private_state *
3948 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3949 {
3950         struct dm_atomic_state *old_state, *new_state;
3951
3952         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3953         if (!new_state)
3954                 return NULL;
3955
3956         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3957
3958         old_state = to_dm_atomic_state(obj->state);
3959
3960         if (old_state && old_state->context)
3961                 new_state->context = dc_copy_state(old_state->context);
3962
3963         if (!new_state->context) {
3964                 kfree(new_state);
3965                 return NULL;
3966         }
3967
3968         return &new_state->base;
3969 }
3970
3971 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3972                                     struct drm_private_state *state)
3973 {
3974         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3975
3976         if (dm_state && dm_state->context)
3977                 dc_release_state(dm_state->context);
3978
3979         kfree(dm_state);
3980 }
3981
3982 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3983         .atomic_duplicate_state = dm_atomic_duplicate_state,
3984         .atomic_destroy_state = dm_atomic_destroy_state,
3985 };
3986
3987 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3988 {
3989         struct dm_atomic_state *state;
3990         int r;
3991
3992         adev->mode_info.mode_config_initialized = true;
3993
3994         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3995         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3996
3997         adev_to_drm(adev)->mode_config.max_width = 16384;
3998         adev_to_drm(adev)->mode_config.max_height = 16384;
3999
4000         adev_to_drm(adev)->mode_config.preferred_depth = 24;
4001         if (adev->asic_type == CHIP_HAWAII)
4002                 /* disable prefer shadow for now due to hibernation issues */
4003                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
4004         else
4005                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4006         /* indicates support for immediate flip */
4007         adev_to_drm(adev)->mode_config.async_page_flip = true;
4008
4009         state = kzalloc(sizeof(*state), GFP_KERNEL);
4010         if (!state)
4011                 return -ENOMEM;
4012
4013         state->context = dc_create_state(adev->dm.dc);
4014         if (!state->context) {
4015                 kfree(state);
4016                 return -ENOMEM;
4017         }
4018
4019         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4020
4021         drm_atomic_private_obj_init(adev_to_drm(adev),
4022                                     &adev->dm.atomic_obj,
4023                                     &state->base,
4024                                     &dm_atomic_state_funcs);
4025
4026         r = amdgpu_display_modeset_create_props(adev);
4027         if (r) {
4028                 dc_release_state(state->context);
4029                 kfree(state);
4030                 return r;
4031         }
4032
4033         r = amdgpu_dm_audio_init(adev);
4034         if (r) {
4035                 dc_release_state(state->context);
4036                 kfree(state);
4037                 return r;
4038         }
4039
4040         return 0;
4041 }
4042
4043 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4044 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4045 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4046
4047 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4048                                             int bl_idx)
4049 {
4050 #if defined(CONFIG_ACPI)
4051         struct amdgpu_dm_backlight_caps caps;
4052
4053         memset(&caps, 0, sizeof(caps));
4054
4055         if (dm->backlight_caps[bl_idx].caps_valid)
4056                 return;
4057
4058         amdgpu_acpi_get_backlight_caps(&caps);
4059         if (caps.caps_valid) {
4060                 dm->backlight_caps[bl_idx].caps_valid = true;
4061                 if (caps.aux_support)
4062                         return;
4063                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4064                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4065         } else {
4066                 dm->backlight_caps[bl_idx].min_input_signal =
4067                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4068                 dm->backlight_caps[bl_idx].max_input_signal =
4069                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4070         }
4071 #else
4072         if (dm->backlight_caps[bl_idx].aux_support)
4073                 return;
4074
4075         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4076         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4077 #endif
4078 }
4079
4080 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4081                                 unsigned int *min, unsigned int *max)
4082 {
4083         if (!caps)
4084                 return 0;
4085
4086         if (caps->aux_support) {
4087                 // Firmware limits are in nits, DC API wants millinits.
4088                 *max = 1000 * caps->aux_max_input_signal;
4089                 *min = 1000 * caps->aux_min_input_signal;
4090         } else {
4091                 // Firmware limits are 8-bit, PWM control is 16-bit.
4092                 *max = 0x101 * caps->max_input_signal;
4093                 *min = 0x101 * caps->min_input_signal;
4094         }
4095         return 1;
4096 }
4097
4098 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4099                                         uint32_t brightness)
4100 {
4101         unsigned int min, max;
4102
4103         if (!get_brightness_range(caps, &min, &max))
4104                 return brightness;
4105
4106         // Rescale 0..255 to min..max
4107         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4108                                        AMDGPU_MAX_BL_LEVEL);
4109 }
4110
4111 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4112                                       uint32_t brightness)
4113 {
4114         unsigned int min, max;
4115
4116         if (!get_brightness_range(caps, &min, &max))
4117                 return brightness;
4118
4119         if (brightness < min)
4120                 return 0;
4121         // Rescale min..max to 0..255
4122         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4123                                  max - min);
4124 }
4125
4126 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4127                                          int bl_idx,
4128                                          u32 user_brightness)
4129 {
4130         struct amdgpu_dm_backlight_caps caps;
4131         struct dc_link *link;
4132         u32 brightness;
4133         bool rc;
4134
4135         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4136         caps = dm->backlight_caps[bl_idx];
4137
4138         dm->brightness[bl_idx] = user_brightness;
4139         /* update scratch register */
4140         if (bl_idx == 0)
4141                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4142         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4143         link = (struct dc_link *)dm->backlight_link[bl_idx];
4144
4145         /* Change brightness based on AUX property */
4146         if (caps.aux_support) {
4147                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4148                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4149                 if (!rc)
4150                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4151         } else {
4152                 rc = dc_link_set_backlight_level(link, brightness, 0);
4153                 if (!rc)
4154                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4155         }
4156
4157         if (rc)
4158                 dm->actual_brightness[bl_idx] = user_brightness;
4159 }
4160
4161 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4162 {
4163         struct amdgpu_display_manager *dm = bl_get_data(bd);
4164         int i;
4165
4166         for (i = 0; i < dm->num_of_edps; i++) {
4167                 if (bd == dm->backlight_dev[i])
4168                         break;
4169         }
4170         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4171                 i = 0;
4172         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4173
4174         return 0;
4175 }
4176
4177 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4178                                          int bl_idx)
4179 {
4180         int ret;
4181         struct amdgpu_dm_backlight_caps caps;
4182         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4183
4184         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4185         caps = dm->backlight_caps[bl_idx];
4186
4187         if (caps.aux_support) {
4188                 u32 avg, peak;
4189                 bool rc;
4190
4191                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4192                 if (!rc)
4193                         return dm->brightness[bl_idx];
4194                 return convert_brightness_to_user(&caps, avg);
4195         }
4196
4197         ret = dc_link_get_backlight_level(link);
4198
4199         if (ret == DC_ERROR_UNEXPECTED)
4200                 return dm->brightness[bl_idx];
4201
4202         return convert_brightness_to_user(&caps, ret);
4203 }
4204
4205 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4206 {
4207         struct amdgpu_display_manager *dm = bl_get_data(bd);
4208         int i;
4209
4210         for (i = 0; i < dm->num_of_edps; i++) {
4211                 if (bd == dm->backlight_dev[i])
4212                         break;
4213         }
4214         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4215                 i = 0;
4216         return amdgpu_dm_backlight_get_level(dm, i);
4217 }
4218
4219 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4220         .options = BL_CORE_SUSPENDRESUME,
4221         .get_brightness = amdgpu_dm_backlight_get_brightness,
4222         .update_status  = amdgpu_dm_backlight_update_status,
4223 };
4224
4225 static void
4226 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4227 {
4228         struct drm_device *drm = aconnector->base.dev;
4229         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4230         struct backlight_properties props = { 0 };
4231         char bl_name[16];
4232
4233         if (aconnector->bl_idx == -1)
4234                 return;
4235
4236         if (!acpi_video_backlight_use_native()) {
4237                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4238                 /* Try registering an ACPI video backlight device instead. */
4239                 acpi_video_register_backlight();
4240                 return;
4241         }
4242
4243         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4244         props.brightness = AMDGPU_MAX_BL_LEVEL;
4245         props.type = BACKLIGHT_RAW;
4246
4247         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4248                  drm->primary->index + aconnector->bl_idx);
4249
4250         dm->backlight_dev[aconnector->bl_idx] =
4251                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4252                                           &amdgpu_dm_backlight_ops, &props);
4253
4254         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4255                 DRM_ERROR("DM: Backlight registration failed!\n");
4256                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4257         } else
4258                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4259 }
4260
4261 static int initialize_plane(struct amdgpu_display_manager *dm,
4262                             struct amdgpu_mode_info *mode_info, int plane_id,
4263                             enum drm_plane_type plane_type,
4264                             const struct dc_plane_cap *plane_cap)
4265 {
4266         struct drm_plane *plane;
4267         unsigned long possible_crtcs;
4268         int ret = 0;
4269
4270         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4271         if (!plane) {
4272                 DRM_ERROR("KMS: Failed to allocate plane\n");
4273                 return -ENOMEM;
4274         }
4275         plane->type = plane_type;
4276
4277         /*
4278          * HACK: IGT tests expect that the primary plane for a CRTC
4279          * can only have one possible CRTC. Only expose support for
4280          * any CRTC if they're not going to be used as a primary plane
4281          * for a CRTC - like overlay or underlay planes.
4282          */
4283         possible_crtcs = 1 << plane_id;
4284         if (plane_id >= dm->dc->caps.max_streams)
4285                 possible_crtcs = 0xff;
4286
4287         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4288
4289         if (ret) {
4290                 DRM_ERROR("KMS: Failed to initialize plane\n");
4291                 kfree(plane);
4292                 return ret;
4293         }
4294
4295         if (mode_info)
4296                 mode_info->planes[plane_id] = plane;
4297
4298         return ret;
4299 }
4300
4301
4302 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4303                                    struct amdgpu_dm_connector *aconnector)
4304 {
4305         struct dc_link *link = aconnector->dc_link;
4306         int bl_idx = dm->num_of_edps;
4307
4308         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4309             link->type == dc_connection_none)
4310                 return;
4311
4312         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4313                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4314                 return;
4315         }
4316
4317         aconnector->bl_idx = bl_idx;
4318
4319         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4320         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4321         dm->backlight_link[bl_idx] = link;
4322         dm->num_of_edps++;
4323
4324         update_connector_ext_caps(aconnector);
4325 }
4326
4327 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4328
4329 /*
4330  * In this architecture, the association
4331  * connector -> encoder -> crtc
4332  * id not really requried. The crtc and connector will hold the
4333  * display_index as an abstraction to use with DAL component
4334  *
4335  * Returns 0 on success
4336  */
4337 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4338 {
4339         struct amdgpu_display_manager *dm = &adev->dm;
4340         s32 i;
4341         struct amdgpu_dm_connector *aconnector = NULL;
4342         struct amdgpu_encoder *aencoder = NULL;
4343         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4344         u32 link_cnt;
4345         s32 primary_planes;
4346         enum dc_connection_type new_connection_type = dc_connection_none;
4347         const struct dc_plane_cap *plane;
4348         bool psr_feature_enabled = false;
4349         bool replay_feature_enabled = false;
4350         int max_overlay = dm->dc->caps.max_slave_planes;
4351
4352         dm->display_indexes_num = dm->dc->caps.max_streams;
4353         /* Update the actual used number of crtc */
4354         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4355
4356         amdgpu_dm_set_irq_funcs(adev);
4357
4358         link_cnt = dm->dc->caps.max_links;
4359         if (amdgpu_dm_mode_config_init(dm->adev)) {
4360                 DRM_ERROR("DM: Failed to initialize mode config\n");
4361                 return -EINVAL;
4362         }
4363
4364         /* There is one primary plane per CRTC */
4365         primary_planes = dm->dc->caps.max_streams;
4366         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4367
4368         /*
4369          * Initialize primary planes, implicit planes for legacy IOCTLS.
4370          * Order is reversed to match iteration order in atomic check.
4371          */
4372         for (i = (primary_planes - 1); i >= 0; i--) {
4373                 plane = &dm->dc->caps.planes[i];
4374
4375                 if (initialize_plane(dm, mode_info, i,
4376                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4377                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4378                         goto fail;
4379                 }
4380         }
4381
4382         /*
4383          * Initialize overlay planes, index starting after primary planes.
4384          * These planes have a higher DRM index than the primary planes since
4385          * they should be considered as having a higher z-order.
4386          * Order is reversed to match iteration order in atomic check.
4387          *
4388          * Only support DCN for now, and only expose one so we don't encourage
4389          * userspace to use up all the pipes.
4390          */
4391         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4392                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4393
4394                 /* Do not create overlay if MPO disabled */
4395                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4396                         break;
4397
4398                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4399                         continue;
4400
4401                 if (!plane->pixel_format_support.argb8888)
4402                         continue;
4403
4404                 if (max_overlay-- == 0)
4405                         break;
4406
4407                 if (initialize_plane(dm, NULL, primary_planes + i,
4408                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4409                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4410                         goto fail;
4411                 }
4412         }
4413
4414         for (i = 0; i < dm->dc->caps.max_streams; i++)
4415                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4416                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4417                         goto fail;
4418                 }
4419
4420         /* Use Outbox interrupt */
4421         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4422         case IP_VERSION(3, 0, 0):
4423         case IP_VERSION(3, 1, 2):
4424         case IP_VERSION(3, 1, 3):
4425         case IP_VERSION(3, 1, 4):
4426         case IP_VERSION(3, 1, 5):
4427         case IP_VERSION(3, 1, 6):
4428         case IP_VERSION(3, 2, 0):
4429         case IP_VERSION(3, 2, 1):
4430         case IP_VERSION(2, 1, 0):
4431         case IP_VERSION(3, 5, 0):
4432                 if (register_outbox_irq_handlers(dm->adev)) {
4433                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4434                         goto fail;
4435                 }
4436                 break;
4437         default:
4438                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4439                               amdgpu_ip_version(adev, DCE_HWIP, 0));
4440         }
4441
4442         /* Determine whether to enable PSR support by default. */
4443         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4444                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4445                 case IP_VERSION(3, 1, 2):
4446                 case IP_VERSION(3, 1, 3):
4447                 case IP_VERSION(3, 1, 4):
4448                 case IP_VERSION(3, 1, 5):
4449                 case IP_VERSION(3, 1, 6):
4450                 case IP_VERSION(3, 2, 0):
4451                 case IP_VERSION(3, 2, 1):
4452                 case IP_VERSION(3, 5, 0):
4453                         psr_feature_enabled = true;
4454                         break;
4455                 default:
4456                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4457                         break;
4458                 }
4459         }
4460
4461         if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4462                 switch (adev->ip_versions[DCE_HWIP][0]) {
4463                 case IP_VERSION(3, 1, 4):
4464                 case IP_VERSION(3, 1, 5):
4465                 case IP_VERSION(3, 1, 6):
4466                 case IP_VERSION(3, 2, 0):
4467                 case IP_VERSION(3, 2, 1):
4468                         replay_feature_enabled = true;
4469                         break;
4470                 default:
4471                         replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4472                         break;
4473                 }
4474         }
4475         /* loops over all connectors on the board */
4476         for (i = 0; i < link_cnt; i++) {
4477                 struct dc_link *link = NULL;
4478
4479                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4480                         DRM_ERROR(
4481                                 "KMS: Cannot support more than %d display indexes\n",
4482                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4483                         continue;
4484                 }
4485
4486                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4487                 if (!aconnector)
4488                         goto fail;
4489
4490                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4491                 if (!aencoder)
4492                         goto fail;
4493
4494                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4495                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4496                         goto fail;
4497                 }
4498
4499                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4500                         DRM_ERROR("KMS: Failed to initialize connector\n");
4501                         goto fail;
4502                 }
4503
4504                 link = dc_get_link_at_index(dm->dc, i);
4505
4506                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4507                         DRM_ERROR("KMS: Failed to detect connector\n");
4508
4509                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4510                         emulated_link_detect(link);
4511                         amdgpu_dm_update_connector_after_detect(aconnector);
4512                 } else {
4513                         bool ret = false;
4514
4515                         mutex_lock(&dm->dc_lock);
4516                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4517                         mutex_unlock(&dm->dc_lock);
4518
4519                         if (ret) {
4520                                 amdgpu_dm_update_connector_after_detect(aconnector);
4521                                 setup_backlight_device(dm, aconnector);
4522
4523                                 /*
4524                                  * Disable psr if replay can be enabled
4525                                  */
4526                                 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4527                                         psr_feature_enabled = false;
4528
4529                                 if (psr_feature_enabled)
4530                                         amdgpu_dm_set_psr_caps(link);
4531
4532                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4533                                  * PSR is also supported.
4534                                  */
4535                                 if (link->psr_settings.psr_feature_enabled)
4536                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4537                         }
4538                 }
4539                 amdgpu_set_panel_orientation(&aconnector->base);
4540         }
4541
4542         /* Software is initialized. Now we can register interrupt handlers. */
4543         switch (adev->asic_type) {
4544 #if defined(CONFIG_DRM_AMD_DC_SI)
4545         case CHIP_TAHITI:
4546         case CHIP_PITCAIRN:
4547         case CHIP_VERDE:
4548         case CHIP_OLAND:
4549                 if (dce60_register_irq_handlers(dm->adev)) {
4550                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4551                         goto fail;
4552                 }
4553                 break;
4554 #endif
4555         case CHIP_BONAIRE:
4556         case CHIP_HAWAII:
4557         case CHIP_KAVERI:
4558         case CHIP_KABINI:
4559         case CHIP_MULLINS:
4560         case CHIP_TONGA:
4561         case CHIP_FIJI:
4562         case CHIP_CARRIZO:
4563         case CHIP_STONEY:
4564         case CHIP_POLARIS11:
4565         case CHIP_POLARIS10:
4566         case CHIP_POLARIS12:
4567         case CHIP_VEGAM:
4568         case CHIP_VEGA10:
4569         case CHIP_VEGA12:
4570         case CHIP_VEGA20:
4571                 if (dce110_register_irq_handlers(dm->adev)) {
4572                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4573                         goto fail;
4574                 }
4575                 break;
4576         default:
4577                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4578                 case IP_VERSION(1, 0, 0):
4579                 case IP_VERSION(1, 0, 1):
4580                 case IP_VERSION(2, 0, 2):
4581                 case IP_VERSION(2, 0, 3):
4582                 case IP_VERSION(2, 0, 0):
4583                 case IP_VERSION(2, 1, 0):
4584                 case IP_VERSION(3, 0, 0):
4585                 case IP_VERSION(3, 0, 2):
4586                 case IP_VERSION(3, 0, 3):
4587                 case IP_VERSION(3, 0, 1):
4588                 case IP_VERSION(3, 1, 2):
4589                 case IP_VERSION(3, 1, 3):
4590                 case IP_VERSION(3, 1, 4):
4591                 case IP_VERSION(3, 1, 5):
4592                 case IP_VERSION(3, 1, 6):
4593                 case IP_VERSION(3, 2, 0):
4594                 case IP_VERSION(3, 2, 1):
4595                 case IP_VERSION(3, 5, 0):
4596                         if (dcn10_register_irq_handlers(dm->adev)) {
4597                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4598                                 goto fail;
4599                         }
4600                         break;
4601                 default:
4602                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4603                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4604                         goto fail;
4605                 }
4606                 break;
4607         }
4608
4609         return 0;
4610 fail:
4611         kfree(aencoder);
4612         kfree(aconnector);
4613
4614         return -EINVAL;
4615 }
4616
4617 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4618 {
4619         drm_atomic_private_obj_fini(&dm->atomic_obj);
4620 }
4621
4622 /******************************************************************************
4623  * amdgpu_display_funcs functions
4624  *****************************************************************************/
4625
4626 /*
4627  * dm_bandwidth_update - program display watermarks
4628  *
4629  * @adev: amdgpu_device pointer
4630  *
4631  * Calculate and program the display watermarks and line buffer allocation.
4632  */
4633 static void dm_bandwidth_update(struct amdgpu_device *adev)
4634 {
4635         /* TODO: implement later */
4636 }
4637
4638 static const struct amdgpu_display_funcs dm_display_funcs = {
4639         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4640         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4641         .backlight_set_level = NULL, /* never called for DC */
4642         .backlight_get_level = NULL, /* never called for DC */
4643         .hpd_sense = NULL,/* called unconditionally */
4644         .hpd_set_polarity = NULL, /* called unconditionally */
4645         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4646         .page_flip_get_scanoutpos =
4647                 dm_crtc_get_scanoutpos,/* called unconditionally */
4648         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4649         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4650 };
4651
4652 #if defined(CONFIG_DEBUG_KERNEL_DC)
4653
4654 static ssize_t s3_debug_store(struct device *device,
4655                               struct device_attribute *attr,
4656                               const char *buf,
4657                               size_t count)
4658 {
4659         int ret;
4660         int s3_state;
4661         struct drm_device *drm_dev = dev_get_drvdata(device);
4662         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4663
4664         ret = kstrtoint(buf, 0, &s3_state);
4665
4666         if (ret == 0) {
4667                 if (s3_state) {
4668                         dm_resume(adev);
4669                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4670                 } else
4671                         dm_suspend(adev);
4672         }
4673
4674         return ret == 0 ? count : 0;
4675 }
4676
4677 DEVICE_ATTR_WO(s3_debug);
4678
4679 #endif
4680
4681 static int dm_init_microcode(struct amdgpu_device *adev)
4682 {
4683         char *fw_name_dmub;
4684         int r;
4685
4686         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4687         case IP_VERSION(2, 1, 0):
4688                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4689                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4690                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4691                 break;
4692         case IP_VERSION(3, 0, 0):
4693                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
4694                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4695                 else
4696                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4697                 break;
4698         case IP_VERSION(3, 0, 1):
4699                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4700                 break;
4701         case IP_VERSION(3, 0, 2):
4702                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4703                 break;
4704         case IP_VERSION(3, 0, 3):
4705                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4706                 break;
4707         case IP_VERSION(3, 1, 2):
4708         case IP_VERSION(3, 1, 3):
4709                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4710                 break;
4711         case IP_VERSION(3, 1, 4):
4712                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4713                 break;
4714         case IP_VERSION(3, 1, 5):
4715                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4716                 break;
4717         case IP_VERSION(3, 1, 6):
4718                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4719                 break;
4720         case IP_VERSION(3, 2, 0):
4721                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4722                 break;
4723         case IP_VERSION(3, 2, 1):
4724                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4725                 break;
4726         case IP_VERSION(3, 5, 0):
4727                 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
4728                 break;
4729         default:
4730                 /* ASIC doesn't support DMUB. */
4731                 return 0;
4732         }
4733         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4734         return r;
4735 }
4736
4737 static int dm_early_init(void *handle)
4738 {
4739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4740         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4741         struct atom_context *ctx = mode_info->atom_context;
4742         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4743         u16 data_offset;
4744
4745         /* if there is no object header, skip DM */
4746         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4747                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4748                 dev_info(adev->dev, "No object header, skipping DM\n");
4749                 return -ENOENT;
4750         }
4751
4752         switch (adev->asic_type) {
4753 #if defined(CONFIG_DRM_AMD_DC_SI)
4754         case CHIP_TAHITI:
4755         case CHIP_PITCAIRN:
4756         case CHIP_VERDE:
4757                 adev->mode_info.num_crtc = 6;
4758                 adev->mode_info.num_hpd = 6;
4759                 adev->mode_info.num_dig = 6;
4760                 break;
4761         case CHIP_OLAND:
4762                 adev->mode_info.num_crtc = 2;
4763                 adev->mode_info.num_hpd = 2;
4764                 adev->mode_info.num_dig = 2;
4765                 break;
4766 #endif
4767         case CHIP_BONAIRE:
4768         case CHIP_HAWAII:
4769                 adev->mode_info.num_crtc = 6;
4770                 adev->mode_info.num_hpd = 6;
4771                 adev->mode_info.num_dig = 6;
4772                 break;
4773         case CHIP_KAVERI:
4774                 adev->mode_info.num_crtc = 4;
4775                 adev->mode_info.num_hpd = 6;
4776                 adev->mode_info.num_dig = 7;
4777                 break;
4778         case CHIP_KABINI:
4779         case CHIP_MULLINS:
4780                 adev->mode_info.num_crtc = 2;
4781                 adev->mode_info.num_hpd = 6;
4782                 adev->mode_info.num_dig = 6;
4783                 break;
4784         case CHIP_FIJI:
4785         case CHIP_TONGA:
4786                 adev->mode_info.num_crtc = 6;
4787                 adev->mode_info.num_hpd = 6;
4788                 adev->mode_info.num_dig = 7;
4789                 break;
4790         case CHIP_CARRIZO:
4791                 adev->mode_info.num_crtc = 3;
4792                 adev->mode_info.num_hpd = 6;
4793                 adev->mode_info.num_dig = 9;
4794                 break;
4795         case CHIP_STONEY:
4796                 adev->mode_info.num_crtc = 2;
4797                 adev->mode_info.num_hpd = 6;
4798                 adev->mode_info.num_dig = 9;
4799                 break;
4800         case CHIP_POLARIS11:
4801         case CHIP_POLARIS12:
4802                 adev->mode_info.num_crtc = 5;
4803                 adev->mode_info.num_hpd = 5;
4804                 adev->mode_info.num_dig = 5;
4805                 break;
4806         case CHIP_POLARIS10:
4807         case CHIP_VEGAM:
4808                 adev->mode_info.num_crtc = 6;
4809                 adev->mode_info.num_hpd = 6;
4810                 adev->mode_info.num_dig = 6;
4811                 break;
4812         case CHIP_VEGA10:
4813         case CHIP_VEGA12:
4814         case CHIP_VEGA20:
4815                 adev->mode_info.num_crtc = 6;
4816                 adev->mode_info.num_hpd = 6;
4817                 adev->mode_info.num_dig = 6;
4818                 break;
4819         default:
4820
4821                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4822                 case IP_VERSION(2, 0, 2):
4823                 case IP_VERSION(3, 0, 0):
4824                         adev->mode_info.num_crtc = 6;
4825                         adev->mode_info.num_hpd = 6;
4826                         adev->mode_info.num_dig = 6;
4827                         break;
4828                 case IP_VERSION(2, 0, 0):
4829                 case IP_VERSION(3, 0, 2):
4830                         adev->mode_info.num_crtc = 5;
4831                         adev->mode_info.num_hpd = 5;
4832                         adev->mode_info.num_dig = 5;
4833                         break;
4834                 case IP_VERSION(2, 0, 3):
4835                 case IP_VERSION(3, 0, 3):
4836                         adev->mode_info.num_crtc = 2;
4837                         adev->mode_info.num_hpd = 2;
4838                         adev->mode_info.num_dig = 2;
4839                         break;
4840                 case IP_VERSION(1, 0, 0):
4841                 case IP_VERSION(1, 0, 1):
4842                 case IP_VERSION(3, 0, 1):
4843                 case IP_VERSION(2, 1, 0):
4844                 case IP_VERSION(3, 1, 2):
4845                 case IP_VERSION(3, 1, 3):
4846                 case IP_VERSION(3, 1, 4):
4847                 case IP_VERSION(3, 1, 5):
4848                 case IP_VERSION(3, 1, 6):
4849                 case IP_VERSION(3, 2, 0):
4850                 case IP_VERSION(3, 2, 1):
4851                 case IP_VERSION(3, 5, 0):
4852                         adev->mode_info.num_crtc = 4;
4853                         adev->mode_info.num_hpd = 4;
4854                         adev->mode_info.num_dig = 4;
4855                         break;
4856                 default:
4857                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4858                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4859                         return -EINVAL;
4860                 }
4861                 break;
4862         }
4863
4864         if (adev->mode_info.funcs == NULL)
4865                 adev->mode_info.funcs = &dm_display_funcs;
4866
4867         /*
4868          * Note: Do NOT change adev->audio_endpt_rreg and
4869          * adev->audio_endpt_wreg because they are initialised in
4870          * amdgpu_device_init()
4871          */
4872 #if defined(CONFIG_DEBUG_KERNEL_DC)
4873         device_create_file(
4874                 adev_to_drm(adev)->dev,
4875                 &dev_attr_s3_debug);
4876 #endif
4877         adev->dc_enabled = true;
4878
4879         return dm_init_microcode(adev);
4880 }
4881
4882 static bool modereset_required(struct drm_crtc_state *crtc_state)
4883 {
4884         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4885 }
4886
4887 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4888 {
4889         drm_encoder_cleanup(encoder);
4890         kfree(encoder);
4891 }
4892
4893 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4894         .destroy = amdgpu_dm_encoder_destroy,
4895 };
4896
4897 static int
4898 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4899                             const enum surface_pixel_format format,
4900                             enum dc_color_space *color_space)
4901 {
4902         bool full_range;
4903
4904         *color_space = COLOR_SPACE_SRGB;
4905
4906         /* DRM color properties only affect non-RGB formats. */
4907         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4908                 return 0;
4909
4910         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4911
4912         switch (plane_state->color_encoding) {
4913         case DRM_COLOR_YCBCR_BT601:
4914                 if (full_range)
4915                         *color_space = COLOR_SPACE_YCBCR601;
4916                 else
4917                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4918                 break;
4919
4920         case DRM_COLOR_YCBCR_BT709:
4921                 if (full_range)
4922                         *color_space = COLOR_SPACE_YCBCR709;
4923                 else
4924                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4925                 break;
4926
4927         case DRM_COLOR_YCBCR_BT2020:
4928                 if (full_range)
4929                         *color_space = COLOR_SPACE_2020_YCBCR;
4930                 else
4931                         return -EINVAL;
4932                 break;
4933
4934         default:
4935                 return -EINVAL;
4936         }
4937
4938         return 0;
4939 }
4940
4941 static int
4942 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4943                             const struct drm_plane_state *plane_state,
4944                             const u64 tiling_flags,
4945                             struct dc_plane_info *plane_info,
4946                             struct dc_plane_address *address,
4947                             bool tmz_surface,
4948                             bool force_disable_dcc)
4949 {
4950         const struct drm_framebuffer *fb = plane_state->fb;
4951         const struct amdgpu_framebuffer *afb =
4952                 to_amdgpu_framebuffer(plane_state->fb);
4953         int ret;
4954
4955         memset(plane_info, 0, sizeof(*plane_info));
4956
4957         switch (fb->format->format) {
4958         case DRM_FORMAT_C8:
4959                 plane_info->format =
4960                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4961                 break;
4962         case DRM_FORMAT_RGB565:
4963                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4964                 break;
4965         case DRM_FORMAT_XRGB8888:
4966         case DRM_FORMAT_ARGB8888:
4967                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4968                 break;
4969         case DRM_FORMAT_XRGB2101010:
4970         case DRM_FORMAT_ARGB2101010:
4971                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4972                 break;
4973         case DRM_FORMAT_XBGR2101010:
4974         case DRM_FORMAT_ABGR2101010:
4975                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4976                 break;
4977         case DRM_FORMAT_XBGR8888:
4978         case DRM_FORMAT_ABGR8888:
4979                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4980                 break;
4981         case DRM_FORMAT_NV21:
4982                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4983                 break;
4984         case DRM_FORMAT_NV12:
4985                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4986                 break;
4987         case DRM_FORMAT_P010:
4988                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4989                 break;
4990         case DRM_FORMAT_XRGB16161616F:
4991         case DRM_FORMAT_ARGB16161616F:
4992                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4993                 break;
4994         case DRM_FORMAT_XBGR16161616F:
4995         case DRM_FORMAT_ABGR16161616F:
4996                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4997                 break;
4998         case DRM_FORMAT_XRGB16161616:
4999         case DRM_FORMAT_ARGB16161616:
5000                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
5001                 break;
5002         case DRM_FORMAT_XBGR16161616:
5003         case DRM_FORMAT_ABGR16161616:
5004                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5005                 break;
5006         default:
5007                 DRM_ERROR(
5008                         "Unsupported screen format %p4cc\n",
5009                         &fb->format->format);
5010                 return -EINVAL;
5011         }
5012
5013         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5014         case DRM_MODE_ROTATE_0:
5015                 plane_info->rotation = ROTATION_ANGLE_0;
5016                 break;
5017         case DRM_MODE_ROTATE_90:
5018                 plane_info->rotation = ROTATION_ANGLE_90;
5019                 break;
5020         case DRM_MODE_ROTATE_180:
5021                 plane_info->rotation = ROTATION_ANGLE_180;
5022                 break;
5023         case DRM_MODE_ROTATE_270:
5024                 plane_info->rotation = ROTATION_ANGLE_270;
5025                 break;
5026         default:
5027                 plane_info->rotation = ROTATION_ANGLE_0;
5028                 break;
5029         }
5030
5031
5032         plane_info->visible = true;
5033         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5034
5035         plane_info->layer_index = plane_state->normalized_zpos;
5036
5037         ret = fill_plane_color_attributes(plane_state, plane_info->format,
5038                                           &plane_info->color_space);
5039         if (ret)
5040                 return ret;
5041
5042         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5043                                            plane_info->rotation, tiling_flags,
5044                                            &plane_info->tiling_info,
5045                                            &plane_info->plane_size,
5046                                            &plane_info->dcc, address,
5047                                            tmz_surface, force_disable_dcc);
5048         if (ret)
5049                 return ret;
5050
5051         amdgpu_dm_plane_fill_blending_from_plane_state(
5052                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5053                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5054
5055         return 0;
5056 }
5057
5058 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5059                                     struct dc_plane_state *dc_plane_state,
5060                                     struct drm_plane_state *plane_state,
5061                                     struct drm_crtc_state *crtc_state)
5062 {
5063         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5064         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5065         struct dc_scaling_info scaling_info;
5066         struct dc_plane_info plane_info;
5067         int ret;
5068         bool force_disable_dcc = false;
5069
5070         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5071         if (ret)
5072                 return ret;
5073
5074         dc_plane_state->src_rect = scaling_info.src_rect;
5075         dc_plane_state->dst_rect = scaling_info.dst_rect;
5076         dc_plane_state->clip_rect = scaling_info.clip_rect;
5077         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5078
5079         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5080         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5081                                           afb->tiling_flags,
5082                                           &plane_info,
5083                                           &dc_plane_state->address,
5084                                           afb->tmz_surface,
5085                                           force_disable_dcc);
5086         if (ret)
5087                 return ret;
5088
5089         dc_plane_state->format = plane_info.format;
5090         dc_plane_state->color_space = plane_info.color_space;
5091         dc_plane_state->format = plane_info.format;
5092         dc_plane_state->plane_size = plane_info.plane_size;
5093         dc_plane_state->rotation = plane_info.rotation;
5094         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5095         dc_plane_state->stereo_format = plane_info.stereo_format;
5096         dc_plane_state->tiling_info = plane_info.tiling_info;
5097         dc_plane_state->visible = plane_info.visible;
5098         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5099         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5100         dc_plane_state->global_alpha = plane_info.global_alpha;
5101         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5102         dc_plane_state->dcc = plane_info.dcc;
5103         dc_plane_state->layer_index = plane_info.layer_index;
5104         dc_plane_state->flip_int_enabled = true;
5105
5106         /*
5107          * Always set input transfer function, since plane state is refreshed
5108          * every time.
5109          */
5110         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5111         if (ret)
5112                 return ret;
5113
5114         return 0;
5115 }
5116
5117 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5118                                       struct rect *dirty_rect, int32_t x,
5119                                       s32 y, s32 width, s32 height,
5120                                       int *i, bool ffu)
5121 {
5122         WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5123
5124         dirty_rect->x = x;
5125         dirty_rect->y = y;
5126         dirty_rect->width = width;
5127         dirty_rect->height = height;
5128
5129         if (ffu)
5130                 drm_dbg(plane->dev,
5131                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5132                         plane->base.id, width, height);
5133         else
5134                 drm_dbg(plane->dev,
5135                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5136                         plane->base.id, x, y, width, height);
5137
5138         (*i)++;
5139 }
5140
5141 /**
5142  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5143  *
5144  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5145  *         remote fb
5146  * @old_plane_state: Old state of @plane
5147  * @new_plane_state: New state of @plane
5148  * @crtc_state: New state of CRTC connected to the @plane
5149  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5150  * @dirty_regions_changed: dirty regions changed
5151  *
5152  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5153  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5154  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5155  * amdgpu_dm's.
5156  *
5157  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5158  * plane with regions that require flushing to the eDP remote buffer. In
5159  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5160  * implicitly provide damage clips without any client support via the plane
5161  * bounds.
5162  */
5163 static void fill_dc_dirty_rects(struct drm_plane *plane,
5164                                 struct drm_plane_state *old_plane_state,
5165                                 struct drm_plane_state *new_plane_state,
5166                                 struct drm_crtc_state *crtc_state,
5167                                 struct dc_flip_addrs *flip_addrs,
5168                                 bool *dirty_regions_changed)
5169 {
5170         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5171         struct rect *dirty_rects = flip_addrs->dirty_rects;
5172         u32 num_clips;
5173         struct drm_mode_rect *clips;
5174         bool bb_changed;
5175         bool fb_changed;
5176         u32 i = 0;
5177         *dirty_regions_changed = false;
5178
5179         /*
5180          * Cursor plane has it's own dirty rect update interface. See
5181          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5182          */
5183         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5184                 return;
5185
5186         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5187         clips = drm_plane_get_damage_clips(new_plane_state);
5188
5189         if (!dm_crtc_state->mpo_requested) {
5190                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5191                         goto ffu;
5192
5193                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5194                         fill_dc_dirty_rect(new_plane_state->plane,
5195                                            &dirty_rects[flip_addrs->dirty_rect_count],
5196                                            clips->x1, clips->y1,
5197                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5198                                            &flip_addrs->dirty_rect_count,
5199                                            false);
5200                 return;
5201         }
5202
5203         /*
5204          * MPO is requested. Add entire plane bounding box to dirty rects if
5205          * flipped to or damaged.
5206          *
5207          * If plane is moved or resized, also add old bounding box to dirty
5208          * rects.
5209          */
5210         fb_changed = old_plane_state->fb->base.id !=
5211                      new_plane_state->fb->base.id;
5212         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5213                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5214                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5215                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5216
5217         drm_dbg(plane->dev,
5218                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5219                 new_plane_state->plane->base.id,
5220                 bb_changed, fb_changed, num_clips);
5221
5222         *dirty_regions_changed = bb_changed;
5223
5224         if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5225                 goto ffu;
5226
5227         if (bb_changed) {
5228                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5229                                    new_plane_state->crtc_x,
5230                                    new_plane_state->crtc_y,
5231                                    new_plane_state->crtc_w,
5232                                    new_plane_state->crtc_h, &i, false);
5233
5234                 /* Add old plane bounding-box if plane is moved or resized */
5235                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5236                                    old_plane_state->crtc_x,
5237                                    old_plane_state->crtc_y,
5238                                    old_plane_state->crtc_w,
5239                                    old_plane_state->crtc_h, &i, false);
5240         }
5241
5242         if (num_clips) {
5243                 for (; i < num_clips; clips++)
5244                         fill_dc_dirty_rect(new_plane_state->plane,
5245                                            &dirty_rects[i], clips->x1,
5246                                            clips->y1, clips->x2 - clips->x1,
5247                                            clips->y2 - clips->y1, &i, false);
5248         } else if (fb_changed && !bb_changed) {
5249                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5250                                    new_plane_state->crtc_x,
5251                                    new_plane_state->crtc_y,
5252                                    new_plane_state->crtc_w,
5253                                    new_plane_state->crtc_h, &i, false);
5254         }
5255
5256         flip_addrs->dirty_rect_count = i;
5257         return;
5258
5259 ffu:
5260         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5261                            dm_crtc_state->base.mode.crtc_hdisplay,
5262                            dm_crtc_state->base.mode.crtc_vdisplay,
5263                            &flip_addrs->dirty_rect_count, true);
5264 }
5265
5266 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5267                                            const struct dm_connector_state *dm_state,
5268                                            struct dc_stream_state *stream)
5269 {
5270         enum amdgpu_rmx_type rmx_type;
5271
5272         struct rect src = { 0 }; /* viewport in composition space*/
5273         struct rect dst = { 0 }; /* stream addressable area */
5274
5275         /* no mode. nothing to be done */
5276         if (!mode)
5277                 return;
5278
5279         /* Full screen scaling by default */
5280         src.width = mode->hdisplay;
5281         src.height = mode->vdisplay;
5282         dst.width = stream->timing.h_addressable;
5283         dst.height = stream->timing.v_addressable;
5284
5285         if (dm_state) {
5286                 rmx_type = dm_state->scaling;
5287                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5288                         if (src.width * dst.height <
5289                                         src.height * dst.width) {
5290                                 /* height needs less upscaling/more downscaling */
5291                                 dst.width = src.width *
5292                                                 dst.height / src.height;
5293                         } else {
5294                                 /* width needs less upscaling/more downscaling */
5295                                 dst.height = src.height *
5296                                                 dst.width / src.width;
5297                         }
5298                 } else if (rmx_type == RMX_CENTER) {
5299                         dst = src;
5300                 }
5301
5302                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5303                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5304
5305                 if (dm_state->underscan_enable) {
5306                         dst.x += dm_state->underscan_hborder / 2;
5307                         dst.y += dm_state->underscan_vborder / 2;
5308                         dst.width -= dm_state->underscan_hborder;
5309                         dst.height -= dm_state->underscan_vborder;
5310                 }
5311         }
5312
5313         stream->src = src;
5314         stream->dst = dst;
5315
5316         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5317                       dst.x, dst.y, dst.width, dst.height);
5318
5319 }
5320
5321 static enum dc_color_depth
5322 convert_color_depth_from_display_info(const struct drm_connector *connector,
5323                                       bool is_y420, int requested_bpc)
5324 {
5325         u8 bpc;
5326
5327         if (is_y420) {
5328                 bpc = 8;
5329
5330                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5331                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5332                         bpc = 16;
5333                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5334                         bpc = 12;
5335                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5336                         bpc = 10;
5337         } else {
5338                 bpc = (uint8_t)connector->display_info.bpc;
5339                 /* Assume 8 bpc by default if no bpc is specified. */
5340                 bpc = bpc ? bpc : 8;
5341         }
5342
5343         if (requested_bpc > 0) {
5344                 /*
5345                  * Cap display bpc based on the user requested value.
5346                  *
5347                  * The value for state->max_bpc may not correctly updated
5348                  * depending on when the connector gets added to the state
5349                  * or if this was called outside of atomic check, so it
5350                  * can't be used directly.
5351                  */
5352                 bpc = min_t(u8, bpc, requested_bpc);
5353
5354                 /* Round down to the nearest even number. */
5355                 bpc = bpc - (bpc & 1);
5356         }
5357
5358         switch (bpc) {
5359         case 0:
5360                 /*
5361                  * Temporary Work around, DRM doesn't parse color depth for
5362                  * EDID revision before 1.4
5363                  * TODO: Fix edid parsing
5364                  */
5365                 return COLOR_DEPTH_888;
5366         case 6:
5367                 return COLOR_DEPTH_666;
5368         case 8:
5369                 return COLOR_DEPTH_888;
5370         case 10:
5371                 return COLOR_DEPTH_101010;
5372         case 12:
5373                 return COLOR_DEPTH_121212;
5374         case 14:
5375                 return COLOR_DEPTH_141414;
5376         case 16:
5377                 return COLOR_DEPTH_161616;
5378         default:
5379                 return COLOR_DEPTH_UNDEFINED;
5380         }
5381 }
5382
5383 static enum dc_aspect_ratio
5384 get_aspect_ratio(const struct drm_display_mode *mode_in)
5385 {
5386         /* 1-1 mapping, since both enums follow the HDMI spec. */
5387         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5388 }
5389
5390 static enum dc_color_space
5391 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5392                        const struct drm_connector_state *connector_state)
5393 {
5394         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5395
5396         switch (connector_state->colorspace) {
5397         case DRM_MODE_COLORIMETRY_BT601_YCC:
5398                 if (dc_crtc_timing->flags.Y_ONLY)
5399                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5400                 else
5401                         color_space = COLOR_SPACE_YCBCR601;
5402                 break;
5403         case DRM_MODE_COLORIMETRY_BT709_YCC:
5404                 if (dc_crtc_timing->flags.Y_ONLY)
5405                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5406                 else
5407                         color_space = COLOR_SPACE_YCBCR709;
5408                 break;
5409         case DRM_MODE_COLORIMETRY_OPRGB:
5410                 color_space = COLOR_SPACE_ADOBERGB;
5411                 break;
5412         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5413         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5414                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5415                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5416                 else
5417                         color_space = COLOR_SPACE_2020_YCBCR;
5418                 break;
5419         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5420         default:
5421                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5422                         color_space = COLOR_SPACE_SRGB;
5423                 /*
5424                  * 27030khz is the separation point between HDTV and SDTV
5425                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5426                  * respectively
5427                  */
5428                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5429                         if (dc_crtc_timing->flags.Y_ONLY)
5430                                 color_space =
5431                                         COLOR_SPACE_YCBCR709_LIMITED;
5432                         else
5433                                 color_space = COLOR_SPACE_YCBCR709;
5434                 } else {
5435                         if (dc_crtc_timing->flags.Y_ONLY)
5436                                 color_space =
5437                                         COLOR_SPACE_YCBCR601_LIMITED;
5438                         else
5439                                 color_space = COLOR_SPACE_YCBCR601;
5440                 }
5441                 break;
5442         }
5443
5444         return color_space;
5445 }
5446
5447 static enum display_content_type
5448 get_output_content_type(const struct drm_connector_state *connector_state)
5449 {
5450         switch (connector_state->content_type) {
5451         default:
5452         case DRM_MODE_CONTENT_TYPE_NO_DATA:
5453                 return DISPLAY_CONTENT_TYPE_NO_DATA;
5454         case DRM_MODE_CONTENT_TYPE_GRAPHICS:
5455                 return DISPLAY_CONTENT_TYPE_GRAPHICS;
5456         case DRM_MODE_CONTENT_TYPE_PHOTO:
5457                 return DISPLAY_CONTENT_TYPE_PHOTO;
5458         case DRM_MODE_CONTENT_TYPE_CINEMA:
5459                 return DISPLAY_CONTENT_TYPE_CINEMA;
5460         case DRM_MODE_CONTENT_TYPE_GAME:
5461                 return DISPLAY_CONTENT_TYPE_GAME;
5462         }
5463 }
5464
5465 static bool adjust_colour_depth_from_display_info(
5466         struct dc_crtc_timing *timing_out,
5467         const struct drm_display_info *info)
5468 {
5469         enum dc_color_depth depth = timing_out->display_color_depth;
5470         int normalized_clk;
5471
5472         do {
5473                 normalized_clk = timing_out->pix_clk_100hz / 10;
5474                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5475                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5476                         normalized_clk /= 2;
5477                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5478                 switch (depth) {
5479                 case COLOR_DEPTH_888:
5480                         break;
5481                 case COLOR_DEPTH_101010:
5482                         normalized_clk = (normalized_clk * 30) / 24;
5483                         break;
5484                 case COLOR_DEPTH_121212:
5485                         normalized_clk = (normalized_clk * 36) / 24;
5486                         break;
5487                 case COLOR_DEPTH_161616:
5488                         normalized_clk = (normalized_clk * 48) / 24;
5489                         break;
5490                 default:
5491                         /* The above depths are the only ones valid for HDMI. */
5492                         return false;
5493                 }
5494                 if (normalized_clk <= info->max_tmds_clock) {
5495                         timing_out->display_color_depth = depth;
5496                         return true;
5497                 }
5498         } while (--depth > COLOR_DEPTH_666);
5499         return false;
5500 }
5501
5502 static void fill_stream_properties_from_drm_display_mode(
5503         struct dc_stream_state *stream,
5504         const struct drm_display_mode *mode_in,
5505         const struct drm_connector *connector,
5506         const struct drm_connector_state *connector_state,
5507         const struct dc_stream_state *old_stream,
5508         int requested_bpc)
5509 {
5510         struct dc_crtc_timing *timing_out = &stream->timing;
5511         const struct drm_display_info *info = &connector->display_info;
5512         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5513         struct hdmi_vendor_infoframe hv_frame;
5514         struct hdmi_avi_infoframe avi_frame;
5515
5516         memset(&hv_frame, 0, sizeof(hv_frame));
5517         memset(&avi_frame, 0, sizeof(avi_frame));
5518
5519         timing_out->h_border_left = 0;
5520         timing_out->h_border_right = 0;
5521         timing_out->v_border_top = 0;
5522         timing_out->v_border_bottom = 0;
5523         /* TODO: un-hardcode */
5524         if (drm_mode_is_420_only(info, mode_in)
5525                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5526                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5527         else if (drm_mode_is_420_also(info, mode_in)
5528                         && aconnector->force_yuv420_output)
5529                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5530         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5531                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5532                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5533         else
5534                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5535
5536         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5537         timing_out->display_color_depth = convert_color_depth_from_display_info(
5538                 connector,
5539                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5540                 requested_bpc);
5541         timing_out->scan_type = SCANNING_TYPE_NODATA;
5542         timing_out->hdmi_vic = 0;
5543
5544         if (old_stream) {
5545                 timing_out->vic = old_stream->timing.vic;
5546                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5547                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5548         } else {
5549                 timing_out->vic = drm_match_cea_mode(mode_in);
5550                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5551                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5552                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5553                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5554         }
5555
5556         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5557                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5558                 timing_out->vic = avi_frame.video_code;
5559                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5560                 timing_out->hdmi_vic = hv_frame.vic;
5561         }
5562
5563         if (is_freesync_video_mode(mode_in, aconnector)) {
5564                 timing_out->h_addressable = mode_in->hdisplay;
5565                 timing_out->h_total = mode_in->htotal;
5566                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5567                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5568                 timing_out->v_total = mode_in->vtotal;
5569                 timing_out->v_addressable = mode_in->vdisplay;
5570                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5571                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5572                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5573         } else {
5574                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5575                 timing_out->h_total = mode_in->crtc_htotal;
5576                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5577                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5578                 timing_out->v_total = mode_in->crtc_vtotal;
5579                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5580                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5581                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5582                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5583         }
5584
5585         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5586
5587         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5588         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5589         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5590                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5591                     drm_mode_is_420_also(info, mode_in) &&
5592                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5593                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5594                         adjust_colour_depth_from_display_info(timing_out, info);
5595                 }
5596         }
5597
5598         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5599         stream->content_type = get_output_content_type(connector_state);
5600 }
5601
5602 static void fill_audio_info(struct audio_info *audio_info,
5603                             const struct drm_connector *drm_connector,
5604                             const struct dc_sink *dc_sink)
5605 {
5606         int i = 0;
5607         int cea_revision = 0;
5608         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5609
5610         audio_info->manufacture_id = edid_caps->manufacturer_id;
5611         audio_info->product_id = edid_caps->product_id;
5612
5613         cea_revision = drm_connector->display_info.cea_rev;
5614
5615         strscpy(audio_info->display_name,
5616                 edid_caps->display_name,
5617                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5618
5619         if (cea_revision >= 3) {
5620                 audio_info->mode_count = edid_caps->audio_mode_count;
5621
5622                 for (i = 0; i < audio_info->mode_count; ++i) {
5623                         audio_info->modes[i].format_code =
5624                                         (enum audio_format_code)
5625                                         (edid_caps->audio_modes[i].format_code);
5626                         audio_info->modes[i].channel_count =
5627                                         edid_caps->audio_modes[i].channel_count;
5628                         audio_info->modes[i].sample_rates.all =
5629                                         edid_caps->audio_modes[i].sample_rate;
5630                         audio_info->modes[i].sample_size =
5631                                         edid_caps->audio_modes[i].sample_size;
5632                 }
5633         }
5634
5635         audio_info->flags.all = edid_caps->speaker_flags;
5636
5637         /* TODO: We only check for the progressive mode, check for interlace mode too */
5638         if (drm_connector->latency_present[0]) {
5639                 audio_info->video_latency = drm_connector->video_latency[0];
5640                 audio_info->audio_latency = drm_connector->audio_latency[0];
5641         }
5642
5643         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5644
5645 }
5646
5647 static void
5648 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5649                                       struct drm_display_mode *dst_mode)
5650 {
5651         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5652         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5653         dst_mode->crtc_clock = src_mode->crtc_clock;
5654         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5655         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5656         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5657         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5658         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5659         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5660         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5661         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5662         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5663         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5664         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5665 }
5666
5667 static void
5668 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5669                                         const struct drm_display_mode *native_mode,
5670                                         bool scale_enabled)
5671 {
5672         if (scale_enabled) {
5673                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5674         } else if (native_mode->clock == drm_mode->clock &&
5675                         native_mode->htotal == drm_mode->htotal &&
5676                         native_mode->vtotal == drm_mode->vtotal) {
5677                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5678         } else {
5679                 /* no scaling nor amdgpu inserted, no need to patch */
5680         }
5681 }
5682
5683 static struct dc_sink *
5684 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5685 {
5686         struct dc_sink_init_data sink_init_data = { 0 };
5687         struct dc_sink *sink = NULL;
5688
5689         sink_init_data.link = aconnector->dc_link;
5690         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5691
5692         sink = dc_sink_create(&sink_init_data);
5693         if (!sink) {
5694                 DRM_ERROR("Failed to create sink!\n");
5695                 return NULL;
5696         }
5697         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5698
5699         return sink;
5700 }
5701
5702 static void set_multisync_trigger_params(
5703                 struct dc_stream_state *stream)
5704 {
5705         struct dc_stream_state *master = NULL;
5706
5707         if (stream->triggered_crtc_reset.enabled) {
5708                 master = stream->triggered_crtc_reset.event_source;
5709                 stream->triggered_crtc_reset.event =
5710                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5711                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5712                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5713         }
5714 }
5715
5716 static void set_master_stream(struct dc_stream_state *stream_set[],
5717                               int stream_count)
5718 {
5719         int j, highest_rfr = 0, master_stream = 0;
5720
5721         for (j = 0;  j < stream_count; j++) {
5722                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5723                         int refresh_rate = 0;
5724
5725                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5726                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5727                         if (refresh_rate > highest_rfr) {
5728                                 highest_rfr = refresh_rate;
5729                                 master_stream = j;
5730                         }
5731                 }
5732         }
5733         for (j = 0;  j < stream_count; j++) {
5734                 if (stream_set[j])
5735                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5736         }
5737 }
5738
5739 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5740 {
5741         int i = 0;
5742         struct dc_stream_state *stream;
5743
5744         if (context->stream_count < 2)
5745                 return;
5746         for (i = 0; i < context->stream_count ; i++) {
5747                 if (!context->streams[i])
5748                         continue;
5749                 /*
5750                  * TODO: add a function to read AMD VSDB bits and set
5751                  * crtc_sync_master.multi_sync_enabled flag
5752                  * For now it's set to false
5753                  */
5754         }
5755
5756         set_master_stream(context->streams, context->stream_count);
5757
5758         for (i = 0; i < context->stream_count ; i++) {
5759                 stream = context->streams[i];
5760
5761                 if (!stream)
5762                         continue;
5763
5764                 set_multisync_trigger_params(stream);
5765         }
5766 }
5767
5768 /**
5769  * DOC: FreeSync Video
5770  *
5771  * When a userspace application wants to play a video, the content follows a
5772  * standard format definition that usually specifies the FPS for that format.
5773  * The below list illustrates some video format and the expected FPS,
5774  * respectively:
5775  *
5776  * - TV/NTSC (23.976 FPS)
5777  * - Cinema (24 FPS)
5778  * - TV/PAL (25 FPS)
5779  * - TV/NTSC (29.97 FPS)
5780  * - TV/NTSC (30 FPS)
5781  * - Cinema HFR (48 FPS)
5782  * - TV/PAL (50 FPS)
5783  * - Commonly used (60 FPS)
5784  * - Multiples of 24 (48,72,96 FPS)
5785  *
5786  * The list of standards video format is not huge and can be added to the
5787  * connector modeset list beforehand. With that, userspace can leverage
5788  * FreeSync to extends the front porch in order to attain the target refresh
5789  * rate. Such a switch will happen seamlessly, without screen blanking or
5790  * reprogramming of the output in any other way. If the userspace requests a
5791  * modesetting change compatible with FreeSync modes that only differ in the
5792  * refresh rate, DC will skip the full update and avoid blink during the
5793  * transition. For example, the video player can change the modesetting from
5794  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5795  * causing any display blink. This same concept can be applied to a mode
5796  * setting change.
5797  */
5798 static struct drm_display_mode *
5799 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5800                 bool use_probed_modes)
5801 {
5802         struct drm_display_mode *m, *m_pref = NULL;
5803         u16 current_refresh, highest_refresh;
5804         struct list_head *list_head = use_probed_modes ?
5805                 &aconnector->base.probed_modes :
5806                 &aconnector->base.modes;
5807
5808         if (aconnector->freesync_vid_base.clock != 0)
5809                 return &aconnector->freesync_vid_base;
5810
5811         /* Find the preferred mode */
5812         list_for_each_entry(m, list_head, head) {
5813                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5814                         m_pref = m;
5815                         break;
5816                 }
5817         }
5818
5819         if (!m_pref) {
5820                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5821                 m_pref = list_first_entry_or_null(
5822                                 &aconnector->base.modes, struct drm_display_mode, head);
5823                 if (!m_pref) {
5824                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5825                         return NULL;
5826                 }
5827         }
5828
5829         highest_refresh = drm_mode_vrefresh(m_pref);
5830
5831         /*
5832          * Find the mode with highest refresh rate with same resolution.
5833          * For some monitors, preferred mode is not the mode with highest
5834          * supported refresh rate.
5835          */
5836         list_for_each_entry(m, list_head, head) {
5837                 current_refresh  = drm_mode_vrefresh(m);
5838
5839                 if (m->hdisplay == m_pref->hdisplay &&
5840                     m->vdisplay == m_pref->vdisplay &&
5841                     highest_refresh < current_refresh) {
5842                         highest_refresh = current_refresh;
5843                         m_pref = m;
5844                 }
5845         }
5846
5847         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5848         return m_pref;
5849 }
5850
5851 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5852                 struct amdgpu_dm_connector *aconnector)
5853 {
5854         struct drm_display_mode *high_mode;
5855         int timing_diff;
5856
5857         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5858         if (!high_mode || !mode)
5859                 return false;
5860
5861         timing_diff = high_mode->vtotal - mode->vtotal;
5862
5863         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5864             high_mode->hdisplay != mode->hdisplay ||
5865             high_mode->vdisplay != mode->vdisplay ||
5866             high_mode->hsync_start != mode->hsync_start ||
5867             high_mode->hsync_end != mode->hsync_end ||
5868             high_mode->htotal != mode->htotal ||
5869             high_mode->hskew != mode->hskew ||
5870             high_mode->vscan != mode->vscan ||
5871             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5872             high_mode->vsync_end - mode->vsync_end != timing_diff)
5873                 return false;
5874         else
5875                 return true;
5876 }
5877
5878 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5879                             struct dc_sink *sink, struct dc_stream_state *stream,
5880                             struct dsc_dec_dpcd_caps *dsc_caps)
5881 {
5882         stream->timing.flags.DSC = 0;
5883         dsc_caps->is_dsc_supported = false;
5884
5885         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5886             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5887                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5888                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5889                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5890                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5891                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5892                                 dsc_caps);
5893         }
5894 }
5895
5896
5897 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5898                                     struct dc_sink *sink, struct dc_stream_state *stream,
5899                                     struct dsc_dec_dpcd_caps *dsc_caps,
5900                                     uint32_t max_dsc_target_bpp_limit_override)
5901 {
5902         const struct dc_link_settings *verified_link_cap = NULL;
5903         u32 link_bw_in_kbps;
5904         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5905         struct dc *dc = sink->ctx->dc;
5906         struct dc_dsc_bw_range bw_range = {0};
5907         struct dc_dsc_config dsc_cfg = {0};
5908         struct dc_dsc_config_options dsc_options = {0};
5909
5910         dc_dsc_get_default_config_option(dc, &dsc_options);
5911         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5912
5913         verified_link_cap = dc_link_get_link_cap(stream->link);
5914         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5915         edp_min_bpp_x16 = 8 * 16;
5916         edp_max_bpp_x16 = 8 * 16;
5917
5918         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5919                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5920
5921         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5922                 edp_min_bpp_x16 = edp_max_bpp_x16;
5923
5924         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5925                                 dc->debug.dsc_min_slice_height_override,
5926                                 edp_min_bpp_x16, edp_max_bpp_x16,
5927                                 dsc_caps,
5928                                 &stream->timing,
5929                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5930                                 &bw_range)) {
5931
5932                 if (bw_range.max_kbps < link_bw_in_kbps) {
5933                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5934                                         dsc_caps,
5935                                         &dsc_options,
5936                                         0,
5937                                         &stream->timing,
5938                                         dc_link_get_highest_encoding_format(aconnector->dc_link),
5939                                         &dsc_cfg)) {
5940                                 stream->timing.dsc_cfg = dsc_cfg;
5941                                 stream->timing.flags.DSC = 1;
5942                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5943                         }
5944                         return;
5945                 }
5946         }
5947
5948         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5949                                 dsc_caps,
5950                                 &dsc_options,
5951                                 link_bw_in_kbps,
5952                                 &stream->timing,
5953                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5954                                 &dsc_cfg)) {
5955                 stream->timing.dsc_cfg = dsc_cfg;
5956                 stream->timing.flags.DSC = 1;
5957         }
5958 }
5959
5960
5961 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5962                                         struct dc_sink *sink, struct dc_stream_state *stream,
5963                                         struct dsc_dec_dpcd_caps *dsc_caps)
5964 {
5965         struct drm_connector *drm_connector = &aconnector->base;
5966         u32 link_bandwidth_kbps;
5967         struct dc *dc = sink->ctx->dc;
5968         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5969         u32 dsc_max_supported_bw_in_kbps;
5970         u32 max_dsc_target_bpp_limit_override =
5971                 drm_connector->display_info.max_dsc_bpp;
5972         struct dc_dsc_config_options dsc_options = {0};
5973
5974         dc_dsc_get_default_config_option(dc, &dsc_options);
5975         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5976
5977         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5978                                                         dc_link_get_link_cap(aconnector->dc_link));
5979
5980         /* Set DSC policy according to dsc_clock_en */
5981         dc_dsc_policy_set_enable_dsc_when_not_needed(
5982                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5983
5984         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5985             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5986             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5987
5988                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5989
5990         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5991                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5992                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5993                                                 dsc_caps,
5994                                                 &dsc_options,
5995                                                 link_bandwidth_kbps,
5996                                                 &stream->timing,
5997                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5998                                                 &stream->timing.dsc_cfg)) {
5999                                 stream->timing.flags.DSC = 1;
6000                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
6001                         }
6002                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6003                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6004                                         dc_link_get_highest_encoding_format(aconnector->dc_link));
6005                         max_supported_bw_in_kbps = link_bandwidth_kbps;
6006                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6007
6008                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6009                                         max_supported_bw_in_kbps > 0 &&
6010                                         dsc_max_supported_bw_in_kbps > 0)
6011                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6012                                                 dsc_caps,
6013                                                 &dsc_options,
6014                                                 dsc_max_supported_bw_in_kbps,
6015                                                 &stream->timing,
6016                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6017                                                 &stream->timing.dsc_cfg)) {
6018                                         stream->timing.flags.DSC = 1;
6019                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
6020                                                                          __func__, drm_connector->name);
6021                                 }
6022                 }
6023         }
6024
6025         /* Overwrite the stream flag if DSC is enabled through debugfs */
6026         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6027                 stream->timing.flags.DSC = 1;
6028
6029         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6030                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6031
6032         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6033                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6034
6035         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6036                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6037 }
6038
6039 static struct dc_stream_state *
6040 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6041                        const struct drm_display_mode *drm_mode,
6042                        const struct dm_connector_state *dm_state,
6043                        const struct dc_stream_state *old_stream,
6044                        int requested_bpc)
6045 {
6046         struct drm_display_mode *preferred_mode = NULL;
6047         struct drm_connector *drm_connector;
6048         const struct drm_connector_state *con_state = &dm_state->base;
6049         struct dc_stream_state *stream = NULL;
6050         struct drm_display_mode mode;
6051         struct drm_display_mode saved_mode;
6052         struct drm_display_mode *freesync_mode = NULL;
6053         bool native_mode_found = false;
6054         bool recalculate_timing = false;
6055         bool scale = dm_state->scaling != RMX_OFF;
6056         int mode_refresh;
6057         int preferred_refresh = 0;
6058         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6059         struct dsc_dec_dpcd_caps dsc_caps;
6060
6061         struct dc_sink *sink = NULL;
6062
6063         drm_mode_init(&mode, drm_mode);
6064         memset(&saved_mode, 0, sizeof(saved_mode));
6065
6066         if (aconnector == NULL) {
6067                 DRM_ERROR("aconnector is NULL!\n");
6068                 return stream;
6069         }
6070
6071         drm_connector = &aconnector->base;
6072
6073         if (!aconnector->dc_sink) {
6074                 sink = create_fake_sink(aconnector);
6075                 if (!sink)
6076                         return stream;
6077         } else {
6078                 sink = aconnector->dc_sink;
6079                 dc_sink_retain(sink);
6080         }
6081
6082         stream = dc_create_stream_for_sink(sink);
6083
6084         if (stream == NULL) {
6085                 DRM_ERROR("Failed to create stream for sink!\n");
6086                 goto finish;
6087         }
6088
6089         stream->dm_stream_context = aconnector;
6090
6091         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6092                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6093
6094         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6095                 /* Search for preferred mode */
6096                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6097                         native_mode_found = true;
6098                         break;
6099                 }
6100         }
6101         if (!native_mode_found)
6102                 preferred_mode = list_first_entry_or_null(
6103                                 &aconnector->base.modes,
6104                                 struct drm_display_mode,
6105                                 head);
6106
6107         mode_refresh = drm_mode_vrefresh(&mode);
6108
6109         if (preferred_mode == NULL) {
6110                 /*
6111                  * This may not be an error, the use case is when we have no
6112                  * usermode calls to reset and set mode upon hotplug. In this
6113                  * case, we call set mode ourselves to restore the previous mode
6114                  * and the modelist may not be filled in time.
6115                  */
6116                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6117         } else {
6118                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6119                 if (recalculate_timing) {
6120                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6121                         drm_mode_copy(&saved_mode, &mode);
6122                         drm_mode_copy(&mode, freesync_mode);
6123                 } else {
6124                         decide_crtc_timing_for_drm_display_mode(
6125                                         &mode, preferred_mode, scale);
6126
6127                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6128                 }
6129         }
6130
6131         if (recalculate_timing)
6132                 drm_mode_set_crtcinfo(&saved_mode, 0);
6133
6134         /*
6135          * If scaling is enabled and refresh rate didn't change
6136          * we copy the vic and polarities of the old timings
6137          */
6138         if (!scale || mode_refresh != preferred_refresh)
6139                 fill_stream_properties_from_drm_display_mode(
6140                         stream, &mode, &aconnector->base, con_state, NULL,
6141                         requested_bpc);
6142         else
6143                 fill_stream_properties_from_drm_display_mode(
6144                         stream, &mode, &aconnector->base, con_state, old_stream,
6145                         requested_bpc);
6146
6147         if (aconnector->timing_changed) {
6148                 drm_dbg(aconnector->base.dev,
6149                         "overriding timing for automated test, bpc %d, changing to %d\n",
6150                         stream->timing.display_color_depth,
6151                         aconnector->timing_requested->display_color_depth);
6152                 stream->timing = *aconnector->timing_requested;
6153         }
6154
6155         /* SST DSC determination policy */
6156         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6157         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6158                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6159
6160         update_stream_scaling_settings(&mode, dm_state, stream);
6161
6162         fill_audio_info(
6163                 &stream->audio_info,
6164                 drm_connector,
6165                 sink);
6166
6167         update_stream_signal(stream, sink);
6168
6169         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6170                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6171
6172         if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6173                 //
6174                 // should decide stream support vsc sdp colorimetry capability
6175                 // before building vsc info packet
6176                 //
6177                 stream->use_vsc_sdp_for_colorimetry = false;
6178                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6179                         stream->use_vsc_sdp_for_colorimetry =
6180                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6181                 } else {
6182                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6183                                 stream->use_vsc_sdp_for_colorimetry = true;
6184                 }
6185                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6186                         tf = TRANSFER_FUNC_GAMMA_22;
6187                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6188                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6189
6190         }
6191 finish:
6192         dc_sink_release(sink);
6193
6194         return stream;
6195 }
6196
6197 static enum drm_connector_status
6198 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6199 {
6200         bool connected;
6201         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6202
6203         /*
6204          * Notes:
6205          * 1. This interface is NOT called in context of HPD irq.
6206          * 2. This interface *is called* in context of user-mode ioctl. Which
6207          * makes it a bad place for *any* MST-related activity.
6208          */
6209
6210         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6211             !aconnector->fake_enable)
6212                 connected = (aconnector->dc_sink != NULL);
6213         else
6214                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6215                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6216
6217         update_subconnector_property(aconnector);
6218
6219         return (connected ? connector_status_connected :
6220                         connector_status_disconnected);
6221 }
6222
6223 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6224                                             struct drm_connector_state *connector_state,
6225                                             struct drm_property *property,
6226                                             uint64_t val)
6227 {
6228         struct drm_device *dev = connector->dev;
6229         struct amdgpu_device *adev = drm_to_adev(dev);
6230         struct dm_connector_state *dm_old_state =
6231                 to_dm_connector_state(connector->state);
6232         struct dm_connector_state *dm_new_state =
6233                 to_dm_connector_state(connector_state);
6234
6235         int ret = -EINVAL;
6236
6237         if (property == dev->mode_config.scaling_mode_property) {
6238                 enum amdgpu_rmx_type rmx_type;
6239
6240                 switch (val) {
6241                 case DRM_MODE_SCALE_CENTER:
6242                         rmx_type = RMX_CENTER;
6243                         break;
6244                 case DRM_MODE_SCALE_ASPECT:
6245                         rmx_type = RMX_ASPECT;
6246                         break;
6247                 case DRM_MODE_SCALE_FULLSCREEN:
6248                         rmx_type = RMX_FULL;
6249                         break;
6250                 case DRM_MODE_SCALE_NONE:
6251                 default:
6252                         rmx_type = RMX_OFF;
6253                         break;
6254                 }
6255
6256                 if (dm_old_state->scaling == rmx_type)
6257                         return 0;
6258
6259                 dm_new_state->scaling = rmx_type;
6260                 ret = 0;
6261         } else if (property == adev->mode_info.underscan_hborder_property) {
6262                 dm_new_state->underscan_hborder = val;
6263                 ret = 0;
6264         } else if (property == adev->mode_info.underscan_vborder_property) {
6265                 dm_new_state->underscan_vborder = val;
6266                 ret = 0;
6267         } else if (property == adev->mode_info.underscan_property) {
6268                 dm_new_state->underscan_enable = val;
6269                 ret = 0;
6270         } else if (property == adev->mode_info.abm_level_property) {
6271                 dm_new_state->abm_level = val;
6272                 ret = 0;
6273         }
6274
6275         return ret;
6276 }
6277
6278 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6279                                             const struct drm_connector_state *state,
6280                                             struct drm_property *property,
6281                                             uint64_t *val)
6282 {
6283         struct drm_device *dev = connector->dev;
6284         struct amdgpu_device *adev = drm_to_adev(dev);
6285         struct dm_connector_state *dm_state =
6286                 to_dm_connector_state(state);
6287         int ret = -EINVAL;
6288
6289         if (property == dev->mode_config.scaling_mode_property) {
6290                 switch (dm_state->scaling) {
6291                 case RMX_CENTER:
6292                         *val = DRM_MODE_SCALE_CENTER;
6293                         break;
6294                 case RMX_ASPECT:
6295                         *val = DRM_MODE_SCALE_ASPECT;
6296                         break;
6297                 case RMX_FULL:
6298                         *val = DRM_MODE_SCALE_FULLSCREEN;
6299                         break;
6300                 case RMX_OFF:
6301                 default:
6302                         *val = DRM_MODE_SCALE_NONE;
6303                         break;
6304                 }
6305                 ret = 0;
6306         } else if (property == adev->mode_info.underscan_hborder_property) {
6307                 *val = dm_state->underscan_hborder;
6308                 ret = 0;
6309         } else if (property == adev->mode_info.underscan_vborder_property) {
6310                 *val = dm_state->underscan_vborder;
6311                 ret = 0;
6312         } else if (property == adev->mode_info.underscan_property) {
6313                 *val = dm_state->underscan_enable;
6314                 ret = 0;
6315         } else if (property == adev->mode_info.abm_level_property) {
6316                 *val = dm_state->abm_level;
6317                 ret = 0;
6318         }
6319
6320         return ret;
6321 }
6322
6323 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6324 {
6325         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6326
6327         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6328 }
6329
6330 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6331 {
6332         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6333         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6334         struct amdgpu_display_manager *dm = &adev->dm;
6335
6336         /*
6337          * Call only if mst_mgr was initialized before since it's not done
6338          * for all connector types.
6339          */
6340         if (aconnector->mst_mgr.dev)
6341                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6342
6343         if (aconnector->bl_idx != -1) {
6344                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6345                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6346         }
6347
6348         if (aconnector->dc_em_sink)
6349                 dc_sink_release(aconnector->dc_em_sink);
6350         aconnector->dc_em_sink = NULL;
6351         if (aconnector->dc_sink)
6352                 dc_sink_release(aconnector->dc_sink);
6353         aconnector->dc_sink = NULL;
6354
6355         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6356         drm_connector_unregister(connector);
6357         drm_connector_cleanup(connector);
6358         if (aconnector->i2c) {
6359                 i2c_del_adapter(&aconnector->i2c->base);
6360                 kfree(aconnector->i2c);
6361         }
6362         kfree(aconnector->dm_dp_aux.aux.name);
6363
6364         kfree(connector);
6365 }
6366
6367 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6368 {
6369         struct dm_connector_state *state =
6370                 to_dm_connector_state(connector->state);
6371
6372         if (connector->state)
6373                 __drm_atomic_helper_connector_destroy_state(connector->state);
6374
6375         kfree(state);
6376
6377         state = kzalloc(sizeof(*state), GFP_KERNEL);
6378
6379         if (state) {
6380                 state->scaling = RMX_OFF;
6381                 state->underscan_enable = false;
6382                 state->underscan_hborder = 0;
6383                 state->underscan_vborder = 0;
6384                 state->base.max_requested_bpc = 8;
6385                 state->vcpi_slots = 0;
6386                 state->pbn = 0;
6387
6388                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6389                         state->abm_level = amdgpu_dm_abm_level;
6390
6391                 __drm_atomic_helper_connector_reset(connector, &state->base);
6392         }
6393 }
6394
6395 struct drm_connector_state *
6396 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6397 {
6398         struct dm_connector_state *state =
6399                 to_dm_connector_state(connector->state);
6400
6401         struct dm_connector_state *new_state =
6402                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6403
6404         if (!new_state)
6405                 return NULL;
6406
6407         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6408
6409         new_state->freesync_capable = state->freesync_capable;
6410         new_state->abm_level = state->abm_level;
6411         new_state->scaling = state->scaling;
6412         new_state->underscan_enable = state->underscan_enable;
6413         new_state->underscan_hborder = state->underscan_hborder;
6414         new_state->underscan_vborder = state->underscan_vborder;
6415         new_state->vcpi_slots = state->vcpi_slots;
6416         new_state->pbn = state->pbn;
6417         return &new_state->base;
6418 }
6419
6420 static int
6421 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6422 {
6423         struct amdgpu_dm_connector *amdgpu_dm_connector =
6424                 to_amdgpu_dm_connector(connector);
6425         int r;
6426
6427         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6428
6429         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6430             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6431                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6432                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6433                 if (r)
6434                         return r;
6435         }
6436
6437 #if defined(CONFIG_DEBUG_FS)
6438         connector_debugfs_init(amdgpu_dm_connector);
6439 #endif
6440
6441         return 0;
6442 }
6443
6444 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6445 {
6446         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6447         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
6448         struct dc_link *dc_link = aconnector->dc_link;
6449         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6450         struct edid *edid;
6451
6452         /*
6453          * Note: drm_get_edid gets edid in the following order:
6454          * 1) override EDID if set via edid_override debugfs,
6455          * 2) firmware EDID if set via edid_firmware module parameter
6456          * 3) regular DDC read.
6457          */
6458         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6459         if (!edid) {
6460                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6461                 return;
6462         }
6463
6464         aconnector->edid = edid;
6465
6466         /* Update emulated (virtual) sink's EDID */
6467         if (dc_em_sink && dc_link) {
6468                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6469                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6470                 dm_helpers_parse_edid_caps(
6471                         dc_link,
6472                         &dc_em_sink->dc_edid,
6473                         &dc_em_sink->edid_caps);
6474         }
6475 }
6476
6477 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6478         .reset = amdgpu_dm_connector_funcs_reset,
6479         .detect = amdgpu_dm_connector_detect,
6480         .fill_modes = drm_helper_probe_single_connector_modes,
6481         .destroy = amdgpu_dm_connector_destroy,
6482         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6483         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6484         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6485         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6486         .late_register = amdgpu_dm_connector_late_register,
6487         .early_unregister = amdgpu_dm_connector_unregister,
6488         .force = amdgpu_dm_connector_funcs_force
6489 };
6490
6491 static int get_modes(struct drm_connector *connector)
6492 {
6493         return amdgpu_dm_connector_get_modes(connector);
6494 }
6495
6496 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6497 {
6498         struct drm_connector *connector = &aconnector->base;
6499         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(&aconnector->base);
6500         struct dc_sink_init_data init_params = {
6501                         .link = aconnector->dc_link,
6502                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6503         };
6504         struct edid *edid;
6505
6506         /*
6507          * Note: drm_get_edid gets edid in the following order:
6508          * 1) override EDID if set via edid_override debugfs,
6509          * 2) firmware EDID if set via edid_firmware module parameter
6510          * 3) regular DDC read.
6511          */
6512         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6513         if (!edid) {
6514                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6515                 return;
6516         }
6517
6518         if (drm_detect_hdmi_monitor(edid))
6519                 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
6520
6521         aconnector->edid = edid;
6522
6523         aconnector->dc_em_sink = dc_link_add_remote_sink(
6524                 aconnector->dc_link,
6525                 (uint8_t *)edid,
6526                 (edid->extensions + 1) * EDID_LENGTH,
6527                 &init_params);
6528
6529         if (aconnector->base.force == DRM_FORCE_ON) {
6530                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6531                 aconnector->dc_link->local_sink :
6532                 aconnector->dc_em_sink;
6533                 dc_sink_retain(aconnector->dc_sink);
6534         }
6535 }
6536
6537 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6538 {
6539         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6540
6541         /*
6542          * In case of headless boot with force on for DP managed connector
6543          * Those settings have to be != 0 to get initial modeset
6544          */
6545         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6546                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6547                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6548         }
6549
6550         create_eml_sink(aconnector);
6551 }
6552
6553 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6554                                                 struct dc_stream_state *stream)
6555 {
6556         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6557         struct dc_plane_state *dc_plane_state = NULL;
6558         struct dc_state *dc_state = NULL;
6559
6560         if (!stream)
6561                 goto cleanup;
6562
6563         dc_plane_state = dc_create_plane_state(dc);
6564         if (!dc_plane_state)
6565                 goto cleanup;
6566
6567         dc_state = dc_create_state(dc);
6568         if (!dc_state)
6569                 goto cleanup;
6570
6571         /* populate stream to plane */
6572         dc_plane_state->src_rect.height  = stream->src.height;
6573         dc_plane_state->src_rect.width   = stream->src.width;
6574         dc_plane_state->dst_rect.height  = stream->src.height;
6575         dc_plane_state->dst_rect.width   = stream->src.width;
6576         dc_plane_state->clip_rect.height = stream->src.height;
6577         dc_plane_state->clip_rect.width  = stream->src.width;
6578         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6579         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6580         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6581         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6582         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6583         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6584         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6585         dc_plane_state->rotation = ROTATION_ANGLE_0;
6586         dc_plane_state->is_tiling_rotated = false;
6587         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6588
6589         dc_result = dc_validate_stream(dc, stream);
6590         if (dc_result == DC_OK)
6591                 dc_result = dc_validate_plane(dc, dc_plane_state);
6592
6593         if (dc_result == DC_OK)
6594                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6595
6596         if (dc_result == DC_OK && !dc_add_plane_to_context(
6597                                                 dc,
6598                                                 stream,
6599                                                 dc_plane_state,
6600                                                 dc_state))
6601                 dc_result = DC_FAIL_ATTACH_SURFACES;
6602
6603         if (dc_result == DC_OK)
6604                 dc_result = dc_validate_global_state(dc, dc_state, true);
6605
6606 cleanup:
6607         if (dc_state)
6608                 dc_release_state(dc_state);
6609
6610         if (dc_plane_state)
6611                 dc_plane_state_release(dc_plane_state);
6612
6613         return dc_result;
6614 }
6615
6616 struct dc_stream_state *
6617 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6618                                 const struct drm_display_mode *drm_mode,
6619                                 const struct dm_connector_state *dm_state,
6620                                 const struct dc_stream_state *old_stream)
6621 {
6622         struct drm_connector *connector = &aconnector->base;
6623         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6624         struct dc_stream_state *stream;
6625         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6626         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6627         enum dc_status dc_result = DC_OK;
6628
6629         do {
6630                 stream = create_stream_for_sink(aconnector, drm_mode,
6631                                                 dm_state, old_stream,
6632                                                 requested_bpc);
6633                 if (stream == NULL) {
6634                         DRM_ERROR("Failed to create stream for sink!\n");
6635                         break;
6636                 }
6637
6638                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6639                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6640                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6641
6642                 if (dc_result == DC_OK)
6643                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6644
6645                 if (dc_result != DC_OK) {
6646                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6647                                       drm_mode->hdisplay,
6648                                       drm_mode->vdisplay,
6649                                       drm_mode->clock,
6650                                       dc_result,
6651                                       dc_status_to_str(dc_result));
6652
6653                         dc_stream_release(stream);
6654                         stream = NULL;
6655                         requested_bpc -= 2; /* lower bpc to retry validation */
6656                 }
6657
6658         } while (stream == NULL && requested_bpc >= 6);
6659
6660         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6661                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6662
6663                 aconnector->force_yuv420_output = true;
6664                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6665                                                 dm_state, old_stream);
6666                 aconnector->force_yuv420_output = false;
6667         }
6668
6669         return stream;
6670 }
6671
6672 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6673                                    struct drm_display_mode *mode)
6674 {
6675         int result = MODE_ERROR;
6676         struct dc_sink *dc_sink;
6677         /* TODO: Unhardcode stream count */
6678         struct dc_stream_state *stream;
6679         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6680
6681         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6682                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6683                 return result;
6684
6685         /*
6686          * Only run this the first time mode_valid is called to initilialize
6687          * EDID mgmt
6688          */
6689         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6690                 !aconnector->dc_em_sink)
6691                 handle_edid_mgmt(aconnector);
6692
6693         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6694
6695         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6696                                 aconnector->base.force != DRM_FORCE_ON) {
6697                 DRM_ERROR("dc_sink is NULL!\n");
6698                 goto fail;
6699         }
6700
6701         drm_mode_set_crtcinfo(mode, 0);
6702
6703         stream = create_validate_stream_for_sink(aconnector, mode,
6704                                                  to_dm_connector_state(connector->state),
6705                                                  NULL);
6706         if (stream) {
6707                 dc_stream_release(stream);
6708                 result = MODE_OK;
6709         }
6710
6711 fail:
6712         /* TODO: error handling*/
6713         return result;
6714 }
6715
6716 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6717                                 struct dc_info_packet *out)
6718 {
6719         struct hdmi_drm_infoframe frame;
6720         unsigned char buf[30]; /* 26 + 4 */
6721         ssize_t len;
6722         int ret, i;
6723
6724         memset(out, 0, sizeof(*out));
6725
6726         if (!state->hdr_output_metadata)
6727                 return 0;
6728
6729         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6730         if (ret)
6731                 return ret;
6732
6733         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6734         if (len < 0)
6735                 return (int)len;
6736
6737         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6738         if (len != 30)
6739                 return -EINVAL;
6740
6741         /* Prepare the infopacket for DC. */
6742         switch (state->connector->connector_type) {
6743         case DRM_MODE_CONNECTOR_HDMIA:
6744                 out->hb0 = 0x87; /* type */
6745                 out->hb1 = 0x01; /* version */
6746                 out->hb2 = 0x1A; /* length */
6747                 out->sb[0] = buf[3]; /* checksum */
6748                 i = 1;
6749                 break;
6750
6751         case DRM_MODE_CONNECTOR_DisplayPort:
6752         case DRM_MODE_CONNECTOR_eDP:
6753                 out->hb0 = 0x00; /* sdp id, zero */
6754                 out->hb1 = 0x87; /* type */
6755                 out->hb2 = 0x1D; /* payload len - 1 */
6756                 out->hb3 = (0x13 << 2); /* sdp version */
6757                 out->sb[0] = 0x01; /* version */
6758                 out->sb[1] = 0x1A; /* length */
6759                 i = 2;
6760                 break;
6761
6762         default:
6763                 return -EINVAL;
6764         }
6765
6766         memcpy(&out->sb[i], &buf[4], 26);
6767         out->valid = true;
6768
6769         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6770                        sizeof(out->sb), false);
6771
6772         return 0;
6773 }
6774
6775 static int
6776 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6777                                  struct drm_atomic_state *state)
6778 {
6779         struct drm_connector_state *new_con_state =
6780                 drm_atomic_get_new_connector_state(state, conn);
6781         struct drm_connector_state *old_con_state =
6782                 drm_atomic_get_old_connector_state(state, conn);
6783         struct drm_crtc *crtc = new_con_state->crtc;
6784         struct drm_crtc_state *new_crtc_state;
6785         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6786         int ret;
6787
6788         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6789
6790         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6791                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6792                 if (ret < 0)
6793                         return ret;
6794         }
6795
6796         if (!crtc)
6797                 return 0;
6798
6799         if (new_con_state->colorspace != old_con_state->colorspace) {
6800                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6801                 if (IS_ERR(new_crtc_state))
6802                         return PTR_ERR(new_crtc_state);
6803
6804                 new_crtc_state->mode_changed = true;
6805         }
6806
6807         if (new_con_state->content_type != old_con_state->content_type) {
6808                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6809                 if (IS_ERR(new_crtc_state))
6810                         return PTR_ERR(new_crtc_state);
6811
6812                 new_crtc_state->mode_changed = true;
6813         }
6814
6815         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6816                 struct dc_info_packet hdr_infopacket;
6817
6818                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6819                 if (ret)
6820                         return ret;
6821
6822                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6823                 if (IS_ERR(new_crtc_state))
6824                         return PTR_ERR(new_crtc_state);
6825
6826                 /*
6827                  * DC considers the stream backends changed if the
6828                  * static metadata changes. Forcing the modeset also
6829                  * gives a simple way for userspace to switch from
6830                  * 8bpc to 10bpc when setting the metadata to enter
6831                  * or exit HDR.
6832                  *
6833                  * Changing the static metadata after it's been
6834                  * set is permissible, however. So only force a
6835                  * modeset if we're entering or exiting HDR.
6836                  */
6837                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6838                         !old_con_state->hdr_output_metadata ||
6839                         !new_con_state->hdr_output_metadata;
6840         }
6841
6842         return 0;
6843 }
6844
6845 static const struct drm_connector_helper_funcs
6846 amdgpu_dm_connector_helper_funcs = {
6847         /*
6848          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6849          * modes will be filtered by drm_mode_validate_size(), and those modes
6850          * are missing after user start lightdm. So we need to renew modes list.
6851          * in get_modes call back, not just return the modes count
6852          */
6853         .get_modes = get_modes,
6854         .mode_valid = amdgpu_dm_connector_mode_valid,
6855         .atomic_check = amdgpu_dm_connector_atomic_check,
6856 };
6857
6858 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6859 {
6860
6861 }
6862
6863 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6864 {
6865         switch (display_color_depth) {
6866         case COLOR_DEPTH_666:
6867                 return 6;
6868         case COLOR_DEPTH_888:
6869                 return 8;
6870         case COLOR_DEPTH_101010:
6871                 return 10;
6872         case COLOR_DEPTH_121212:
6873                 return 12;
6874         case COLOR_DEPTH_141414:
6875                 return 14;
6876         case COLOR_DEPTH_161616:
6877                 return 16;
6878         default:
6879                 break;
6880         }
6881         return 0;
6882 }
6883
6884 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6885                                           struct drm_crtc_state *crtc_state,
6886                                           struct drm_connector_state *conn_state)
6887 {
6888         struct drm_atomic_state *state = crtc_state->state;
6889         struct drm_connector *connector = conn_state->connector;
6890         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6891         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6892         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6893         struct drm_dp_mst_topology_mgr *mst_mgr;
6894         struct drm_dp_mst_port *mst_port;
6895         struct drm_dp_mst_topology_state *mst_state;
6896         enum dc_color_depth color_depth;
6897         int clock, bpp = 0;
6898         bool is_y420 = false;
6899
6900         if (!aconnector->mst_output_port)
6901                 return 0;
6902
6903         mst_port = aconnector->mst_output_port;
6904         mst_mgr = &aconnector->mst_root->mst_mgr;
6905
6906         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6907                 return 0;
6908
6909         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6910         if (IS_ERR(mst_state))
6911                 return PTR_ERR(mst_state);
6912
6913         if (!mst_state->pbn_div.full)
6914                 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));
6915
6916         if (!state->duplicated) {
6917                 int max_bpc = conn_state->max_requested_bpc;
6918
6919                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6920                           aconnector->force_yuv420_output;
6921                 color_depth = convert_color_depth_from_display_info(connector,
6922                                                                     is_y420,
6923                                                                     max_bpc);
6924                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6925                 clock = adjusted_mode->clock;
6926                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
6927         }
6928
6929         dm_new_connector_state->vcpi_slots =
6930                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6931                                               dm_new_connector_state->pbn);
6932         if (dm_new_connector_state->vcpi_slots < 0) {
6933                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6934                 return dm_new_connector_state->vcpi_slots;
6935         }
6936         return 0;
6937 }
6938
6939 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6940         .disable = dm_encoder_helper_disable,
6941         .atomic_check = dm_encoder_helper_atomic_check
6942 };
6943
6944 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6945                                             struct dc_state *dc_state,
6946                                             struct dsc_mst_fairness_vars *vars)
6947 {
6948         struct dc_stream_state *stream = NULL;
6949         struct drm_connector *connector;
6950         struct drm_connector_state *new_con_state;
6951         struct amdgpu_dm_connector *aconnector;
6952         struct dm_connector_state *dm_conn_state;
6953         int i, j, ret;
6954         int vcpi, pbn_div, pbn, slot_num = 0;
6955
6956         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6957
6958                 aconnector = to_amdgpu_dm_connector(connector);
6959
6960                 if (!aconnector->mst_output_port)
6961                         continue;
6962
6963                 if (!new_con_state || !new_con_state->crtc)
6964                         continue;
6965
6966                 dm_conn_state = to_dm_connector_state(new_con_state);
6967
6968                 for (j = 0; j < dc_state->stream_count; j++) {
6969                         stream = dc_state->streams[j];
6970                         if (!stream)
6971                                 continue;
6972
6973                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6974                                 break;
6975
6976                         stream = NULL;
6977                 }
6978
6979                 if (!stream)
6980                         continue;
6981
6982                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6983                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6984                 for (j = 0; j < dc_state->stream_count; j++) {
6985                         if (vars[j].aconnector == aconnector) {
6986                                 pbn = vars[j].pbn;
6987                                 break;
6988                         }
6989                 }
6990
6991                 if (j == dc_state->stream_count)
6992                         continue;
6993
6994                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6995
6996                 if (stream->timing.flags.DSC != 1) {
6997                         dm_conn_state->pbn = pbn;
6998                         dm_conn_state->vcpi_slots = slot_num;
6999
7000                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
7001                                                            dm_conn_state->pbn, false);
7002                         if (ret < 0)
7003                                 return ret;
7004
7005                         continue;
7006                 }
7007
7008                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7009                 if (vcpi < 0)
7010                         return vcpi;
7011
7012                 dm_conn_state->pbn = pbn;
7013                 dm_conn_state->vcpi_slots = vcpi;
7014         }
7015         return 0;
7016 }
7017
7018 static int to_drm_connector_type(enum signal_type st)
7019 {
7020         switch (st) {
7021         case SIGNAL_TYPE_HDMI_TYPE_A:
7022                 return DRM_MODE_CONNECTOR_HDMIA;
7023         case SIGNAL_TYPE_EDP:
7024                 return DRM_MODE_CONNECTOR_eDP;
7025         case SIGNAL_TYPE_LVDS:
7026                 return DRM_MODE_CONNECTOR_LVDS;
7027         case SIGNAL_TYPE_RGB:
7028                 return DRM_MODE_CONNECTOR_VGA;
7029         case SIGNAL_TYPE_DISPLAY_PORT:
7030         case SIGNAL_TYPE_DISPLAY_PORT_MST:
7031                 return DRM_MODE_CONNECTOR_DisplayPort;
7032         case SIGNAL_TYPE_DVI_DUAL_LINK:
7033         case SIGNAL_TYPE_DVI_SINGLE_LINK:
7034                 return DRM_MODE_CONNECTOR_DVID;
7035         case SIGNAL_TYPE_VIRTUAL:
7036                 return DRM_MODE_CONNECTOR_VIRTUAL;
7037
7038         default:
7039                 return DRM_MODE_CONNECTOR_Unknown;
7040         }
7041 }
7042
7043 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7044 {
7045         struct drm_encoder *encoder;
7046
7047         /* There is only one encoder per connector */
7048         drm_connector_for_each_possible_encoder(connector, encoder)
7049                 return encoder;
7050
7051         return NULL;
7052 }
7053
7054 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7055 {
7056         struct drm_encoder *encoder;
7057         struct amdgpu_encoder *amdgpu_encoder;
7058
7059         encoder = amdgpu_dm_connector_to_encoder(connector);
7060
7061         if (encoder == NULL)
7062                 return;
7063
7064         amdgpu_encoder = to_amdgpu_encoder(encoder);
7065
7066         amdgpu_encoder->native_mode.clock = 0;
7067
7068         if (!list_empty(&connector->probed_modes)) {
7069                 struct drm_display_mode *preferred_mode = NULL;
7070
7071                 list_for_each_entry(preferred_mode,
7072                                     &connector->probed_modes,
7073                                     head) {
7074                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7075                                 amdgpu_encoder->native_mode = *preferred_mode;
7076
7077                         break;
7078                 }
7079
7080         }
7081 }
7082
7083 static struct drm_display_mode *
7084 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7085                              char *name,
7086                              int hdisplay, int vdisplay)
7087 {
7088         struct drm_device *dev = encoder->dev;
7089         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7090         struct drm_display_mode *mode = NULL;
7091         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7092
7093         mode = drm_mode_duplicate(dev, native_mode);
7094
7095         if (mode == NULL)
7096                 return NULL;
7097
7098         mode->hdisplay = hdisplay;
7099         mode->vdisplay = vdisplay;
7100         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7101         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7102
7103         return mode;
7104
7105 }
7106
7107 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7108                                                  struct drm_connector *connector)
7109 {
7110         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7111         struct drm_display_mode *mode = NULL;
7112         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7113         struct amdgpu_dm_connector *amdgpu_dm_connector =
7114                                 to_amdgpu_dm_connector(connector);
7115         int i;
7116         int n;
7117         struct mode_size {
7118                 char name[DRM_DISPLAY_MODE_LEN];
7119                 int w;
7120                 int h;
7121         } common_modes[] = {
7122                 {  "640x480",  640,  480},
7123                 {  "800x600",  800,  600},
7124                 { "1024x768", 1024,  768},
7125                 { "1280x720", 1280,  720},
7126                 { "1280x800", 1280,  800},
7127                 {"1280x1024", 1280, 1024},
7128                 { "1440x900", 1440,  900},
7129                 {"1680x1050", 1680, 1050},
7130                 {"1600x1200", 1600, 1200},
7131                 {"1920x1080", 1920, 1080},
7132                 {"1920x1200", 1920, 1200}
7133         };
7134
7135         n = ARRAY_SIZE(common_modes);
7136
7137         for (i = 0; i < n; i++) {
7138                 struct drm_display_mode *curmode = NULL;
7139                 bool mode_existed = false;
7140
7141                 if (common_modes[i].w > native_mode->hdisplay ||
7142                     common_modes[i].h > native_mode->vdisplay ||
7143                    (common_modes[i].w == native_mode->hdisplay &&
7144                     common_modes[i].h == native_mode->vdisplay))
7145                         continue;
7146
7147                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7148                         if (common_modes[i].w == curmode->hdisplay &&
7149                             common_modes[i].h == curmode->vdisplay) {
7150                                 mode_existed = true;
7151                                 break;
7152                         }
7153                 }
7154
7155                 if (mode_existed)
7156                         continue;
7157
7158                 mode = amdgpu_dm_create_common_mode(encoder,
7159                                 common_modes[i].name, common_modes[i].w,
7160                                 common_modes[i].h);
7161                 if (!mode)
7162                         continue;
7163
7164                 drm_mode_probed_add(connector, mode);
7165                 amdgpu_dm_connector->num_modes++;
7166         }
7167 }
7168
7169 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7170 {
7171         struct drm_encoder *encoder;
7172         struct amdgpu_encoder *amdgpu_encoder;
7173         const struct drm_display_mode *native_mode;
7174
7175         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7176             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7177                 return;
7178
7179         mutex_lock(&connector->dev->mode_config.mutex);
7180         amdgpu_dm_connector_get_modes(connector);
7181         mutex_unlock(&connector->dev->mode_config.mutex);
7182
7183         encoder = amdgpu_dm_connector_to_encoder(connector);
7184         if (!encoder)
7185                 return;
7186
7187         amdgpu_encoder = to_amdgpu_encoder(encoder);
7188
7189         native_mode = &amdgpu_encoder->native_mode;
7190         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7191                 return;
7192
7193         drm_connector_set_panel_orientation_with_quirk(connector,
7194                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7195                                                        native_mode->hdisplay,
7196                                                        native_mode->vdisplay);
7197 }
7198
7199 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7200                                               struct edid *edid)
7201 {
7202         struct amdgpu_dm_connector *amdgpu_dm_connector =
7203                         to_amdgpu_dm_connector(connector);
7204
7205         if (edid) {
7206                 /* empty probed_modes */
7207                 INIT_LIST_HEAD(&connector->probed_modes);
7208                 amdgpu_dm_connector->num_modes =
7209                                 drm_add_edid_modes(connector, edid);
7210
7211                 /* sorting the probed modes before calling function
7212                  * amdgpu_dm_get_native_mode() since EDID can have
7213                  * more than one preferred mode. The modes that are
7214                  * later in the probed mode list could be of higher
7215                  * and preferred resolution. For example, 3840x2160
7216                  * resolution in base EDID preferred timing and 4096x2160
7217                  * preferred resolution in DID extension block later.
7218                  */
7219                 drm_mode_sort(&connector->probed_modes);
7220                 amdgpu_dm_get_native_mode(connector);
7221
7222                 /* Freesync capabilities are reset by calling
7223                  * drm_add_edid_modes() and need to be
7224                  * restored here.
7225                  */
7226                 amdgpu_dm_update_freesync_caps(connector, edid);
7227         } else {
7228                 amdgpu_dm_connector->num_modes = 0;
7229         }
7230 }
7231
7232 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7233                               struct drm_display_mode *mode)
7234 {
7235         struct drm_display_mode *m;
7236
7237         list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7238                 if (drm_mode_equal(m, mode))
7239                         return true;
7240         }
7241
7242         return false;
7243 }
7244
7245 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7246 {
7247         const struct drm_display_mode *m;
7248         struct drm_display_mode *new_mode;
7249         uint i;
7250         u32 new_modes_count = 0;
7251
7252         /* Standard FPS values
7253          *
7254          * 23.976       - TV/NTSC
7255          * 24           - Cinema
7256          * 25           - TV/PAL
7257          * 29.97        - TV/NTSC
7258          * 30           - TV/NTSC
7259          * 48           - Cinema HFR
7260          * 50           - TV/PAL
7261          * 60           - Commonly used
7262          * 48,72,96,120 - Multiples of 24
7263          */
7264         static const u32 common_rates[] = {
7265                 23976, 24000, 25000, 29970, 30000,
7266                 48000, 50000, 60000, 72000, 96000, 120000
7267         };
7268
7269         /*
7270          * Find mode with highest refresh rate with the same resolution
7271          * as the preferred mode. Some monitors report a preferred mode
7272          * with lower resolution than the highest refresh rate supported.
7273          */
7274
7275         m = get_highest_refresh_rate_mode(aconnector, true);
7276         if (!m)
7277                 return 0;
7278
7279         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7280                 u64 target_vtotal, target_vtotal_diff;
7281                 u64 num, den;
7282
7283                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7284                         continue;
7285
7286                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7287                     common_rates[i] > aconnector->max_vfreq * 1000)
7288                         continue;
7289
7290                 num = (unsigned long long)m->clock * 1000 * 1000;
7291                 den = common_rates[i] * (unsigned long long)m->htotal;
7292                 target_vtotal = div_u64(num, den);
7293                 target_vtotal_diff = target_vtotal - m->vtotal;
7294
7295                 /* Check for illegal modes */
7296                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7297                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7298                     m->vtotal + target_vtotal_diff < m->vsync_end)
7299                         continue;
7300
7301                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7302                 if (!new_mode)
7303                         goto out;
7304
7305                 new_mode->vtotal += (u16)target_vtotal_diff;
7306                 new_mode->vsync_start += (u16)target_vtotal_diff;
7307                 new_mode->vsync_end += (u16)target_vtotal_diff;
7308                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7309                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7310
7311                 if (!is_duplicate_mode(aconnector, new_mode)) {
7312                         drm_mode_probed_add(&aconnector->base, new_mode);
7313                         new_modes_count += 1;
7314                 } else
7315                         drm_mode_destroy(aconnector->base.dev, new_mode);
7316         }
7317  out:
7318         return new_modes_count;
7319 }
7320
7321 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7322                                                    struct edid *edid)
7323 {
7324         struct amdgpu_dm_connector *amdgpu_dm_connector =
7325                 to_amdgpu_dm_connector(connector);
7326
7327         if (!edid)
7328                 return;
7329
7330         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7331                 amdgpu_dm_connector->num_modes +=
7332                         add_fs_modes(amdgpu_dm_connector);
7333 }
7334
7335 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7336 {
7337         struct amdgpu_dm_connector *amdgpu_dm_connector =
7338                         to_amdgpu_dm_connector(connector);
7339         struct drm_encoder *encoder;
7340         struct edid *edid = amdgpu_dm_connector->edid;
7341         struct dc_link_settings *verified_link_cap =
7342                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7343         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7344
7345         encoder = amdgpu_dm_connector_to_encoder(connector);
7346
7347         if (!drm_edid_is_valid(edid)) {
7348                 amdgpu_dm_connector->num_modes =
7349                                 drm_add_modes_noedid(connector, 640, 480);
7350                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7351                         amdgpu_dm_connector->num_modes +=
7352                                 drm_add_modes_noedid(connector, 1920, 1080);
7353         } else {
7354                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7355                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7356                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7357         }
7358         amdgpu_dm_fbc_init(connector);
7359
7360         return amdgpu_dm_connector->num_modes;
7361 }
7362
7363 static const u32 supported_colorspaces =
7364         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7365         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7366         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7367         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7368
7369 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7370                                      struct amdgpu_dm_connector *aconnector,
7371                                      int connector_type,
7372                                      struct dc_link *link,
7373                                      int link_index)
7374 {
7375         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7376
7377         /*
7378          * Some of the properties below require access to state, like bpc.
7379          * Allocate some default initial connector state with our reset helper.
7380          */
7381         if (aconnector->base.funcs->reset)
7382                 aconnector->base.funcs->reset(&aconnector->base);
7383
7384         aconnector->connector_id = link_index;
7385         aconnector->bl_idx = -1;
7386         aconnector->dc_link = link;
7387         aconnector->base.interlace_allowed = false;
7388         aconnector->base.doublescan_allowed = false;
7389         aconnector->base.stereo_allowed = false;
7390         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7391         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7392         aconnector->audio_inst = -1;
7393         aconnector->pack_sdp_v1_3 = false;
7394         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7395         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7396         mutex_init(&aconnector->hpd_lock);
7397         mutex_init(&aconnector->handle_mst_msg_ready);
7398
7399         /*
7400          * configure support HPD hot plug connector_>polled default value is 0
7401          * which means HPD hot plug not supported
7402          */
7403         switch (connector_type) {
7404         case DRM_MODE_CONNECTOR_HDMIA:
7405                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7406                 aconnector->base.ycbcr_420_allowed =
7407                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7408                 break;
7409         case DRM_MODE_CONNECTOR_DisplayPort:
7410                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7411                 link->link_enc = link_enc_cfg_get_link_enc(link);
7412                 ASSERT(link->link_enc);
7413                 if (link->link_enc)
7414                         aconnector->base.ycbcr_420_allowed =
7415                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7416                 break;
7417         case DRM_MODE_CONNECTOR_DVID:
7418                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7419                 break;
7420         default:
7421                 break;
7422         }
7423
7424         drm_object_attach_property(&aconnector->base.base,
7425                                 dm->ddev->mode_config.scaling_mode_property,
7426                                 DRM_MODE_SCALE_NONE);
7427
7428         drm_object_attach_property(&aconnector->base.base,
7429                                 adev->mode_info.underscan_property,
7430                                 UNDERSCAN_OFF);
7431         drm_object_attach_property(&aconnector->base.base,
7432                                 adev->mode_info.underscan_hborder_property,
7433                                 0);
7434         drm_object_attach_property(&aconnector->base.base,
7435                                 adev->mode_info.underscan_vborder_property,
7436                                 0);
7437
7438         if (!aconnector->mst_root)
7439                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7440
7441         aconnector->base.state->max_bpc = 16;
7442         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7443
7444         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7445             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7446                 drm_object_attach_property(&aconnector->base.base,
7447                                 adev->mode_info.abm_level_property, 0);
7448         }
7449
7450         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7451                 /* Content Type is currently only implemented for HDMI. */
7452                 drm_connector_attach_content_type_property(&aconnector->base);
7453         }
7454
7455         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7456                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7457                         drm_connector_attach_colorspace_property(&aconnector->base);
7458         } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7459                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7460                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7461                         drm_connector_attach_colorspace_property(&aconnector->base);
7462         }
7463
7464         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7465             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7466             connector_type == DRM_MODE_CONNECTOR_eDP) {
7467                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7468
7469                 if (!aconnector->mst_root)
7470                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7471
7472                 if (adev->dm.hdcp_workqueue)
7473                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7474         }
7475 }
7476
7477 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7478                               struct i2c_msg *msgs, int num)
7479 {
7480         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7481         struct ddc_service *ddc_service = i2c->ddc_service;
7482         struct i2c_command cmd;
7483         int i;
7484         int result = -EIO;
7485
7486         if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
7487                 return result;
7488
7489         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7490
7491         if (!cmd.payloads)
7492                 return result;
7493
7494         cmd.number_of_payloads = num;
7495         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7496         cmd.speed = 100;
7497
7498         for (i = 0; i < num; i++) {
7499                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7500                 cmd.payloads[i].address = msgs[i].addr;
7501                 cmd.payloads[i].length = msgs[i].len;
7502                 cmd.payloads[i].data = msgs[i].buf;
7503         }
7504
7505         if (dc_submit_i2c(
7506                         ddc_service->ctx->dc,
7507                         ddc_service->link->link_index,
7508                         &cmd))
7509                 result = num;
7510
7511         kfree(cmd.payloads);
7512         return result;
7513 }
7514
7515 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7516 {
7517         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7518 }
7519
7520 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7521         .master_xfer = amdgpu_dm_i2c_xfer,
7522         .functionality = amdgpu_dm_i2c_func,
7523 };
7524
7525 static struct amdgpu_i2c_adapter *
7526 create_i2c(struct ddc_service *ddc_service,
7527            int link_index,
7528            int *res)
7529 {
7530         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7531         struct amdgpu_i2c_adapter *i2c;
7532
7533         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7534         if (!i2c)
7535                 return NULL;
7536         i2c->base.owner = THIS_MODULE;
7537         i2c->base.class = I2C_CLASS_DDC;
7538         i2c->base.dev.parent = &adev->pdev->dev;
7539         i2c->base.algo = &amdgpu_dm_i2c_algo;
7540         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7541         i2c_set_adapdata(&i2c->base, i2c);
7542         i2c->ddc_service = ddc_service;
7543
7544         return i2c;
7545 }
7546
7547
7548 /*
7549  * Note: this function assumes that dc_link_detect() was called for the
7550  * dc_link which will be represented by this aconnector.
7551  */
7552 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7553                                     struct amdgpu_dm_connector *aconnector,
7554                                     u32 link_index,
7555                                     struct amdgpu_encoder *aencoder)
7556 {
7557         int res = 0;
7558         int connector_type;
7559         struct dc *dc = dm->dc;
7560         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7561         struct amdgpu_i2c_adapter *i2c;
7562
7563         link->priv = aconnector;
7564
7565
7566         i2c = create_i2c(link->ddc, link->link_index, &res);
7567         if (!i2c) {
7568                 DRM_ERROR("Failed to create i2c adapter data\n");
7569                 return -ENOMEM;
7570         }
7571
7572         aconnector->i2c = i2c;
7573         res = i2c_add_adapter(&i2c->base);
7574
7575         if (res) {
7576                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7577                 goto out_free;
7578         }
7579
7580         connector_type = to_drm_connector_type(link->connector_signal);
7581
7582         res = drm_connector_init_with_ddc(
7583                         dm->ddev,
7584                         &aconnector->base,
7585                         &amdgpu_dm_connector_funcs,
7586                         connector_type,
7587                         &i2c->base);
7588
7589         if (res) {
7590                 DRM_ERROR("connector_init failed\n");
7591                 aconnector->connector_id = -1;
7592                 goto out_free;
7593         }
7594
7595         drm_connector_helper_add(
7596                         &aconnector->base,
7597                         &amdgpu_dm_connector_helper_funcs);
7598
7599         amdgpu_dm_connector_init_helper(
7600                 dm,
7601                 aconnector,
7602                 connector_type,
7603                 link,
7604                 link_index);
7605
7606         drm_connector_attach_encoder(
7607                 &aconnector->base, &aencoder->base);
7608
7609         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7610                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7611                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7612
7613 out_free:
7614         if (res) {
7615                 kfree(i2c);
7616                 aconnector->i2c = NULL;
7617         }
7618         return res;
7619 }
7620
7621 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7622 {
7623         switch (adev->mode_info.num_crtc) {
7624         case 1:
7625                 return 0x1;
7626         case 2:
7627                 return 0x3;
7628         case 3:
7629                 return 0x7;
7630         case 4:
7631                 return 0xf;
7632         case 5:
7633                 return 0x1f;
7634         case 6:
7635         default:
7636                 return 0x3f;
7637         }
7638 }
7639
7640 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7641                                   struct amdgpu_encoder *aencoder,
7642                                   uint32_t link_index)
7643 {
7644         struct amdgpu_device *adev = drm_to_adev(dev);
7645
7646         int res = drm_encoder_init(dev,
7647                                    &aencoder->base,
7648                                    &amdgpu_dm_encoder_funcs,
7649                                    DRM_MODE_ENCODER_TMDS,
7650                                    NULL);
7651
7652         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7653
7654         if (!res)
7655                 aencoder->encoder_id = link_index;
7656         else
7657                 aencoder->encoder_id = -1;
7658
7659         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7660
7661         return res;
7662 }
7663
7664 static void manage_dm_interrupts(struct amdgpu_device *adev,
7665                                  struct amdgpu_crtc *acrtc,
7666                                  bool enable)
7667 {
7668         /*
7669          * We have no guarantee that the frontend index maps to the same
7670          * backend index - some even map to more than one.
7671          *
7672          * TODO: Use a different interrupt or check DC itself for the mapping.
7673          */
7674         int irq_type =
7675                 amdgpu_display_crtc_idx_to_irq_type(
7676                         adev,
7677                         acrtc->crtc_id);
7678
7679         if (enable) {
7680                 drm_crtc_vblank_on(&acrtc->base);
7681                 amdgpu_irq_get(
7682                         adev,
7683                         &adev->pageflip_irq,
7684                         irq_type);
7685 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7686                 amdgpu_irq_get(
7687                         adev,
7688                         &adev->vline0_irq,
7689                         irq_type);
7690 #endif
7691         } else {
7692 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7693                 amdgpu_irq_put(
7694                         adev,
7695                         &adev->vline0_irq,
7696                         irq_type);
7697 #endif
7698                 amdgpu_irq_put(
7699                         adev,
7700                         &adev->pageflip_irq,
7701                         irq_type);
7702                 drm_crtc_vblank_off(&acrtc->base);
7703         }
7704 }
7705
7706 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7707                                       struct amdgpu_crtc *acrtc)
7708 {
7709         int irq_type =
7710                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7711
7712         /**
7713          * This reads the current state for the IRQ and force reapplies
7714          * the setting to hardware.
7715          */
7716         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7717 }
7718
7719 static bool
7720 is_scaling_state_different(const struct dm_connector_state *dm_state,
7721                            const struct dm_connector_state *old_dm_state)
7722 {
7723         if (dm_state->scaling != old_dm_state->scaling)
7724                 return true;
7725         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7726                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7727                         return true;
7728         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7729                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7730                         return true;
7731         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7732                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7733                 return true;
7734         return false;
7735 }
7736
7737 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7738                                             struct drm_crtc_state *old_crtc_state,
7739                                             struct drm_connector_state *new_conn_state,
7740                                             struct drm_connector_state *old_conn_state,
7741                                             const struct drm_connector *connector,
7742                                             struct hdcp_workqueue *hdcp_w)
7743 {
7744         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7745         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7746
7747         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7748                 connector->index, connector->status, connector->dpms);
7749         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7750                 old_conn_state->content_protection, new_conn_state->content_protection);
7751
7752         if (old_crtc_state)
7753                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7754                 old_crtc_state->enable,
7755                 old_crtc_state->active,
7756                 old_crtc_state->mode_changed,
7757                 old_crtc_state->active_changed,
7758                 old_crtc_state->connectors_changed);
7759
7760         if (new_crtc_state)
7761                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7762                 new_crtc_state->enable,
7763                 new_crtc_state->active,
7764                 new_crtc_state->mode_changed,
7765                 new_crtc_state->active_changed,
7766                 new_crtc_state->connectors_changed);
7767
7768         /* hdcp content type change */
7769         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7770             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7771                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7772                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7773                 return true;
7774         }
7775
7776         /* CP is being re enabled, ignore this */
7777         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7778             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7779                 if (new_crtc_state && new_crtc_state->mode_changed) {
7780                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7781                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7782                         return true;
7783                 }
7784                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7785                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7786                 return false;
7787         }
7788
7789         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7790          *
7791          * Handles:     UNDESIRED -> ENABLED
7792          */
7793         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7794             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7795                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7796
7797         /* Stream removed and re-enabled
7798          *
7799          * Can sometimes overlap with the HPD case,
7800          * thus set update_hdcp to false to avoid
7801          * setting HDCP multiple times.
7802          *
7803          * Handles:     DESIRED -> DESIRED (Special case)
7804          */
7805         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7806                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7807                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7808                 dm_con_state->update_hdcp = false;
7809                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7810                         __func__);
7811                 return true;
7812         }
7813
7814         /* Hot-plug, headless s3, dpms
7815          *
7816          * Only start HDCP if the display is connected/enabled.
7817          * update_hdcp flag will be set to false until the next
7818          * HPD comes in.
7819          *
7820          * Handles:     DESIRED -> DESIRED (Special case)
7821          */
7822         if (dm_con_state->update_hdcp &&
7823         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7824         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7825                 dm_con_state->update_hdcp = false;
7826                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7827                         __func__);
7828                 return true;
7829         }
7830
7831         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7832                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7833                         if (new_crtc_state && new_crtc_state->mode_changed) {
7834                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7835                                         __func__);
7836                                 return true;
7837                         }
7838                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7839                                 __func__);
7840                         return false;
7841                 }
7842
7843                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7844                 return false;
7845         }
7846
7847         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7848                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7849                         __func__);
7850                 return true;
7851         }
7852
7853         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7854         return false;
7855 }
7856
7857 static void remove_stream(struct amdgpu_device *adev,
7858                           struct amdgpu_crtc *acrtc,
7859                           struct dc_stream_state *stream)
7860 {
7861         /* this is the update mode case */
7862
7863         acrtc->otg_inst = -1;
7864         acrtc->enabled = false;
7865 }
7866
7867 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7868 {
7869
7870         assert_spin_locked(&acrtc->base.dev->event_lock);
7871         WARN_ON(acrtc->event);
7872
7873         acrtc->event = acrtc->base.state->event;
7874
7875         /* Set the flip status */
7876         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7877
7878         /* Mark this event as consumed */
7879         acrtc->base.state->event = NULL;
7880
7881         drm_dbg_state(acrtc->base.dev,
7882                       "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7883                       acrtc->crtc_id);
7884 }
7885
7886 static void update_freesync_state_on_stream(
7887         struct amdgpu_display_manager *dm,
7888         struct dm_crtc_state *new_crtc_state,
7889         struct dc_stream_state *new_stream,
7890         struct dc_plane_state *surface,
7891         u32 flip_timestamp_in_us)
7892 {
7893         struct mod_vrr_params vrr_params;
7894         struct dc_info_packet vrr_infopacket = {0};
7895         struct amdgpu_device *adev = dm->adev;
7896         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7897         unsigned long flags;
7898         bool pack_sdp_v1_3 = false;
7899         struct amdgpu_dm_connector *aconn;
7900         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7901
7902         if (!new_stream)
7903                 return;
7904
7905         /*
7906          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7907          * For now it's sufficient to just guard against these conditions.
7908          */
7909
7910         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7911                 return;
7912
7913         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7914         vrr_params = acrtc->dm_irq_params.vrr_params;
7915
7916         if (surface) {
7917                 mod_freesync_handle_preflip(
7918                         dm->freesync_module,
7919                         surface,
7920                         new_stream,
7921                         flip_timestamp_in_us,
7922                         &vrr_params);
7923
7924                 if (adev->family < AMDGPU_FAMILY_AI &&
7925                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7926                         mod_freesync_handle_v_update(dm->freesync_module,
7927                                                      new_stream, &vrr_params);
7928
7929                         /* Need to call this before the frame ends. */
7930                         dc_stream_adjust_vmin_vmax(dm->dc,
7931                                                    new_crtc_state->stream,
7932                                                    &vrr_params.adjust);
7933                 }
7934         }
7935
7936         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7937
7938         if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7939                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7940
7941                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7942                         packet_type = PACKET_TYPE_FS_V1;
7943                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7944                         packet_type = PACKET_TYPE_FS_V2;
7945                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7946                         packet_type = PACKET_TYPE_FS_V3;
7947
7948                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7949                                         &new_stream->adaptive_sync_infopacket);
7950         }
7951
7952         mod_freesync_build_vrr_infopacket(
7953                 dm->freesync_module,
7954                 new_stream,
7955                 &vrr_params,
7956                 packet_type,
7957                 TRANSFER_FUNC_UNKNOWN,
7958                 &vrr_infopacket,
7959                 pack_sdp_v1_3);
7960
7961         new_crtc_state->freesync_vrr_info_changed |=
7962                 (memcmp(&new_crtc_state->vrr_infopacket,
7963                         &vrr_infopacket,
7964                         sizeof(vrr_infopacket)) != 0);
7965
7966         acrtc->dm_irq_params.vrr_params = vrr_params;
7967         new_crtc_state->vrr_infopacket = vrr_infopacket;
7968
7969         new_stream->vrr_infopacket = vrr_infopacket;
7970         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7971
7972         if (new_crtc_state->freesync_vrr_info_changed)
7973                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7974                               new_crtc_state->base.crtc->base.id,
7975                               (int)new_crtc_state->base.vrr_enabled,
7976                               (int)vrr_params.state);
7977
7978         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7979 }
7980
7981 static void update_stream_irq_parameters(
7982         struct amdgpu_display_manager *dm,
7983         struct dm_crtc_state *new_crtc_state)
7984 {
7985         struct dc_stream_state *new_stream = new_crtc_state->stream;
7986         struct mod_vrr_params vrr_params;
7987         struct mod_freesync_config config = new_crtc_state->freesync_config;
7988         struct amdgpu_device *adev = dm->adev;
7989         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7990         unsigned long flags;
7991
7992         if (!new_stream)
7993                 return;
7994
7995         /*
7996          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7997          * For now it's sufficient to just guard against these conditions.
7998          */
7999         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8000                 return;
8001
8002         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8003         vrr_params = acrtc->dm_irq_params.vrr_params;
8004
8005         if (new_crtc_state->vrr_supported &&
8006             config.min_refresh_in_uhz &&
8007             config.max_refresh_in_uhz) {
8008                 /*
8009                  * if freesync compatible mode was set, config.state will be set
8010                  * in atomic check
8011                  */
8012                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8013                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8014                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8015                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8016                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8017                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8018                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8019                 } else {
8020                         config.state = new_crtc_state->base.vrr_enabled ?
8021                                                      VRR_STATE_ACTIVE_VARIABLE :
8022                                                      VRR_STATE_INACTIVE;
8023                 }
8024         } else {
8025                 config.state = VRR_STATE_UNSUPPORTED;
8026         }
8027
8028         mod_freesync_build_vrr_params(dm->freesync_module,
8029                                       new_stream,
8030                                       &config, &vrr_params);
8031
8032         new_crtc_state->freesync_config = config;
8033         /* Copy state for access from DM IRQ handler */
8034         acrtc->dm_irq_params.freesync_config = config;
8035         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8036         acrtc->dm_irq_params.vrr_params = vrr_params;
8037         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8038 }
8039
8040 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8041                                             struct dm_crtc_state *new_state)
8042 {
8043         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8044         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8045
8046         if (!old_vrr_active && new_vrr_active) {
8047                 /* Transition VRR inactive -> active:
8048                  * While VRR is active, we must not disable vblank irq, as a
8049                  * reenable after disable would compute bogus vblank/pflip
8050                  * timestamps if it likely happened inside display front-porch.
8051                  *
8052                  * We also need vupdate irq for the actual core vblank handling
8053                  * at end of vblank.
8054                  */
8055                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8056                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8057                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8058                                  __func__, new_state->base.crtc->base.id);
8059         } else if (old_vrr_active && !new_vrr_active) {
8060                 /* Transition VRR active -> inactive:
8061                  * Allow vblank irq disable again for fixed refresh rate.
8062                  */
8063                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8064                 drm_crtc_vblank_put(new_state->base.crtc);
8065                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8066                                  __func__, new_state->base.crtc->base.id);
8067         }
8068 }
8069
8070 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8071 {
8072         struct drm_plane *plane;
8073         struct drm_plane_state *old_plane_state;
8074         int i;
8075
8076         /*
8077          * TODO: Make this per-stream so we don't issue redundant updates for
8078          * commits with multiple streams.
8079          */
8080         for_each_old_plane_in_state(state, plane, old_plane_state, i)
8081                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8082                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8083 }
8084
8085 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8086 {
8087         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8088
8089         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8090 }
8091
8092 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8093                                     struct drm_device *dev,
8094                                     struct amdgpu_display_manager *dm,
8095                                     struct drm_crtc *pcrtc,
8096                                     bool wait_for_vblank)
8097 {
8098         u32 i;
8099         u64 timestamp_ns = ktime_get_ns();
8100         struct drm_plane *plane;
8101         struct drm_plane_state *old_plane_state, *new_plane_state;
8102         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8103         struct drm_crtc_state *new_pcrtc_state =
8104                         drm_atomic_get_new_crtc_state(state, pcrtc);
8105         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8106         struct dm_crtc_state *dm_old_crtc_state =
8107                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8108         int planes_count = 0, vpos, hpos;
8109         unsigned long flags;
8110         u32 target_vblank, last_flip_vblank;
8111         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8112         bool cursor_update = false;
8113         bool pflip_present = false;
8114         bool dirty_rects_changed = false;
8115         struct {
8116                 struct dc_surface_update surface_updates[MAX_SURFACES];
8117                 struct dc_plane_info plane_infos[MAX_SURFACES];
8118                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8119                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8120                 struct dc_stream_update stream_update;
8121         } *bundle;
8122
8123         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8124
8125         if (!bundle) {
8126                 drm_err(dev, "Failed to allocate update bundle\n");
8127                 goto cleanup;
8128         }
8129
8130         /*
8131          * Disable the cursor first if we're disabling all the planes.
8132          * It'll remain on the screen after the planes are re-enabled
8133          * if we don't.
8134          */
8135         if (acrtc_state->active_planes == 0)
8136                 amdgpu_dm_commit_cursors(state);
8137
8138         /* update planes when needed */
8139         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8140                 struct drm_crtc *crtc = new_plane_state->crtc;
8141                 struct drm_crtc_state *new_crtc_state;
8142                 struct drm_framebuffer *fb = new_plane_state->fb;
8143                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8144                 bool plane_needs_flip;
8145                 struct dc_plane_state *dc_plane;
8146                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8147
8148                 /* Cursor plane is handled after stream updates */
8149                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8150                         if ((fb && crtc == pcrtc) ||
8151                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8152                                 cursor_update = true;
8153
8154                         continue;
8155                 }
8156
8157                 if (!fb || !crtc || pcrtc != crtc)
8158                         continue;
8159
8160                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8161                 if (!new_crtc_state->active)
8162                         continue;
8163
8164                 dc_plane = dm_new_plane_state->dc_state;
8165                 if (!dc_plane)
8166                         continue;
8167
8168                 bundle->surface_updates[planes_count].surface = dc_plane;
8169                 if (new_pcrtc_state->color_mgmt_changed) {
8170                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8171                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8172                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8173                 }
8174
8175                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8176                                      &bundle->scaling_infos[planes_count]);
8177
8178                 bundle->surface_updates[planes_count].scaling_info =
8179                         &bundle->scaling_infos[planes_count];
8180
8181                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8182
8183                 pflip_present = pflip_present || plane_needs_flip;
8184
8185                 if (!plane_needs_flip) {
8186                         planes_count += 1;
8187                         continue;
8188                 }
8189
8190                 fill_dc_plane_info_and_addr(
8191                         dm->adev, new_plane_state,
8192                         afb->tiling_flags,
8193                         &bundle->plane_infos[planes_count],
8194                         &bundle->flip_addrs[planes_count].address,
8195                         afb->tmz_surface, false);
8196
8197                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8198                                  new_plane_state->plane->index,
8199                                  bundle->plane_infos[planes_count].dcc.enable);
8200
8201                 bundle->surface_updates[planes_count].plane_info =
8202                         &bundle->plane_infos[planes_count];
8203
8204                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8205                     acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8206                         fill_dc_dirty_rects(plane, old_plane_state,
8207                                             new_plane_state, new_crtc_state,
8208                                             &bundle->flip_addrs[planes_count],
8209                                             &dirty_rects_changed);
8210
8211                         /*
8212                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8213                          * and enabled it again after dirty regions are stable to avoid video glitch.
8214                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8215                          * during the PSR-SU was disabled.
8216                          */
8217                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8218                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8219 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8220                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8221 #endif
8222                             dirty_rects_changed) {
8223                                 mutex_lock(&dm->dc_lock);
8224                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8225                                 timestamp_ns;
8226                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8227                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8228                                 mutex_unlock(&dm->dc_lock);
8229                         }
8230                 }
8231
8232                 /*
8233                  * Only allow immediate flips for fast updates that don't
8234                  * change memory domain, FB pitch, DCC state, rotation or
8235                  * mirroring.
8236                  *
8237                  * dm_crtc_helper_atomic_check() only accepts async flips with
8238                  * fast updates.
8239                  */
8240                 if (crtc->state->async_flip &&
8241                     (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8242                      get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8243                         drm_warn_once(state->dev,
8244                                       "[PLANE:%d:%s] async flip with non-fast update\n",
8245                                       plane->base.id, plane->name);
8246
8247                 bundle->flip_addrs[planes_count].flip_immediate =
8248                         crtc->state->async_flip &&
8249                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8250                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8251
8252                 timestamp_ns = ktime_get_ns();
8253                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8254                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8255                 bundle->surface_updates[planes_count].surface = dc_plane;
8256
8257                 if (!bundle->surface_updates[planes_count].surface) {
8258                         DRM_ERROR("No surface for CRTC: id=%d\n",
8259                                         acrtc_attach->crtc_id);
8260                         continue;
8261                 }
8262
8263                 if (plane == pcrtc->primary)
8264                         update_freesync_state_on_stream(
8265                                 dm,
8266                                 acrtc_state,
8267                                 acrtc_state->stream,
8268                                 dc_plane,
8269                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8270
8271                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8272                                  __func__,
8273                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8274                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8275
8276                 planes_count += 1;
8277
8278         }
8279
8280         if (pflip_present) {
8281                 if (!vrr_active) {
8282                         /* Use old throttling in non-vrr fixed refresh rate mode
8283                          * to keep flip scheduling based on target vblank counts
8284                          * working in a backwards compatible way, e.g., for
8285                          * clients using the GLX_OML_sync_control extension or
8286                          * DRI3/Present extension with defined target_msc.
8287                          */
8288                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8289                 } else {
8290                         /* For variable refresh rate mode only:
8291                          * Get vblank of last completed flip to avoid > 1 vrr
8292                          * flips per video frame by use of throttling, but allow
8293                          * flip programming anywhere in the possibly large
8294                          * variable vrr vblank interval for fine-grained flip
8295                          * timing control and more opportunity to avoid stutter
8296                          * on late submission of flips.
8297                          */
8298                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8299                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8300                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8301                 }
8302
8303                 target_vblank = last_flip_vblank + wait_for_vblank;
8304
8305                 /*
8306                  * Wait until we're out of the vertical blank period before the one
8307                  * targeted by the flip
8308                  */
8309                 while ((acrtc_attach->enabled &&
8310                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8311                                                             0, &vpos, &hpos, NULL,
8312                                                             NULL, &pcrtc->hwmode)
8313                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8314                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8315                         (int)(target_vblank -
8316                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8317                         usleep_range(1000, 1100);
8318                 }
8319
8320                 /**
8321                  * Prepare the flip event for the pageflip interrupt to handle.
8322                  *
8323                  * This only works in the case where we've already turned on the
8324                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8325                  * from 0 -> n planes we have to skip a hardware generated event
8326                  * and rely on sending it from software.
8327                  */
8328                 if (acrtc_attach->base.state->event &&
8329                     acrtc_state->active_planes > 0) {
8330                         drm_crtc_vblank_get(pcrtc);
8331
8332                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8333
8334                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8335                         prepare_flip_isr(acrtc_attach);
8336
8337                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8338                 }
8339
8340                 if (acrtc_state->stream) {
8341                         if (acrtc_state->freesync_vrr_info_changed)
8342                                 bundle->stream_update.vrr_infopacket =
8343                                         &acrtc_state->stream->vrr_infopacket;
8344                 }
8345         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8346                    acrtc_attach->base.state->event) {
8347                 drm_crtc_vblank_get(pcrtc);
8348
8349                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8350
8351                 acrtc_attach->event = acrtc_attach->base.state->event;
8352                 acrtc_attach->base.state->event = NULL;
8353
8354                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8355         }
8356
8357         /* Update the planes if changed or disable if we don't have any. */
8358         if ((planes_count || acrtc_state->active_planes == 0) &&
8359                 acrtc_state->stream) {
8360                 /*
8361                  * If PSR or idle optimizations are enabled then flush out
8362                  * any pending work before hardware programming.
8363                  */
8364                 if (dm->vblank_control_workqueue)
8365                         flush_workqueue(dm->vblank_control_workqueue);
8366
8367                 bundle->stream_update.stream = acrtc_state->stream;
8368                 if (new_pcrtc_state->mode_changed) {
8369                         bundle->stream_update.src = acrtc_state->stream->src;
8370                         bundle->stream_update.dst = acrtc_state->stream->dst;
8371                 }
8372
8373                 if (new_pcrtc_state->color_mgmt_changed) {
8374                         /*
8375                          * TODO: This isn't fully correct since we've actually
8376                          * already modified the stream in place.
8377                          */
8378                         bundle->stream_update.gamut_remap =
8379                                 &acrtc_state->stream->gamut_remap_matrix;
8380                         bundle->stream_update.output_csc_transform =
8381                                 &acrtc_state->stream->csc_color_matrix;
8382                         bundle->stream_update.out_transfer_func =
8383                                 acrtc_state->stream->out_transfer_func;
8384                 }
8385
8386                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8387                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8388                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8389
8390                 mutex_lock(&dm->dc_lock);
8391                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8392                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8393                         amdgpu_dm_psr_disable(acrtc_state->stream);
8394                 mutex_unlock(&dm->dc_lock);
8395
8396                 /*
8397                  * If FreeSync state on the stream has changed then we need to
8398                  * re-adjust the min/max bounds now that DC doesn't handle this
8399                  * as part of commit.
8400                  */
8401                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8402                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8403                         dc_stream_adjust_vmin_vmax(
8404                                 dm->dc, acrtc_state->stream,
8405                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8406                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8407                 }
8408                 mutex_lock(&dm->dc_lock);
8409                 update_planes_and_stream_adapter(dm->dc,
8410                                          acrtc_state->update_type,
8411                                          planes_count,
8412                                          acrtc_state->stream,
8413                                          &bundle->stream_update,
8414                                          bundle->surface_updates);
8415
8416                 /**
8417                  * Enable or disable the interrupts on the backend.
8418                  *
8419                  * Most pipes are put into power gating when unused.
8420                  *
8421                  * When power gating is enabled on a pipe we lose the
8422                  * interrupt enablement state when power gating is disabled.
8423                  *
8424                  * So we need to update the IRQ control state in hardware
8425                  * whenever the pipe turns on (since it could be previously
8426                  * power gated) or off (since some pipes can't be power gated
8427                  * on some ASICs).
8428                  */
8429                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8430                         dm_update_pflip_irq_state(drm_to_adev(dev),
8431                                                   acrtc_attach);
8432
8433                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8434                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8435                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8436                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8437
8438                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8439                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8440                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8441                         struct amdgpu_dm_connector *aconn =
8442                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8443
8444                         if (aconn->psr_skip_count > 0)
8445                                 aconn->psr_skip_count--;
8446
8447                         /* Allow PSR when skip count is 0. */
8448                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8449
8450                         /*
8451                          * If sink supports PSR SU, there is no need to rely on
8452                          * a vblank event disable request to enable PSR. PSR SU
8453                          * can be enabled immediately once OS demonstrates an
8454                          * adequate number of fast atomic commits to notify KMD
8455                          * of update events. See `vblank_control_worker()`.
8456                          */
8457                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8458                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8459 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8460                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8461 #endif
8462                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8463                             (timestamp_ns -
8464                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8465                             500000000)
8466                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8467                 } else {
8468                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8469                 }
8470
8471                 mutex_unlock(&dm->dc_lock);
8472         }
8473
8474         /*
8475          * Update cursor state *after* programming all the planes.
8476          * This avoids redundant programming in the case where we're going
8477          * to be disabling a single plane - those pipes are being disabled.
8478          */
8479         if (acrtc_state->active_planes)
8480                 amdgpu_dm_commit_cursors(state);
8481
8482 cleanup:
8483         kfree(bundle);
8484 }
8485
8486 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8487                                    struct drm_atomic_state *state)
8488 {
8489         struct amdgpu_device *adev = drm_to_adev(dev);
8490         struct amdgpu_dm_connector *aconnector;
8491         struct drm_connector *connector;
8492         struct drm_connector_state *old_con_state, *new_con_state;
8493         struct drm_crtc_state *new_crtc_state;
8494         struct dm_crtc_state *new_dm_crtc_state;
8495         const struct dc_stream_status *status;
8496         int i, inst;
8497
8498         /* Notify device removals. */
8499         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8500                 if (old_con_state->crtc != new_con_state->crtc) {
8501                         /* CRTC changes require notification. */
8502                         goto notify;
8503                 }
8504
8505                 if (!new_con_state->crtc)
8506                         continue;
8507
8508                 new_crtc_state = drm_atomic_get_new_crtc_state(
8509                         state, new_con_state->crtc);
8510
8511                 if (!new_crtc_state)
8512                         continue;
8513
8514                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8515                         continue;
8516
8517 notify:
8518                 aconnector = to_amdgpu_dm_connector(connector);
8519
8520                 mutex_lock(&adev->dm.audio_lock);
8521                 inst = aconnector->audio_inst;
8522                 aconnector->audio_inst = -1;
8523                 mutex_unlock(&adev->dm.audio_lock);
8524
8525                 amdgpu_dm_audio_eld_notify(adev, inst);
8526         }
8527
8528         /* Notify audio device additions. */
8529         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8530                 if (!new_con_state->crtc)
8531                         continue;
8532
8533                 new_crtc_state = drm_atomic_get_new_crtc_state(
8534                         state, new_con_state->crtc);
8535
8536                 if (!new_crtc_state)
8537                         continue;
8538
8539                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8540                         continue;
8541
8542                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8543                 if (!new_dm_crtc_state->stream)
8544                         continue;
8545
8546                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8547                 if (!status)
8548                         continue;
8549
8550                 aconnector = to_amdgpu_dm_connector(connector);
8551
8552                 mutex_lock(&adev->dm.audio_lock);
8553                 inst = status->audio_inst;
8554                 aconnector->audio_inst = inst;
8555                 mutex_unlock(&adev->dm.audio_lock);
8556
8557                 amdgpu_dm_audio_eld_notify(adev, inst);
8558         }
8559 }
8560
8561 /*
8562  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8563  * @crtc_state: the DRM CRTC state
8564  * @stream_state: the DC stream state.
8565  *
8566  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8567  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8568  */
8569 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8570                                                 struct dc_stream_state *stream_state)
8571 {
8572         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8573 }
8574
8575 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8576                                         struct dc_state *dc_state)
8577 {
8578         struct drm_device *dev = state->dev;
8579         struct amdgpu_device *adev = drm_to_adev(dev);
8580         struct amdgpu_display_manager *dm = &adev->dm;
8581         struct drm_crtc *crtc;
8582         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8583         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8584         bool mode_set_reset_required = false;
8585         u32 i;
8586
8587         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8588                                       new_crtc_state, i) {
8589                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8590
8591                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8592
8593                 if (old_crtc_state->active &&
8594                     (!new_crtc_state->active ||
8595                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8596                         manage_dm_interrupts(adev, acrtc, false);
8597                         dc_stream_release(dm_old_crtc_state->stream);
8598                 }
8599         }
8600
8601         drm_atomic_helper_calc_timestamping_constants(state);
8602
8603         /* update changed items */
8604         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8605                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8606
8607                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8608                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8609
8610                 drm_dbg_state(state->dev,
8611                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8612                         acrtc->crtc_id,
8613                         new_crtc_state->enable,
8614                         new_crtc_state->active,
8615                         new_crtc_state->planes_changed,
8616                         new_crtc_state->mode_changed,
8617                         new_crtc_state->active_changed,
8618                         new_crtc_state->connectors_changed);
8619
8620                 /* Disable cursor if disabling crtc */
8621                 if (old_crtc_state->active && !new_crtc_state->active) {
8622                         struct dc_cursor_position position;
8623
8624                         memset(&position, 0, sizeof(position));
8625                         mutex_lock(&dm->dc_lock);
8626                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8627                         mutex_unlock(&dm->dc_lock);
8628                 }
8629
8630                 /* Copy all transient state flags into dc state */
8631                 if (dm_new_crtc_state->stream) {
8632                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8633                                                             dm_new_crtc_state->stream);
8634                 }
8635
8636                 /* handles headless hotplug case, updating new_state and
8637                  * aconnector as needed
8638                  */
8639
8640                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8641
8642                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8643
8644                         if (!dm_new_crtc_state->stream) {
8645                                 /*
8646                                  * this could happen because of issues with
8647                                  * userspace notifications delivery.
8648                                  * In this case userspace tries to set mode on
8649                                  * display which is disconnected in fact.
8650                                  * dc_sink is NULL in this case on aconnector.
8651                                  * We expect reset mode will come soon.
8652                                  *
8653                                  * This can also happen when unplug is done
8654                                  * during resume sequence ended
8655                                  *
8656                                  * In this case, we want to pretend we still
8657                                  * have a sink to keep the pipe running so that
8658                                  * hw state is consistent with the sw state
8659                                  */
8660                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8661                                                 __func__, acrtc->base.base.id);
8662                                 continue;
8663                         }
8664
8665                         if (dm_old_crtc_state->stream)
8666                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8667
8668                         pm_runtime_get_noresume(dev->dev);
8669
8670                         acrtc->enabled = true;
8671                         acrtc->hw_mode = new_crtc_state->mode;
8672                         crtc->hwmode = new_crtc_state->mode;
8673                         mode_set_reset_required = true;
8674                 } else if (modereset_required(new_crtc_state)) {
8675                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8676                         /* i.e. reset mode */
8677                         if (dm_old_crtc_state->stream)
8678                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8679
8680                         mode_set_reset_required = true;
8681                 }
8682         } /* for_each_crtc_in_state() */
8683
8684         /* if there mode set or reset, disable eDP PSR */
8685         if (mode_set_reset_required) {
8686                 if (dm->vblank_control_workqueue)
8687                         flush_workqueue(dm->vblank_control_workqueue);
8688
8689                 amdgpu_dm_psr_disable_all(dm);
8690         }
8691
8692         dm_enable_per_frame_crtc_master_sync(dc_state);
8693         mutex_lock(&dm->dc_lock);
8694         WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8695
8696         /* Allow idle optimization when vblank count is 0 for display off */
8697         if (dm->active_vblank_irq_count == 0)
8698                 dc_allow_idle_optimizations(dm->dc, true);
8699         mutex_unlock(&dm->dc_lock);
8700
8701         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8702                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8703
8704                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8705
8706                 if (dm_new_crtc_state->stream != NULL) {
8707                         const struct dc_stream_status *status =
8708                                         dc_stream_get_status(dm_new_crtc_state->stream);
8709
8710                         if (!status)
8711                                 status = dc_stream_get_status_from_state(dc_state,
8712                                                                          dm_new_crtc_state->stream);
8713                         if (!status)
8714                                 drm_err(dev,
8715                                         "got no status for stream %p on acrtc%p\n",
8716                                         dm_new_crtc_state->stream, acrtc);
8717                         else
8718                                 acrtc->otg_inst = status->primary_otg_inst;
8719                 }
8720         }
8721 }
8722
8723 /**
8724  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8725  * @state: The atomic state to commit
8726  *
8727  * This will tell DC to commit the constructed DC state from atomic_check,
8728  * programming the hardware. Any failures here implies a hardware failure, since
8729  * atomic check should have filtered anything non-kosher.
8730  */
8731 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8732 {
8733         struct drm_device *dev = state->dev;
8734         struct amdgpu_device *adev = drm_to_adev(dev);
8735         struct amdgpu_display_manager *dm = &adev->dm;
8736         struct dm_atomic_state *dm_state;
8737         struct dc_state *dc_state = NULL;
8738         u32 i, j;
8739         struct drm_crtc *crtc;
8740         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8741         unsigned long flags;
8742         bool wait_for_vblank = true;
8743         struct drm_connector *connector;
8744         struct drm_connector_state *old_con_state, *new_con_state;
8745         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8746         int crtc_disable_count = 0;
8747
8748         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8749
8750         if (dm->dc->caps.ips_support) {
8751                 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8752                         if (new_con_state->crtc &&
8753                                 new_con_state->crtc->state->active &&
8754                                 drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
8755                                 dc_dmub_srv_exit_low_power_state(dm->dc);
8756                                 break;
8757                         }
8758                 }
8759         }
8760
8761         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8762         drm_dp_mst_atomic_wait_for_dependencies(state);
8763
8764         dm_state = dm_atomic_get_new_state(state);
8765         if (dm_state && dm_state->context) {
8766                 dc_state = dm_state->context;
8767                 amdgpu_dm_commit_streams(state, dc_state);
8768         }
8769
8770         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8771                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8772                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8773                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8774
8775                 if (!adev->dm.hdcp_workqueue)
8776                         continue;
8777
8778                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8779
8780                 if (!connector)
8781                         continue;
8782
8783                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8784                         connector->index, connector->status, connector->dpms);
8785                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8786                         old_con_state->content_protection, new_con_state->content_protection);
8787
8788                 if (aconnector->dc_sink) {
8789                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8790                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8791                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8792                                 aconnector->dc_sink->edid_caps.display_name);
8793                         }
8794                 }
8795
8796                 new_crtc_state = NULL;
8797                 old_crtc_state = NULL;
8798
8799                 if (acrtc) {
8800                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8801                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8802                 }
8803
8804                 if (old_crtc_state)
8805                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8806                         old_crtc_state->enable,
8807                         old_crtc_state->active,
8808                         old_crtc_state->mode_changed,
8809                         old_crtc_state->active_changed,
8810                         old_crtc_state->connectors_changed);
8811
8812                 if (new_crtc_state)
8813                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8814                         new_crtc_state->enable,
8815                         new_crtc_state->active,
8816                         new_crtc_state->mode_changed,
8817                         new_crtc_state->active_changed,
8818                         new_crtc_state->connectors_changed);
8819         }
8820
8821         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8822                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8823                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8824                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8825
8826                 if (!adev->dm.hdcp_workqueue)
8827                         continue;
8828
8829                 new_crtc_state = NULL;
8830                 old_crtc_state = NULL;
8831
8832                 if (acrtc) {
8833                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8834                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8835                 }
8836
8837                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8838
8839                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8840                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8841                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8842                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8843                         dm_new_con_state->update_hdcp = true;
8844                         continue;
8845                 }
8846
8847                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8848                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8849                         /* when display is unplugged from mst hub, connctor will
8850                          * be destroyed within dm_dp_mst_connector_destroy. connector
8851                          * hdcp perperties, like type, undesired, desired, enabled,
8852                          * will be lost. So, save hdcp properties into hdcp_work within
8853                          * amdgpu_dm_atomic_commit_tail. if the same display is
8854                          * plugged back with same display index, its hdcp properties
8855                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8856                          */
8857
8858                         bool enable_encryption = false;
8859
8860                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8861                                 enable_encryption = true;
8862
8863                         if (aconnector->dc_link && aconnector->dc_sink &&
8864                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8865                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8866                                 struct hdcp_workqueue *hdcp_w =
8867                                         &hdcp_work[aconnector->dc_link->link_index];
8868
8869                                 hdcp_w->hdcp_content_type[connector->index] =
8870                                         new_con_state->hdcp_content_type;
8871                                 hdcp_w->content_protection[connector->index] =
8872                                         new_con_state->content_protection;
8873                         }
8874
8875                         if (new_crtc_state && new_crtc_state->mode_changed &&
8876                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8877                                 enable_encryption = true;
8878
8879                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8880
8881                         hdcp_update_display(
8882                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8883                                 new_con_state->hdcp_content_type, enable_encryption);
8884                 }
8885         }
8886
8887         /* Handle connector state changes */
8888         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8889                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8890                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8891                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8892                 struct dc_surface_update *dummy_updates;
8893                 struct dc_stream_update stream_update;
8894                 struct dc_info_packet hdr_packet;
8895                 struct dc_stream_status *status = NULL;
8896                 bool abm_changed, hdr_changed, scaling_changed;
8897
8898                 memset(&stream_update, 0, sizeof(stream_update));
8899
8900                 if (acrtc) {
8901                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8902                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8903                 }
8904
8905                 /* Skip any modesets/resets */
8906                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8907                         continue;
8908
8909                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8910                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8911
8912                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8913                                                              dm_old_con_state);
8914
8915                 abm_changed = dm_new_crtc_state->abm_level !=
8916                               dm_old_crtc_state->abm_level;
8917
8918                 hdr_changed =
8919                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8920
8921                 if (!scaling_changed && !abm_changed && !hdr_changed)
8922                         continue;
8923
8924                 stream_update.stream = dm_new_crtc_state->stream;
8925                 if (scaling_changed) {
8926                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8927                                         dm_new_con_state, dm_new_crtc_state->stream);
8928
8929                         stream_update.src = dm_new_crtc_state->stream->src;
8930                         stream_update.dst = dm_new_crtc_state->stream->dst;
8931                 }
8932
8933                 if (abm_changed) {
8934                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8935
8936                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8937                 }
8938
8939                 if (hdr_changed) {
8940                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8941                         stream_update.hdr_static_metadata = &hdr_packet;
8942                 }
8943
8944                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8945
8946                 if (WARN_ON(!status))
8947                         continue;
8948
8949                 WARN_ON(!status->plane_count);
8950
8951                 /*
8952                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8953                  * Here we create an empty update on each plane.
8954                  * To fix this, DC should permit updating only stream properties.
8955                  */
8956                 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8957                 for (j = 0; j < status->plane_count; j++)
8958                         dummy_updates[j].surface = status->plane_states[0];
8959
8960
8961                 mutex_lock(&dm->dc_lock);
8962                 dc_update_planes_and_stream(dm->dc,
8963                                             dummy_updates,
8964                                             status->plane_count,
8965                                             dm_new_crtc_state->stream,
8966                                             &stream_update);
8967                 mutex_unlock(&dm->dc_lock);
8968                 kfree(dummy_updates);
8969         }
8970
8971         /**
8972          * Enable interrupts for CRTCs that are newly enabled or went through
8973          * a modeset. It was intentionally deferred until after the front end
8974          * state was modified to wait until the OTG was on and so the IRQ
8975          * handlers didn't access stale or invalid state.
8976          */
8977         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8978                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8979 #ifdef CONFIG_DEBUG_FS
8980                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8981 #endif
8982                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8983                 if (old_crtc_state->active && !new_crtc_state->active)
8984                         crtc_disable_count++;
8985
8986                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8987                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8988
8989                 /* For freesync config update on crtc state and params for irq */
8990                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8991
8992 #ifdef CONFIG_DEBUG_FS
8993                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8994                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8995                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8996 #endif
8997
8998                 if (new_crtc_state->active &&
8999                     (!old_crtc_state->active ||
9000                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9001                         dc_stream_retain(dm_new_crtc_state->stream);
9002                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
9003                         manage_dm_interrupts(adev, acrtc, true);
9004                 }
9005                 /* Handle vrr on->off / off->on transitions */
9006                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
9007
9008 #ifdef CONFIG_DEBUG_FS
9009                 if (new_crtc_state->active &&
9010                     (!old_crtc_state->active ||
9011                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9012                         /**
9013                          * Frontend may have changed so reapply the CRC capture
9014                          * settings for the stream.
9015                          */
9016                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
9017 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
9018                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
9019                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9020                                         acrtc->dm_irq_params.window_param.update_win = true;
9021
9022                                         /**
9023                                          * It takes 2 frames for HW to stably generate CRC when
9024                                          * resuming from suspend, so we set skip_frame_cnt 2.
9025                                          */
9026                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
9027                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9028                                 }
9029 #endif
9030                                 if (amdgpu_dm_crtc_configure_crc_source(
9031                                         crtc, dm_new_crtc_state, cur_crc_src))
9032                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
9033                         }
9034                 }
9035 #endif
9036         }
9037
9038         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
9039                 if (new_crtc_state->async_flip)
9040                         wait_for_vblank = false;
9041
9042         /* update planes when needed per crtc*/
9043         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
9044                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9045
9046                 if (dm_new_crtc_state->stream)
9047                         amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
9048         }
9049
9050         /* Update audio instances for each connector. */
9051         amdgpu_dm_commit_audio(dev, state);
9052
9053         /* restore the backlight level */
9054         for (i = 0; i < dm->num_of_edps; i++) {
9055                 if (dm->backlight_dev[i] &&
9056                     (dm->actual_brightness[i] != dm->brightness[i]))
9057                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9058         }
9059
9060         /*
9061          * send vblank event on all events not handled in flip and
9062          * mark consumed event for drm_atomic_helper_commit_hw_done
9063          */
9064         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9065         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9066
9067                 if (new_crtc_state->event)
9068                         drm_send_event_locked(dev, &new_crtc_state->event->base);
9069
9070                 new_crtc_state->event = NULL;
9071         }
9072         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9073
9074         /* Signal HW programming completion */
9075         drm_atomic_helper_commit_hw_done(state);
9076
9077         if (wait_for_vblank)
9078                 drm_atomic_helper_wait_for_flip_done(dev, state);
9079
9080         drm_atomic_helper_cleanup_planes(dev, state);
9081
9082         /* Don't free the memory if we are hitting this as part of suspend.
9083          * This way we don't free any memory during suspend; see
9084          * amdgpu_bo_free_kernel().  The memory will be freed in the first
9085          * non-suspend modeset or when the driver is torn down.
9086          */
9087         if (!adev->in_suspend) {
9088                 /* return the stolen vga memory back to VRAM */
9089                 if (!adev->mman.keep_stolen_vga_memory)
9090                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9091                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9092         }
9093
9094         /*
9095          * Finally, drop a runtime PM reference for each newly disabled CRTC,
9096          * so we can put the GPU into runtime suspend if we're not driving any
9097          * displays anymore
9098          */
9099         for (i = 0; i < crtc_disable_count; i++)
9100                 pm_runtime_put_autosuspend(dev->dev);
9101         pm_runtime_mark_last_busy(dev->dev);
9102 }
9103
9104 static int dm_force_atomic_commit(struct drm_connector *connector)
9105 {
9106         int ret = 0;
9107         struct drm_device *ddev = connector->dev;
9108         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9109         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9110         struct drm_plane *plane = disconnected_acrtc->base.primary;
9111         struct drm_connector_state *conn_state;
9112         struct drm_crtc_state *crtc_state;
9113         struct drm_plane_state *plane_state;
9114
9115         if (!state)
9116                 return -ENOMEM;
9117
9118         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9119
9120         /* Construct an atomic state to restore previous display setting */
9121
9122         /*
9123          * Attach connectors to drm_atomic_state
9124          */
9125         conn_state = drm_atomic_get_connector_state(state, connector);
9126
9127         ret = PTR_ERR_OR_ZERO(conn_state);
9128         if (ret)
9129                 goto out;
9130
9131         /* Attach crtc to drm_atomic_state*/
9132         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9133
9134         ret = PTR_ERR_OR_ZERO(crtc_state);
9135         if (ret)
9136                 goto out;
9137
9138         /* force a restore */
9139         crtc_state->mode_changed = true;
9140
9141         /* Attach plane to drm_atomic_state */
9142         plane_state = drm_atomic_get_plane_state(state, plane);
9143
9144         ret = PTR_ERR_OR_ZERO(plane_state);
9145         if (ret)
9146                 goto out;
9147
9148         /* Call commit internally with the state we just constructed */
9149         ret = drm_atomic_commit(state);
9150
9151 out:
9152         drm_atomic_state_put(state);
9153         if (ret)
9154                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9155
9156         return ret;
9157 }
9158
9159 /*
9160  * This function handles all cases when set mode does not come upon hotplug.
9161  * This includes when a display is unplugged then plugged back into the
9162  * same port and when running without usermode desktop manager supprot
9163  */
9164 void dm_restore_drm_connector_state(struct drm_device *dev,
9165                                     struct drm_connector *connector)
9166 {
9167         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9168         struct amdgpu_crtc *disconnected_acrtc;
9169         struct dm_crtc_state *acrtc_state;
9170
9171         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9172                 return;
9173
9174         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9175         if (!disconnected_acrtc)
9176                 return;
9177
9178         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9179         if (!acrtc_state->stream)
9180                 return;
9181
9182         /*
9183          * If the previous sink is not released and different from the current,
9184          * we deduce we are in a state where we can not rely on usermode call
9185          * to turn on the display, so we do it here
9186          */
9187         if (acrtc_state->stream->sink != aconnector->dc_sink)
9188                 dm_force_atomic_commit(&aconnector->base);
9189 }
9190
9191 /*
9192  * Grabs all modesetting locks to serialize against any blocking commits,
9193  * Waits for completion of all non blocking commits.
9194  */
9195 static int do_aquire_global_lock(struct drm_device *dev,
9196                                  struct drm_atomic_state *state)
9197 {
9198         struct drm_crtc *crtc;
9199         struct drm_crtc_commit *commit;
9200         long ret;
9201
9202         /*
9203          * Adding all modeset locks to aquire_ctx will
9204          * ensure that when the framework release it the
9205          * extra locks we are locking here will get released to
9206          */
9207         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9208         if (ret)
9209                 return ret;
9210
9211         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9212                 spin_lock(&crtc->commit_lock);
9213                 commit = list_first_entry_or_null(&crtc->commit_list,
9214                                 struct drm_crtc_commit, commit_entry);
9215                 if (commit)
9216                         drm_crtc_commit_get(commit);
9217                 spin_unlock(&crtc->commit_lock);
9218
9219                 if (!commit)
9220                         continue;
9221
9222                 /*
9223                  * Make sure all pending HW programming completed and
9224                  * page flips done
9225                  */
9226                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9227
9228                 if (ret > 0)
9229                         ret = wait_for_completion_interruptible_timeout(
9230                                         &commit->flip_done, 10*HZ);
9231
9232                 if (ret == 0)
9233                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9234                                   crtc->base.id, crtc->name);
9235
9236                 drm_crtc_commit_put(commit);
9237         }
9238
9239         return ret < 0 ? ret : 0;
9240 }
9241
9242 static void get_freesync_config_for_crtc(
9243         struct dm_crtc_state *new_crtc_state,
9244         struct dm_connector_state *new_con_state)
9245 {
9246         struct mod_freesync_config config = {0};
9247         struct amdgpu_dm_connector *aconnector =
9248                         to_amdgpu_dm_connector(new_con_state->base.connector);
9249         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9250         int vrefresh = drm_mode_vrefresh(mode);
9251         bool fs_vid_mode = false;
9252
9253         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9254                                         vrefresh >= aconnector->min_vfreq &&
9255                                         vrefresh <= aconnector->max_vfreq;
9256
9257         if (new_crtc_state->vrr_supported) {
9258                 new_crtc_state->stream->ignore_msa_timing_param = true;
9259                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9260
9261                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9262                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9263                 config.vsif_supported = true;
9264                 config.btr = true;
9265
9266                 if (fs_vid_mode) {
9267                         config.state = VRR_STATE_ACTIVE_FIXED;
9268                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9269                         goto out;
9270                 } else if (new_crtc_state->base.vrr_enabled) {
9271                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9272                 } else {
9273                         config.state = VRR_STATE_INACTIVE;
9274                 }
9275         }
9276 out:
9277         new_crtc_state->freesync_config = config;
9278 }
9279
9280 static void reset_freesync_config_for_crtc(
9281         struct dm_crtc_state *new_crtc_state)
9282 {
9283         new_crtc_state->vrr_supported = false;
9284
9285         memset(&new_crtc_state->vrr_infopacket, 0,
9286                sizeof(new_crtc_state->vrr_infopacket));
9287 }
9288
9289 static bool
9290 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9291                                  struct drm_crtc_state *new_crtc_state)
9292 {
9293         const struct drm_display_mode *old_mode, *new_mode;
9294
9295         if (!old_crtc_state || !new_crtc_state)
9296                 return false;
9297
9298         old_mode = &old_crtc_state->mode;
9299         new_mode = &new_crtc_state->mode;
9300
9301         if (old_mode->clock       == new_mode->clock &&
9302             old_mode->hdisplay    == new_mode->hdisplay &&
9303             old_mode->vdisplay    == new_mode->vdisplay &&
9304             old_mode->htotal      == new_mode->htotal &&
9305             old_mode->vtotal      != new_mode->vtotal &&
9306             old_mode->hsync_start == new_mode->hsync_start &&
9307             old_mode->vsync_start != new_mode->vsync_start &&
9308             old_mode->hsync_end   == new_mode->hsync_end &&
9309             old_mode->vsync_end   != new_mode->vsync_end &&
9310             old_mode->hskew       == new_mode->hskew &&
9311             old_mode->vscan       == new_mode->vscan &&
9312             (old_mode->vsync_end - old_mode->vsync_start) ==
9313             (new_mode->vsync_end - new_mode->vsync_start))
9314                 return true;
9315
9316         return false;
9317 }
9318
9319 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9320 {
9321         u64 num, den, res;
9322         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9323
9324         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9325
9326         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9327         den = (unsigned long long)new_crtc_state->mode.htotal *
9328               (unsigned long long)new_crtc_state->mode.vtotal;
9329
9330         res = div_u64(num, den);
9331         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9332 }
9333
9334 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9335                          struct drm_atomic_state *state,
9336                          struct drm_crtc *crtc,
9337                          struct drm_crtc_state *old_crtc_state,
9338                          struct drm_crtc_state *new_crtc_state,
9339                          bool enable,
9340                          bool *lock_and_validation_needed)
9341 {
9342         struct dm_atomic_state *dm_state = NULL;
9343         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9344         struct dc_stream_state *new_stream;
9345         int ret = 0;
9346
9347         /*
9348          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9349          * update changed items
9350          */
9351         struct amdgpu_crtc *acrtc = NULL;
9352         struct amdgpu_dm_connector *aconnector = NULL;
9353         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9354         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9355
9356         new_stream = NULL;
9357
9358         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9359         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9360         acrtc = to_amdgpu_crtc(crtc);
9361         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9362
9363         /* TODO This hack should go away */
9364         if (aconnector && enable) {
9365                 /* Make sure fake sink is created in plug-in scenario */
9366                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9367                                                             &aconnector->base);
9368                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9369                                                             &aconnector->base);
9370
9371                 if (IS_ERR(drm_new_conn_state)) {
9372                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9373                         goto fail;
9374                 }
9375
9376                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9377                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9378
9379                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9380                         goto skip_modeset;
9381
9382                 new_stream = create_validate_stream_for_sink(aconnector,
9383                                                              &new_crtc_state->mode,
9384                                                              dm_new_conn_state,
9385                                                              dm_old_crtc_state->stream);
9386
9387                 /*
9388                  * we can have no stream on ACTION_SET if a display
9389                  * was disconnected during S3, in this case it is not an
9390                  * error, the OS will be updated after detection, and
9391                  * will do the right thing on next atomic commit
9392                  */
9393
9394                 if (!new_stream) {
9395                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9396                                         __func__, acrtc->base.base.id);
9397                         ret = -ENOMEM;
9398                         goto fail;
9399                 }
9400
9401                 /*
9402                  * TODO: Check VSDB bits to decide whether this should
9403                  * be enabled or not.
9404                  */
9405                 new_stream->triggered_crtc_reset.enabled =
9406                         dm->force_timing_sync;
9407
9408                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9409
9410                 ret = fill_hdr_info_packet(drm_new_conn_state,
9411                                            &new_stream->hdr_static_metadata);
9412                 if (ret)
9413                         goto fail;
9414
9415                 /*
9416                  * If we already removed the old stream from the context
9417                  * (and set the new stream to NULL) then we can't reuse
9418                  * the old stream even if the stream and scaling are unchanged.
9419                  * We'll hit the BUG_ON and black screen.
9420                  *
9421                  * TODO: Refactor this function to allow this check to work
9422                  * in all conditions.
9423                  */
9424                 if (dm_new_crtc_state->stream &&
9425                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9426                         goto skip_modeset;
9427
9428                 if (dm_new_crtc_state->stream &&
9429                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9430                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9431                         new_crtc_state->mode_changed = false;
9432                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9433                                          new_crtc_state->mode_changed);
9434                 }
9435         }
9436
9437         /* mode_changed flag may get updated above, need to check again */
9438         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9439                 goto skip_modeset;
9440
9441         drm_dbg_state(state->dev,
9442                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9443                 acrtc->crtc_id,
9444                 new_crtc_state->enable,
9445                 new_crtc_state->active,
9446                 new_crtc_state->planes_changed,
9447                 new_crtc_state->mode_changed,
9448                 new_crtc_state->active_changed,
9449                 new_crtc_state->connectors_changed);
9450
9451         /* Remove stream for any changed/disabled CRTC */
9452         if (!enable) {
9453
9454                 if (!dm_old_crtc_state->stream)
9455                         goto skip_modeset;
9456
9457                 /* Unset freesync video if it was active before */
9458                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9459                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9460                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9461                 }
9462
9463                 /* Now check if we should set freesync video mode */
9464                 if (dm_new_crtc_state->stream &&
9465                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9466                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9467                     is_timing_unchanged_for_freesync(new_crtc_state,
9468                                                      old_crtc_state)) {
9469                         new_crtc_state->mode_changed = false;
9470                         DRM_DEBUG_DRIVER(
9471                                 "Mode change not required for front porch change, setting mode_changed to %d",
9472                                 new_crtc_state->mode_changed);
9473
9474                         set_freesync_fixed_config(dm_new_crtc_state);
9475
9476                         goto skip_modeset;
9477                 } else if (aconnector &&
9478                            is_freesync_video_mode(&new_crtc_state->mode,
9479                                                   aconnector)) {
9480                         struct drm_display_mode *high_mode;
9481
9482                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9483                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9484                                 set_freesync_fixed_config(dm_new_crtc_state);
9485                 }
9486
9487                 ret = dm_atomic_get_state(state, &dm_state);
9488                 if (ret)
9489                         goto fail;
9490
9491                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9492                                 crtc->base.id);
9493
9494                 /* i.e. reset mode */
9495                 if (dc_remove_stream_from_ctx(
9496                                 dm->dc,
9497                                 dm_state->context,
9498                                 dm_old_crtc_state->stream) != DC_OK) {
9499                         ret = -EINVAL;
9500                         goto fail;
9501                 }
9502
9503                 dc_stream_release(dm_old_crtc_state->stream);
9504                 dm_new_crtc_state->stream = NULL;
9505
9506                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9507
9508                 *lock_and_validation_needed = true;
9509
9510         } else {/* Add stream for any updated/enabled CRTC */
9511                 /*
9512                  * Quick fix to prevent NULL pointer on new_stream when
9513                  * added MST connectors not found in existing crtc_state in the chained mode
9514                  * TODO: need to dig out the root cause of that
9515                  */
9516                 if (!aconnector)
9517                         goto skip_modeset;
9518
9519                 if (modereset_required(new_crtc_state))
9520                         goto skip_modeset;
9521
9522                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9523                                      dm_old_crtc_state->stream)) {
9524
9525                         WARN_ON(dm_new_crtc_state->stream);
9526
9527                         ret = dm_atomic_get_state(state, &dm_state);
9528                         if (ret)
9529                                 goto fail;
9530
9531                         dm_new_crtc_state->stream = new_stream;
9532
9533                         dc_stream_retain(new_stream);
9534
9535                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9536                                          crtc->base.id);
9537
9538                         if (dc_add_stream_to_ctx(
9539                                         dm->dc,
9540                                         dm_state->context,
9541                                         dm_new_crtc_state->stream) != DC_OK) {
9542                                 ret = -EINVAL;
9543                                 goto fail;
9544                         }
9545
9546                         *lock_and_validation_needed = true;
9547                 }
9548         }
9549
9550 skip_modeset:
9551         /* Release extra reference */
9552         if (new_stream)
9553                 dc_stream_release(new_stream);
9554
9555         /*
9556          * We want to do dc stream updates that do not require a
9557          * full modeset below.
9558          */
9559         if (!(enable && aconnector && new_crtc_state->active))
9560                 return 0;
9561         /*
9562          * Given above conditions, the dc state cannot be NULL because:
9563          * 1. We're in the process of enabling CRTCs (just been added
9564          *    to the dc context, or already is on the context)
9565          * 2. Has a valid connector attached, and
9566          * 3. Is currently active and enabled.
9567          * => The dc stream state currently exists.
9568          */
9569         BUG_ON(dm_new_crtc_state->stream == NULL);
9570
9571         /* Scaling or underscan settings */
9572         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9573                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9574                 update_stream_scaling_settings(
9575                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9576
9577         /* ABM settings */
9578         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9579
9580         /*
9581          * Color management settings. We also update color properties
9582          * when a modeset is needed, to ensure it gets reprogrammed.
9583          */
9584         if (dm_new_crtc_state->base.color_mgmt_changed ||
9585             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9586                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9587                 if (ret)
9588                         goto fail;
9589         }
9590
9591         /* Update Freesync settings. */
9592         get_freesync_config_for_crtc(dm_new_crtc_state,
9593                                      dm_new_conn_state);
9594
9595         return ret;
9596
9597 fail:
9598         if (new_stream)
9599                 dc_stream_release(new_stream);
9600         return ret;
9601 }
9602
9603 static bool should_reset_plane(struct drm_atomic_state *state,
9604                                struct drm_plane *plane,
9605                                struct drm_plane_state *old_plane_state,
9606                                struct drm_plane_state *new_plane_state)
9607 {
9608         struct drm_plane *other;
9609         struct drm_plane_state *old_other_state, *new_other_state;
9610         struct drm_crtc_state *new_crtc_state;
9611         struct amdgpu_device *adev = drm_to_adev(plane->dev);
9612         int i;
9613
9614         /*
9615          * TODO: Remove this hack for all asics once it proves that the
9616          * fast updates works fine on DCN3.2+.
9617          */
9618         if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset)
9619                 return true;
9620
9621         /* Exit early if we know that we're adding or removing the plane. */
9622         if (old_plane_state->crtc != new_plane_state->crtc)
9623                 return true;
9624
9625         /* old crtc == new_crtc == NULL, plane not in context. */
9626         if (!new_plane_state->crtc)
9627                 return false;
9628
9629         new_crtc_state =
9630                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9631
9632         if (!new_crtc_state)
9633                 return true;
9634
9635         /* CRTC Degamma changes currently require us to recreate planes. */
9636         if (new_crtc_state->color_mgmt_changed)
9637                 return true;
9638
9639         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9640                 return true;
9641
9642         /*
9643          * If there are any new primary or overlay planes being added or
9644          * removed then the z-order can potentially change. To ensure
9645          * correct z-order and pipe acquisition the current DC architecture
9646          * requires us to remove and recreate all existing planes.
9647          *
9648          * TODO: Come up with a more elegant solution for this.
9649          */
9650         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9651                 struct amdgpu_framebuffer *old_afb, *new_afb;
9652
9653                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9654                         continue;
9655
9656                 if (old_other_state->crtc != new_plane_state->crtc &&
9657                     new_other_state->crtc != new_plane_state->crtc)
9658                         continue;
9659
9660                 if (old_other_state->crtc != new_other_state->crtc)
9661                         return true;
9662
9663                 /* Src/dst size and scaling updates. */
9664                 if (old_other_state->src_w != new_other_state->src_w ||
9665                     old_other_state->src_h != new_other_state->src_h ||
9666                     old_other_state->crtc_w != new_other_state->crtc_w ||
9667                     old_other_state->crtc_h != new_other_state->crtc_h)
9668                         return true;
9669
9670                 /* Rotation / mirroring updates. */
9671                 if (old_other_state->rotation != new_other_state->rotation)
9672                         return true;
9673
9674                 /* Blending updates. */
9675                 if (old_other_state->pixel_blend_mode !=
9676                     new_other_state->pixel_blend_mode)
9677                         return true;
9678
9679                 /* Alpha updates. */
9680                 if (old_other_state->alpha != new_other_state->alpha)
9681                         return true;
9682
9683                 /* Colorspace changes. */
9684                 if (old_other_state->color_range != new_other_state->color_range ||
9685                     old_other_state->color_encoding != new_other_state->color_encoding)
9686                         return true;
9687
9688                 /* Framebuffer checks fall at the end. */
9689                 if (!old_other_state->fb || !new_other_state->fb)
9690                         continue;
9691
9692                 /* Pixel format changes can require bandwidth updates. */
9693                 if (old_other_state->fb->format != new_other_state->fb->format)
9694                         return true;
9695
9696                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9697                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9698
9699                 /* Tiling and DCC changes also require bandwidth updates. */
9700                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9701                     old_afb->base.modifier != new_afb->base.modifier)
9702                         return true;
9703         }
9704
9705         return false;
9706 }
9707
9708 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9709                               struct drm_plane_state *new_plane_state,
9710                               struct drm_framebuffer *fb)
9711 {
9712         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9713         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9714         unsigned int pitch;
9715         bool linear;
9716
9717         if (fb->width > new_acrtc->max_cursor_width ||
9718             fb->height > new_acrtc->max_cursor_height) {
9719                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9720                                  new_plane_state->fb->width,
9721                                  new_plane_state->fb->height);
9722                 return -EINVAL;
9723         }
9724         if (new_plane_state->src_w != fb->width << 16 ||
9725             new_plane_state->src_h != fb->height << 16) {
9726                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9727                 return -EINVAL;
9728         }
9729
9730         /* Pitch in pixels */
9731         pitch = fb->pitches[0] / fb->format->cpp[0];
9732
9733         if (fb->width != pitch) {
9734                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9735                                  fb->width, pitch);
9736                 return -EINVAL;
9737         }
9738
9739         switch (pitch) {
9740         case 64:
9741         case 128:
9742         case 256:
9743                 /* FB pitch is supported by cursor plane */
9744                 break;
9745         default:
9746                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9747                 return -EINVAL;
9748         }
9749
9750         /* Core DRM takes care of checking FB modifiers, so we only need to
9751          * check tiling flags when the FB doesn't have a modifier.
9752          */
9753         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9754                 if (adev->family < AMDGPU_FAMILY_AI) {
9755                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9756                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9757                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9758                 } else {
9759                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9760                 }
9761                 if (!linear) {
9762                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9763                         return -EINVAL;
9764                 }
9765         }
9766
9767         return 0;
9768 }
9769
9770 static int dm_update_plane_state(struct dc *dc,
9771                                  struct drm_atomic_state *state,
9772                                  struct drm_plane *plane,
9773                                  struct drm_plane_state *old_plane_state,
9774                                  struct drm_plane_state *new_plane_state,
9775                                  bool enable,
9776                                  bool *lock_and_validation_needed,
9777                                  bool *is_top_most_overlay)
9778 {
9779
9780         struct dm_atomic_state *dm_state = NULL;
9781         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9782         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9783         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9784         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9785         struct amdgpu_crtc *new_acrtc;
9786         bool needs_reset;
9787         int ret = 0;
9788
9789
9790         new_plane_crtc = new_plane_state->crtc;
9791         old_plane_crtc = old_plane_state->crtc;
9792         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9793         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9794
9795         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9796                 if (!enable || !new_plane_crtc ||
9797                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9798                         return 0;
9799
9800                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9801
9802                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9803                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9804                         return -EINVAL;
9805                 }
9806
9807                 if (new_plane_state->fb) {
9808                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9809                                                  new_plane_state->fb);
9810                         if (ret)
9811                                 return ret;
9812                 }
9813
9814                 return 0;
9815         }
9816
9817         needs_reset = should_reset_plane(state, plane, old_plane_state,
9818                                          new_plane_state);
9819
9820         /* Remove any changed/removed planes */
9821         if (!enable) {
9822                 if (!needs_reset)
9823                         return 0;
9824
9825                 if (!old_plane_crtc)
9826                         return 0;
9827
9828                 old_crtc_state = drm_atomic_get_old_crtc_state(
9829                                 state, old_plane_crtc);
9830                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9831
9832                 if (!dm_old_crtc_state->stream)
9833                         return 0;
9834
9835                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9836                                 plane->base.id, old_plane_crtc->base.id);
9837
9838                 ret = dm_atomic_get_state(state, &dm_state);
9839                 if (ret)
9840                         return ret;
9841
9842                 if (!dc_remove_plane_from_context(
9843                                 dc,
9844                                 dm_old_crtc_state->stream,
9845                                 dm_old_plane_state->dc_state,
9846                                 dm_state->context)) {
9847
9848                         return -EINVAL;
9849                 }
9850
9851                 if (dm_old_plane_state->dc_state)
9852                         dc_plane_state_release(dm_old_plane_state->dc_state);
9853
9854                 dm_new_plane_state->dc_state = NULL;
9855
9856                 *lock_and_validation_needed = true;
9857
9858         } else { /* Add new planes */
9859                 struct dc_plane_state *dc_new_plane_state;
9860
9861                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9862                         return 0;
9863
9864                 if (!new_plane_crtc)
9865                         return 0;
9866
9867                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9868                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9869
9870                 if (!dm_new_crtc_state->stream)
9871                         return 0;
9872
9873                 if (!needs_reset)
9874                         return 0;
9875
9876                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9877                 if (ret)
9878                         return ret;
9879
9880                 WARN_ON(dm_new_plane_state->dc_state);
9881
9882                 dc_new_plane_state = dc_create_plane_state(dc);
9883                 if (!dc_new_plane_state)
9884                         return -ENOMEM;
9885
9886                 /* Block top most plane from being a video plane */
9887                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9888                         if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9889                                 return -EINVAL;
9890
9891                         *is_top_most_overlay = false;
9892                 }
9893
9894                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9895                                  plane->base.id, new_plane_crtc->base.id);
9896
9897                 ret = fill_dc_plane_attributes(
9898                         drm_to_adev(new_plane_crtc->dev),
9899                         dc_new_plane_state,
9900                         new_plane_state,
9901                         new_crtc_state);
9902                 if (ret) {
9903                         dc_plane_state_release(dc_new_plane_state);
9904                         return ret;
9905                 }
9906
9907                 ret = dm_atomic_get_state(state, &dm_state);
9908                 if (ret) {
9909                         dc_plane_state_release(dc_new_plane_state);
9910                         return ret;
9911                 }
9912
9913                 /*
9914                  * Any atomic check errors that occur after this will
9915                  * not need a release. The plane state will be attached
9916                  * to the stream, and therefore part of the atomic
9917                  * state. It'll be released when the atomic state is
9918                  * cleaned.
9919                  */
9920                 if (!dc_add_plane_to_context(
9921                                 dc,
9922                                 dm_new_crtc_state->stream,
9923                                 dc_new_plane_state,
9924                                 dm_state->context)) {
9925
9926                         dc_plane_state_release(dc_new_plane_state);
9927                         return -EINVAL;
9928                 }
9929
9930                 dm_new_plane_state->dc_state = dc_new_plane_state;
9931
9932                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9933
9934                 /* Tell DC to do a full surface update every time there
9935                  * is a plane change. Inefficient, but works for now.
9936                  */
9937                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9938
9939                 *lock_and_validation_needed = true;
9940         }
9941
9942
9943         return ret;
9944 }
9945
9946 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9947                                        int *src_w, int *src_h)
9948 {
9949         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9950         case DRM_MODE_ROTATE_90:
9951         case DRM_MODE_ROTATE_270:
9952                 *src_w = plane_state->src_h >> 16;
9953                 *src_h = plane_state->src_w >> 16;
9954                 break;
9955         case DRM_MODE_ROTATE_0:
9956         case DRM_MODE_ROTATE_180:
9957         default:
9958                 *src_w = plane_state->src_w >> 16;
9959                 *src_h = plane_state->src_h >> 16;
9960                 break;
9961         }
9962 }
9963
9964 static void
9965 dm_get_plane_scale(struct drm_plane_state *plane_state,
9966                    int *out_plane_scale_w, int *out_plane_scale_h)
9967 {
9968         int plane_src_w, plane_src_h;
9969
9970         dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
9971         *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
9972         *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9973 }
9974
9975 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9976                                 struct drm_crtc *crtc,
9977                                 struct drm_crtc_state *new_crtc_state)
9978 {
9979         struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
9980         struct drm_plane_state *old_plane_state, *new_plane_state;
9981         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9982         int i;
9983         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9984         bool any_relevant_change = false;
9985
9986         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9987          * cursor per pipe but it's going to inherit the scaling and
9988          * positioning from the underlying pipe. Check the cursor plane's
9989          * blending properties match the underlying planes'.
9990          */
9991
9992         /* If no plane was enabled or changed scaling, no need to check again */
9993         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9994                 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
9995
9996                 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
9997                         continue;
9998
9999                 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
10000                         any_relevant_change = true;
10001                         break;
10002                 }
10003
10004                 if (new_plane_state->fb == old_plane_state->fb &&
10005                     new_plane_state->crtc_w == old_plane_state->crtc_w &&
10006                     new_plane_state->crtc_h == old_plane_state->crtc_h)
10007                         continue;
10008
10009                 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
10010                 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
10011
10012                 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
10013                         any_relevant_change = true;
10014                         break;
10015                 }
10016         }
10017
10018         if (!any_relevant_change)
10019                 return 0;
10020
10021         new_cursor_state = drm_atomic_get_plane_state(state, cursor);
10022         if (IS_ERR(new_cursor_state))
10023                 return PTR_ERR(new_cursor_state);
10024
10025         if (!new_cursor_state->fb)
10026                 return 0;
10027
10028         dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
10029
10030         /* Need to check all enabled planes, even if this commit doesn't change
10031          * their state
10032          */
10033         i = drm_atomic_add_affected_planes(state, crtc);
10034         if (i)
10035                 return i;
10036
10037         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
10038                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
10039                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
10040                         continue;
10041
10042                 /* Ignore disabled planes */
10043                 if (!new_underlying_state->fb)
10044                         continue;
10045
10046                 dm_get_plane_scale(new_underlying_state,
10047                                    &underlying_scale_w, &underlying_scale_h);
10048
10049                 if (cursor_scale_w != underlying_scale_w ||
10050                     cursor_scale_h != underlying_scale_h) {
10051                         drm_dbg_atomic(crtc->dev,
10052                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
10053                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
10054                         return -EINVAL;
10055                 }
10056
10057                 /* If this plane covers the whole CRTC, no need to check planes underneath */
10058                 if (new_underlying_state->crtc_x <= 0 &&
10059                     new_underlying_state->crtc_y <= 0 &&
10060                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
10061                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
10062                         break;
10063         }
10064
10065         return 0;
10066 }
10067
10068 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10069 {
10070         struct drm_connector *connector;
10071         struct drm_connector_state *conn_state, *old_conn_state;
10072         struct amdgpu_dm_connector *aconnector = NULL;
10073         int i;
10074
10075         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10076                 if (!conn_state->crtc)
10077                         conn_state = old_conn_state;
10078
10079                 if (conn_state->crtc != crtc)
10080                         continue;
10081
10082                 aconnector = to_amdgpu_dm_connector(connector);
10083                 if (!aconnector->mst_output_port || !aconnector->mst_root)
10084                         aconnector = NULL;
10085                 else
10086                         break;
10087         }
10088
10089         if (!aconnector)
10090                 return 0;
10091
10092         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10093 }
10094
10095 /**
10096  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10097  *
10098  * @dev: The DRM device
10099  * @state: The atomic state to commit
10100  *
10101  * Validate that the given atomic state is programmable by DC into hardware.
10102  * This involves constructing a &struct dc_state reflecting the new hardware
10103  * state we wish to commit, then querying DC to see if it is programmable. It's
10104  * important not to modify the existing DC state. Otherwise, atomic_check
10105  * may unexpectedly commit hardware changes.
10106  *
10107  * When validating the DC state, it's important that the right locks are
10108  * acquired. For full updates case which removes/adds/updates streams on one
10109  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10110  * that any such full update commit will wait for completion of any outstanding
10111  * flip using DRMs synchronization events.
10112  *
10113  * Note that DM adds the affected connectors for all CRTCs in state, when that
10114  * might not seem necessary. This is because DC stream creation requires the
10115  * DC sink, which is tied to the DRM connector state. Cleaning this up should
10116  * be possible but non-trivial - a possible TODO item.
10117  *
10118  * Return: -Error code if validation failed.
10119  */
10120 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10121                                   struct drm_atomic_state *state)
10122 {
10123         struct amdgpu_device *adev = drm_to_adev(dev);
10124         struct dm_atomic_state *dm_state = NULL;
10125         struct dc *dc = adev->dm.dc;
10126         struct drm_connector *connector;
10127         struct drm_connector_state *old_con_state, *new_con_state;
10128         struct drm_crtc *crtc;
10129         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10130         struct drm_plane *plane;
10131         struct drm_plane_state *old_plane_state, *new_plane_state;
10132         enum dc_status status;
10133         int ret, i;
10134         bool lock_and_validation_needed = false;
10135         bool is_top_most_overlay = true;
10136         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10137         struct drm_dp_mst_topology_mgr *mgr;
10138         struct drm_dp_mst_topology_state *mst_state;
10139         struct dsc_mst_fairness_vars vars[MAX_PIPES];
10140
10141         trace_amdgpu_dm_atomic_check_begin(state);
10142
10143         ret = drm_atomic_helper_check_modeset(dev, state);
10144         if (ret) {
10145                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10146                 goto fail;
10147         }
10148
10149         /* Check connector changes */
10150         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10151                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10152                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10153
10154                 /* Skip connectors that are disabled or part of modeset already. */
10155                 if (!new_con_state->crtc)
10156                         continue;
10157
10158                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10159                 if (IS_ERR(new_crtc_state)) {
10160                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10161                         ret = PTR_ERR(new_crtc_state);
10162                         goto fail;
10163                 }
10164
10165                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10166                     dm_old_con_state->scaling != dm_new_con_state->scaling)
10167                         new_crtc_state->connectors_changed = true;
10168         }
10169
10170         if (dc_resource_is_dsc_encoding_supported(dc)) {
10171                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10172                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10173                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10174                                 if (ret) {
10175                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10176                                         goto fail;
10177                                 }
10178                         }
10179                 }
10180         }
10181         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10182                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10183
10184                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10185                     !new_crtc_state->color_mgmt_changed &&
10186                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10187                         dm_old_crtc_state->dsc_force_changed == false)
10188                         continue;
10189
10190                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10191                 if (ret) {
10192                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10193                         goto fail;
10194                 }
10195
10196                 if (!new_crtc_state->enable)
10197                         continue;
10198
10199                 ret = drm_atomic_add_affected_connectors(state, crtc);
10200                 if (ret) {
10201                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10202                         goto fail;
10203                 }
10204
10205                 ret = drm_atomic_add_affected_planes(state, crtc);
10206                 if (ret) {
10207                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10208                         goto fail;
10209                 }
10210
10211                 if (dm_old_crtc_state->dsc_force_changed)
10212                         new_crtc_state->mode_changed = true;
10213         }
10214
10215         /*
10216          * Add all primary and overlay planes on the CRTC to the state
10217          * whenever a plane is enabled to maintain correct z-ordering
10218          * and to enable fast surface updates.
10219          */
10220         drm_for_each_crtc(crtc, dev) {
10221                 bool modified = false;
10222
10223                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10224                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10225                                 continue;
10226
10227                         if (new_plane_state->crtc == crtc ||
10228                             old_plane_state->crtc == crtc) {
10229                                 modified = true;
10230                                 break;
10231                         }
10232                 }
10233
10234                 if (!modified)
10235                         continue;
10236
10237                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10238                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10239                                 continue;
10240
10241                         new_plane_state =
10242                                 drm_atomic_get_plane_state(state, plane);
10243
10244                         if (IS_ERR(new_plane_state)) {
10245                                 ret = PTR_ERR(new_plane_state);
10246                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10247                                 goto fail;
10248                         }
10249                 }
10250         }
10251
10252         /*
10253          * DC consults the zpos (layer_index in DC terminology) to determine the
10254          * hw plane on which to enable the hw cursor (see
10255          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10256          * atomic state, so call drm helper to normalize zpos.
10257          */
10258         ret = drm_atomic_normalize_zpos(dev, state);
10259         if (ret) {
10260                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10261                 goto fail;
10262         }
10263
10264         /* Remove exiting planes if they are modified */
10265         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10266                 if (old_plane_state->fb && new_plane_state->fb &&
10267                     get_mem_type(old_plane_state->fb) !=
10268                     get_mem_type(new_plane_state->fb))
10269                         lock_and_validation_needed = true;
10270
10271                 ret = dm_update_plane_state(dc, state, plane,
10272                                             old_plane_state,
10273                                             new_plane_state,
10274                                             false,
10275                                             &lock_and_validation_needed,
10276                                             &is_top_most_overlay);
10277                 if (ret) {
10278                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10279                         goto fail;
10280                 }
10281         }
10282
10283         /* Disable all crtcs which require disable */
10284         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10285                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10286                                            old_crtc_state,
10287                                            new_crtc_state,
10288                                            false,
10289                                            &lock_and_validation_needed);
10290                 if (ret) {
10291                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10292                         goto fail;
10293                 }
10294         }
10295
10296         /* Enable all crtcs which require enable */
10297         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10298                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10299                                            old_crtc_state,
10300                                            new_crtc_state,
10301                                            true,
10302                                            &lock_and_validation_needed);
10303                 if (ret) {
10304                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10305                         goto fail;
10306                 }
10307         }
10308
10309         /* Add new/modified planes */
10310         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10311                 ret = dm_update_plane_state(dc, state, plane,
10312                                             old_plane_state,
10313                                             new_plane_state,
10314                                             true,
10315                                             &lock_and_validation_needed,
10316                                             &is_top_most_overlay);
10317                 if (ret) {
10318                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10319                         goto fail;
10320                 }
10321         }
10322
10323         if (dc_resource_is_dsc_encoding_supported(dc)) {
10324                 ret = pre_validate_dsc(state, &dm_state, vars);
10325                 if (ret != 0)
10326                         goto fail;
10327         }
10328
10329         /* Run this here since we want to validate the streams we created */
10330         ret = drm_atomic_helper_check_planes(dev, state);
10331         if (ret) {
10332                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10333                 goto fail;
10334         }
10335
10336         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10337                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10338                 if (dm_new_crtc_state->mpo_requested)
10339                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10340         }
10341
10342         /* Check cursor planes scaling */
10343         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10344                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10345                 if (ret) {
10346                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10347                         goto fail;
10348                 }
10349         }
10350
10351         if (state->legacy_cursor_update) {
10352                 /*
10353                  * This is a fast cursor update coming from the plane update
10354                  * helper, check if it can be done asynchronously for better
10355                  * performance.
10356                  */
10357                 state->async_update =
10358                         !drm_atomic_helper_async_check(dev, state);
10359
10360                 /*
10361                  * Skip the remaining global validation if this is an async
10362                  * update. Cursor updates can be done without affecting
10363                  * state or bandwidth calcs and this avoids the performance
10364                  * penalty of locking the private state object and
10365                  * allocating a new dc_state.
10366                  */
10367                 if (state->async_update)
10368                         return 0;
10369         }
10370
10371         /* Check scaling and underscan changes*/
10372         /* TODO Removed scaling changes validation due to inability to commit
10373          * new stream into context w\o causing full reset. Need to
10374          * decide how to handle.
10375          */
10376         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10377                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10378                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10379                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10380
10381                 /* Skip any modesets/resets */
10382                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10383                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10384                         continue;
10385
10386                 /* Skip any thing not scale or underscan changes */
10387                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10388                         continue;
10389
10390                 lock_and_validation_needed = true;
10391         }
10392
10393         /* set the slot info for each mst_state based on the link encoding format */
10394         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10395                 struct amdgpu_dm_connector *aconnector;
10396                 struct drm_connector *connector;
10397                 struct drm_connector_list_iter iter;
10398                 u8 link_coding_cap;
10399
10400                 drm_connector_list_iter_begin(dev, &iter);
10401                 drm_for_each_connector_iter(connector, &iter) {
10402                         if (connector->index == mst_state->mgr->conn_base_id) {
10403                                 aconnector = to_amdgpu_dm_connector(connector);
10404                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10405                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10406
10407                                 break;
10408                         }
10409                 }
10410                 drm_connector_list_iter_end(&iter);
10411         }
10412
10413         /**
10414          * Streams and planes are reset when there are changes that affect
10415          * bandwidth. Anything that affects bandwidth needs to go through
10416          * DC global validation to ensure that the configuration can be applied
10417          * to hardware.
10418          *
10419          * We have to currently stall out here in atomic_check for outstanding
10420          * commits to finish in this case because our IRQ handlers reference
10421          * DRM state directly - we can end up disabling interrupts too early
10422          * if we don't.
10423          *
10424          * TODO: Remove this stall and drop DM state private objects.
10425          */
10426         if (lock_and_validation_needed) {
10427                 ret = dm_atomic_get_state(state, &dm_state);
10428                 if (ret) {
10429                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10430                         goto fail;
10431                 }
10432
10433                 ret = do_aquire_global_lock(dev, state);
10434                 if (ret) {
10435                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10436                         goto fail;
10437                 }
10438
10439                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10440                 if (ret) {
10441                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10442                         ret = -EINVAL;
10443                         goto fail;
10444                 }
10445
10446                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10447                 if (ret) {
10448                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10449                         goto fail;
10450                 }
10451
10452                 /*
10453                  * Perform validation of MST topology in the state:
10454                  * We need to perform MST atomic check before calling
10455                  * dc_validate_global_state(), or there is a chance
10456                  * to get stuck in an infinite loop and hang eventually.
10457                  */
10458                 ret = drm_dp_mst_atomic_check(state);
10459                 if (ret) {
10460                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10461                         goto fail;
10462                 }
10463                 status = dc_validate_global_state(dc, dm_state->context, true);
10464                 if (status != DC_OK) {
10465                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10466                                        dc_status_to_str(status), status);
10467                         ret = -EINVAL;
10468                         goto fail;
10469                 }
10470         } else {
10471                 /*
10472                  * The commit is a fast update. Fast updates shouldn't change
10473                  * the DC context, affect global validation, and can have their
10474                  * commit work done in parallel with other commits not touching
10475                  * the same resource. If we have a new DC context as part of
10476                  * the DM atomic state from validation we need to free it and
10477                  * retain the existing one instead.
10478                  *
10479                  * Furthermore, since the DM atomic state only contains the DC
10480                  * context and can safely be annulled, we can free the state
10481                  * and clear the associated private object now to free
10482                  * some memory and avoid a possible use-after-free later.
10483                  */
10484
10485                 for (i = 0; i < state->num_private_objs; i++) {
10486                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10487
10488                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10489                                 int j = state->num_private_objs-1;
10490
10491                                 dm_atomic_destroy_state(obj,
10492                                                 state->private_objs[i].state);
10493
10494                                 /* If i is not at the end of the array then the
10495                                  * last element needs to be moved to where i was
10496                                  * before the array can safely be truncated.
10497                                  */
10498                                 if (i != j)
10499                                         state->private_objs[i] =
10500                                                 state->private_objs[j];
10501
10502                                 state->private_objs[j].ptr = NULL;
10503                                 state->private_objs[j].state = NULL;
10504                                 state->private_objs[j].old_state = NULL;
10505                                 state->private_objs[j].new_state = NULL;
10506
10507                                 state->num_private_objs = j;
10508                                 break;
10509                         }
10510                 }
10511         }
10512
10513         /* Store the overall update type for use later in atomic check. */
10514         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10515                 struct dm_crtc_state *dm_new_crtc_state =
10516                         to_dm_crtc_state(new_crtc_state);
10517
10518                 /*
10519                  * Only allow async flips for fast updates that don't change
10520                  * the FB pitch, the DCC state, rotation, etc.
10521                  */
10522                 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10523                         drm_dbg_atomic(crtc->dev,
10524                                        "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10525                                        crtc->base.id, crtc->name);
10526                         ret = -EINVAL;
10527                         goto fail;
10528                 }
10529
10530                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10531                         UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10532         }
10533
10534         /* Must be success */
10535         WARN_ON(ret);
10536
10537         trace_amdgpu_dm_atomic_check_finish(state, ret);
10538
10539         return ret;
10540
10541 fail:
10542         if (ret == -EDEADLK)
10543                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10544         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10545                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10546         else
10547                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10548
10549         trace_amdgpu_dm_atomic_check_finish(state, ret);
10550
10551         return ret;
10552 }
10553
10554 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10555                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10556 {
10557         u8 dpcd_data;
10558         bool capable = false;
10559
10560         if (amdgpu_dm_connector->dc_link &&
10561                 dm_helpers_dp_read_dpcd(
10562                                 NULL,
10563                                 amdgpu_dm_connector->dc_link,
10564                                 DP_DOWN_STREAM_PORT_COUNT,
10565                                 &dpcd_data,
10566                                 sizeof(dpcd_data))) {
10567                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10568         }
10569
10570         return capable;
10571 }
10572
10573 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10574                 unsigned int offset,
10575                 unsigned int total_length,
10576                 u8 *data,
10577                 unsigned int length,
10578                 struct amdgpu_hdmi_vsdb_info *vsdb)
10579 {
10580         bool res;
10581         union dmub_rb_cmd cmd;
10582         struct dmub_cmd_send_edid_cea *input;
10583         struct dmub_cmd_edid_cea_output *output;
10584
10585         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10586                 return false;
10587
10588         memset(&cmd, 0, sizeof(cmd));
10589
10590         input = &cmd.edid_cea.data.input;
10591
10592         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10593         cmd.edid_cea.header.sub_type = 0;
10594         cmd.edid_cea.header.payload_bytes =
10595                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10596         input->offset = offset;
10597         input->length = length;
10598         input->cea_total_length = total_length;
10599         memcpy(input->payload, data, length);
10600
10601         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10602         if (!res) {
10603                 DRM_ERROR("EDID CEA parser failed\n");
10604                 return false;
10605         }
10606
10607         output = &cmd.edid_cea.data.output;
10608
10609         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10610                 if (!output->ack.success) {
10611                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10612                                         output->ack.offset);
10613                 }
10614         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10615                 if (!output->amd_vsdb.vsdb_found)
10616                         return false;
10617
10618                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10619                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10620                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10621                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10622         } else {
10623                 DRM_WARN("Unknown EDID CEA parser results\n");
10624                 return false;
10625         }
10626
10627         return true;
10628 }
10629
10630 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10631                 u8 *edid_ext, int len,
10632                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10633 {
10634         int i;
10635
10636         /* send extension block to DMCU for parsing */
10637         for (i = 0; i < len; i += 8) {
10638                 bool res;
10639                 int offset;
10640
10641                 /* send 8 bytes a time */
10642                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10643                         return false;
10644
10645                 if (i+8 == len) {
10646                         /* EDID block sent completed, expect result */
10647                         int version, min_rate, max_rate;
10648
10649                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10650                         if (res) {
10651                                 /* amd vsdb found */
10652                                 vsdb_info->freesync_supported = 1;
10653                                 vsdb_info->amd_vsdb_version = version;
10654                                 vsdb_info->min_refresh_rate_hz = min_rate;
10655                                 vsdb_info->max_refresh_rate_hz = max_rate;
10656                                 return true;
10657                         }
10658                         /* not amd vsdb */
10659                         return false;
10660                 }
10661
10662                 /* check for ack*/
10663                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10664                 if (!res)
10665                         return false;
10666         }
10667
10668         return false;
10669 }
10670
10671 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10672                 u8 *edid_ext, int len,
10673                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10674 {
10675         int i;
10676
10677         /* send extension block to DMCU for parsing */
10678         for (i = 0; i < len; i += 8) {
10679                 /* send 8 bytes a time */
10680                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10681                         return false;
10682         }
10683
10684         return vsdb_info->freesync_supported;
10685 }
10686
10687 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10688                 u8 *edid_ext, int len,
10689                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10690 {
10691         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10692         bool ret;
10693
10694         mutex_lock(&adev->dm.dc_lock);
10695         if (adev->dm.dmub_srv)
10696                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10697         else
10698                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10699         mutex_unlock(&adev->dm.dc_lock);
10700         return ret;
10701 }
10702
10703 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10704                           struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10705 {
10706         u8 *edid_ext = NULL;
10707         int i;
10708         int j = 0;
10709
10710         if (edid == NULL || edid->extensions == 0)
10711                 return -ENODEV;
10712
10713         /* Find DisplayID extension */
10714         for (i = 0; i < edid->extensions; i++) {
10715                 edid_ext = (void *)(edid + (i + 1));
10716                 if (edid_ext[0] == DISPLAYID_EXT)
10717                         break;
10718         }
10719
10720         while (j < EDID_LENGTH) {
10721                 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10722                 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10723
10724                 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10725                                 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10726                         vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10727                         vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10728                         DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10729
10730                         return true;
10731                 }
10732                 j++;
10733         }
10734
10735         return false;
10736 }
10737
10738 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10739                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10740 {
10741         u8 *edid_ext = NULL;
10742         int i;
10743         bool valid_vsdb_found = false;
10744
10745         /*----- drm_find_cea_extension() -----*/
10746         /* No EDID or EDID extensions */
10747         if (edid == NULL || edid->extensions == 0)
10748                 return -ENODEV;
10749
10750         /* Find CEA extension */
10751         for (i = 0; i < edid->extensions; i++) {
10752                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10753                 if (edid_ext[0] == CEA_EXT)
10754                         break;
10755         }
10756
10757         if (i == edid->extensions)
10758                 return -ENODEV;
10759
10760         /*----- cea_db_offsets() -----*/
10761         if (edid_ext[0] != CEA_EXT)
10762                 return -ENODEV;
10763
10764         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10765
10766         return valid_vsdb_found ? i : -ENODEV;
10767 }
10768
10769 /**
10770  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10771  *
10772  * @connector: Connector to query.
10773  * @edid: EDID from monitor
10774  *
10775  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10776  * track of some of the display information in the internal data struct used by
10777  * amdgpu_dm. This function checks which type of connector we need to set the
10778  * FreeSync parameters.
10779  */
10780 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10781                                     struct edid *edid)
10782 {
10783         int i = 0;
10784         struct detailed_timing *timing;
10785         struct detailed_non_pixel *data;
10786         struct detailed_data_monitor_range *range;
10787         struct amdgpu_dm_connector *amdgpu_dm_connector =
10788                         to_amdgpu_dm_connector(connector);
10789         struct dm_connector_state *dm_con_state = NULL;
10790         struct dc_sink *sink;
10791
10792         struct drm_device *dev = connector->dev;
10793         struct amdgpu_device *adev = drm_to_adev(dev);
10794         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10795         bool freesync_capable = false;
10796         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10797
10798         if (!connector->state) {
10799                 DRM_ERROR("%s - Connector has no state", __func__);
10800                 goto update;
10801         }
10802
10803         sink = amdgpu_dm_connector->dc_sink ?
10804                 amdgpu_dm_connector->dc_sink :
10805                 amdgpu_dm_connector->dc_em_sink;
10806
10807         if (!edid || !sink) {
10808                 dm_con_state = to_dm_connector_state(connector->state);
10809
10810                 amdgpu_dm_connector->min_vfreq = 0;
10811                 amdgpu_dm_connector->max_vfreq = 0;
10812                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10813                 connector->display_info.monitor_range.min_vfreq = 0;
10814                 connector->display_info.monitor_range.max_vfreq = 0;
10815                 freesync_capable = false;
10816
10817                 goto update;
10818         }
10819
10820         dm_con_state = to_dm_connector_state(connector->state);
10821
10822         if (!adev->dm.freesync_module)
10823                 goto update;
10824
10825         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10826                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10827                 bool edid_check_required = false;
10828
10829                 if (edid) {
10830                         edid_check_required = is_dp_capable_without_timing_msa(
10831                                                 adev->dm.dc,
10832                                                 amdgpu_dm_connector);
10833                 }
10834
10835                 if (edid_check_required == true && (edid->version > 1 ||
10836                    (edid->version == 1 && edid->revision > 1))) {
10837                         for (i = 0; i < 4; i++) {
10838
10839                                 timing  = &edid->detailed_timings[i];
10840                                 data    = &timing->data.other_data;
10841                                 range   = &data->data.range;
10842                                 /*
10843                                  * Check if monitor has continuous frequency mode
10844                                  */
10845                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10846                                         continue;
10847                                 /*
10848                                  * Check for flag range limits only. If flag == 1 then
10849                                  * no additional timing information provided.
10850                                  * Default GTF, GTF Secondary curve and CVT are not
10851                                  * supported
10852                                  */
10853                                 if (range->flags != 1)
10854                                         continue;
10855
10856                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10857                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10858                                 amdgpu_dm_connector->pixel_clock_mhz =
10859                                         range->pixel_clock_mhz * 10;
10860
10861                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10862                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10863
10864                                 break;
10865                         }
10866
10867                         if (amdgpu_dm_connector->max_vfreq -
10868                             amdgpu_dm_connector->min_vfreq > 10) {
10869
10870                                 freesync_capable = true;
10871                         }
10872                 }
10873                 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10874
10875                 if (vsdb_info.replay_mode) {
10876                         amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10877                         amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10878                         amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10879                 }
10880
10881         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10882                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10883                 if (i >= 0 && vsdb_info.freesync_supported) {
10884                         timing  = &edid->detailed_timings[i];
10885                         data    = &timing->data.other_data;
10886
10887                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10888                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10889                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10890                                 freesync_capable = true;
10891
10892                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10893                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10894                 }
10895         }
10896
10897         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10898
10899         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10900                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10901                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10902
10903                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10904                         amdgpu_dm_connector->as_type = as_type;
10905                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10906
10907                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10908                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10909                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10910                                 freesync_capable = true;
10911
10912                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10913                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10914                 }
10915         }
10916
10917 update:
10918         if (dm_con_state)
10919                 dm_con_state->freesync_capable = freesync_capable;
10920
10921         if (connector->vrr_capable_property)
10922                 drm_connector_set_vrr_capable_property(connector,
10923                                                        freesync_capable);
10924 }
10925
10926 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10927 {
10928         struct amdgpu_device *adev = drm_to_adev(dev);
10929         struct dc *dc = adev->dm.dc;
10930         int i;
10931
10932         mutex_lock(&adev->dm.dc_lock);
10933         if (dc->current_state) {
10934                 for (i = 0; i < dc->current_state->stream_count; ++i)
10935                         dc->current_state->streams[i]
10936                                 ->triggered_crtc_reset.enabled =
10937                                 adev->dm.force_timing_sync;
10938
10939                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10940                 dc_trigger_sync(dc, dc->current_state);
10941         }
10942         mutex_unlock(&adev->dm.dc_lock);
10943 }
10944
10945 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10946                        u32 value, const char *func_name)
10947 {
10948 #ifdef DM_CHECK_ADDR_0
10949         if (address == 0) {
10950                 drm_err(adev_to_drm(ctx->driver_context),
10951                         "invalid register write. address = 0");
10952                 return;
10953         }
10954 #endif
10955         cgs_write_register(ctx->cgs_device, address, value);
10956         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10957 }
10958
10959 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10960                           const char *func_name)
10961 {
10962         u32 value;
10963 #ifdef DM_CHECK_ADDR_0
10964         if (address == 0) {
10965                 drm_err(adev_to_drm(ctx->driver_context),
10966                         "invalid register read; address = 0\n");
10967                 return 0;
10968         }
10969 #endif
10970
10971         if (ctx->dmub_srv &&
10972             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10973             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10974                 ASSERT(false);
10975                 return 0;
10976         }
10977
10978         value = cgs_read_register(ctx->cgs_device, address);
10979
10980         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10981
10982         return value;
10983 }
10984
10985 int amdgpu_dm_process_dmub_aux_transfer_sync(
10986                 struct dc_context *ctx,
10987                 unsigned int link_index,
10988                 struct aux_payload *payload,
10989                 enum aux_return_code_type *operation_result)
10990 {
10991         struct amdgpu_device *adev = ctx->driver_context;
10992         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10993         int ret = -1;
10994
10995         mutex_lock(&adev->dm.dpia_aux_lock);
10996         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10997                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10998                 goto out;
10999         }
11000
11001         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11002                 DRM_ERROR("wait_for_completion_timeout timeout!");
11003                 *operation_result = AUX_RET_ERROR_TIMEOUT;
11004                 goto out;
11005         }
11006
11007         if (p_notify->result != AUX_RET_SUCCESS) {
11008                 /*
11009                  * Transient states before tunneling is enabled could
11010                  * lead to this error. We can ignore this for now.
11011                  */
11012                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
11013                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
11014                                         payload->address, payload->length,
11015                                         p_notify->result);
11016                 }
11017                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11018                 goto out;
11019         }
11020
11021
11022         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
11023         if (!payload->write && p_notify->aux_reply.length &&
11024                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
11025
11026                 if (payload->length != p_notify->aux_reply.length) {
11027                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
11028                                 p_notify->aux_reply.length,
11029                                         payload->address, payload->length);
11030                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11031                         goto out;
11032                 }
11033
11034                 memcpy(payload->data, p_notify->aux_reply.data,
11035                                 p_notify->aux_reply.length);
11036         }
11037
11038         /* success */
11039         ret = p_notify->aux_reply.length;
11040         *operation_result = p_notify->result;
11041 out:
11042         reinit_completion(&adev->dm.dmub_aux_transfer_done);
11043         mutex_unlock(&adev->dm.dpia_aux_lock);
11044         return ret;
11045 }
11046
11047 int amdgpu_dm_process_dmub_set_config_sync(
11048                 struct dc_context *ctx,
11049                 unsigned int link_index,
11050                 struct set_config_cmd_payload *payload,
11051                 enum set_config_status *operation_result)
11052 {
11053         struct amdgpu_device *adev = ctx->driver_context;
11054         bool is_cmd_complete;
11055         int ret;
11056
11057         mutex_lock(&adev->dm.dpia_aux_lock);
11058         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11059                         link_index, payload, adev->dm.dmub_notify);
11060
11061         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11062                 ret = 0;
11063                 *operation_result = adev->dm.dmub_notify->sc_status;
11064         } else {
11065                 DRM_ERROR("wait_for_completion_timeout timeout!");
11066                 ret = -1;
11067                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
11068         }
11069
11070         if (!is_cmd_complete)
11071                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11072         mutex_unlock(&adev->dm.dpia_aux_lock);
11073         return ret;
11074 }
11075
11076 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11077 {
11078         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11079 }
11080
11081 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11082 {
11083         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
11084 }