drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/iommu.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/reset.h>
  15
  16 #include <soc/tegra/pmc.h>
  17
  18 #include "dc.h"
  19 #include "drm.h"
  20 #include "gem.h"
  21
  22 #include <drm/drm_atomic.h>
  23 #include <drm/drm_atomic_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 struct tegra_dc_soc_info {
  27         bool supports_border_color;
  28         bool supports_interlacing;
  29         bool supports_cursor;
  30         bool supports_block_linear;
  31         unsigned int pitch_align;
  32         bool has_powergate;
  33 };
  34
  35 struct tegra_plane {
  36         struct drm_plane base;
  37         unsigned int index;
  38 };
  39
  40 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
  41 {
  42         return container_of(plane, struct tegra_plane, base);
  43 }
  44
  45 struct tegra_dc_state {
  46         struct drm_crtc_state base;
  47
  48         struct clk *clk;
  49         unsigned long pclk;
  50         unsigned int div;
  51
  52         u32 planes;
  53 };
  54
  55 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
  56 {
  57         if (state)
  58                 return container_of(state, struct tegra_dc_state, base);
  59
  60         return NULL;
  61 }
  62
  63 struct tegra_plane_state {
  64         struct drm_plane_state base;
  65
  66         struct tegra_bo_tiling tiling;
  67         u32 format;
  68         u32 swap;
  69 };
  70
  71 static inline struct tegra_plane_state *
  72 to_tegra_plane_state(struct drm_plane_state *state)
  73 {
  74         if (state)
  75                 return container_of(state, struct tegra_plane_state, base);
  76
  77         return NULL;
  78 }
  79
  80 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  81 {
  82         stats->frames = 0;
  83         stats->vblank = 0;
  84         stats->underflow = 0;
  85         stats->overflow = 0;
  86 }
  87
  88 /*
  89  * Reads the active copy of a register. This takes the dc->lock spinlock to
  90  * prevent races with the VBLANK processing which also needs access to the
  91  * active copy of some registers.
  92  */
  93 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  94 {
  95         unsigned long flags;
  96         u32 value;
  97
  98         spin_lock_irqsave(&dc->lock, flags);
  99
 100         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 101         value = tegra_dc_readl(dc, offset);
 102         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 103
 104         spin_unlock_irqrestore(&dc->lock, flags);
 105         return value;
 106 }
 107
 108 /*
 109  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
 110  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 111  * Latching happens mmediately if the display controller is in STOP mode or
 112  * on the next frame boundary otherwise.
 113  *
 114  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 115  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 116  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 117  * into the ACTIVE copy, either immediately if the display controller is in
 118  * STOP mode, or at the next frame boundary otherwise.
 119  */
 120 void tegra_dc_commit(struct tegra_dc *dc)
 121 {
 122         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 123         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 124 }
 125
 126 static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
 127 {
 128         /* assume no swapping of fetched data */
 129         if (swap)
 130                 *swap = BYTE_SWAP_NOSWAP;
 131
 132         switch (fourcc) {
 133         case DRM_FORMAT_XBGR8888:
 134                 *format = WIN_COLOR_DEPTH_R8G8B8A8;
 135                 break;
 136
 137         case DRM_FORMAT_XRGB8888:
 138                 *format = WIN_COLOR_DEPTH_B8G8R8A8;
 139                 break;
 140
 141         case DRM_FORMAT_RGB565:
 142                 *format = WIN_COLOR_DEPTH_B5G6R5;
 143                 break;
 144
 145         case DRM_FORMAT_UYVY:
 146                 *format = WIN_COLOR_DEPTH_YCbCr422;
 147                 break;
 148
 149         case DRM_FORMAT_YUYV:
 150                 if (swap)
 151                         *swap = BYTE_SWAP_SWAP2;
 152
 153                 *format = WIN_COLOR_DEPTH_YCbCr422;
 154                 break;
 155
 156         case DRM_FORMAT_YUV420:
 157                 *format = WIN_COLOR_DEPTH_YCbCr420P;
 158                 break;
 159
 160         case DRM_FORMAT_YUV422:
 161                 *format = WIN_COLOR_DEPTH_YCbCr422P;
 162                 break;
 163
 164         default:
 165                 return -EINVAL;
 166         }
 167
 168         return 0;
 169 }
 170
 171 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
 172 {
 173         switch (format) {
 174         case WIN_COLOR_DEPTH_YCbCr422:
 175         case WIN_COLOR_DEPTH_YUV422:
 176                 if (planar)
 177                         *planar = false;
 178
 179                 return true;
 180
 181         case WIN_COLOR_DEPTH_YCbCr420P:
 182         case WIN_COLOR_DEPTH_YUV420P:
 183         case WIN_COLOR_DEPTH_YCbCr422P:
 184         case WIN_COLOR_DEPTH_YUV422P:
 185         case WIN_COLOR_DEPTH_YCbCr422R:
 186         case WIN_COLOR_DEPTH_YUV422R:
 187         case WIN_COLOR_DEPTH_YCbCr422RA:
 188         case WIN_COLOR_DEPTH_YUV422RA:
 189                 if (planar)
 190                         *planar = true;
 191
 192                 return true;
 193         }
 194
 195         if (planar)
 196                 *planar = false;
 197
 198         return false;
 199 }
 200
 201 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 202                                   unsigned int bpp)
 203 {
 204         fixed20_12 outf = dfixed_init(out);
 205         fixed20_12 inf = dfixed_init(in);
 206         u32 dda_inc;
 207         int max;
 208
 209         if (v)
 210                 max = 15;
 211         else {
 212                 switch (bpp) {
 213                 case 2:
 214                         max = 8;
 215                         break;
 216
 217                 default:
 218                         WARN_ON_ONCE(1);
 219                         /* fallthrough */
 220                 case 4:
 221                         max = 4;
 222                         break;
 223                 }
 224         }
 225
 226         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 227         inf.full -= dfixed_const(1);
 228
 229         dda_inc = dfixed_div(inf, outf);
 230         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 231
 232         return dda_inc;
 233 }
 234
 235 static inline u32 compute_initial_dda(unsigned int in)
 236 {
 237         fixed20_12 inf = dfixed_init(in);
 238         return dfixed_frac(inf);
 239 }
 240
 241 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 242                                   const struct tegra_dc_window *window)
 243 {
 244         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 245         unsigned long value, flags;
 246         bool yuv, planar;
 247
 248         /*
 249          * For YUV planar modes, the number of bytes per pixel takes into
 250          * account only the luma component and therefore is 1.
 251          */
 252         yuv = tegra_dc_format_is_yuv(window->format, &planar);
 253         if (!yuv)
 254                 bpp = window->bits_per_pixel / 8;
 255         else
 256                 bpp = planar ? 1 : 2;
 257
 258         spin_lock_irqsave(&dc->lock, flags);
 259
 260         value = WINDOW_A_SELECT << index;
 261         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 262
 263         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
 264         tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
 265
 266         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 267         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 268
 269         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 270         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 271
 272         h_offset = window->src.x * bpp;
 273         v_offset = window->src.y;
 274         h_size = window->src.w * bpp;
 275         v_size = window->src.h;
 276
 277         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 278         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 279
 280         /*
 281          * For DDA computations the number of bytes per pixel for YUV planar
 282          * modes needs to take into account all Y, U and V components.
 283          */
 284         if (yuv && planar)
 285                 bpp = 2;
 286
 287         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 288         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 289
 290         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 291         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 292
 293         h_dda = compute_initial_dda(window->src.x);
 294         v_dda = compute_initial_dda(window->src.y);
 295
 296         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 297         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 298
 299         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 300         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 301
 302         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
 303
 304         if (yuv && planar) {
 305                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
 306                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
 307                 value = window->stride[1] << 16 | window->stride[0];
 308                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
 309         } else {
 310                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
 311         }
 312
 313         if (window->bottom_up)
 314                 v_offset += window->src.h - 1;
 315
 316         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 317         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 318
 319         if (dc->soc->supports_block_linear) {
 320                 unsigned long height = window->tiling.value;
 321
 322                 switch (window->tiling.mode) {
 323                 case TEGRA_BO_TILING_MODE_PITCH:
 324                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 325                         break;
 326
 327                 case TEGRA_BO_TILING_MODE_TILED:
 328                         value = DC_WINBUF_SURFACE_KIND_TILED;
 329                         break;
 330
 331                 case TEGRA_BO_TILING_MODE_BLOCK:
 332                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 333                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 334                         break;
 335                 }
 336
 337                 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
 338         } else {
 339                 switch (window->tiling.mode) {
 340                 case TEGRA_BO_TILING_MODE_PITCH:
 341                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 342                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 343                         break;
 344
 345                 case TEGRA_BO_TILING_MODE_TILED:
 346                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 347                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 348                         break;
 349
 350                 case TEGRA_BO_TILING_MODE_BLOCK:
 351                         /*
 352                          * No need to handle this here because ->atomic_check
 353                          * will already have filtered it out.
 354                          */
 355                         break;
 356                 }
 357
 358                 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
 359         }
 360
 361         value = WIN_ENABLE;
 362
 363         if (yuv) {
 364                 /* setup default colorspace conversion coefficients */
 365                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 366                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 367                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 368                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 369                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 370                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 371                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 372                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 373
 374                 value |= CSC_ENABLE;
 375         } else if (window->bits_per_pixel < 24) {
 376                 value |= COLOR_EXPAND;
 377         }
 378
 379         if (window->bottom_up)
 380                 value |= V_DIRECTION;
 381
 382         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 383
 384         /*
 385          * Disable blending and assume Window A is the bottom-most window,
 386          * Window C is the top-most window and Window B is in the middle.
 387          */
 388         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
 389         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
 390
 391         switch (index) {
 392         case 0:
 393                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
 394                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 395                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 396                 break;
 397
 398         case 1:
 399                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 400                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 401                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 402                 break;
 403
 404         case 2:
 405                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 406                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
 407                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
 408                 break;
 409         }
 410
 411         spin_unlock_irqrestore(&dc->lock, flags);
 412 }
 413
 414 static void tegra_plane_destroy(struct drm_plane *plane)
 415 {
 416         struct tegra_plane *p = to_tegra_plane(plane);
 417
 418         drm_plane_cleanup(plane);
 419         kfree(p);
 420 }
 421
 422 static const u32 tegra_primary_plane_formats[] = {
 423         DRM_FORMAT_XBGR8888,
 424         DRM_FORMAT_XRGB8888,
 425         DRM_FORMAT_RGB565,
 426 };
 427
 428 static void tegra_primary_plane_destroy(struct drm_plane *plane)
 429 {
 430         tegra_plane_destroy(plane);
 431 }
 432
 433 static void tegra_plane_reset(struct drm_plane *plane)
 434 {
 435         struct tegra_plane_state *state;
 436
 437         if (plane->state)
 438                 __drm_atomic_helper_plane_destroy_state(plane->state);
 439
 440         kfree(plane->state);
 441         plane->state = NULL;
 442
 443         state = kzalloc(sizeof(*state), GFP_KERNEL);
 444         if (state) {
 445                 plane->state = &state->base;
 446                 plane->state->plane = plane;
 447         }
 448 }
 449
 450 static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
 451 {
 452         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 453         struct tegra_plane_state *copy;
 454
 455         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
 456         if (!copy)
 457                 return NULL;
 458
 459         __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
 460         copy->tiling = state->tiling;
 461         copy->format = state->format;
 462         copy->swap = state->swap;
 463
 464         return &copy->base;
 465 }
 466
 467 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
 468                                              struct drm_plane_state *state)
 469 {
 470         __drm_atomic_helper_plane_destroy_state(state);
 471         kfree(state);
 472 }
 473
 474 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
 475         .update_plane = drm_atomic_helper_update_plane,
 476         .disable_plane = drm_atomic_helper_disable_plane,
 477         .destroy = tegra_primary_plane_destroy,
 478         .reset = tegra_plane_reset,
 479         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 480         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 481 };
 482
 483 static int tegra_plane_state_add(struct tegra_plane *plane,
 484                                  struct drm_plane_state *state)
 485 {
 486         struct drm_crtc_state *crtc_state;
 487         struct tegra_dc_state *tegra;
 488
 489         /* Propagate errors from allocation or locking failures. */
 490         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 491         if (IS_ERR(crtc_state))
 492                 return PTR_ERR(crtc_state);
 493
 494         tegra = to_dc_state(crtc_state);
 495
 496         tegra->planes |= WIN_A_ACT_REQ << plane->index;
 497
 498         return 0;
 499 }
 500
 501 static int tegra_plane_atomic_check(struct drm_plane *plane,
 502                                     struct drm_plane_state *state)
 503 {
 504         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 505         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 506         struct tegra_plane *tegra = to_tegra_plane(plane);
 507         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 508         int err;
 509
 510         /* no need for further checks if the plane is being disabled */
 511         if (!state->crtc)
 512                 return 0;
 513
 514         err = tegra_dc_format(state->fb->format->format, &plane_state->format,
 515                               &plane_state->swap);
 516         if (err < 0)
 517                 return err;
 518
 519         err = tegra_fb_get_tiling(state->fb, tiling);
 520         if (err < 0)
 521                 return err;
 522
 523         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 524             !dc->soc->supports_block_linear) {
 525                 DRM_ERROR("hardware doesn't support block linear mode\n");
 526                 return -EINVAL;
 527         }
 528
 529         /*
 530          * Tegra doesn't support different strides for U and V planes so we
 531          * error out if the user tries to display a framebuffer with such a
 532          * configuration.
 533          */
 534         if (state->fb->format->num_planes > 2) {
 535                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 536                         DRM_ERROR("unsupported UV-plane configuration\n");
 537                         return -EINVAL;
 538                 }
 539         }
 540
 541         err = tegra_plane_state_add(tegra, state);
 542         if (err < 0)
 543                 return err;
 544
 545         return 0;
 546 }
 547
 548 static void tegra_plane_atomic_update(struct drm_plane *plane,
 549                                       struct drm_plane_state *old_state)
 550 {
 551         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 552         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 553         struct drm_framebuffer *fb = plane->state->fb;
 554         struct tegra_plane *p = to_tegra_plane(plane);
 555         struct tegra_dc_window window;
 556         unsigned int i;
 557
 558         /* rien ne va plus */
 559         if (!plane->state->crtc || !plane->state->fb)
 560                 return;
 561
 562         memset(&window, 0, sizeof(window));
 563         window.src.x = plane->state->src_x >> 16;
 564         window.src.y = plane->state->src_y >> 16;
 565         window.src.w = plane->state->src_w >> 16;
 566         window.src.h = plane->state->src_h >> 16;
 567         window.dst.x = plane->state->crtc_x;
 568         window.dst.y = plane->state->crtc_y;
 569         window.dst.w = plane->state->crtc_w;
 570         window.dst.h = plane->state->crtc_h;
 571         window.bits_per_pixel = fb->format->cpp[0] * 8;
 572         window.bottom_up = tegra_fb_is_bottom_up(fb);
 573
 574         /* copy from state */
 575         window.tiling = state->tiling;
 576         window.format = state->format;
 577         window.swap = state->swap;
 578
 579         for (i = 0; i < fb->format->num_planes; i++) {
 580                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 581
 582                 window.base[i] = bo->paddr + fb->offsets[i];
 583
 584                 /*
 585                  * Tegra uses a shared stride for UV planes. Framebuffers are
 586                  * already checked for this in the tegra_plane_atomic_check()
 587                  * function, so it's safe to ignore the V-plane pitch here.
 588                  */
 589                 if (i < 2)
 590                         window.stride[i] = fb->pitches[i];
 591         }
 592
 593         tegra_dc_setup_window(dc, p->index, &window);
 594 }
 595
 596 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 597                                        struct drm_plane_state *old_state)
 598 {
 599         struct tegra_plane *p = to_tegra_plane(plane);
 600         struct tegra_dc *dc;
 601         unsigned long flags;
 602         u32 value;
 603
 604         /* rien ne va plus */
 605         if (!old_state || !old_state->crtc)
 606                 return;
 607
 608         dc = to_tegra_dc(old_state->crtc);
 609
 610         spin_lock_irqsave(&dc->lock, flags);
 611
 612         value = WINDOW_A_SELECT << p->index;
 613         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 614
 615         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 616         value &= ~WIN_ENABLE;
 617         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 618
 619         spin_unlock_irqrestore(&dc->lock, flags);
 620 }
 621
 622 static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
 623         .atomic_check = tegra_plane_atomic_check,
 624         .atomic_update = tegra_plane_atomic_update,
 625         .atomic_disable = tegra_plane_atomic_disable,
 626 };
 627
 628 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
 629                                                        struct tegra_dc *dc)
 630 {
 631         /*
 632          * Ideally this would use drm_crtc_mask(), but that would require the
 633          * CRTC to already be in the mode_config's list of CRTCs. However, it
 634          * will only be added to that list in the drm_crtc_init_with_planes()
 635          * (in tegra_dc_init()), which in turn requires registration of these
 636          * planes. So we have ourselves a nice little chicken and egg problem
 637          * here.
 638          *
 639          * We work around this by manually creating the mask from the number
 640          * of CRTCs that have been registered, and should therefore always be
 641          * the same as drm_crtc_index() after registration.
 642          */
 643         unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
 644         struct tegra_plane *plane;
 645         unsigned int num_formats;
 646         const u32 *formats;
 647         int err;
 648
 649         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 650         if (!plane)
 651                 return ERR_PTR(-ENOMEM);
 652
 653         num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
 654         formats = tegra_primary_plane_formats;
 655
 656         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 657                                        &tegra_primary_plane_funcs, formats,
 658                                        num_formats, DRM_PLANE_TYPE_PRIMARY,
 659                                        NULL);
 660         if (err < 0) {
 661                 kfree(plane);
 662                 return ERR_PTR(err);
 663         }
 664
 665         drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
 666
 667         return &plane->base;
 668 }
 669
 670 static const u32 tegra_cursor_plane_formats[] = {
 671         DRM_FORMAT_RGBA8888,
 672 };
 673
 674 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 675                                      struct drm_plane_state *state)
 676 {
 677         struct tegra_plane *tegra = to_tegra_plane(plane);
 678         int err;
 679
 680         /* no need for further checks if the plane is being disabled */
 681         if (!state->crtc)
 682                 return 0;
 683
 684         /* scaling not supported for cursor */
 685         if ((state->src_w >> 16 != state->crtc_w) ||
 686             (state->src_h >> 16 != state->crtc_h))
 687                 return -EINVAL;
 688
 689         /* only square cursors supported */
 690         if (state->src_w != state->src_h)
 691                 return -EINVAL;
 692
 693         if (state->crtc_w != 32 && state->crtc_w != 64 &&
 694             state->crtc_w != 128 && state->crtc_w != 256)
 695                 return -EINVAL;
 696
 697         err = tegra_plane_state_add(tegra, state);
 698         if (err < 0)
 699                 return err;
 700
 701         return 0;
 702 }
 703
 704 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 705                                        struct drm_plane_state *old_state)
 706 {
 707         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
 708         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 709         struct drm_plane_state *state = plane->state;
 710         u32 value = CURSOR_CLIP_DISPLAY;
 711
 712         /* rien ne va plus */
 713         if (!plane->state->crtc || !plane->state->fb)
 714                 return;
 715
 716         switch (state->crtc_w) {
 717         case 32:
 718                 value |= CURSOR_SIZE_32x32;
 719                 break;
 720
 721         case 64:
 722                 value |= CURSOR_SIZE_64x64;
 723                 break;
 724
 725         case 128:
 726                 value |= CURSOR_SIZE_128x128;
 727                 break;
 728
 729         case 256:
 730                 value |= CURSOR_SIZE_256x256;
 731                 break;
 732
 733         default:
 734                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
 735                      state->crtc_h);
 736                 return;
 737         }
 738
 739         value |= (bo->paddr >> 10) & 0x3fffff;
 740         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 741
 742 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 743         value = (bo->paddr >> 32) & 0x3;
 744         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 745 #endif
 746
 747         /* enable cursor and set blend mode */
 748         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 749         value |= CURSOR_ENABLE;
 750         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 751
 752         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 753         value &= ~CURSOR_DST_BLEND_MASK;
 754         value &= ~CURSOR_SRC_BLEND_MASK;
 755         value |= CURSOR_MODE_NORMAL;
 756         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 757         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 758         value |= CURSOR_ALPHA;
 759         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 760
 761         /* position the cursor */
 762         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
 763         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 764 }
 765
 766 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 767                                         struct drm_plane_state *old_state)
 768 {
 769         struct tegra_dc *dc;
 770         u32 value;
 771
 772         /* rien ne va plus */
 773         if (!old_state || !old_state->crtc)
 774                 return;
 775
 776         dc = to_tegra_dc(old_state->crtc);
 777
 778         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 779         value &= ~CURSOR_ENABLE;
 780         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 781 }
 782
 783 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
 784         .update_plane = drm_atomic_helper_update_plane,
 785         .disable_plane = drm_atomic_helper_disable_plane,
 786         .destroy = tegra_plane_destroy,
 787         .reset = tegra_plane_reset,
 788         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 789         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 790 };
 791
 792 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 793         .atomic_check = tegra_cursor_atomic_check,
 794         .atomic_update = tegra_cursor_atomic_update,
 795         .atomic_disable = tegra_cursor_atomic_disable,
 796 };
 797
 798 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
 799                                                       struct tegra_dc *dc)
 800 {
 801         struct tegra_plane *plane;
 802         unsigned int num_formats;
 803         const u32 *formats;
 804         int err;
 805
 806         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 807         if (!plane)
 808                 return ERR_PTR(-ENOMEM);
 809
 810         /*
 811          * This index is kind of fake. The cursor isn't a regular plane, but
 812          * its update and activation request bits in DC_CMD_STATE_CONTROL do
 813          * use the same programming. Setting this fake index here allows the
 814          * code in tegra_add_plane_state() to do the right thing without the
 815          * need to special-casing the cursor plane.
 816          */
 817         plane->index = 6;
 818
 819         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
 820         formats = tegra_cursor_plane_formats;
 821
 822         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 823                                        &tegra_cursor_plane_funcs, formats,
 824                                        num_formats, DRM_PLANE_TYPE_CURSOR,
 825                                        NULL);
 826         if (err < 0) {
 827                 kfree(plane);
 828                 return ERR_PTR(err);
 829         }
 830
 831         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
 832
 833         return &plane->base;
 834 }
 835
 836 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
 837 {
 838         tegra_plane_destroy(plane);
 839 }
 840
 841 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
 842         .update_plane = drm_atomic_helper_update_plane,
 843         .disable_plane = drm_atomic_helper_disable_plane,
 844         .destroy = tegra_overlay_plane_destroy,
 845         .reset = tegra_plane_reset,
 846         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 847         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 848 };
 849
 850 static const uint32_t tegra_overlay_plane_formats[] = {
 851         DRM_FORMAT_XBGR8888,
 852         DRM_FORMAT_XRGB8888,
 853         DRM_FORMAT_RGB565,
 854         DRM_FORMAT_UYVY,
 855         DRM_FORMAT_YUYV,
 856         DRM_FORMAT_YUV420,
 857         DRM_FORMAT_YUV422,
 858 };
 859
 860 static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
 861         .atomic_check = tegra_plane_atomic_check,
 862         .atomic_update = tegra_plane_atomic_update,
 863         .atomic_disable = tegra_plane_atomic_disable,
 864 };
 865
 866 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
 867                                                        struct tegra_dc *dc,
 868                                                        unsigned int index)
 869 {
 870         struct tegra_plane *plane;
 871         unsigned int num_formats;
 872         const u32 *formats;
 873         int err;
 874
 875         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 876         if (!plane)
 877                 return ERR_PTR(-ENOMEM);
 878
 879         plane->index = index;
 880
 881         num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
 882         formats = tegra_overlay_plane_formats;
 883
 884         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 885                                        &tegra_overlay_plane_funcs, formats,
 886                                        num_formats, DRM_PLANE_TYPE_OVERLAY,
 887                                        NULL);
 888         if (err < 0) {
 889                 kfree(plane);
 890                 return ERR_PTR(err);
 891         }
 892
 893         drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
 894
 895         return &plane->base;
 896 }
 897
 898 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
 899 {
 900         struct drm_plane *plane;
 901         unsigned int i;
 902
 903         for (i = 0; i < 2; i++) {
 904                 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
 905                 if (IS_ERR(plane))
 906                         return PTR_ERR(plane);
 907         }
 908
 909         return 0;
 910 }
 911
 912 u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
 913 {
 914         if (dc->syncpt)
 915                 return host1x_syncpt_read(dc->syncpt);
 916
 917         /* fallback to software emulated VBLANK counter */
 918         return drm_crtc_vblank_count(&dc->base);
 919 }
 920
 921 void tegra_dc_enable_vblank(struct tegra_dc *dc)
 922 {
 923         unsigned long value, flags;
 924
 925         spin_lock_irqsave(&dc->lock, flags);
 926
 927         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 928         value |= VBLANK_INT;
 929         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 930
 931         spin_unlock_irqrestore(&dc->lock, flags);
 932 }
 933
 934 void tegra_dc_disable_vblank(struct tegra_dc *dc)
 935 {
 936         unsigned long value, flags;
 937
 938         spin_lock_irqsave(&dc->lock, flags);
 939
 940         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 941         value &= ~VBLANK_INT;
 942         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 943
 944         spin_unlock_irqrestore(&dc->lock, flags);
 945 }
 946
 947 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
 948 {
 949         struct drm_device *drm = dc->base.dev;
 950         struct drm_crtc *crtc = &dc->base;
 951         unsigned long flags, base;
 952         struct tegra_bo *bo;
 953
 954         spin_lock_irqsave(&drm->event_lock, flags);
 955
 956         if (!dc->event) {
 957                 spin_unlock_irqrestore(&drm->event_lock, flags);
 958                 return;
 959         }
 960
 961         bo = tegra_fb_get_plane(crtc->primary->fb, 0);
 962
 963         spin_lock(&dc->lock);
 964
 965         /* check if new start address has been latched */
 966         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
 967         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 968         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
 969         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 970
 971         spin_unlock(&dc->lock);
 972
 973         if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
 974                 drm_crtc_send_vblank_event(crtc, dc->event);
 975                 drm_crtc_vblank_put(crtc);
 976                 dc->event = NULL;
 977         }
 978
 979         spin_unlock_irqrestore(&drm->event_lock, flags);
 980 }
 981
 982 static void tegra_dc_destroy(struct drm_crtc *crtc)
 983 {
 984         drm_crtc_cleanup(crtc);
 985 }
 986
 987 static void tegra_crtc_reset(struct drm_crtc *crtc)
 988 {
 989         struct tegra_dc_state *state;
 990
 991         if (crtc->state)
 992                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 993
 994         kfree(crtc->state);
 995         crtc->state = NULL;
 996
 997         state = kzalloc(sizeof(*state), GFP_KERNEL);
 998         if (state) {
 999                 crtc->state = &state->base;
1000                 crtc->state->crtc = crtc;
1001         }
1002
1003         drm_crtc_vblank_reset(crtc);
1004 }
1005
1006 static struct drm_crtc_state *
1007 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1008 {
1009         struct tegra_dc_state *state = to_dc_state(crtc->state);
1010         struct tegra_dc_state *copy;
1011
1012         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1013         if (!copy)
1014                 return NULL;
1015
1016         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1017         copy->clk = state->clk;
1018         copy->pclk = state->pclk;
1019         copy->div = state->div;
1020         copy->planes = state->planes;
1021
1022         return &copy->base;
1023 }
1024
1025 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1026                                             struct drm_crtc_state *state)
1027 {
1028         __drm_atomic_helper_crtc_destroy_state(state);
1029         kfree(state);
1030 }
1031
1032 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1033         .page_flip = drm_atomic_helper_page_flip,
1034         .set_config = drm_atomic_helper_set_config,
1035         .destroy = tegra_dc_destroy,
1036         .reset = tegra_crtc_reset,
1037         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1038         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1039 };
1040
1041 static int tegra_dc_set_timings(struct tegra_dc *dc,
1042                                 struct drm_display_mode *mode)
1043 {
1044         unsigned int h_ref_to_sync = 1;
1045         unsigned int v_ref_to_sync = 1;
1046         unsigned long value;
1047
1048         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1049
1050         value = (v_ref_to_sync << 16) | h_ref_to_sync;
1051         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1052
1053         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1054                 ((mode->hsync_end - mode->hsync_start) <<  0);
1055         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1056
1057         value = ((mode->vtotal - mode->vsync_end) << 16) |
1058                 ((mode->htotal - mode->hsync_end) <<  0);
1059         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1060
1061         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1062                 ((mode->hsync_start - mode->hdisplay) <<  0);
1063         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1064
1065         value = (mode->vdisplay << 16) | mode->hdisplay;
1066         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1067
1068         return 0;
1069 }
1070
1071 /**
1072  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1073  *     state
1074  * @dc: display controller
1075  * @crtc_state: CRTC atomic state
1076  * @clk: parent clock for display controller
1077  * @pclk: pixel clock
1078  * @div: shift clock divider
1079  *
1080  * Returns:
1081  * 0 on success or a negative error-code on failure.
1082  */
1083 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1084                                struct drm_crtc_state *crtc_state,
1085                                struct clk *clk, unsigned long pclk,
1086                                unsigned int div)
1087 {
1088         struct tegra_dc_state *state = to_dc_state(crtc_state);
1089
1090         if (!clk_has_parent(dc->clk, clk))
1091                 return -EINVAL;
1092
1093         state->clk = clk;
1094         state->pclk = pclk;
1095         state->div = div;
1096
1097         return 0;
1098 }
1099
1100 static void tegra_dc_commit_state(struct tegra_dc *dc,
1101                                   struct tegra_dc_state *state)
1102 {
1103         u32 value;
1104         int err;
1105
1106         err = clk_set_parent(dc->clk, state->clk);
1107         if (err < 0)
1108                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1109
1110         /*
1111          * Outputs may not want to change the parent clock rate. This is only
1112          * relevant to Tegra20 where only a single display PLL is available.
1113          * Since that PLL would typically be used for HDMI, an internal LVDS
1114          * panel would need to be driven by some other clock such as PLL_P
1115          * which is shared with other peripherals. Changing the clock rate
1116          * should therefore be avoided.
1117          */
1118         if (state->pclk > 0) {
1119                 err = clk_set_rate(state->clk, state->pclk);
1120                 if (err < 0)
1121                         dev_err(dc->dev,
1122                                 "failed to set clock rate to %lu Hz\n",
1123                                 state->pclk);
1124         }
1125
1126         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1127                       state->div);
1128         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1129
1130         value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1131         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1132 }
1133
1134 static void tegra_dc_stop(struct tegra_dc *dc)
1135 {
1136         u32 value;
1137
1138         /* stop the display controller */
1139         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1140         value &= ~DISP_CTRL_MODE_MASK;
1141         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1142
1143         tegra_dc_commit(dc);
1144 }
1145
1146 static bool tegra_dc_idle(struct tegra_dc *dc)
1147 {
1148         u32 value;
1149
1150         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1151
1152         return (value & DISP_CTRL_MODE_MASK) == 0;
1153 }
1154
1155 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1156 {
1157         timeout = jiffies + msecs_to_jiffies(timeout);
1158
1159         while (time_before(jiffies, timeout)) {
1160                 if (tegra_dc_idle(dc))
1161                         return 0;
1162
1163                 usleep_range(1000, 2000);
1164         }
1165
1166         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1167         return -ETIMEDOUT;
1168 }
1169
1170 static void tegra_crtc_disable(struct drm_crtc *crtc)
1171 {
1172         struct tegra_dc *dc = to_tegra_dc(crtc);
1173         u32 value;
1174
1175         if (!tegra_dc_idle(dc)) {
1176                 tegra_dc_stop(dc);
1177
1178                 /*
1179                  * Ignore the return value, there isn't anything useful to do
1180                  * in case this fails.
1181                  */
1182                 tegra_dc_wait_idle(dc, 100);
1183         }
1184
1185         /*
1186          * This should really be part of the RGB encoder driver, but clearing
1187          * these bits has the side-effect of stopping the display controller.
1188          * When that happens no VBLANK interrupts will be raised. At the same
1189          * time the encoder is disabled before the display controller, so the
1190          * above code is always going to timeout waiting for the controller
1191          * to go idle.
1192          *
1193          * Given the close coupling between the RGB encoder and the display
1194          * controller doing it here is still kind of okay. None of the other
1195          * encoder drivers require these bits to be cleared.
1196          *
1197          * XXX: Perhaps given that the display controller is switched off at
1198          * this point anyway maybe clearing these bits isn't even useful for
1199          * the RGB encoder?
1200          */
1201         if (dc->rgb) {
1202                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1203                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1204                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1205                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1206         }
1207
1208         tegra_dc_stats_reset(&dc->stats);
1209         drm_crtc_vblank_off(crtc);
1210
1211         pm_runtime_put_sync(dc->dev);
1212 }
1213
1214 static void tegra_crtc_enable(struct drm_crtc *crtc)
1215 {
1216         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1217         struct tegra_dc_state *state = to_dc_state(crtc->state);
1218         struct tegra_dc *dc = to_tegra_dc(crtc);
1219         u32 value;
1220
1221         pm_runtime_get_sync(dc->dev);
1222
1223         /* initialize display controller */
1224         if (dc->syncpt) {
1225                 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1226
1227                 value = SYNCPT_CNTRL_NO_STALL;
1228                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1229
1230                 value = SYNCPT_VSYNC_ENABLE | syncpt;
1231                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1232         }
1233
1234         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1235                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1236         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1237
1238         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1239                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1240         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1241
1242         /* initialize timer */
1243         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1244                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1245         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1246
1247         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1248                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1249         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1250
1251         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1252                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1253         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1254
1255         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1256                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1257         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1258
1259         if (dc->soc->supports_border_color)
1260                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1261
1262         /* apply PLL and pixel clock changes */
1263         tegra_dc_commit_state(dc, state);
1264
1265         /* program display mode */
1266         tegra_dc_set_timings(dc, mode);
1267
1268         /* interlacing isn't supported yet, so disable it */
1269         if (dc->soc->supports_interlacing) {
1270                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1271                 value &= ~INTERLACE_ENABLE;
1272                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1273         }
1274
1275         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1276         value &= ~DISP_CTRL_MODE_MASK;
1277         value |= DISP_CTRL_MODE_C_DISPLAY;
1278         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1279
1280         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1281         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1282                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1283         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1284
1285         tegra_dc_commit(dc);
1286
1287         drm_crtc_vblank_on(crtc);
1288 }
1289
1290 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1291                                    struct drm_crtc_state *state)
1292 {
1293         return 0;
1294 }
1295
1296 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1297                                     struct drm_crtc_state *old_crtc_state)
1298 {
1299         struct tegra_dc *dc = to_tegra_dc(crtc);
1300
1301         if (crtc->state->event) {
1302                 crtc->state->event->pipe = drm_crtc_index(crtc);
1303
1304                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1305
1306                 dc->event = crtc->state->event;
1307                 crtc->state->event = NULL;
1308         }
1309 }
1310
1311 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1312                                     struct drm_crtc_state *old_crtc_state)
1313 {
1314         struct tegra_dc_state *state = to_dc_state(crtc->state);
1315         struct tegra_dc *dc = to_tegra_dc(crtc);
1316
1317         tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1318         tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1319 }
1320
1321 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1322         .disable = tegra_crtc_disable,
1323         .enable = tegra_crtc_enable,
1324         .atomic_check = tegra_crtc_atomic_check,
1325         .atomic_begin = tegra_crtc_atomic_begin,
1326         .atomic_flush = tegra_crtc_atomic_flush,
1327 };
1328
1329 static irqreturn_t tegra_dc_irq(int irq, void *data)
1330 {
1331         struct tegra_dc *dc = data;
1332         unsigned long status;
1333
1334         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1335         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1336
1337         if (status & FRAME_END_INT) {
1338                 /*
1339                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1340                 */
1341                 dc->stats.frames++;
1342         }
1343
1344         if (status & VBLANK_INT) {
1345                 /*
1346                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1347                 */
1348                 drm_crtc_handle_vblank(&dc->base);
1349                 tegra_dc_finish_page_flip(dc);
1350                 dc->stats.vblank++;
1351         }
1352
1353         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1354                 /*
1355                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1356                 */
1357                 dc->stats.underflow++;
1358         }
1359
1360         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1361                 /*
1362                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1363                 */
1364                 dc->stats.overflow++;
1365         }
1366
1367         return IRQ_HANDLED;
1368 }
1369
1370 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1371 {
1372         struct drm_info_node *node = s->private;
1373         struct tegra_dc *dc = node->info_ent->data;
1374         int err = 0;
1375
1376         drm_modeset_lock_crtc(&dc->base, NULL);
1377
1378         if (!dc->base.state->active) {
1379                 err = -EBUSY;
1380                 goto unlock;
1381         }
1382
1383 #define DUMP_REG(name)                                          \
1384         seq_printf(s, "%-40s %#05x %08x\n", #name, name,        \
1385                    tegra_dc_readl(dc, name))
1386
1387         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1388         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1389         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1390         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1391         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1392         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1393         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1394         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1395         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1396         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1397         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1398         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1399         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1400         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1401         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1402         DUMP_REG(DC_CMD_SIGNAL_RAISE);
1403         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1404         DUMP_REG(DC_CMD_INT_STATUS);
1405         DUMP_REG(DC_CMD_INT_MASK);
1406         DUMP_REG(DC_CMD_INT_ENABLE);
1407         DUMP_REG(DC_CMD_INT_TYPE);
1408         DUMP_REG(DC_CMD_INT_POLARITY);
1409         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1410         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1411         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1412         DUMP_REG(DC_CMD_STATE_ACCESS);
1413         DUMP_REG(DC_CMD_STATE_CONTROL);
1414         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1415         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1416         DUMP_REG(DC_COM_CRC_CONTROL);
1417         DUMP_REG(DC_COM_CRC_CHECKSUM);
1418         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1419         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1420         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1421         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1422         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1423         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1424         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1425         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1426         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1427         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1428         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1429         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1430         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1431         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1432         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1433         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1434         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1435         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1436         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1437         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1438         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1439         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1440         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1441         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1442         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1443         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1444         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1445         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1446         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1447         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1448         DUMP_REG(DC_COM_SPI_CONTROL);
1449         DUMP_REG(DC_COM_SPI_START_BYTE);
1450         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1451         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1452         DUMP_REG(DC_COM_HSPI_CS_DC);
1453         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1454         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1455         DUMP_REG(DC_COM_GPIO_CTRL);
1456         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1457         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1458         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1459         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1460         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1461         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1462         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1463         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1464         DUMP_REG(DC_DISP_REF_TO_SYNC);
1465         DUMP_REG(DC_DISP_SYNC_WIDTH);
1466         DUMP_REG(DC_DISP_BACK_PORCH);
1467         DUMP_REG(DC_DISP_ACTIVE);
1468         DUMP_REG(DC_DISP_FRONT_PORCH);
1469         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1470         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1471         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1472         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1473         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1474         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1475         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1476         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1477         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1478         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1479         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1480         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1481         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1482         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1483         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1484         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1485         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1486         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1487         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1488         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1489         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1490         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1491         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1492         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1493         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1494         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1495         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1496         DUMP_REG(DC_DISP_M0_CONTROL);
1497         DUMP_REG(DC_DISP_M1_CONTROL);
1498         DUMP_REG(DC_DISP_DI_CONTROL);
1499         DUMP_REG(DC_DISP_PP_CONTROL);
1500         DUMP_REG(DC_DISP_PP_SELECT_A);
1501         DUMP_REG(DC_DISP_PP_SELECT_B);
1502         DUMP_REG(DC_DISP_PP_SELECT_C);
1503         DUMP_REG(DC_DISP_PP_SELECT_D);
1504         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1505         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1506         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1507         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1508         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1509         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1510         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1511         DUMP_REG(DC_DISP_BORDER_COLOR);
1512         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1513         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1514         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1515         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1516         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1517         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1518         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1519         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1520         DUMP_REG(DC_DISP_CURSOR_POSITION);
1521         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1522         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1523         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1524         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1525         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1526         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1527         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1528         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1529         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1530         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1531         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1532         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1533         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1534         DUMP_REG(DC_DISP_SD_CONTROL);
1535         DUMP_REG(DC_DISP_SD_CSC_COEFF);
1536         DUMP_REG(DC_DISP_SD_LUT(0));
1537         DUMP_REG(DC_DISP_SD_LUT(1));
1538         DUMP_REG(DC_DISP_SD_LUT(2));
1539         DUMP_REG(DC_DISP_SD_LUT(3));
1540         DUMP_REG(DC_DISP_SD_LUT(4));
1541         DUMP_REG(DC_DISP_SD_LUT(5));
1542         DUMP_REG(DC_DISP_SD_LUT(6));
1543         DUMP_REG(DC_DISP_SD_LUT(7));
1544         DUMP_REG(DC_DISP_SD_LUT(8));
1545         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1546         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1547         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1548         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1549         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1550         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1551         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1552         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1553         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1554         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1555         DUMP_REG(DC_DISP_SD_BL_TF(0));
1556         DUMP_REG(DC_DISP_SD_BL_TF(1));
1557         DUMP_REG(DC_DISP_SD_BL_TF(2));
1558         DUMP_REG(DC_DISP_SD_BL_TF(3));
1559         DUMP_REG(DC_DISP_SD_BL_CONTROL);
1560         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1561         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1562         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1563         DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1564         DUMP_REG(DC_WIN_WIN_OPTIONS);
1565         DUMP_REG(DC_WIN_BYTE_SWAP);
1566         DUMP_REG(DC_WIN_BUFFER_CONTROL);
1567         DUMP_REG(DC_WIN_COLOR_DEPTH);
1568         DUMP_REG(DC_WIN_POSITION);
1569         DUMP_REG(DC_WIN_SIZE);
1570         DUMP_REG(DC_WIN_PRESCALED_SIZE);
1571         DUMP_REG(DC_WIN_H_INITIAL_DDA);
1572         DUMP_REG(DC_WIN_V_INITIAL_DDA);
1573         DUMP_REG(DC_WIN_DDA_INC);
1574         DUMP_REG(DC_WIN_LINE_STRIDE);
1575         DUMP_REG(DC_WIN_BUF_STRIDE);
1576         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1577         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1578         DUMP_REG(DC_WIN_DV_CONTROL);
1579         DUMP_REG(DC_WIN_BLEND_NOKEY);
1580         DUMP_REG(DC_WIN_BLEND_1WIN);
1581         DUMP_REG(DC_WIN_BLEND_2WIN_X);
1582         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1583         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1584         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1585         DUMP_REG(DC_WINBUF_START_ADDR);
1586         DUMP_REG(DC_WINBUF_START_ADDR_NS);
1587         DUMP_REG(DC_WINBUF_START_ADDR_U);
1588         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1589         DUMP_REG(DC_WINBUF_START_ADDR_V);
1590         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1591         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1592         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1593         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1594         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1595         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1596         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1597         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1598         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1599
1600 #undef DUMP_REG
1601
1602 unlock:
1603         drm_modeset_unlock_crtc(&dc->base);
1604         return err;
1605 }
1606
1607 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1608 {
1609         struct drm_info_node *node = s->private;
1610         struct tegra_dc *dc = node->info_ent->data;
1611         int err = 0;
1612         u32 value;
1613
1614         drm_modeset_lock_crtc(&dc->base, NULL);
1615
1616         if (!dc->base.state->active) {
1617                 err = -EBUSY;
1618                 goto unlock;
1619         }
1620
1621         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1622         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1623         tegra_dc_commit(dc);
1624
1625         drm_crtc_wait_one_vblank(&dc->base);
1626         drm_crtc_wait_one_vblank(&dc->base);
1627
1628         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1629         seq_printf(s, "%08x\n", value);
1630
1631         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1632
1633 unlock:
1634         drm_modeset_unlock_crtc(&dc->base);
1635         return err;
1636 }
1637
1638 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1639 {
1640         struct drm_info_node *node = s->private;
1641         struct tegra_dc *dc = node->info_ent->data;
1642
1643         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1644         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1645         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1646         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1647
1648         return 0;
1649 }
1650
1651 static struct drm_info_list debugfs_files[] = {
1652         { "regs", tegra_dc_show_regs, 0, NULL },
1653         { "crc", tegra_dc_show_crc, 0, NULL },
1654         { "stats", tegra_dc_show_stats, 0, NULL },
1655 };
1656
1657 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1658 {
1659         unsigned int i;
1660         char *name;
1661         int err;
1662
1663         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1664         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1665         kfree(name);
1666
1667         if (!dc->debugfs)
1668                 return -ENOMEM;
1669
1670         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1671                                     GFP_KERNEL);
1672         if (!dc->debugfs_files) {
1673                 err = -ENOMEM;
1674                 goto remove;
1675         }
1676
1677         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1678                 dc->debugfs_files[i].data = dc;
1679
1680         err = drm_debugfs_create_files(dc->debugfs_files,
1681                                        ARRAY_SIZE(debugfs_files),
1682                                        dc->debugfs, minor);
1683         if (err < 0)
1684                 goto free;
1685
1686         dc->minor = minor;
1687
1688         return 0;
1689
1690 free:
1691         kfree(dc->debugfs_files);
1692         dc->debugfs_files = NULL;
1693 remove:
1694         debugfs_remove(dc->debugfs);
1695         dc->debugfs = NULL;
1696
1697         return err;
1698 }
1699
1700 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1701 {
1702         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1703                                  dc->minor);
1704         dc->minor = NULL;
1705
1706         kfree(dc->debugfs_files);
1707         dc->debugfs_files = NULL;
1708
1709         debugfs_remove(dc->debugfs);
1710         dc->debugfs = NULL;
1711
1712         return 0;
1713 }
1714
1715 static int tegra_dc_init(struct host1x_client *client)
1716 {
1717         struct drm_device *drm = dev_get_drvdata(client->parent);
1718         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1719         struct tegra_dc *dc = host1x_client_to_dc(client);
1720         struct tegra_drm *tegra = drm->dev_private;
1721         struct drm_plane *primary = NULL;
1722         struct drm_plane *cursor = NULL;
1723         int err;
1724
1725         dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1726         if (!dc->syncpt)
1727                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1728
1729         if (tegra->domain) {
1730                 err = iommu_attach_device(tegra->domain, dc->dev);
1731                 if (err < 0) {
1732                         dev_err(dc->dev, "failed to attach to domain: %d\n",
1733                                 err);
1734                         return err;
1735                 }
1736
1737                 dc->domain = tegra->domain;
1738         }
1739
1740         primary = tegra_dc_primary_plane_create(drm, dc);
1741         if (IS_ERR(primary)) {
1742                 err = PTR_ERR(primary);
1743                 goto cleanup;
1744         }
1745
1746         if (dc->soc->supports_cursor) {
1747                 cursor = tegra_dc_cursor_plane_create(drm, dc);
1748                 if (IS_ERR(cursor)) {
1749                         err = PTR_ERR(cursor);
1750                         goto cleanup;
1751                 }
1752         }
1753
1754         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1755                                         &tegra_crtc_funcs, NULL);
1756         if (err < 0)
1757                 goto cleanup;
1758
1759         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1760
1761         /*
1762          * Keep track of the minimum pitch alignment across all display
1763          * controllers.
1764          */
1765         if (dc->soc->pitch_align > tegra->pitch_align)
1766                 tegra->pitch_align = dc->soc->pitch_align;
1767
1768         err = tegra_dc_rgb_init(drm, dc);
1769         if (err < 0 && err != -ENODEV) {
1770                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1771                 goto cleanup;
1772         }
1773
1774         err = tegra_dc_add_planes(drm, dc);
1775         if (err < 0)
1776                 goto cleanup;
1777
1778         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1779                 err = tegra_dc_debugfs_init(dc, drm->primary);
1780                 if (err < 0)
1781                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1782         }
1783
1784         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1785                                dev_name(dc->dev), dc);
1786         if (err < 0) {
1787                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1788                         err);
1789                 goto cleanup;
1790         }
1791
1792         return 0;
1793
1794 cleanup:
1795         if (cursor)
1796                 drm_plane_cleanup(cursor);
1797
1798         if (primary)
1799                 drm_plane_cleanup(primary);
1800
1801         if (tegra->domain) {
1802                 iommu_detach_device(tegra->domain, dc->dev);
1803                 dc->domain = NULL;
1804         }
1805
1806         return err;
1807 }
1808
1809 static int tegra_dc_exit(struct host1x_client *client)
1810 {
1811         struct tegra_dc *dc = host1x_client_to_dc(client);
1812         int err;
1813
1814         devm_free_irq(dc->dev, dc->irq, dc);
1815
1816         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1817                 err = tegra_dc_debugfs_exit(dc);
1818                 if (err < 0)
1819                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1820         }
1821
1822         err = tegra_dc_rgb_exit(dc);
1823         if (err) {
1824                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1825                 return err;
1826         }
1827
1828         if (dc->domain) {
1829                 iommu_detach_device(dc->domain, dc->dev);
1830                 dc->domain = NULL;
1831         }
1832
1833         host1x_syncpt_free(dc->syncpt);
1834
1835         return 0;
1836 }
1837
1838 static const struct host1x_client_ops dc_client_ops = {
1839         .init = tegra_dc_init,
1840         .exit = tegra_dc_exit,
1841 };
1842
1843 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1844         .supports_border_color = true,
1845         .supports_interlacing = false,
1846         .supports_cursor = false,
1847         .supports_block_linear = false,
1848         .pitch_align = 8,
1849         .has_powergate = false,
1850 };
1851
1852 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1853         .supports_border_color = true,
1854         .supports_interlacing = false,
1855         .supports_cursor = false,
1856         .supports_block_linear = false,
1857         .pitch_align = 8,
1858         .has_powergate = false,
1859 };
1860
1861 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1862         .supports_border_color = true,
1863         .supports_interlacing = false,
1864         .supports_cursor = false,
1865         .supports_block_linear = false,
1866         .pitch_align = 64,
1867         .has_powergate = true,
1868 };
1869
1870 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1871         .supports_border_color = false,
1872         .supports_interlacing = true,
1873         .supports_cursor = true,
1874         .supports_block_linear = true,
1875         .pitch_align = 64,
1876         .has_powergate = true,
1877 };
1878
1879 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1880         .supports_border_color = false,
1881         .supports_interlacing = true,
1882         .supports_cursor = true,
1883         .supports_block_linear = true,
1884         .pitch_align = 64,
1885         .has_powergate = true,
1886 };
1887
1888 static const struct of_device_id tegra_dc_of_match[] = {
1889         {
1890                 .compatible = "nvidia,tegra210-dc",
1891                 .data = &tegra210_dc_soc_info,
1892         }, {
1893                 .compatible = "nvidia,tegra124-dc",
1894                 .data = &tegra124_dc_soc_info,
1895         }, {
1896                 .compatible = "nvidia,tegra114-dc",
1897                 .data = &tegra114_dc_soc_info,
1898         }, {
1899                 .compatible = "nvidia,tegra30-dc",
1900                 .data = &tegra30_dc_soc_info,
1901         }, {
1902                 .compatible = "nvidia,tegra20-dc",
1903                 .data = &tegra20_dc_soc_info,
1904         }, {
1905                 /* sentinel */
1906         }
1907 };
1908 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1909
1910 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1911 {
1912         struct device_node *np;
1913         u32 value = 0;
1914         int err;
1915
1916         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1917         if (err < 0) {
1918                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1919
1920                 /*
1921                  * If the nvidia,head property isn't present, try to find the
1922                  * correct head number by looking up the position of this
1923                  * display controller's node within the device tree. Assuming
1924                  * that the nodes are ordered properly in the DTS file and
1925                  * that the translation into a flattened device tree blob
1926                  * preserves that ordering this will actually yield the right
1927                  * head number.
1928                  *
1929                  * If those assumptions don't hold, this will still work for
1930                  * cases where only a single display controller is used.
1931                  */
1932                 for_each_matching_node(np, tegra_dc_of_match) {
1933                         if (np == dc->dev->of_node) {
1934                                 of_node_put(np);
1935                                 break;
1936                         }
1937
1938                         value++;
1939                 }
1940         }
1941
1942         dc->pipe = value;
1943
1944         return 0;
1945 }
1946
1947 static int tegra_dc_probe(struct platform_device *pdev)
1948 {
1949         const struct of_device_id *id;
1950         struct resource *regs;
1951         struct tegra_dc *dc;
1952         int err;
1953
1954         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1955         if (!dc)
1956                 return -ENOMEM;
1957
1958         id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1959         if (!id)
1960                 return -ENODEV;
1961
1962         spin_lock_init(&dc->lock);
1963         INIT_LIST_HEAD(&dc->list);
1964         dc->dev = &pdev->dev;
1965         dc->soc = id->data;
1966
1967         err = tegra_dc_parse_dt(dc);
1968         if (err < 0)
1969                 return err;
1970
1971         dc->clk = devm_clk_get(&pdev->dev, NULL);
1972         if (IS_ERR(dc->clk)) {
1973                 dev_err(&pdev->dev, "failed to get clock\n");
1974                 return PTR_ERR(dc->clk);
1975         }
1976
1977         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1978         if (IS_ERR(dc->rst)) {
1979                 dev_err(&pdev->dev, "failed to get reset\n");
1980                 return PTR_ERR(dc->rst);
1981         }
1982
1983         reset_control_assert(dc->rst);
1984
1985         if (dc->soc->has_powergate) {
1986                 if (dc->pipe == 0)
1987                         dc->powergate = TEGRA_POWERGATE_DIS;
1988                 else
1989                         dc->powergate = TEGRA_POWERGATE_DISB;
1990
1991                 tegra_powergate_power_off(dc->powergate);
1992         }
1993
1994         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1995         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1996         if (IS_ERR(dc->regs))
1997                 return PTR_ERR(dc->regs);
1998
1999         dc->irq = platform_get_irq(pdev, 0);
2000         if (dc->irq < 0) {
2001                 dev_err(&pdev->dev, "failed to get IRQ\n");
2002                 return -ENXIO;
2003         }
2004
2005         err = tegra_dc_rgb_probe(dc);
2006         if (err < 0 && err != -ENODEV) {
2007                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2008                 return err;
2009         }
2010
2011         platform_set_drvdata(pdev, dc);
2012         pm_runtime_enable(&pdev->dev);
2013
2014         INIT_LIST_HEAD(&dc->client.list);
2015         dc->client.ops = &dc_client_ops;
2016         dc->client.dev = &pdev->dev;
2017
2018         err = host1x_client_register(&dc->client);
2019         if (err < 0) {
2020                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2021                         err);
2022                 return err;
2023         }
2024
2025         return 0;
2026 }
2027
2028 static int tegra_dc_remove(struct platform_device *pdev)
2029 {
2030         struct tegra_dc *dc = platform_get_drvdata(pdev);
2031         int err;
2032
2033         err = host1x_client_unregister(&dc->client);
2034         if (err < 0) {
2035                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2036                         err);
2037                 return err;
2038         }
2039
2040         err = tegra_dc_rgb_remove(dc);
2041         if (err < 0) {
2042                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2043                 return err;
2044         }
2045
2046         pm_runtime_disable(&pdev->dev);
2047
2048         return 0;
2049 }
2050
2051 #ifdef CONFIG_PM
2052 static int tegra_dc_suspend(struct device *dev)
2053 {
2054         struct tegra_dc *dc = dev_get_drvdata(dev);
2055         int err;
2056
2057         err = reset_control_assert(dc->rst);
2058         if (err < 0) {
2059                 dev_err(dev, "failed to assert reset: %d\n", err);
2060                 return err;
2061         }
2062
2063         if (dc->soc->has_powergate)
2064                 tegra_powergate_power_off(dc->powergate);
2065
2066         clk_disable_unprepare(dc->clk);
2067
2068         return 0;
2069 }
2070
2071 static int tegra_dc_resume(struct device *dev)
2072 {
2073         struct tegra_dc *dc = dev_get_drvdata(dev);
2074         int err;
2075
2076         if (dc->soc->has_powergate) {
2077                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2078                                                         dc->rst);
2079                 if (err < 0) {
2080                         dev_err(dev, "failed to power partition: %d\n", err);
2081                         return err;
2082                 }
2083         } else {
2084                 err = clk_prepare_enable(dc->clk);
2085                 if (err < 0) {
2086                         dev_err(dev, "failed to enable clock: %d\n", err);
2087                         return err;
2088                 }
2089
2090                 err = reset_control_deassert(dc->rst);
2091                 if (err < 0) {
2092                         dev_err(dev, "failed to deassert reset: %d\n", err);
2093                         return err;
2094                 }
2095         }
2096
2097         return 0;
2098 }
2099 #endif
2100
2101 static const struct dev_pm_ops tegra_dc_pm_ops = {
2102         SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2103 };
2104
2105 struct platform_driver tegra_dc_driver = {
2106         .driver = {
2107                 .name = "tegra-dc",
2108                 .of_match_table = tegra_dc_of_match,
2109                 .pm = &tegra_dc_pm_ops,
2110         },
2111         .probe = tegra_dc_probe,
2112         .remove = tegra_dc_remove,
2113 };