drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34
  35 static void psp_set_funcs(struct amdgpu_device *adev);
  36
  37 static int psp_early_init(void *handle)
  38 {
  39         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  40
  41         psp_set_funcs(adev);
  42
  43         return 0;
  44 }
  45
  46 static int psp_sw_init(void *handle)
  47 {
  48         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  49         struct psp_context *psp = &adev->psp;
  50         int ret;
  51
  52         switch (adev->asic_type) {
  53         case CHIP_VEGA10:
  54         case CHIP_VEGA12:
  55                 psp_v3_1_set_psp_funcs(psp);
  56                 break;
  57         case CHIP_RAVEN:
  58                 psp_v10_0_set_psp_funcs(psp);
  59                 break;
  60         default:
  61                 return -EINVAL;
  62         }
  63
  64         psp->adev = adev;
  65
  66         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  67                 return 0;
  68
  69         ret = psp_init_microcode(psp);
  70         if (ret) {
  71                 DRM_ERROR("Failed to load psp firmware!\n");
  72                 return ret;
  73         }
  74
  75         return 0;
  76 }
  77
  78 static int psp_sw_fini(void *handle)
  79 {
  80         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  81
  82         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  83                 return 0;
  84
  85         release_firmware(adev->psp.sos_fw);
  86         adev->psp.sos_fw = NULL;
  87         release_firmware(adev->psp.asd_fw);
  88         adev->psp.asd_fw = NULL;
  89         return 0;
  90 }
  91
  92 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  93                  uint32_t reg_val, uint32_t mask, bool check_changed)
  94 {
  95         uint32_t val;
  96         int i;
  97         struct amdgpu_device *adev = psp->adev;
  98
  99         for (i = 0; i < adev->usec_timeout; i++) {
 100                 val = RREG32(reg_index);
 101                 if (check_changed) {
 102                         if (val != reg_val)
 103                                 return 0;
 104                 } else {
 105                         if ((val & mask) == reg_val)
 106                                 return 0;
 107                 }
 108                 udelay(1);
 109         }
 110
 111         return -ETIME;
 112 }
 113
 114 static int
 115 psp_cmd_submit_buf(struct psp_context *psp,
 116                    struct amdgpu_firmware_info *ucode,
 117                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
 118                    int index)
 119 {
 120         int ret;
 121
 122         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 123
 124         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 125
 126         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 127                              fence_mc_addr, index);
 128
 129         while (*((unsigned int *)psp->fence_buf) != index) {
 130                 msleep(1);
 131         }
 132
 133         return ret;
 134 }
 135
 136 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 137                                  uint64_t tmr_mc, uint32_t size)
 138 {
 139         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 140         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 141         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 142         cmd->cmd.cmd_setup_tmr.buf_size = size;
 143 }
 144
 145 /* Set up Trusted Memory Region */
 146 static int psp_tmr_init(struct psp_context *psp)
 147 {
 148         int ret;
 149
 150         /*
 151          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 152          * physical).
 153          *
 154          * Note: this memory need be reserved till the driver
 155          * uninitializes.
 156          */
 157         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
 158                                       AMDGPU_GEM_DOMAIN_VRAM,
 159                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 160
 161         return ret;
 162 }
 163
 164 static int psp_tmr_load(struct psp_context *psp)
 165 {
 166         int ret;
 167         struct psp_gfx_cmd_resp *cmd;
 168
 169         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 170         if (!cmd)
 171                 return -ENOMEM;
 172
 173         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
 174
 175         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 176                                  psp->fence_buf_mc_addr, 1);
 177         if (ret)
 178                 goto failed;
 179
 180         kfree(cmd);
 181
 182         return 0;
 183
 184 failed:
 185         kfree(cmd);
 186         return ret;
 187 }
 188
 189 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 190                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 191                                  uint32_t size, uint32_t shared_size)
 192 {
 193         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 194         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 195         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 196         cmd->cmd.cmd_load_ta.app_len = size;
 197
 198         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 199         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 200         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 201 }
 202
 203 static int psp_asd_init(struct psp_context *psp)
 204 {
 205         int ret;
 206
 207         /*
 208          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 209          * physical) for shared ASD <-> Driver
 210          */
 211         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 212                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 213                                       &psp->asd_shared_bo,
 214                                       &psp->asd_shared_mc_addr,
 215                                       &psp->asd_shared_buf);
 216
 217         return ret;
 218 }
 219
 220 static int psp_asd_load(struct psp_context *psp)
 221 {
 222         int ret;
 223         struct psp_gfx_cmd_resp *cmd;
 224
 225         /* If PSP version doesn't match ASD version, asd loading will be failed.
 226          * add workaround to bypass it for sriov now.
 227          * TODO: add version check to make it common
 228          */
 229         if (amdgpu_sriov_vf(psp->adev))
 230                 return 0;
 231
 232         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 233         if (!cmd)
 234                 return -ENOMEM;
 235
 236         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 237         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 238
 239         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 240                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 241
 242         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 243                                  psp->fence_buf_mc_addr, 2);
 244
 245         kfree(cmd);
 246
 247         return ret;
 248 }
 249
 250 static int psp_hw_start(struct psp_context *psp)
 251 {
 252         struct amdgpu_device *adev = psp->adev;
 253         int ret;
 254
 255         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
 256                 ret = psp_bootloader_load_sysdrv(psp);
 257                 if (ret)
 258                         return ret;
 259
 260                 ret = psp_bootloader_load_sos(psp);
 261                 if (ret)
 262                         return ret;
 263         }
 264
 265         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 266         if (ret)
 267                 return ret;
 268
 269         ret = psp_tmr_load(psp);
 270         if (ret)
 271                 return ret;
 272
 273         ret = psp_asd_load(psp);
 274         if (ret)
 275                 return ret;
 276
 277         return 0;
 278 }
 279
 280 static int psp_np_fw_load(struct psp_context *psp)
 281 {
 282         int i, ret;
 283         struct amdgpu_firmware_info *ucode;
 284         struct amdgpu_device* adev = psp->adev;
 285
 286         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 287                 ucode = &adev->firmware.ucode[i];
 288                 if (!ucode->fw)
 289                         continue;
 290
 291                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 292                     psp_smu_reload_quirk(psp))
 293                         continue;
 294                 if (amdgpu_sriov_vf(adev) &&
 295                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 296                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 297                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 298                         /*skip ucode loading in SRIOV VF */
 299                         continue;
 300
 301                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 302                 if (ret)
 303                         return ret;
 304
 305                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 306                                          psp->fence_buf_mc_addr, i + 3);
 307                 if (ret)
 308                         return ret;
 309
 310 #if 0
 311                 /* check if firmware loaded sucessfully */
 312                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 313                         return -EINVAL;
 314 #endif
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int psp_load_fw(struct amdgpu_device *adev)
 321 {
 322         int ret;
 323         struct psp_context *psp = &adev->psp;
 324
 325         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0)
 326                 goto skip_memalloc;
 327
 328         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 329         if (!psp->cmd)
 330                 return -ENOMEM;
 331
 332         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 333                                         AMDGPU_GEM_DOMAIN_GTT,
 334                                         &psp->fw_pri_bo,
 335                                         &psp->fw_pri_mc_addr,
 336                                         &psp->fw_pri_buf);
 337         if (ret)
 338                 goto failed;
 339
 340         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 341                                         AMDGPU_GEM_DOMAIN_VRAM,
 342                                         &psp->fence_buf_bo,
 343                                         &psp->fence_buf_mc_addr,
 344                                         &psp->fence_buf);
 345         if (ret)
 346                 goto failed_mem2;
 347
 348         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 349                                       AMDGPU_GEM_DOMAIN_VRAM,
 350                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 351                                       (void **)&psp->cmd_buf_mem);
 352         if (ret)
 353                 goto failed_mem1;
 354
 355         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 356
 357         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 358         if (ret)
 359                 goto failed_mem;
 360
 361         ret = psp_tmr_init(psp);
 362         if (ret)
 363                 goto failed_mem;
 364
 365         ret = psp_asd_init(psp);
 366         if (ret)
 367                 goto failed_mem;
 368
 369 skip_memalloc:
 370         ret = psp_hw_start(psp);
 371         if (ret)
 372                 goto failed_mem;
 373
 374         ret = psp_np_fw_load(psp);
 375         if (ret)
 376                 goto failed_mem;
 377
 378         return 0;
 379
 380 failed_mem:
 381         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
 382                               &psp->cmd_buf_mc_addr,
 383                               (void **)&psp->cmd_buf_mem);
 384 failed_mem1:
 385         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 386                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 387 failed_mem2:
 388         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 389                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 390 failed:
 391         kfree(psp->cmd);
 392         psp->cmd = NULL;
 393         return ret;
 394 }
 395
 396 static int psp_hw_init(void *handle)
 397 {
 398         int ret;
 399         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 400
 401
 402         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 403                 return 0;
 404
 405         mutex_lock(&adev->firmware.mutex);
 406         /*
 407          * This sequence is just used on hw_init only once, no need on
 408          * resume.
 409          */
 410         ret = amdgpu_ucode_init_bo(adev);
 411         if (ret)
 412                 goto failed;
 413
 414         ret = psp_load_fw(adev);
 415         if (ret) {
 416                 DRM_ERROR("PSP firmware loading failed\n");
 417                 goto failed;
 418         }
 419
 420         mutex_unlock(&adev->firmware.mutex);
 421         return 0;
 422
 423 failed:
 424         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 425         mutex_unlock(&adev->firmware.mutex);
 426         return -EINVAL;
 427 }
 428
 429 static int psp_hw_fini(void *handle)
 430 {
 431         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 432         struct psp_context *psp = &adev->psp;
 433
 434         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 435                 return 0;
 436
 437         amdgpu_ucode_fini_bo(adev);
 438
 439         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 440
 441         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 442         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 443                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 444         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 445                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 446         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
 447                               &psp->asd_shared_buf);
 448         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 449                               (void **)&psp->cmd_buf_mem);
 450
 451         kfree(psp->cmd);
 452         psp->cmd = NULL;
 453
 454         return 0;
 455 }
 456
 457 static int psp_suspend(void *handle)
 458 {
 459         int ret;
 460         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 461         struct psp_context *psp = &adev->psp;
 462
 463         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 464                 return 0;
 465
 466         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
 467         if (ret) {
 468                 DRM_ERROR("PSP ring stop failed\n");
 469                 return ret;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int psp_resume(void *handle)
 476 {
 477         int ret;
 478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 479         struct psp_context *psp = &adev->psp;
 480
 481         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 482                 return 0;
 483
 484         DRM_INFO("PSP is resuming...\n");
 485
 486         mutex_lock(&adev->firmware.mutex);
 487
 488         ret = psp_hw_start(psp);
 489         if (ret)
 490                 goto failed;
 491
 492         ret = psp_np_fw_load(psp);
 493         if (ret)
 494                 goto failed;
 495
 496         mutex_unlock(&adev->firmware.mutex);
 497
 498         return 0;
 499
 500 failed:
 501         DRM_ERROR("PSP resume failed\n");
 502         mutex_unlock(&adev->firmware.mutex);
 503         return ret;
 504 }
 505
 506 int psp_gpu_reset(struct amdgpu_device *adev)
 507 {
 508         return psp_mode1_reset(&adev->psp);
 509 }
 510
 511 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 512                                         enum AMDGPU_UCODE_ID ucode_type)
 513 {
 514         struct amdgpu_firmware_info *ucode = NULL;
 515
 516         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 517                 DRM_INFO("firmware is not loaded by PSP\n");
 518                 return true;
 519         }
 520
 521         if (!adev->firmware.fw_size)
 522                 return false;
 523
 524         ucode = &adev->firmware.ucode[ucode_type];
 525         if (!ucode->fw || !ucode->ucode_size)
 526                 return false;
 527
 528         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 529 }
 530
 531 static int psp_set_clockgating_state(void *handle,
 532                                      enum amd_clockgating_state state)
 533 {
 534         return 0;
 535 }
 536
 537 static int psp_set_powergating_state(void *handle,
 538                                      enum amd_powergating_state state)
 539 {
 540         return 0;
 541 }
 542
 543 const struct amd_ip_funcs psp_ip_funcs = {
 544         .name = "psp",
 545         .early_init = psp_early_init,
 546         .late_init = NULL,
 547         .sw_init = psp_sw_init,
 548         .sw_fini = psp_sw_fini,
 549         .hw_init = psp_hw_init,
 550         .hw_fini = psp_hw_fini,
 551         .suspend = psp_suspend,
 552         .resume = psp_resume,
 553         .is_idle = NULL,
 554         .check_soft_reset = NULL,
 555         .wait_for_idle = NULL,
 556         .soft_reset = NULL,
 557         .set_clockgating_state = psp_set_clockgating_state,
 558         .set_powergating_state = psp_set_powergating_state,
 559 };
 560
 561 static const struct amdgpu_psp_funcs psp_funcs = {
 562         .check_fw_loading_status = psp_check_fw_loading_status,
 563 };
 564
 565 static void psp_set_funcs(struct amdgpu_device *adev)
 566 {
 567         if (NULL == adev->firmware.funcs)
 568                 adev->firmware.funcs = &psp_funcs;
 569 }
 570
 571 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 572 {
 573         .type = AMD_IP_BLOCK_TYPE_PSP,
 574         .major = 3,
 575         .minor = 1,
 576         .rev = 0,
 577         .funcs = &psp_ip_funcs,
 578 };
 579
 580 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
 581 {
 582         .type = AMD_IP_BLOCK_TYPE_PSP,
 583         .major = 10,
 584         .minor = 0,
 585         .rev = 0,
 586         .funcs = &psp_ip_funcs,
 587 };