drivers/iommu/intel/debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright © 2018 Intel Corporation.
   4  *
   5  * Authors: Gayatri Kammela <[email protected]>
   6  *          Sohil Mehta <[email protected]>
   7  *          Jacob Pan <[email protected]>
   8  *          Lu Baolu <[email protected]>
   9  */
  10
  11 #include <linux/debugfs.h>
  12 #include <linux/dmar.h>
  13 #include <linux/pci.h>
  14
  15 #include <asm/irq_remapping.h>
  16
  17 #include "iommu.h"
  18 #include "pasid.h"
  19 #include "perf.h"
  20
  21 struct tbl_walk {
  22         u16 bus;
  23         u16 devfn;
  24         u32 pasid;
  25         struct root_entry *rt_entry;
  26         struct context_entry *ctx_entry;
  27         struct pasid_entry *pasid_tbl_entry;
  28 };
  29
  30 struct iommu_regset {
  31         int offset;
  32         const char *regs;
  33 };
  34
  35 #define DEBUG_BUFFER_SIZE       1024
  36 static char debug_buf[DEBUG_BUFFER_SIZE];
  37
  38 #define IOMMU_REGSET_ENTRY(_reg_)                                       \
  39         { DMAR_##_reg_##_REG, __stringify(_reg_) }
  40
  41 static const struct iommu_regset iommu_regs_32[] = {
  42         IOMMU_REGSET_ENTRY(VER),
  43         IOMMU_REGSET_ENTRY(GCMD),
  44         IOMMU_REGSET_ENTRY(GSTS),
  45         IOMMU_REGSET_ENTRY(FSTS),
  46         IOMMU_REGSET_ENTRY(FECTL),
  47         IOMMU_REGSET_ENTRY(FEDATA),
  48         IOMMU_REGSET_ENTRY(FEADDR),
  49         IOMMU_REGSET_ENTRY(FEUADDR),
  50         IOMMU_REGSET_ENTRY(PMEN),
  51         IOMMU_REGSET_ENTRY(PLMBASE),
  52         IOMMU_REGSET_ENTRY(PLMLIMIT),
  53         IOMMU_REGSET_ENTRY(ICS),
  54         IOMMU_REGSET_ENTRY(PRS),
  55         IOMMU_REGSET_ENTRY(PECTL),
  56         IOMMU_REGSET_ENTRY(PEDATA),
  57         IOMMU_REGSET_ENTRY(PEADDR),
  58         IOMMU_REGSET_ENTRY(PEUADDR),
  59 };
  60
  61 static const struct iommu_regset iommu_regs_64[] = {
  62         IOMMU_REGSET_ENTRY(CAP),
  63         IOMMU_REGSET_ENTRY(ECAP),
  64         IOMMU_REGSET_ENTRY(RTADDR),
  65         IOMMU_REGSET_ENTRY(CCMD),
  66         IOMMU_REGSET_ENTRY(AFLOG),
  67         IOMMU_REGSET_ENTRY(PHMBASE),
  68         IOMMU_REGSET_ENTRY(PHMLIMIT),
  69         IOMMU_REGSET_ENTRY(IQH),
  70         IOMMU_REGSET_ENTRY(IQT),
  71         IOMMU_REGSET_ENTRY(IQA),
  72         IOMMU_REGSET_ENTRY(IRTA),
  73         IOMMU_REGSET_ENTRY(PQH),
  74         IOMMU_REGSET_ENTRY(PQT),
  75         IOMMU_REGSET_ENTRY(PQA),
  76         IOMMU_REGSET_ENTRY(MTRRCAP),
  77         IOMMU_REGSET_ENTRY(MTRRDEF),
  78         IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),
  79         IOMMU_REGSET_ENTRY(MTRR_FIX16K_80000),
  80         IOMMU_REGSET_ENTRY(MTRR_FIX16K_A0000),
  81         IOMMU_REGSET_ENTRY(MTRR_FIX4K_C0000),
  82         IOMMU_REGSET_ENTRY(MTRR_FIX4K_C8000),
  83         IOMMU_REGSET_ENTRY(MTRR_FIX4K_D0000),
  84         IOMMU_REGSET_ENTRY(MTRR_FIX4K_D8000),
  85         IOMMU_REGSET_ENTRY(MTRR_FIX4K_E0000),
  86         IOMMU_REGSET_ENTRY(MTRR_FIX4K_E8000),
  87         IOMMU_REGSET_ENTRY(MTRR_FIX4K_F0000),
  88         IOMMU_REGSET_ENTRY(MTRR_FIX4K_F8000),
  89         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE0),
  90         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK0),
  91         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE1),
  92         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK1),
  93         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE2),
  94         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK2),
  95         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE3),
  96         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK3),
  97         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE4),
  98         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK4),
  99         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE5),
 100         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK5),
 101         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE6),
 102         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK6),
 103         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE7),
 104         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK7),
 105         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE8),
 106         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8),
 107         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9),
 108         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9),
 109         IOMMU_REGSET_ENTRY(VCCAP),
 110         IOMMU_REGSET_ENTRY(VCMD),
 111         IOMMU_REGSET_ENTRY(VCRSP),
 112 };
 113
 114 static int iommu_regset_show(struct seq_file *m, void *unused)
 115 {
 116         struct dmar_drhd_unit *drhd;
 117         struct intel_iommu *iommu;
 118         unsigned long flag;
 119         int i, ret = 0;
 120         u64 value;
 121
 122         rcu_read_lock();
 123         for_each_active_iommu(iommu, drhd) {
 124                 if (!drhd->reg_base_addr) {
 125                         seq_puts(m, "IOMMU: Invalid base address\n");
 126                         ret = -EINVAL;
 127                         goto out;
 128                 }
 129
 130                 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
 131                            iommu->name, drhd->reg_base_addr);
 132                 seq_puts(m, "Name\t\t\tOffset\t\tContents\n");
 133                 /*
 134                  * Publish the contents of the 64-bit hardware registers
 135                  * by adding the offset to the pointer (virtual address).
 136                  */
 137                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
 138                 for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) {
 139                         value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);
 140                         seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
 141                                    iommu_regs_32[i].regs, iommu_regs_32[i].offset,
 142                                    value);
 143                 }
 144                 for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) {
 145                         value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
 146                         seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
 147                                    iommu_regs_64[i].regs, iommu_regs_64[i].offset,
 148                                    value);
 149                 }
 150                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 151                 seq_putc(m, '\n');
 152         }
 153 out:
 154         rcu_read_unlock();
 155
 156         return ret;
 157 }
 158 DEFINE_SHOW_ATTRIBUTE(iommu_regset);
 159
 160 static inline void print_tbl_walk(struct seq_file *m)
 161 {
 162         struct tbl_walk *tbl_wlk = m->private;
 163
 164         seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t",
 165                    tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn),
 166                    PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi,
 167                    tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi,
 168                    tbl_wlk->ctx_entry->lo);
 169
 170         /*
 171          * A legacy mode DMAR doesn't support PASID, hence default it to -1
 172          * indicating that it's invalid. Also, default all PASID related fields
 173          * to 0.
 174          */
 175         if (!tbl_wlk->pasid_tbl_entry)
 176                 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1,
 177                            (u64)0, (u64)0, (u64)0);
 178         else
 179                 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n",
 180                            tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2],
 181                            tbl_wlk->pasid_tbl_entry->val[1],
 182                            tbl_wlk->pasid_tbl_entry->val[0]);
 183 }
 184
 185 static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry,
 186                            u16 dir_idx)
 187 {
 188         struct tbl_walk *tbl_wlk = m->private;
 189         u8 tbl_idx;
 190
 191         for (tbl_idx = 0; tbl_idx < PASID_TBL_ENTRIES; tbl_idx++) {
 192                 if (pasid_pte_is_present(tbl_entry)) {
 193                         tbl_wlk->pasid_tbl_entry = tbl_entry;
 194                         tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx;
 195                         print_tbl_walk(m);
 196                 }
 197
 198                 tbl_entry++;
 199         }
 200 }
 201
 202 static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr,
 203                            u16 pasid_dir_size)
 204 {
 205         struct pasid_dir_entry *dir_entry = phys_to_virt(pasid_dir_ptr);
 206         struct pasid_entry *pasid_tbl;
 207         u16 dir_idx;
 208
 209         for (dir_idx = 0; dir_idx < pasid_dir_size; dir_idx++) {
 210                 pasid_tbl = get_pasid_table_from_pde(dir_entry);
 211                 if (pasid_tbl)
 212                         pasid_tbl_walk(m, pasid_tbl, dir_idx);
 213
 214                 dir_entry++;
 215         }
 216 }
 217
 218 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)
 219 {
 220         struct context_entry *context;
 221         u16 devfn, pasid_dir_size;
 222         u64 pasid_dir_ptr;
 223
 224         for (devfn = 0; devfn < 256; devfn++) {
 225                 struct tbl_walk tbl_wlk = {0};
 226
 227                 /*
 228                  * Scalable mode root entry points to upper scalable mode
 229                  * context table and lower scalable mode context table. Each
 230                  * scalable mode context table has 128 context entries where as
 231                  * legacy mode context table has 256 context entries. So in
 232                  * scalable mode, the context entries for former 128 devices are
 233                  * in the lower scalable mode context table, while the latter
 234                  * 128 devices are in the upper scalable mode context table.
 235                  * In scalable mode, when devfn > 127, iommu_context_addr()
 236                  * automatically refers to upper scalable mode context table and
 237                  * hence the caller doesn't have to worry about differences
 238                  * between scalable mode and non scalable mode.
 239                  */
 240                 context = iommu_context_addr(iommu, bus, devfn, 0);
 241                 if (!context)
 242                         return;
 243
 244                 if (!context_present(context))
 245                         continue;
 246
 247                 tbl_wlk.bus = bus;
 248                 tbl_wlk.devfn = devfn;
 249                 tbl_wlk.rt_entry = &iommu->root_entry[bus];
 250                 tbl_wlk.ctx_entry = context;
 251                 m->private = &tbl_wlk;
 252
 253                 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
 254                         pasid_dir_ptr = context->lo & VTD_PAGE_MASK;
 255                         pasid_dir_size = get_pasid_dir_size(context);
 256                         pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size);
 257                         continue;
 258                 }
 259
 260                 print_tbl_walk(m);
 261         }
 262 }
 263
 264 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)
 265 {
 266         u16 bus;
 267
 268         spin_lock(&iommu->lock);
 269         seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,
 270                    (u64)virt_to_phys(iommu->root_entry));
 271         seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n");
 272
 273         /*
 274          * No need to check if the root entry is present or not because
 275          * iommu_context_addr() performs the same check before returning
 276          * context entry.
 277          */
 278         for (bus = 0; bus < 256; bus++)
 279                 ctx_tbl_walk(m, iommu, bus);
 280         spin_unlock(&iommu->lock);
 281 }
 282
 283 static int dmar_translation_struct_show(struct seq_file *m, void *unused)
 284 {
 285         struct dmar_drhd_unit *drhd;
 286         struct intel_iommu *iommu;
 287         u32 sts;
 288
 289         rcu_read_lock();
 290         for_each_active_iommu(iommu, drhd) {
 291                 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
 292                 if (!(sts & DMA_GSTS_TES)) {
 293                         seq_printf(m, "DMA Remapping is not enabled on %s\n",
 294                                    iommu->name);
 295                         continue;
 296                 }
 297                 root_tbl_walk(m, iommu);
 298                 seq_putc(m, '\n');
 299         }
 300         rcu_read_unlock();
 301
 302         return 0;
 303 }
 304 DEFINE_SHOW_ATTRIBUTE(dmar_translation_struct);
 305
 306 static inline unsigned long level_to_directory_size(int level)
 307 {
 308         return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1));
 309 }
 310
 311 static inline void
 312 dump_page_info(struct seq_file *m, unsigned long iova, u64 *path)
 313 {
 314         seq_printf(m, "0x%013lx |\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\n",
 315                    iova >> VTD_PAGE_SHIFT, path[5], path[4],
 316                    path[3], path[2], path[1]);
 317 }
 318
 319 static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde,
 320                                int level, unsigned long start,
 321                                u64 *path)
 322 {
 323         int i;
 324
 325         if (level > 5 || level < 1)
 326                 return;
 327
 328         for (i = 0; i < BIT_ULL(VTD_STRIDE_SHIFT);
 329                         i++, pde++, start += level_to_directory_size(level)) {
 330                 if (!dma_pte_present(pde))
 331                         continue;
 332
 333                 path[level] = pde->val;
 334                 if (dma_pte_superpage(pde) || level == 1)
 335                         dump_page_info(m, start, path);
 336                 else
 337                         pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)),
 338                                            level - 1, start, path);
 339                 path[level] = 0;
 340         }
 341 }
 342
 343 static int __show_device_domain_translation(struct device *dev, void *data)
 344 {
 345         struct dmar_domain *domain;
 346         struct seq_file *m = data;
 347         u64 path[6] = { 0 };
 348
 349         domain = to_dmar_domain(iommu_get_domain_for_dev(dev));
 350         if (!domain)
 351                 return 0;
 352
 353         seq_printf(m, "Device %s @0x%llx\n", dev_name(dev),
 354                    (u64)virt_to_phys(domain->pgd));
 355         seq_puts(m, "IOVA_PFN\t\tPML5E\t\t\tPML4E\t\t\tPDPE\t\t\tPDE\t\t\tPTE\n");
 356
 357         pgtable_walk_level(m, domain->pgd, domain->agaw + 2, 0, path);
 358         seq_putc(m, '\n');
 359
 360         /* Don't iterate */
 361         return 1;
 362 }
 363
 364 static int show_device_domain_translation(struct device *dev, void *data)
 365 {
 366         struct iommu_group *group;
 367
 368         group = iommu_group_get(dev);
 369         if (group) {
 370                 /*
 371                  * The group->mutex is held across the callback, which will
 372                  * block calls to iommu_attach/detach_group/device. Hence,
 373                  * the domain of the device will not change during traversal.
 374                  *
 375                  * All devices in an iommu group share a single domain, hence
 376                  * we only dump the domain of the first device. Even though,
 377                  * this code still possibly races with the iommu_unmap()
 378                  * interface. This could be solved by RCU-freeing the page
 379                  * table pages in the iommu_unmap() path.
 380                  */
 381                 iommu_group_for_each_dev(group, data,
 382                                          __show_device_domain_translation);
 383                 iommu_group_put(group);
 384         }
 385
 386         return 0;
 387 }
 388
 389 static int domain_translation_struct_show(struct seq_file *m, void *unused)
 390 {
 391         return bus_for_each_dev(&pci_bus_type, NULL, m,
 392                                 show_device_domain_translation);
 393 }
 394 DEFINE_SHOW_ATTRIBUTE(domain_translation_struct);
 395
 396 static void invalidation_queue_entry_show(struct seq_file *m,
 397                                           struct intel_iommu *iommu)
 398 {
 399         int index, shift = qi_shift(iommu);
 400         struct qi_desc *desc;
 401         int offset;
 402
 403         if (ecap_smts(iommu->ecap))
 404                 seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tqw2\t\t\tqw3\t\t\tstatus\n");
 405         else
 406                 seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tstatus\n");
 407
 408         for (index = 0; index < QI_LENGTH; index++) {
 409                 offset = index << shift;
 410                 desc = iommu->qi->desc + offset;
 411                 if (ecap_smts(iommu->ecap))
 412                         seq_printf(m, "%5d\t%016llx\t%016llx\t%016llx\t%016llx\t%016x\n",
 413                                    index, desc->qw0, desc->qw1,
 414                                    desc->qw2, desc->qw3,
 415                                    iommu->qi->desc_status[index]);
 416                 else
 417                         seq_printf(m, "%5d\t%016llx\t%016llx\t%016x\n",
 418                                    index, desc->qw0, desc->qw1,
 419                                    iommu->qi->desc_status[index]);
 420         }
 421 }
 422
 423 static int invalidation_queue_show(struct seq_file *m, void *unused)
 424 {
 425         struct dmar_drhd_unit *drhd;
 426         struct intel_iommu *iommu;
 427         unsigned long flags;
 428         struct q_inval *qi;
 429         int shift;
 430
 431         rcu_read_lock();
 432         for_each_active_iommu(iommu, drhd) {
 433                 qi = iommu->qi;
 434                 shift = qi_shift(iommu);
 435
 436                 if (!qi || !ecap_qis(iommu->ecap))
 437                         continue;
 438
 439                 seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);
 440
 441                 raw_spin_lock_irqsave(&qi->q_lock, flags);
 442                 seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n",
 443                            (u64)virt_to_phys(qi->desc),
 444                            dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,
 445                            dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);
 446                 invalidation_queue_entry_show(m, iommu);
 447                 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
 448                 seq_putc(m, '\n');
 449         }
 450         rcu_read_unlock();
 451
 452         return 0;
 453 }
 454 DEFINE_SHOW_ATTRIBUTE(invalidation_queue);
 455
 456 #ifdef CONFIG_IRQ_REMAP
 457 static void ir_tbl_remap_entry_show(struct seq_file *m,
 458                                     struct intel_iommu *iommu)
 459 {
 460         struct irte *ri_entry;
 461         unsigned long flags;
 462         int idx;
 463
 464         seq_puts(m, " Entry SrcID   DstID    Vct IRTE_high\t\tIRTE_low\n");
 465
 466         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 467         for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
 468                 ri_entry = &iommu->ir_table->base[idx];
 469                 if (!ri_entry->present || ri_entry->p_pst)
 470                         continue;
 471
 472                 seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x  %016llx\t%016llx\n",
 473                            idx, PCI_BUS_NUM(ri_entry->sid),
 474                            PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid),
 475                            ri_entry->dest_id, ri_entry->vector,
 476                            ri_entry->high, ri_entry->low);
 477         }
 478         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 479 }
 480
 481 static void ir_tbl_posted_entry_show(struct seq_file *m,
 482                                      struct intel_iommu *iommu)
 483 {
 484         struct irte *pi_entry;
 485         unsigned long flags;
 486         int idx;
 487
 488         seq_puts(m, " Entry SrcID   PDA_high PDA_low  Vct IRTE_high\t\tIRTE_low\n");
 489
 490         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 491         for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
 492                 pi_entry = &iommu->ir_table->base[idx];
 493                 if (!pi_entry->present || !pi_entry->p_pst)
 494                         continue;
 495
 496                 seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x  %016llx\t%016llx\n",
 497                            idx, PCI_BUS_NUM(pi_entry->sid),
 498                            PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid),
 499                            pi_entry->pda_h, pi_entry->pda_l << 6,
 500                            pi_entry->vector, pi_entry->high,
 501                            pi_entry->low);
 502         }
 503         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 504 }
 505
 506 /*
 507  * For active IOMMUs go through the Interrupt remapping
 508  * table and print valid entries in a table format for
 509  * Remapped and Posted Interrupts.
 510  */
 511 static int ir_translation_struct_show(struct seq_file *m, void *unused)
 512 {
 513         struct dmar_drhd_unit *drhd;
 514         struct intel_iommu *iommu;
 515         u64 irta;
 516         u32 sts;
 517
 518         rcu_read_lock();
 519         for_each_active_iommu(iommu, drhd) {
 520                 if (!ecap_ir_support(iommu->ecap))
 521                         continue;
 522
 523                 seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
 524                            iommu->name);
 525
 526                 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
 527                 if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {
 528                         irta = virt_to_phys(iommu->ir_table->base);
 529                         seq_printf(m, " IR table address:%llx\n", irta);
 530                         ir_tbl_remap_entry_show(m, iommu);
 531                 } else {
 532                         seq_puts(m, "Interrupt Remapping is not enabled\n");
 533                 }
 534                 seq_putc(m, '\n');
 535         }
 536
 537         seq_puts(m, "****\n\n");
 538
 539         for_each_active_iommu(iommu, drhd) {
 540                 if (!cap_pi_support(iommu->cap))
 541                         continue;
 542
 543                 seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",
 544                            iommu->name);
 545
 546                 if (iommu->ir_table) {
 547                         irta = virt_to_phys(iommu->ir_table->base);
 548                         seq_printf(m, " IR table address:%llx\n", irta);
 549                         ir_tbl_posted_entry_show(m, iommu);
 550                 } else {
 551                         seq_puts(m, "Interrupt Remapping is not enabled\n");
 552                 }
 553                 seq_putc(m, '\n');
 554         }
 555         rcu_read_unlock();
 556
 557         return 0;
 558 }
 559 DEFINE_SHOW_ATTRIBUTE(ir_translation_struct);
 560 #endif
 561
 562 static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu,
 563                              struct dmar_drhd_unit *drhd)
 564 {
 565         int ret;
 566
 567         seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
 568                    iommu->name, drhd->reg_base_addr);
 569
 570         ret = dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);
 571         if (ret < 0)
 572                 seq_puts(m, "Failed to get latency snapshot");
 573         else
 574                 seq_puts(m, debug_buf);
 575         seq_puts(m, "\n");
 576 }
 577
 578 static int latency_show(struct seq_file *m, void *v)
 579 {
 580         struct dmar_drhd_unit *drhd;
 581         struct intel_iommu *iommu;
 582
 583         rcu_read_lock();
 584         for_each_active_iommu(iommu, drhd)
 585                 latency_show_one(m, iommu, drhd);
 586         rcu_read_unlock();
 587
 588         return 0;
 589 }
 590
 591 static int dmar_perf_latency_open(struct inode *inode, struct file *filp)
 592 {
 593         return single_open(filp, latency_show, NULL);
 594 }
 595
 596 static ssize_t dmar_perf_latency_write(struct file *filp,
 597                                        const char __user *ubuf,
 598                                        size_t cnt, loff_t *ppos)
 599 {
 600         struct dmar_drhd_unit *drhd;
 601         struct intel_iommu *iommu;
 602         int counting;
 603         char buf[64];
 604
 605         if (cnt > 63)
 606                 cnt = 63;
 607
 608         if (copy_from_user(&buf, ubuf, cnt))
 609                 return -EFAULT;
 610
 611         buf[cnt] = 0;
 612
 613         if (kstrtoint(buf, 0, &counting))
 614                 return -EINVAL;
 615
 616         switch (counting) {
 617         case 0:
 618                 rcu_read_lock();
 619                 for_each_active_iommu(iommu, drhd) {
 620                         dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB);
 621                         dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB);
 622                         dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC);
 623                         dmar_latency_disable(iommu, DMAR_LATENCY_PRQ);
 624                 }
 625                 rcu_read_unlock();
 626                 break;
 627         case 1:
 628                 rcu_read_lock();
 629                 for_each_active_iommu(iommu, drhd)
 630                         dmar_latency_enable(iommu, DMAR_LATENCY_INV_IOTLB);
 631                 rcu_read_unlock();
 632                 break;
 633         case 2:
 634                 rcu_read_lock();
 635                 for_each_active_iommu(iommu, drhd)
 636                         dmar_latency_enable(iommu, DMAR_LATENCY_INV_DEVTLB);
 637                 rcu_read_unlock();
 638                 break;
 639         case 3:
 640                 rcu_read_lock();
 641                 for_each_active_iommu(iommu, drhd)
 642                         dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC);
 643                 rcu_read_unlock();
 644                 break;
 645         case 4:
 646                 rcu_read_lock();
 647                 for_each_active_iommu(iommu, drhd)
 648                         dmar_latency_enable(iommu, DMAR_LATENCY_PRQ);
 649                 rcu_read_unlock();
 650                 break;
 651         default:
 652                 return -EINVAL;
 653         }
 654
 655         *ppos += cnt;
 656         return cnt;
 657 }
 658
 659 static const struct file_operations dmar_perf_latency_fops = {
 660         .open           = dmar_perf_latency_open,
 661         .write          = dmar_perf_latency_write,
 662         .read           = seq_read,
 663         .llseek         = seq_lseek,
 664         .release        = single_release,
 665 };
 666
 667 void __init intel_iommu_debugfs_init(void)
 668 {
 669         struct dentry *intel_iommu_debug = debugfs_create_dir("intel",
 670                                                 iommu_debugfs_dir);
 671
 672         debugfs_create_file("iommu_regset", 0444, intel_iommu_debug, NULL,
 673                             &iommu_regset_fops);
 674         debugfs_create_file("dmar_translation_struct", 0444, intel_iommu_debug,
 675                             NULL, &dmar_translation_struct_fops);
 676         debugfs_create_file("domain_translation_struct", 0444,
 677                             intel_iommu_debug, NULL,
 678                             &domain_translation_struct_fops);
 679         debugfs_create_file("invalidation_queue", 0444, intel_iommu_debug,
 680                             NULL, &invalidation_queue_fops);
 681 #ifdef CONFIG_IRQ_REMAP
 682         debugfs_create_file("ir_translation_struct", 0444, intel_iommu_debug,
 683                             NULL, &ir_translation_struct_fops);
 684 #endif
 685         debugfs_create_file("dmar_perf_latency", 0644, intel_iommu_debug,
 686                             NULL, &dmar_perf_latency_fops);
 687 }