drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "uvd/uvd_7_0_offset.h"
  41 #include "gc/gc_9_0_offset.h"
  42 #include "gc/gc_9_0_sh_mask.h"
  43 #include "sdma0/sdma0_4_0_offset.h"
  44 #include "sdma1/sdma1_4_0_offset.h"
  45 #include "nbio/nbio_7_0_default.h"
  46 #include "nbio/nbio_7_0_offset.h"
  47 #include "nbio/nbio_7_0_sh_mask.h"
  48 #include "nbio/nbio_7_0_smn.h"
  49 #include "mp/mp_9_0_offset.h"
  50
  51 #include "soc15.h"
  52 #include "soc15_common.h"
  53 #include "gfx_v9_0.h"
  54 #include "gmc_v9_0.h"
  55 #include "gfxhub_v1_0.h"
  56 #include "mmhub_v1_0.h"
  57 #include "df_v1_7.h"
  58 #include "df_v3_6.h"
  59 #include "nbio_v6_1.h"
  60 #include "nbio_v7_0.h"
  61 #include "nbio_v7_4.h"
  62 #include "hdp_v4_0.h"
  63 #include "vega10_ih.h"
  64 #include "vega20_ih.h"
  65 #include "navi10_ih.h"
  66 #include "sdma_v4_0.h"
  67 #include "uvd_v7_0.h"
  68 #include "vce_v4_0.h"
  69 #include "vcn_v1_0.h"
  70 #include "vcn_v2_0.h"
  71 #include "jpeg_v2_0.h"
  72 #include "vcn_v2_5.h"
  73 #include "jpeg_v2_5.h"
  74 #include "smuio_v9_0.h"
  75 #include "smuio_v11_0.h"
  76 #include "smuio_v13_0.h"
  77 #include "amdgpu_vkms.h"
  78 #include "mxgpu_ai.h"
  79 #include "amdgpu_ras.h"
  80 #include "amdgpu_xgmi.h"
  81 #include <uapi/linux/kfd_ioctl.h>
  82
  83 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  87
  88 static const struct amd_ip_funcs soc15_common_ip_funcs;
  89
  90 /* Vega, Raven, Arcturus */
  91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
  92 {
  93         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  94         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  95 };
  96
  97 static const struct amdgpu_video_codecs vega_video_codecs_encode =
  98 {
  99         .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
 100         .codec_array = vega_video_codecs_encode_array,
 101 };
 102
 103 /* Vega */
 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
 105 {
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
 111         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 112 };
 113
 114 static const struct amdgpu_video_codecs vega_video_codecs_decode =
 115 {
 116         .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
 117         .codec_array = vega_video_codecs_decode_array,
 118 };
 119
 120 /* Raven */
 121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
 122 {
 123         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 124         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 125         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 126         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 127         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
 128         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 129         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
 130 };
 131
 132 static const struct amdgpu_video_codecs rv_video_codecs_decode =
 133 {
 134         .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
 135         .codec_array = rv_video_codecs_decode_array,
 136 };
 137
 138 /* Renoir, Arcturus */
 139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
 140 {
 141         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 142         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 143         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 144         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 145         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 146         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 147         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 148 };
 149
 150 static const struct amdgpu_video_codecs rn_video_codecs_decode =
 151 {
 152         .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
 153         .codec_array = rn_video_codecs_decode_array,
 154 };
 155
 156 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
 157                                     const struct amdgpu_video_codecs **codecs)
 158 {
 159         if (adev->ip_versions[VCE_HWIP][0]) {
 160                 switch (adev->ip_versions[VCE_HWIP][0]) {
 161                 case IP_VERSION(4, 0, 0):
 162                 case IP_VERSION(4, 1, 0):
 163                         if (encode)
 164                                 *codecs = &vega_video_codecs_encode;
 165                         else
 166                                 *codecs = &vega_video_codecs_decode;
 167                         return 0;
 168                 default:
 169                         return -EINVAL;
 170                 }
 171         } else {
 172                 switch (adev->ip_versions[UVD_HWIP][0]) {
 173                 case IP_VERSION(1, 0, 0):
 174                 case IP_VERSION(1, 0, 1):
 175                         if (encode)
 176                                 *codecs = &vega_video_codecs_encode;
 177                         else
 178                                 *codecs = &rv_video_codecs_decode;
 179                         return 0;
 180                 case IP_VERSION(2, 5, 0):
 181                 case IP_VERSION(2, 6, 0):
 182                 case IP_VERSION(2, 2, 0):
 183                         if (encode)
 184                                 *codecs = &vega_video_codecs_encode;
 185                         else
 186                                 *codecs = &rn_video_codecs_decode;
 187                         return 0;
 188                 default:
 189                         return -EINVAL;
 190                 }
 191         }
 192 }
 193
 194 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 195 {
 196         unsigned long flags, address, data;
 197         u32 r;
 198
 199         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 200         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 201
 202         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 203         WREG32(address, ((reg) & 0x1ff));
 204         r = RREG32(data);
 205         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 206         return r;
 207 }
 208
 209 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 210 {
 211         unsigned long flags, address, data;
 212
 213         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 214         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 215
 216         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 217         WREG32(address, ((reg) & 0x1ff));
 218         WREG32(data, (v));
 219         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 220 }
 221
 222 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 223 {
 224         unsigned long flags, address, data;
 225         u32 r;
 226
 227         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 228         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 229
 230         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 231         WREG32(address, (reg));
 232         r = RREG32(data);
 233         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 234         return r;
 235 }
 236
 237 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 238 {
 239         unsigned long flags, address, data;
 240
 241         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 242         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 243
 244         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 245         WREG32(address, (reg));
 246         WREG32(data, (v));
 247         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 248 }
 249
 250 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 251 {
 252         unsigned long flags;
 253         u32 r;
 254
 255         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 256         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 257         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 258         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 259         return r;
 260 }
 261
 262 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 263 {
 264         unsigned long flags;
 265
 266         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 267         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 268         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 269         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 270 }
 271
 272 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 273 {
 274         unsigned long flags;
 275         u32 r;
 276
 277         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 278         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 279         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 280         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 281         return r;
 282 }
 283
 284 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 285 {
 286         unsigned long flags;
 287
 288         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 289         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 290         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 291         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 292 }
 293
 294 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 295 {
 296         return adev->nbio.funcs->get_memsize(adev);
 297 }
 298
 299 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 300 {
 301         u32 reference_clock = adev->clock.spll.reference_freq;
 302
 303         if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
 304             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
 305                 return 10000;
 306         if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
 307             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
 308                 return reference_clock / 4;
 309
 310         return reference_clock;
 311 }
 312
 313
 314 void soc15_grbm_select(struct amdgpu_device *adev,
 315                      u32 me, u32 pipe, u32 queue, u32 vmid)
 316 {
 317         u32 grbm_gfx_cntl = 0;
 318         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 319         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 320         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 321         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 322
 323         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 324 }
 325
 326 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 327 {
 328         /* todo */
 329 }
 330
 331 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 332 {
 333         /* todo */
 334         return false;
 335 }
 336
 337 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 338         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 339         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 340         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 341         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 342         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 343         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 344         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 345         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 346         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 347         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 348         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 349         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 350         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 351         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 352         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 353         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 354         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 355         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 356         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 357         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 358 };
 359
 360 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 361                                          u32 sh_num, u32 reg_offset)
 362 {
 363         uint32_t val;
 364
 365         mutex_lock(&adev->grbm_idx_mutex);
 366         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 367                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 368
 369         val = RREG32(reg_offset);
 370
 371         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 372                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 373         mutex_unlock(&adev->grbm_idx_mutex);
 374         return val;
 375 }
 376
 377 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 378                                          bool indexed, u32 se_num,
 379                                          u32 sh_num, u32 reg_offset)
 380 {
 381         if (indexed) {
 382                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 383         } else {
 384                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 385                         return adev->gfx.config.gb_addr_config;
 386                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 387                         return adev->gfx.config.db_debug2;
 388                 return RREG32(reg_offset);
 389         }
 390 }
 391
 392 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 393                             u32 sh_num, u32 reg_offset, u32 *value)
 394 {
 395         uint32_t i;
 396         struct soc15_allowed_register_entry  *en;
 397
 398         *value = 0;
 399         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 400                 en = &soc15_allowed_read_registers[i];
 401                 if (!adev->reg_offset[en->hwip][en->inst])
 402                         continue;
 403                 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 404                                         + en->reg_offset))
 405                         continue;
 406
 407                 *value = soc15_get_register_value(adev,
 408                                                   soc15_allowed_read_registers[i].grbm_indexed,
 409                                                   se_num, sh_num, reg_offset);
 410                 return 0;
 411         }
 412         return -EINVAL;
 413 }
 414
 415
 416 /**
 417  * soc15_program_register_sequence - program an array of registers.
 418  *
 419  * @adev: amdgpu_device pointer
 420  * @regs: pointer to the register array
 421  * @array_size: size of the register array
 422  *
 423  * Programs an array or registers with and and or masks.
 424  * This is a helper for setting golden registers.
 425  */
 426
 427 void soc15_program_register_sequence(struct amdgpu_device *adev,
 428                                              const struct soc15_reg_golden *regs,
 429                                              const u32 array_size)
 430 {
 431         const struct soc15_reg_golden *entry;
 432         u32 tmp, reg;
 433         int i;
 434
 435         for (i = 0; i < array_size; ++i) {
 436                 entry = &regs[i];
 437                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 438
 439                 if (entry->and_mask == 0xffffffff) {
 440                         tmp = entry->or_mask;
 441                 } else {
 442                         tmp = (entry->hwip == GC_HWIP) ?
 443                                 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
 444
 445                         tmp &= ~(entry->and_mask);
 446                         tmp |= (entry->or_mask & entry->and_mask);
 447                 }
 448
 449                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 450                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 451                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 452                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 453                         WREG32_RLC(reg, tmp);
 454                 else
 455                         (entry->hwip == GC_HWIP) ?
 456                                 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
 457
 458         }
 459
 460 }
 461
 462 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 463 {
 464         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 465         int ret = 0;
 466
 467         /* avoid NBIF got stuck when do RAS recovery in BACO reset */
 468         if (ras && adev->ras_enabled)
 469                 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 470
 471         ret = amdgpu_dpm_baco_reset(adev);
 472         if (ret)
 473                 return ret;
 474
 475         /* re-enable doorbell interrupt after BACO exit */
 476         if (ras && adev->ras_enabled)
 477                 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 478
 479         return 0;
 480 }
 481
 482 static enum amd_reset_method
 483 soc15_asic_reset_method(struct amdgpu_device *adev)
 484 {
 485         bool baco_reset = false;
 486         bool connected_to_cpu = false;
 487         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 488
 489         if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
 490                 connected_to_cpu = true;
 491
 492         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 493             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 494             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 495             amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
 496                 /* If connected to cpu, driver only support mode2 */
 497                 if (connected_to_cpu)
 498                         return AMD_RESET_METHOD_MODE2;
 499                 return amdgpu_reset_method;
 500         }
 501
 502         if (amdgpu_reset_method != -1)
 503                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 504                                   amdgpu_reset_method);
 505
 506         switch (adev->ip_versions[MP1_HWIP][0]) {
 507         case IP_VERSION(10, 0, 0):
 508         case IP_VERSION(10, 0, 1):
 509         case IP_VERSION(12, 0, 0):
 510         case IP_VERSION(12, 0, 1):
 511                 return AMD_RESET_METHOD_MODE2;
 512         case IP_VERSION(9, 0, 0):
 513         case IP_VERSION(11, 0, 2):
 514                 if (adev->asic_type == CHIP_VEGA20) {
 515                         if (adev->psp.sos.fw_version >= 0x80067)
 516                                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 517                         /*
 518                          * 1. PMFW version > 0x284300: all cases use baco
 519                          * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
 520                          */
 521                         if (ras && adev->ras_enabled &&
 522                             adev->pm.fw_version <= 0x283400)
 523                                 baco_reset = false;
 524                 } else {
 525                         baco_reset = amdgpu_dpm_is_baco_supported(adev);
 526                 }
 527                 break;
 528         case IP_VERSION(13, 0, 2):
 529                  /*
 530                  * 1.connected to cpu: driver issue mode2 reset
 531                  * 2.discret gpu: driver issue mode1 reset
 532                  */
 533                 if (connected_to_cpu)
 534                         return AMD_RESET_METHOD_MODE2;
 535                 break;
 536         default:
 537                 break;
 538         }
 539
 540         if (baco_reset)
 541                 return AMD_RESET_METHOD_BACO;
 542         else
 543                 return AMD_RESET_METHOD_MODE1;
 544 }
 545
 546 static int soc15_asic_reset(struct amdgpu_device *adev)
 547 {
 548         /* original raven doesn't have full asic reset */
 549         if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
 550             (adev->apu_flags & AMD_APU_IS_RAVEN2))
 551                 return 0;
 552
 553         switch (soc15_asic_reset_method(adev)) {
 554         case AMD_RESET_METHOD_PCI:
 555                 dev_info(adev->dev, "PCI reset\n");
 556                 return amdgpu_device_pci_reset(adev);
 557         case AMD_RESET_METHOD_BACO:
 558                 dev_info(adev->dev, "BACO reset\n");
 559                 return soc15_asic_baco_reset(adev);
 560         case AMD_RESET_METHOD_MODE2:
 561                 dev_info(adev->dev, "MODE2 reset\n");
 562                 return amdgpu_dpm_mode2_reset(adev);
 563         default:
 564                 dev_info(adev->dev, "MODE1 reset\n");
 565                 return amdgpu_device_mode1_reset(adev);
 566         }
 567 }
 568
 569 static bool soc15_supports_baco(struct amdgpu_device *adev)
 570 {
 571         switch (adev->ip_versions[MP1_HWIP][0]) {
 572         case IP_VERSION(9, 0, 0):
 573         case IP_VERSION(11, 0, 2):
 574                 if (adev->asic_type == CHIP_VEGA20) {
 575                         if (adev->psp.sos.fw_version >= 0x80067)
 576                                 return amdgpu_dpm_is_baco_supported(adev);
 577                         return false;
 578                 } else {
 579                         return amdgpu_dpm_is_baco_supported(adev);
 580                 }
 581                 break;
 582         default:
 583                 return false;
 584         }
 585 }
 586
 587 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 588                         u32 cntl_reg, u32 status_reg)
 589 {
 590         return 0;
 591 }*/
 592
 593 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 594 {
 595         /*int r;
 596
 597         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 598         if (r)
 599                 return r;
 600
 601         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 602         */
 603         return 0;
 604 }
 605
 606 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 607 {
 608         /* todo */
 609
 610         return 0;
 611 }
 612
 613 static void soc15_program_aspm(struct amdgpu_device *adev)
 614 {
 615         if (!amdgpu_device_should_use_aspm(adev))
 616                 return;
 617
 618         if (!(adev->flags & AMD_IS_APU) &&
 619             (adev->nbio.funcs->program_aspm))
 620                 adev->nbio.funcs->program_aspm(adev);
 621 }
 622
 623 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 624                                            bool enable)
 625 {
 626         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 627         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 628 }
 629
 630 const struct amdgpu_ip_block_version vega10_common_ip_block =
 631 {
 632         .type = AMD_IP_BLOCK_TYPE_COMMON,
 633         .major = 2,
 634         .minor = 0,
 635         .rev = 0,
 636         .funcs = &soc15_common_ip_funcs,
 637 };
 638
 639 static void soc15_reg_base_init(struct amdgpu_device *adev)
 640 {
 641         /* Set IP register base before any HW register access */
 642         switch (adev->asic_type) {
 643         case CHIP_VEGA10:
 644         case CHIP_VEGA12:
 645         case CHIP_RAVEN:
 646         case CHIP_RENOIR:
 647                 vega10_reg_base_init(adev);
 648                 break;
 649         case CHIP_VEGA20:
 650                 vega20_reg_base_init(adev);
 651                 break;
 652         case CHIP_ARCTURUS:
 653                 arct_reg_base_init(adev);
 654                 break;
 655         case CHIP_ALDEBARAN:
 656                 aldebaran_reg_base_init(adev);
 657                 break;
 658         default:
 659                 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
 660                 break;
 661         }
 662 }
 663
 664 void soc15_set_virt_ops(struct amdgpu_device *adev)
 665 {
 666         adev->virt.ops = &xgpu_ai_virt_ops;
 667
 668         /* init soc15 reg base early enough so we can
 669          * request request full access for sriov before
 670          * set_ip_blocks. */
 671         soc15_reg_base_init(adev);
 672 }
 673
 674 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 675 {
 676         /* change this when we implement soft reset */
 677         return true;
 678 }
 679
 680 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 681                                  uint64_t *count1)
 682 {
 683         uint32_t perfctr = 0;
 684         uint64_t cnt0_of, cnt1_of;
 685         int tmp;
 686
 687         /* This reports 0 on APUs, so return to avoid writing/reading registers
 688          * that may or may not be different from their GPU counterparts
 689          */
 690         if (adev->flags & AMD_IS_APU)
 691                 return;
 692
 693         /* Set the 2 events that we wish to watch, defined above */
 694         /* Reg 40 is # received msgs */
 695         /* Reg 104 is # of posted requests sent */
 696         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 697         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 698
 699         /* Write to enable desired perf counters */
 700         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 701         /* Zero out and enable the perf counters
 702          * Write 0x5:
 703          * Bit 0 = Start all counters(1)
 704          * Bit 2 = Global counter reset enable(1)
 705          */
 706         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 707
 708         msleep(1000);
 709
 710         /* Load the shadow and disable the perf counters
 711          * Write 0x2:
 712          * Bit 0 = Stop counters(0)
 713          * Bit 1 = Load the shadow counters(1)
 714          */
 715         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 716
 717         /* Read register values to get any >32bit overflow */
 718         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 719         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 720         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 721
 722         /* Get the values and add the overflow */
 723         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 724         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 725 }
 726
 727 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 728                                  uint64_t *count1)
 729 {
 730         uint32_t perfctr = 0;
 731         uint64_t cnt0_of, cnt1_of;
 732         int tmp;
 733
 734         /* This reports 0 on APUs, so return to avoid writing/reading registers
 735          * that may or may not be different from their GPU counterparts
 736          */
 737         if (adev->flags & AMD_IS_APU)
 738                 return;
 739
 740         /* Set the 2 events that we wish to watch, defined above */
 741         /* Reg 40 is # received msgs */
 742         /* Reg 108 is # of posted requests sent on VG20 */
 743         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 744                                 EVENT0_SEL, 40);
 745         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 746                                 EVENT1_SEL, 108);
 747
 748         /* Write to enable desired perf counters */
 749         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
 750         /* Zero out and enable the perf counters
 751          * Write 0x5:
 752          * Bit 0 = Start all counters(1)
 753          * Bit 2 = Global counter reset enable(1)
 754          */
 755         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 756
 757         msleep(1000);
 758
 759         /* Load the shadow and disable the perf counters
 760          * Write 0x2:
 761          * Bit 0 = Stop counters(0)
 762          * Bit 1 = Load the shadow counters(1)
 763          */
 764         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 765
 766         /* Read register values to get any >32bit overflow */
 767         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
 768         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
 769         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
 770
 771         /* Get the values and add the overflow */
 772         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
 773         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
 774 }
 775
 776 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 777 {
 778         u32 sol_reg;
 779
 780         /* CP hangs in IGT reloading test on RN, reset to WA */
 781         if (adev->asic_type == CHIP_RENOIR)
 782                 return true;
 783
 784         /* Just return false for soc15 GPUs.  Reset does not seem to
 785          * be necessary.
 786          */
 787         if (!amdgpu_passthrough(adev))
 788                 return false;
 789
 790         if (adev->flags & AMD_IS_APU)
 791                 return false;
 792
 793         /* Check sOS sign of life register to confirm sys driver and sOS
 794          * are already been loaded.
 795          */
 796         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 797         if (sol_reg)
 798                 return true;
 799
 800         return false;
 801 }
 802
 803 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 804 {
 805         uint64_t nak_r, nak_g;
 806
 807         /* Get the number of NAKs received and generated */
 808         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 809         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 810
 811         /* Add the total number of NAKs, i.e the number of replays */
 812         return (nak_r + nak_g);
 813 }
 814
 815 static void soc15_pre_asic_init(struct amdgpu_device *adev)
 816 {
 817         gmc_v9_0_restore_registers(adev);
 818 }
 819
 820 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 821 {
 822         .read_disabled_bios = &soc15_read_disabled_bios,
 823         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 824         .read_register = &soc15_read_register,
 825         .reset = &soc15_asic_reset,
 826         .reset_method = &soc15_asic_reset_method,
 827         .set_vga_state = &soc15_vga_set_state,
 828         .get_xclk = &soc15_get_xclk,
 829         .set_uvd_clocks = &soc15_set_uvd_clocks,
 830         .set_vce_clocks = &soc15_set_vce_clocks,
 831         .get_config_memsize = &soc15_get_config_memsize,
 832         .need_full_reset = &soc15_need_full_reset,
 833         .init_doorbell_index = &vega10_doorbell_index_init,
 834         .get_pcie_usage = &soc15_get_pcie_usage,
 835         .need_reset_on_init = &soc15_need_reset_on_init,
 836         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 837         .supports_baco = &soc15_supports_baco,
 838         .pre_asic_init = &soc15_pre_asic_init,
 839         .query_video_codecs = &soc15_query_video_codecs,
 840 };
 841
 842 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 843 {
 844         .read_disabled_bios = &soc15_read_disabled_bios,
 845         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 846         .read_register = &soc15_read_register,
 847         .reset = &soc15_asic_reset,
 848         .reset_method = &soc15_asic_reset_method,
 849         .set_vga_state = &soc15_vga_set_state,
 850         .get_xclk = &soc15_get_xclk,
 851         .set_uvd_clocks = &soc15_set_uvd_clocks,
 852         .set_vce_clocks = &soc15_set_vce_clocks,
 853         .get_config_memsize = &soc15_get_config_memsize,
 854         .need_full_reset = &soc15_need_full_reset,
 855         .init_doorbell_index = &vega20_doorbell_index_init,
 856         .get_pcie_usage = &vega20_get_pcie_usage,
 857         .need_reset_on_init = &soc15_need_reset_on_init,
 858         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 859         .supports_baco = &soc15_supports_baco,
 860         .pre_asic_init = &soc15_pre_asic_init,
 861         .query_video_codecs = &soc15_query_video_codecs,
 862 };
 863
 864 static int soc15_common_early_init(void *handle)
 865 {
 866 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 867         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 868
 869         if (!amdgpu_sriov_vf(adev)) {
 870                 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 871                 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 872         }
 873         adev->smc_rreg = NULL;
 874         adev->smc_wreg = NULL;
 875         adev->pcie_rreg = &amdgpu_device_indirect_rreg;
 876         adev->pcie_wreg = &amdgpu_device_indirect_wreg;
 877         adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
 878         adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
 879         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 880         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 881         adev->didt_rreg = &soc15_didt_rreg;
 882         adev->didt_wreg = &soc15_didt_wreg;
 883         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 884         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 885         adev->se_cac_rreg = &soc15_se_cac_rreg;
 886         adev->se_cac_wreg = &soc15_se_cac_wreg;
 887
 888         adev->rev_id = amdgpu_device_get_rev_id(adev);
 889         adev->external_rev_id = 0xFF;
 890         /* TODO: split the GC and PG flags based on the relevant IP version for which
 891          * they are relevant.
 892          */
 893         switch (adev->ip_versions[GC_HWIP][0]) {
 894         case IP_VERSION(9, 0, 1):
 895                 adev->asic_funcs = &soc15_asic_funcs;
 896                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 897                         AMD_CG_SUPPORT_GFX_MGLS |
 898                         AMD_CG_SUPPORT_GFX_RLC_LS |
 899                         AMD_CG_SUPPORT_GFX_CP_LS |
 900                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 901                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 902                         AMD_CG_SUPPORT_GFX_CGCG |
 903                         AMD_CG_SUPPORT_GFX_CGLS |
 904                         AMD_CG_SUPPORT_BIF_MGCG |
 905                         AMD_CG_SUPPORT_BIF_LS |
 906                         AMD_CG_SUPPORT_HDP_LS |
 907                         AMD_CG_SUPPORT_DRM_MGCG |
 908                         AMD_CG_SUPPORT_DRM_LS |
 909                         AMD_CG_SUPPORT_ROM_MGCG |
 910                         AMD_CG_SUPPORT_DF_MGCG |
 911                         AMD_CG_SUPPORT_SDMA_MGCG |
 912                         AMD_CG_SUPPORT_SDMA_LS |
 913                         AMD_CG_SUPPORT_MC_MGCG |
 914                         AMD_CG_SUPPORT_MC_LS;
 915                 adev->pg_flags = 0;
 916                 adev->external_rev_id = 0x1;
 917                 break;
 918         case IP_VERSION(9, 2, 1):
 919                 adev->asic_funcs = &soc15_asic_funcs;
 920                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 921                         AMD_CG_SUPPORT_GFX_MGLS |
 922                         AMD_CG_SUPPORT_GFX_CGCG |
 923                         AMD_CG_SUPPORT_GFX_CGLS |
 924                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 925                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 926                         AMD_CG_SUPPORT_GFX_CP_LS |
 927                         AMD_CG_SUPPORT_MC_LS |
 928                         AMD_CG_SUPPORT_MC_MGCG |
 929                         AMD_CG_SUPPORT_SDMA_MGCG |
 930                         AMD_CG_SUPPORT_SDMA_LS |
 931                         AMD_CG_SUPPORT_BIF_MGCG |
 932                         AMD_CG_SUPPORT_BIF_LS |
 933                         AMD_CG_SUPPORT_HDP_MGCG |
 934                         AMD_CG_SUPPORT_HDP_LS |
 935                         AMD_CG_SUPPORT_ROM_MGCG |
 936                         AMD_CG_SUPPORT_VCE_MGCG |
 937                         AMD_CG_SUPPORT_UVD_MGCG;
 938                 adev->pg_flags = 0;
 939                 adev->external_rev_id = adev->rev_id + 0x14;
 940                 break;
 941         case IP_VERSION(9, 4, 0):
 942                 adev->asic_funcs = &vega20_asic_funcs;
 943                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 944                         AMD_CG_SUPPORT_GFX_MGLS |
 945                         AMD_CG_SUPPORT_GFX_CGCG |
 946                         AMD_CG_SUPPORT_GFX_CGLS |
 947                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 948                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 949                         AMD_CG_SUPPORT_GFX_CP_LS |
 950                         AMD_CG_SUPPORT_MC_LS |
 951                         AMD_CG_SUPPORT_MC_MGCG |
 952                         AMD_CG_SUPPORT_SDMA_MGCG |
 953                         AMD_CG_SUPPORT_SDMA_LS |
 954                         AMD_CG_SUPPORT_BIF_MGCG |
 955                         AMD_CG_SUPPORT_BIF_LS |
 956                         AMD_CG_SUPPORT_HDP_MGCG |
 957                         AMD_CG_SUPPORT_HDP_LS |
 958                         AMD_CG_SUPPORT_ROM_MGCG |
 959                         AMD_CG_SUPPORT_VCE_MGCG |
 960                         AMD_CG_SUPPORT_UVD_MGCG;
 961                 adev->pg_flags = 0;
 962                 adev->external_rev_id = adev->rev_id + 0x28;
 963                 break;
 964         case IP_VERSION(9, 1, 0):
 965         case IP_VERSION(9, 2, 2):
 966                 adev->asic_funcs = &soc15_asic_funcs;
 967
 968                 if (adev->rev_id >= 0x8)
 969                         adev->apu_flags |= AMD_APU_IS_RAVEN2;
 970
 971                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 972                         adev->external_rev_id = adev->rev_id + 0x79;
 973                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
 974                         adev->external_rev_id = adev->rev_id + 0x41;
 975                 else if (adev->rev_id == 1)
 976                         adev->external_rev_id = adev->rev_id + 0x20;
 977                 else
 978                         adev->external_rev_id = adev->rev_id + 0x01;
 979
 980                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
 981                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 982                                 AMD_CG_SUPPORT_GFX_MGLS |
 983                                 AMD_CG_SUPPORT_GFX_CP_LS |
 984                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 985                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 986                                 AMD_CG_SUPPORT_GFX_CGCG |
 987                                 AMD_CG_SUPPORT_GFX_CGLS |
 988                                 AMD_CG_SUPPORT_BIF_LS |
 989                                 AMD_CG_SUPPORT_HDP_LS |
 990                                 AMD_CG_SUPPORT_MC_MGCG |
 991                                 AMD_CG_SUPPORT_MC_LS |
 992                                 AMD_CG_SUPPORT_SDMA_MGCG |
 993                                 AMD_CG_SUPPORT_SDMA_LS |
 994                                 AMD_CG_SUPPORT_VCN_MGCG;
 995
 996                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 997                 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
 998                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 999                                 AMD_CG_SUPPORT_GFX_MGLS |
1000                                 AMD_CG_SUPPORT_GFX_CP_LS |
1001                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1002                                 AMD_CG_SUPPORT_GFX_CGCG |
1003                                 AMD_CG_SUPPORT_GFX_CGLS |
1004                                 AMD_CG_SUPPORT_BIF_LS |
1005                                 AMD_CG_SUPPORT_HDP_LS |
1006                                 AMD_CG_SUPPORT_MC_MGCG |
1007                                 AMD_CG_SUPPORT_MC_LS |
1008                                 AMD_CG_SUPPORT_SDMA_MGCG |
1009                                 AMD_CG_SUPPORT_SDMA_LS |
1010                                 AMD_CG_SUPPORT_VCN_MGCG;
1011
1012                         /*
1013                          * MMHUB PG needs to be disabled for Picasso for
1014                          * stability reasons.
1015                          */
1016                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1017                                 AMD_PG_SUPPORT_VCN;
1018                 } else {
1019                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1020                                 AMD_CG_SUPPORT_GFX_MGLS |
1021                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1022                                 AMD_CG_SUPPORT_GFX_CP_LS |
1023                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1024                                 AMD_CG_SUPPORT_GFX_CGCG |
1025                                 AMD_CG_SUPPORT_GFX_CGLS |
1026                                 AMD_CG_SUPPORT_BIF_MGCG |
1027                                 AMD_CG_SUPPORT_BIF_LS |
1028                                 AMD_CG_SUPPORT_HDP_MGCG |
1029                                 AMD_CG_SUPPORT_HDP_LS |
1030                                 AMD_CG_SUPPORT_DRM_MGCG |
1031                                 AMD_CG_SUPPORT_DRM_LS |
1032                                 AMD_CG_SUPPORT_MC_MGCG |
1033                                 AMD_CG_SUPPORT_MC_LS |
1034                                 AMD_CG_SUPPORT_SDMA_MGCG |
1035                                 AMD_CG_SUPPORT_SDMA_LS |
1036                                 AMD_CG_SUPPORT_VCN_MGCG;
1037
1038                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1039                 }
1040                 break;
1041         case IP_VERSION(9, 4, 1):
1042                 adev->asic_funcs = &vega20_asic_funcs;
1043                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1044                         AMD_CG_SUPPORT_GFX_MGLS |
1045                         AMD_CG_SUPPORT_GFX_CGCG |
1046                         AMD_CG_SUPPORT_GFX_CGLS |
1047                         AMD_CG_SUPPORT_GFX_CP_LS |
1048                         AMD_CG_SUPPORT_HDP_MGCG |
1049                         AMD_CG_SUPPORT_HDP_LS |
1050                         AMD_CG_SUPPORT_SDMA_MGCG |
1051                         AMD_CG_SUPPORT_SDMA_LS |
1052                         AMD_CG_SUPPORT_MC_MGCG |
1053                         AMD_CG_SUPPORT_MC_LS |
1054                         AMD_CG_SUPPORT_IH_CG |
1055                         AMD_CG_SUPPORT_VCN_MGCG |
1056                         AMD_CG_SUPPORT_JPEG_MGCG;
1057                 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1058                 adev->external_rev_id = adev->rev_id + 0x32;
1059                 break;
1060         case IP_VERSION(9, 3, 0):
1061                 adev->asic_funcs = &soc15_asic_funcs;
1062
1063                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1064                         adev->external_rev_id = adev->rev_id + 0x91;
1065                 else
1066                         adev->external_rev_id = adev->rev_id + 0xa1;
1067                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1068                                  AMD_CG_SUPPORT_GFX_MGLS |
1069                                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1070                                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1071                                  AMD_CG_SUPPORT_GFX_CGCG |
1072                                  AMD_CG_SUPPORT_GFX_CGLS |
1073                                  AMD_CG_SUPPORT_GFX_CP_LS |
1074                                  AMD_CG_SUPPORT_MC_MGCG |
1075                                  AMD_CG_SUPPORT_MC_LS |
1076                                  AMD_CG_SUPPORT_SDMA_MGCG |
1077                                  AMD_CG_SUPPORT_SDMA_LS |
1078                                  AMD_CG_SUPPORT_BIF_LS |
1079                                  AMD_CG_SUPPORT_HDP_LS |
1080                                  AMD_CG_SUPPORT_VCN_MGCG |
1081                                  AMD_CG_SUPPORT_JPEG_MGCG |
1082                                  AMD_CG_SUPPORT_IH_CG |
1083                                  AMD_CG_SUPPORT_ATHUB_LS |
1084                                  AMD_CG_SUPPORT_ATHUB_MGCG |
1085                                  AMD_CG_SUPPORT_DF_MGCG;
1086                 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1087                                  AMD_PG_SUPPORT_VCN |
1088                                  AMD_PG_SUPPORT_JPEG |
1089                                  AMD_PG_SUPPORT_VCN_DPG;
1090                 break;
1091         case IP_VERSION(9, 4, 2):
1092                 adev->asic_funcs = &vega20_asic_funcs;
1093                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1094                         AMD_CG_SUPPORT_GFX_MGLS |
1095                         AMD_CG_SUPPORT_GFX_CP_LS |
1096                         AMD_CG_SUPPORT_HDP_LS |
1097                         AMD_CG_SUPPORT_SDMA_MGCG |
1098                         AMD_CG_SUPPORT_SDMA_LS |
1099                         AMD_CG_SUPPORT_IH_CG |
1100                         AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1101                 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1102                 adev->external_rev_id = adev->rev_id + 0x3c;
1103                 break;
1104         default:
1105                 /* FIXME: not supported yet */
1106                 return -EINVAL;
1107         }
1108
1109         if (amdgpu_sriov_vf(adev)) {
1110                 amdgpu_virt_init_setting(adev);
1111                 xgpu_ai_mailbox_set_irq_funcs(adev);
1112         }
1113
1114         return 0;
1115 }
1116
1117 static int soc15_common_late_init(void *handle)
1118 {
1119         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120
1121         if (amdgpu_sriov_vf(adev))
1122                 xgpu_ai_mailbox_get_irq(adev);
1123
1124         return 0;
1125 }
1126
1127 static int soc15_common_sw_init(void *handle)
1128 {
1129         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1130
1131         if (amdgpu_sriov_vf(adev))
1132                 xgpu_ai_mailbox_add_irq_id(adev);
1133
1134         if (adev->df.funcs &&
1135             adev->df.funcs->sw_init)
1136                 adev->df.funcs->sw_init(adev);
1137
1138         return 0;
1139 }
1140
1141 static int soc15_common_sw_fini(void *handle)
1142 {
1143         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1144
1145         if (adev->df.funcs &&
1146             adev->df.funcs->sw_fini)
1147                 adev->df.funcs->sw_fini(adev);
1148         return 0;
1149 }
1150
1151 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1152 {
1153         int i;
1154
1155         /* sdma doorbell range is programed by hypervisor */
1156         if (!amdgpu_sriov_vf(adev)) {
1157                 for (i = 0; i < adev->sdma.num_instances; i++) {
1158                         adev->nbio.funcs->sdma_doorbell_range(adev, i,
1159                                 true, adev->doorbell_index.sdma_engine[i] << 1,
1160                                 adev->doorbell_index.sdma_doorbell_range);
1161                 }
1162         }
1163 }
1164
1165 static int soc15_common_hw_init(void *handle)
1166 {
1167         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1168
1169         /* enable aspm */
1170         soc15_program_aspm(adev);
1171         /* setup nbio registers */
1172         adev->nbio.funcs->init_registers(adev);
1173         /* remap HDP registers to a hole in mmio space,
1174          * for the purpose of expose those registers
1175          * to process space
1176          */
1177         if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1178                 adev->nbio.funcs->remap_hdp_registers(adev);
1179
1180         /* enable the doorbell aperture */
1181         soc15_enable_doorbell_aperture(adev, true);
1182         /* HW doorbell routing policy: doorbell writing not
1183          * in SDMA/IH/MM/ACV range will be routed to CP. So
1184          * we need to init SDMA doorbell range prior
1185          * to CP ip block init and ring test.  IH already
1186          * happens before CP.
1187          */
1188         soc15_sdma_doorbell_range_init(adev);
1189
1190         return 0;
1191 }
1192
1193 static int soc15_common_hw_fini(void *handle)
1194 {
1195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196
1197         /* disable the doorbell aperture */
1198         soc15_enable_doorbell_aperture(adev, false);
1199         if (amdgpu_sriov_vf(adev))
1200                 xgpu_ai_mailbox_put_irq(adev);
1201
1202         if (adev->nbio.ras_if &&
1203             amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1204                 if (adev->nbio.ras &&
1205                     adev->nbio.ras->init_ras_controller_interrupt)
1206                         amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1207                 if (adev->nbio.ras &&
1208                     adev->nbio.ras->init_ras_err_event_athub_interrupt)
1209                         amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1210         }
1211
1212         return 0;
1213 }
1214
1215 static int soc15_common_suspend(void *handle)
1216 {
1217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218
1219         return soc15_common_hw_fini(adev);
1220 }
1221
1222 static int soc15_common_resume(void *handle)
1223 {
1224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225
1226         return soc15_common_hw_init(adev);
1227 }
1228
1229 static bool soc15_common_is_idle(void *handle)
1230 {
1231         return true;
1232 }
1233
1234 static int soc15_common_wait_for_idle(void *handle)
1235 {
1236         return 0;
1237 }
1238
1239 static int soc15_common_soft_reset(void *handle)
1240 {
1241         return 0;
1242 }
1243
1244 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1245 {
1246         uint32_t def, data;
1247
1248         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1249
1250         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1251                 data &= ~(0x01000000 |
1252                           0x02000000 |
1253                           0x04000000 |
1254                           0x08000000 |
1255                           0x10000000 |
1256                           0x20000000 |
1257                           0x40000000 |
1258                           0x80000000);
1259         else
1260                 data |= (0x01000000 |
1261                          0x02000000 |
1262                          0x04000000 |
1263                          0x08000000 |
1264                          0x10000000 |
1265                          0x20000000 |
1266                          0x40000000 |
1267                          0x80000000);
1268
1269         if (def != data)
1270                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1271 }
1272
1273 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1274 {
1275         uint32_t def, data;
1276
1277         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1278
1279         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1280                 data |= 1;
1281         else
1282                 data &= ~1;
1283
1284         if (def != data)
1285                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1286 }
1287
1288 static int soc15_common_set_clockgating_state(void *handle,
1289                                             enum amd_clockgating_state state)
1290 {
1291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292
1293         if (amdgpu_sriov_vf(adev))
1294                 return 0;
1295
1296         switch (adev->ip_versions[NBIO_HWIP][0]) {
1297         case IP_VERSION(6, 1, 0):
1298         case IP_VERSION(6, 2, 0):
1299         case IP_VERSION(7, 4, 0):
1300                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1301                                 state == AMD_CG_STATE_GATE);
1302                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1303                                 state == AMD_CG_STATE_GATE);
1304                 adev->hdp.funcs->update_clock_gating(adev,
1305                                 state == AMD_CG_STATE_GATE);
1306                 soc15_update_drm_clock_gating(adev,
1307                                 state == AMD_CG_STATE_GATE);
1308                 soc15_update_drm_light_sleep(adev,
1309                                 state == AMD_CG_STATE_GATE);
1310                 adev->smuio.funcs->update_rom_clock_gating(adev,
1311                                 state == AMD_CG_STATE_GATE);
1312                 adev->df.funcs->update_medium_grain_clock_gating(adev,
1313                                 state == AMD_CG_STATE_GATE);
1314                 break;
1315         case IP_VERSION(7, 0, 0):
1316         case IP_VERSION(7, 0, 1):
1317         case IP_VERSION(2, 5, 0):
1318                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1319                                 state == AMD_CG_STATE_GATE);
1320                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1321                                 state == AMD_CG_STATE_GATE);
1322                 adev->hdp.funcs->update_clock_gating(adev,
1323                                 state == AMD_CG_STATE_GATE);
1324                 soc15_update_drm_clock_gating(adev,
1325                                 state == AMD_CG_STATE_GATE);
1326                 soc15_update_drm_light_sleep(adev,
1327                                 state == AMD_CG_STATE_GATE);
1328                 break;
1329         case IP_VERSION(7, 4, 1):
1330         case IP_VERSION(7, 4, 4):
1331                 adev->hdp.funcs->update_clock_gating(adev,
1332                                 state == AMD_CG_STATE_GATE);
1333                 break;
1334         default:
1335                 break;
1336         }
1337         return 0;
1338 }
1339
1340 static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1341 {
1342         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1343         int data;
1344
1345         if (amdgpu_sriov_vf(adev))
1346                 *flags = 0;
1347
1348         adev->nbio.funcs->get_clockgating_state(adev, flags);
1349
1350         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1351
1352         if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
1353
1354                 /* AMD_CG_SUPPORT_DRM_MGCG */
1355                 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1356                 if (!(data & 0x01000000))
1357                         *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1358
1359                 /* AMD_CG_SUPPORT_DRM_LS */
1360                 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1361                 if (data & 0x1)
1362                         *flags |= AMD_CG_SUPPORT_DRM_LS;
1363         }
1364
1365         /* AMD_CG_SUPPORT_ROM_MGCG */
1366         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1367
1368         adev->df.funcs->get_clockgating_state(adev, flags);
1369 }
1370
1371 static int soc15_common_set_powergating_state(void *handle,
1372                                             enum amd_powergating_state state)
1373 {
1374         /* todo */
1375         return 0;
1376 }
1377
1378 static const struct amd_ip_funcs soc15_common_ip_funcs = {
1379         .name = "soc15_common",
1380         .early_init = soc15_common_early_init,
1381         .late_init = soc15_common_late_init,
1382         .sw_init = soc15_common_sw_init,
1383         .sw_fini = soc15_common_sw_fini,
1384         .hw_init = soc15_common_hw_init,
1385         .hw_fini = soc15_common_hw_fini,
1386         .suspend = soc15_common_suspend,
1387         .resume = soc15_common_resume,
1388         .is_idle = soc15_common_is_idle,
1389         .wait_for_idle = soc15_common_wait_for_idle,
1390         .soft_reset = soc15_common_soft_reset,
1391         .set_clockgating_state = soc15_common_set_clockgating_state,
1392         .set_powergating_state = soc15_common_set_powergating_state,
1393         .get_clockgating_state= soc15_common_get_clockgating_state,
1394 };