2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
46 #include "drm_crtc_internal.h"
48 static int oui(u8 first, u8 second, u8 third)
50 return (first << 16) | (second << 8) | third;
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
90 /* Cap the DSC target bitrate to 15bpp */
91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
93 #define MICROSOFT_IEEE_OUI 0xca125c
95 struct detailed_mode_closure {
96 struct drm_connector *connector;
97 const struct drm_edid *drm_edid;
107 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
114 static const struct edid_quirk {
117 } edid_quirk_list[] = {
119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
126 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
127 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
129 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
130 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
132 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
133 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
135 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
138 /* Belinea 10 15 55 */
139 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
140 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
142 /* Envision Peripherals, Inc. EN-7100e */
143 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
144 /* Envision EN2028 */
145 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
147 /* Funai Electronics PM36B */
148 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
149 EDID_QUIRK_DETAILED_IN_CM),
152 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
155 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
157 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
158 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
160 /* LG Philips LCD LP154W01-A5 */
161 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
162 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
164 /* Samsung SyncMaster 205BW. Note: irony */
165 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
166 /* Samsung SyncMaster 22[5-6]BW */
167 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
168 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
170 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
171 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
173 /* ViewSonic VA2026w */
174 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
176 /* Medion MD 30217 PG */
177 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
180 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
182 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
183 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
185 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
186 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
188 /* Valve Index Headset */
189 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
207 /* HTC Vive and Vive Pro VR Headsets */
208 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
211 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
212 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
217 /* Windows Mixed Reality Headsets */
218 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
222 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
225 /* Sony PlayStation VR Headset */
226 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
228 /* Sensics VR Headsets */
229 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
231 /* OSVR HDK and HDK2 VR Headsets */
232 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
233 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
237 * Autogenerated from the DMT spec.
238 * This table is copied from xfree86/modes/xf86EdidModes.c.
240 static const struct drm_display_mode drm_dmt_modes[] = {
241 /* 0x01 - 640x350@85Hz */
242 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
243 736, 832, 0, 350, 382, 385, 445, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x02 - 640x400@85Hz */
246 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
247 736, 832, 0, 400, 401, 404, 445, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 0x03 - 720x400@85Hz */
250 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
251 828, 936, 0, 400, 401, 404, 446, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x04 - 640x480@60Hz */
254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
255 752, 800, 0, 480, 490, 492, 525, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
257 /* 0x05 - 640x480@72Hz */
258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
259 704, 832, 0, 480, 489, 492, 520, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x06 - 640x480@75Hz */
262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
263 720, 840, 0, 480, 481, 484, 500, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
265 /* 0x07 - 640x480@85Hz */
266 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
267 752, 832, 0, 480, 481, 484, 509, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
269 /* 0x08 - 800x600@56Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
271 896, 1024, 0, 600, 601, 603, 625, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x09 - 800x600@60Hz */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
275 968, 1056, 0, 600, 601, 605, 628, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x0a - 800x600@72Hz */
278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
279 976, 1040, 0, 600, 637, 643, 666, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0b - 800x600@75Hz */
282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
283 896, 1056, 0, 600, 601, 604, 625, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
285 /* 0x0c - 800x600@85Hz */
286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
287 896, 1048, 0, 600, 601, 604, 631, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x0d - 800x600@120Hz RB */
290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
291 880, 960, 0, 600, 603, 607, 636, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
293 /* 0x0e - 848x480@60Hz */
294 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
295 976, 1088, 0, 480, 486, 494, 517, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 0x0f - 1024x768@43Hz, interlace */
298 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
299 1208, 1264, 0, 768, 768, 776, 817, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
301 DRM_MODE_FLAG_INTERLACE) },
302 /* 0x10 - 1024x768@60Hz */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
304 1184, 1344, 0, 768, 771, 777, 806, 0,
305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
306 /* 0x11 - 1024x768@70Hz */
307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
308 1184, 1328, 0, 768, 771, 777, 806, 0,
309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
310 /* 0x12 - 1024x768@75Hz */
311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
312 1136, 1312, 0, 768, 769, 772, 800, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x13 - 1024x768@85Hz */
315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
316 1168, 1376, 0, 768, 769, 772, 808, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x14 - 1024x768@120Hz RB */
319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
320 1104, 1184, 0, 768, 771, 775, 813, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
322 /* 0x15 - 1152x864@75Hz */
323 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
324 1344, 1600, 0, 864, 865, 868, 900, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x55 - 1280x720@60Hz */
327 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
328 1430, 1650, 0, 720, 725, 730, 750, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x16 - 1280x768@60Hz RB */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
332 1360, 1440, 0, 768, 771, 778, 790, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x17 - 1280x768@60Hz */
335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
336 1472, 1664, 0, 768, 771, 778, 798, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x18 - 1280x768@75Hz */
339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
340 1488, 1696, 0, 768, 771, 778, 805, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x19 - 1280x768@85Hz */
343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
344 1496, 1712, 0, 768, 771, 778, 809, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x1a - 1280x768@120Hz RB */
347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
348 1360, 1440, 0, 768, 771, 778, 813, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 0x1b - 1280x800@60Hz RB */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
352 1360, 1440, 0, 800, 803, 809, 823, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x1c - 1280x800@60Hz */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
356 1480, 1680, 0, 800, 803, 809, 831, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x1d - 1280x800@75Hz */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
360 1488, 1696, 0, 800, 803, 809, 838, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x1e - 1280x800@85Hz */
363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
364 1496, 1712, 0, 800, 803, 809, 843, 0,
365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x1f - 1280x800@120Hz RB */
367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
368 1360, 1440, 0, 800, 803, 809, 847, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
370 /* 0x20 - 1280x960@60Hz */
371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
372 1488, 1800, 0, 960, 961, 964, 1000, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x21 - 1280x960@85Hz */
375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
376 1504, 1728, 0, 960, 961, 964, 1011, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x22 - 1280x960@120Hz RB */
379 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
380 1360, 1440, 0, 960, 963, 967, 1017, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
382 /* 0x23 - 1280x1024@60Hz */
383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
384 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x24 - 1280x1024@75Hz */
387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
388 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x25 - 1280x1024@85Hz */
391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
392 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x26 - 1280x1024@120Hz RB */
395 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
396 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398 /* 0x27 - 1360x768@60Hz */
399 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
400 1536, 1792, 0, 768, 771, 777, 795, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x28 - 1360x768@120Hz RB */
403 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
404 1440, 1520, 0, 768, 771, 776, 813, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
406 /* 0x51 - 1366x768@60Hz */
407 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
408 1579, 1792, 0, 768, 771, 774, 798, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x56 - 1366x768@60Hz */
411 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
412 1436, 1500, 0, 768, 769, 772, 800, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x29 - 1400x1050@60Hz RB */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
416 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 0x2a - 1400x1050@60Hz */
419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
420 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x2b - 1400x1050@75Hz */
423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
424 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x2c - 1400x1050@85Hz */
427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
428 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x2d - 1400x1050@120Hz RB */
431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
432 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
434 /* 0x2e - 1440x900@60Hz RB */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
436 1520, 1600, 0, 900, 903, 909, 926, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x2f - 1440x900@60Hz */
439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
440 1672, 1904, 0, 900, 903, 909, 934, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x30 - 1440x900@75Hz */
443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
444 1688, 1936, 0, 900, 903, 909, 942, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x31 - 1440x900@85Hz */
447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
448 1696, 1952, 0, 900, 903, 909, 948, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x32 - 1440x900@120Hz RB */
451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
452 1520, 1600, 0, 900, 903, 909, 953, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
454 /* 0x53 - 1600x900@60Hz */
455 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
456 1704, 1800, 0, 900, 901, 904, 1000, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x33 - 1600x1200@60Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x34 - 1600x1200@65Hz */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x35 - 1600x1200@70Hz */
467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x36 - 1600x1200@75Hz */
471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x37 - 1600x1200@85Hz */
475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x38 - 1600x1200@120Hz RB */
479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
480 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x39 - 1680x1050@60Hz RB */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
484 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x3a - 1680x1050@60Hz */
487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
488 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3b - 1680x1050@75Hz */
491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
492 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x3c - 1680x1050@85Hz */
495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
496 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x3d - 1680x1050@120Hz RB */
499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
500 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
502 /* 0x3e - 1792x1344@60Hz */
503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
504 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x3f - 1792x1344@75Hz */
507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
508 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x40 - 1792x1344@120Hz RB */
511 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
512 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x41 - 1856x1392@60Hz */
515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
516 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
518 /* 0x42 - 1856x1392@75Hz */
519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
520 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x43 - 1856x1392@120Hz RB */
523 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
524 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
526 /* 0x52 - 1920x1080@60Hz */
527 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
528 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
530 /* 0x44 - 1920x1200@60Hz RB */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
532 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
534 /* 0x45 - 1920x1200@60Hz */
535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
536 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x46 - 1920x1200@75Hz */
539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
540 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x47 - 1920x1200@85Hz */
543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
544 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x48 - 1920x1200@120Hz RB */
547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
548 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
550 /* 0x49 - 1920x1440@60Hz */
551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
552 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
554 /* 0x4a - 1920x1440@75Hz */
555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
556 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4b - 1920x1440@120Hz RB */
559 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
560 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
562 /* 0x54 - 2048x1152@60Hz */
563 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
564 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x4c - 2560x1600@60Hz RB */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
568 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
570 /* 0x4d - 2560x1600@60Hz */
571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
572 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
574 /* 0x4e - 2560x1600@75Hz */
575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
576 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
578 /* 0x4f - 2560x1600@85Hz */
579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
580 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
582 /* 0x50 - 2560x1600@120Hz RB */
583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
584 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
586 /* 0x57 - 4096x2160@60Hz RB */
587 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
588 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
592 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
597 * These more or less come from the DMT spec. The 720x400 modes are
598 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
599 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
600 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
603 * The DMT modes have been fact-checked; the rest are mild guesses.
605 static const struct drm_display_mode edid_est_modes[] = {
606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
607 968, 1056, 0, 600, 601, 605, 628, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
610 896, 1024, 0, 600, 601, 603, 625, 0,
611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
613 720, 840, 0, 480, 481, 484, 500, 0,
614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
616 704, 832, 0, 480, 489, 492, 520, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
619 768, 864, 0, 480, 483, 486, 525, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
622 752, 800, 0, 480, 490, 492, 525, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
625 846, 900, 0, 400, 421, 423, 449, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
628 846, 900, 0, 400, 412, 414, 449, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
630 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
631 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
634 1136, 1312, 0, 768, 769, 772, 800, 0,
635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
637 1184, 1328, 0, 768, 771, 777, 806, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
640 1184, 1344, 0, 768, 771, 777, 806, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
642 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
643 1208, 1264, 0, 768, 768, 776, 817, 0,
644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
645 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
646 928, 1152, 0, 624, 625, 628, 667, 0,
647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
649 896, 1056, 0, 600, 601, 604, 625, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
652 976, 1040, 0, 600, 637, 643, 666, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
654 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
655 1344, 1600, 0, 864, 865, 868, 900, 0,
656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
666 static const struct minimode est3_modes[] = {
674 { 1024, 768, 85, 0 },
675 { 1152, 864, 75, 0 },
677 { 1280, 768, 60, 1 },
678 { 1280, 768, 60, 0 },
679 { 1280, 768, 75, 0 },
680 { 1280, 768, 85, 0 },
681 { 1280, 960, 60, 0 },
682 { 1280, 960, 85, 0 },
683 { 1280, 1024, 60, 0 },
684 { 1280, 1024, 85, 0 },
686 { 1360, 768, 60, 0 },
687 { 1440, 900, 60, 1 },
688 { 1440, 900, 60, 0 },
689 { 1440, 900, 75, 0 },
690 { 1440, 900, 85, 0 },
691 { 1400, 1050, 60, 1 },
692 { 1400, 1050, 60, 0 },
693 { 1400, 1050, 75, 0 },
695 { 1400, 1050, 85, 0 },
696 { 1680, 1050, 60, 1 },
697 { 1680, 1050, 60, 0 },
698 { 1680, 1050, 75, 0 },
699 { 1680, 1050, 85, 0 },
700 { 1600, 1200, 60, 0 },
701 { 1600, 1200, 65, 0 },
702 { 1600, 1200, 70, 0 },
704 { 1600, 1200, 75, 0 },
705 { 1600, 1200, 85, 0 },
706 { 1792, 1344, 60, 0 },
707 { 1792, 1344, 75, 0 },
708 { 1856, 1392, 60, 0 },
709 { 1856, 1392, 75, 0 },
710 { 1920, 1200, 60, 1 },
711 { 1920, 1200, 60, 0 },
713 { 1920, 1200, 75, 0 },
714 { 1920, 1200, 85, 0 },
715 { 1920, 1440, 60, 0 },
716 { 1920, 1440, 75, 0 },
719 static const struct minimode extra_modes[] = {
720 { 1024, 576, 60, 0 },
721 { 1366, 768, 60, 0 },
722 { 1600, 900, 60, 0 },
723 { 1680, 945, 60, 0 },
724 { 1920, 1080, 60, 0 },
725 { 2048, 1152, 60, 0 },
726 { 2048, 1536, 60, 0 },
730 * From CEA/CTA-861 spec.
732 * Do not access directly, instead always use cea_mode_for_vic().
734 static const struct drm_display_mode edid_cea_modes_1[] = {
735 /* 1 - 640x480@60Hz 4:3 */
736 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
737 752, 800, 0, 480, 490, 492, 525, 0,
738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
739 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
740 /* 2 - 720x480@60Hz 4:3 */
741 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
742 798, 858, 0, 480, 489, 495, 525, 0,
743 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
745 /* 3 - 720x480@60Hz 16:9 */
746 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
747 798, 858, 0, 480, 489, 495, 525, 0,
748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
749 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
750 /* 4 - 1280x720@60Hz 16:9 */
751 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
752 1430, 1650, 0, 720, 725, 730, 750, 0,
753 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
755 /* 5 - 1920x1080i@60Hz 16:9 */
756 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
757 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
759 DRM_MODE_FLAG_INTERLACE),
760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 6 - 720(1440)x480i@60Hz 4:3 */
762 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
763 801, 858, 0, 480, 488, 494, 525, 0,
764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
765 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
767 /* 7 - 720(1440)x480i@60Hz 16:9 */
768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
769 801, 858, 0, 480, 488, 494, 525, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
773 /* 8 - 720(1440)x240@60Hz 4:3 */
774 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
775 801, 858, 0, 240, 244, 247, 262, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
777 DRM_MODE_FLAG_DBLCLK),
778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
779 /* 9 - 720(1440)x240@60Hz 16:9 */
780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
781 801, 858, 0, 240, 244, 247, 262, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
783 DRM_MODE_FLAG_DBLCLK),
784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
785 /* 10 - 2880x480i@60Hz 4:3 */
786 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
787 3204, 3432, 0, 480, 488, 494, 525, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_INTERLACE),
790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
791 /* 11 - 2880x480i@60Hz 16:9 */
792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
793 3204, 3432, 0, 480, 488, 494, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
795 DRM_MODE_FLAG_INTERLACE),
796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
797 /* 12 - 2880x240@60Hz 4:3 */
798 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
799 3204, 3432, 0, 240, 244, 247, 262, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
802 /* 13 - 2880x240@60Hz 16:9 */
803 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
804 3204, 3432, 0, 240, 244, 247, 262, 0,
805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
806 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
807 /* 14 - 1440x480@60Hz 4:3 */
808 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
809 1596, 1716, 0, 480, 489, 495, 525, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
812 /* 15 - 1440x480@60Hz 16:9 */
813 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
814 1596, 1716, 0, 480, 489, 495, 525, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
817 /* 16 - 1920x1080@60Hz 16:9 */
818 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
819 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 17 - 720x576@50Hz 4:3 */
823 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
824 796, 864, 0, 576, 581, 586, 625, 0,
825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
827 /* 18 - 720x576@50Hz 16:9 */
828 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
829 796, 864, 0, 576, 581, 586, 625, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 19 - 1280x720@50Hz 16:9 */
833 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
834 1760, 1980, 0, 720, 725, 730, 750, 0,
835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
837 /* 20 - 1920x1080i@50Hz 16:9 */
838 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
839 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
841 DRM_MODE_FLAG_INTERLACE),
842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 21 - 720(1440)x576i@50Hz 4:3 */
844 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
845 795, 864, 0, 576, 580, 586, 625, 0,
846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
847 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
849 /* 22 - 720(1440)x576i@50Hz 16:9 */
850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
851 795, 864, 0, 576, 580, 586, 625, 0,
852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
855 /* 23 - 720(1440)x288@50Hz 4:3 */
856 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
857 795, 864, 0, 288, 290, 293, 312, 0,
858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
859 DRM_MODE_FLAG_DBLCLK),
860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
861 /* 24 - 720(1440)x288@50Hz 16:9 */
862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
863 795, 864, 0, 288, 290, 293, 312, 0,
864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
865 DRM_MODE_FLAG_DBLCLK),
866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
867 /* 25 - 2880x576i@50Hz 4:3 */
868 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
869 3180, 3456, 0, 576, 580, 586, 625, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
871 DRM_MODE_FLAG_INTERLACE),
872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
873 /* 26 - 2880x576i@50Hz 16:9 */
874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
875 3180, 3456, 0, 576, 580, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
877 DRM_MODE_FLAG_INTERLACE),
878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
879 /* 27 - 2880x288@50Hz 4:3 */
880 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
881 3180, 3456, 0, 288, 290, 293, 312, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
884 /* 28 - 2880x288@50Hz 16:9 */
885 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
886 3180, 3456, 0, 288, 290, 293, 312, 0,
887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
888 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
889 /* 29 - 1440x576@50Hz 4:3 */
890 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
891 1592, 1728, 0, 576, 581, 586, 625, 0,
892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
894 /* 30 - 1440x576@50Hz 16:9 */
895 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
896 1592, 1728, 0, 576, 581, 586, 625, 0,
897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
899 /* 31 - 1920x1080@50Hz 16:9 */
900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
901 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 32 - 1920x1080@24Hz 16:9 */
905 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
906 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
909 /* 33 - 1920x1080@25Hz 16:9 */
910 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
911 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
914 /* 34 - 1920x1080@30Hz 16:9 */
915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
916 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
919 /* 35 - 2880x480@60Hz 4:3 */
920 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
921 3192, 3432, 0, 480, 489, 495, 525, 0,
922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
924 /* 36 - 2880x480@60Hz 16:9 */
925 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
926 3192, 3432, 0, 480, 489, 495, 525, 0,
927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 37 - 2880x576@50Hz 4:3 */
930 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
931 3184, 3456, 0, 576, 581, 586, 625, 0,
932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
934 /* 38 - 2880x576@50Hz 16:9 */
935 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
936 3184, 3456, 0, 576, 581, 586, 625, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
939 /* 39 - 1920x1080i@50Hz 16:9 */
940 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
941 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
943 DRM_MODE_FLAG_INTERLACE),
944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 40 - 1920x1080i@100Hz 16:9 */
946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
947 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
949 DRM_MODE_FLAG_INTERLACE),
950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
951 /* 41 - 1280x720@100Hz 16:9 */
952 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
953 1760, 1980, 0, 720, 725, 730, 750, 0,
954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
956 /* 42 - 720x576@100Hz 4:3 */
957 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
958 796, 864, 0, 576, 581, 586, 625, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
961 /* 43 - 720x576@100Hz 16:9 */
962 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
963 796, 864, 0, 576, 581, 586, 625, 0,
964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
966 /* 44 - 720(1440)x576i@100Hz 4:3 */
967 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
968 795, 864, 0, 576, 580, 586, 625, 0,
969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
972 /* 45 - 720(1440)x576i@100Hz 16:9 */
973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
974 795, 864, 0, 576, 580, 586, 625, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978 /* 46 - 1920x1080i@120Hz 16:9 */
979 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
980 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
982 DRM_MODE_FLAG_INTERLACE),
983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 47 - 1280x720@120Hz 16:9 */
985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
986 1430, 1650, 0, 720, 725, 730, 750, 0,
987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
989 /* 48 - 720x480@120Hz 4:3 */
990 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
991 798, 858, 0, 480, 489, 495, 525, 0,
992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
994 /* 49 - 720x480@120Hz 16:9 */
995 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
996 798, 858, 0, 480, 489, 495, 525, 0,
997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 50 - 720(1440)x480i@120Hz 4:3 */
1000 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1001 801, 858, 0, 480, 488, 494, 525, 0,
1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1003 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1005 /* 51 - 720(1440)x480i@120Hz 16:9 */
1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1007 801, 858, 0, 480, 488, 494, 525, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1011 /* 52 - 720x576@200Hz 4:3 */
1012 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1013 796, 864, 0, 576, 581, 586, 625, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1015 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1016 /* 53 - 720x576@200Hz 16:9 */
1017 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1018 796, 864, 0, 576, 581, 586, 625, 0,
1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1021 /* 54 - 720(1440)x576i@200Hz 4:3 */
1022 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1023 795, 864, 0, 576, 580, 586, 625, 0,
1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1025 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1027 /* 55 - 720(1440)x576i@200Hz 16:9 */
1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1029 795, 864, 0, 576, 580, 586, 625, 0,
1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1033 /* 56 - 720x480@240Hz 4:3 */
1034 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1035 798, 858, 0, 480, 489, 495, 525, 0,
1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1037 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1038 /* 57 - 720x480@240Hz 16:9 */
1039 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1040 798, 858, 0, 480, 489, 495, 525, 0,
1041 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1043 /* 58 - 720(1440)x480i@240Hz 4:3 */
1044 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1045 801, 858, 0, 480, 488, 494, 525, 0,
1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1047 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1049 /* 59 - 720(1440)x480i@240Hz 16:9 */
1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1051 801, 858, 0, 480, 488, 494, 525, 0,
1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1055 /* 60 - 1280x720@24Hz 16:9 */
1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1057 3080, 3300, 0, 720, 725, 730, 750, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1060 /* 61 - 1280x720@25Hz 16:9 */
1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1062 3740, 3960, 0, 720, 725, 730, 750, 0,
1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1065 /* 62 - 1280x720@30Hz 16:9 */
1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1067 3080, 3300, 0, 720, 725, 730, 750, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1070 /* 63 - 1920x1080@120Hz 16:9 */
1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1072 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1075 /* 64 - 1920x1080@100Hz 16:9 */
1076 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1077 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1080 /* 65 - 1280x720@24Hz 64:27 */
1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1082 3080, 3300, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085 /* 66 - 1280x720@25Hz 64:27 */
1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1087 3740, 3960, 0, 720, 725, 730, 750, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090 /* 67 - 1280x720@30Hz 64:27 */
1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1092 3080, 3300, 0, 720, 725, 730, 750, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095 /* 68 - 1280x720@50Hz 64:27 */
1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1097 1760, 1980, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 69 - 1280x720@60Hz 64:27 */
1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1102 1430, 1650, 0, 720, 725, 730, 750, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 70 - 1280x720@100Hz 64:27 */
1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1107 1760, 1980, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 71 - 1280x720@120Hz 64:27 */
1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1112 1430, 1650, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 72 - 1920x1080@24Hz 64:27 */
1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1117 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 73 - 1920x1080@25Hz 64:27 */
1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1122 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 74 - 1920x1080@30Hz 64:27 */
1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1127 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 75 - 1920x1080@50Hz 64:27 */
1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1132 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 76 - 1920x1080@60Hz 64:27 */
1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1137 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 77 - 1920x1080@100Hz 64:27 */
1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1142 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 78 - 1920x1080@120Hz 64:27 */
1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1147 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 79 - 1680x720@24Hz 64:27 */
1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1152 3080, 3300, 0, 720, 725, 730, 750, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 80 - 1680x720@25Hz 64:27 */
1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1157 2948, 3168, 0, 720, 725, 730, 750, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 81 - 1680x720@30Hz 64:27 */
1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1162 2420, 2640, 0, 720, 725, 730, 750, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 82 - 1680x720@50Hz 64:27 */
1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1167 1980, 2200, 0, 720, 725, 730, 750, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 83 - 1680x720@60Hz 64:27 */
1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1172 1980, 2200, 0, 720, 725, 730, 750, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 84 - 1680x720@100Hz 64:27 */
1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1177 1780, 2000, 0, 720, 725, 730, 825, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 85 - 1680x720@120Hz 64:27 */
1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1182 1780, 2000, 0, 720, 725, 730, 825, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 86 - 2560x1080@24Hz 64:27 */
1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1187 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190 /* 87 - 2560x1080@25Hz 64:27 */
1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1192 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195 /* 88 - 2560x1080@30Hz 64:27 */
1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1197 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200 /* 89 - 2560x1080@50Hz 64:27 */
1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1202 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1205 /* 90 - 2560x1080@60Hz 64:27 */
1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1207 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1210 /* 91 - 2560x1080@100Hz 64:27 */
1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1212 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1215 /* 92 - 2560x1080@120Hz 64:27 */
1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1217 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1220 /* 93 - 3840x2160@24Hz 16:9 */
1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1222 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1225 /* 94 - 3840x2160@25Hz 16:9 */
1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1227 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1230 /* 95 - 3840x2160@30Hz 16:9 */
1231 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1232 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1235 /* 96 - 3840x2160@50Hz 16:9 */
1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1237 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1240 /* 97 - 3840x2160@60Hz 16:9 */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1242 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1245 /* 98 - 4096x2160@24Hz 256:135 */
1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1247 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1250 /* 99 - 4096x2160@25Hz 256:135 */
1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1252 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1255 /* 100 - 4096x2160@30Hz 256:135 */
1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1257 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1260 /* 101 - 4096x2160@50Hz 256:135 */
1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1262 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1265 /* 102 - 4096x2160@60Hz 256:135 */
1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1267 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1270 /* 103 - 3840x2160@24Hz 64:27 */
1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1272 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1275 /* 104 - 3840x2160@25Hz 64:27 */
1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1277 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1280 /* 105 - 3840x2160@30Hz 64:27 */
1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1282 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1285 /* 106 - 3840x2160@50Hz 64:27 */
1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1287 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1290 /* 107 - 3840x2160@60Hz 64:27 */
1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1292 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1295 /* 108 - 1280x720@48Hz 16:9 */
1296 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1297 2280, 2500, 0, 720, 725, 730, 750, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1300 /* 109 - 1280x720@48Hz 64:27 */
1301 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1302 2280, 2500, 0, 720, 725, 730, 750, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1305 /* 110 - 1680x720@48Hz 64:27 */
1306 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1307 2530, 2750, 0, 720, 725, 730, 750, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1310 /* 111 - 1920x1080@48Hz 16:9 */
1311 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1312 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1315 /* 112 - 1920x1080@48Hz 64:27 */
1316 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1317 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1320 /* 113 - 2560x1080@48Hz 64:27 */
1321 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1322 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1325 /* 114 - 3840x2160@48Hz 16:9 */
1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1327 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1330 /* 115 - 4096x2160@48Hz 256:135 */
1331 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1332 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1335 /* 116 - 3840x2160@48Hz 64:27 */
1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1337 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1340 /* 117 - 3840x2160@100Hz 16:9 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1342 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1345 /* 118 - 3840x2160@120Hz 16:9 */
1346 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1347 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1350 /* 119 - 3840x2160@100Hz 64:27 */
1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1352 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1355 /* 120 - 3840x2160@120Hz 64:27 */
1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1357 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1360 /* 121 - 5120x2160@24Hz 64:27 */
1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1362 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1365 /* 122 - 5120x2160@25Hz 64:27 */
1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1367 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1370 /* 123 - 5120x2160@30Hz 64:27 */
1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1372 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1375 /* 124 - 5120x2160@48Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1377 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1380 /* 125 - 5120x2160@50Hz 64:27 */
1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1382 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1385 /* 126 - 5120x2160@60Hz 64:27 */
1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1387 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 /* 127 - 5120x2160@100Hz 64:27 */
1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1392 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1398 * From CEA/CTA-861 spec.
1400 * Do not access directly, instead always use cea_mode_for_vic().
1402 static const struct drm_display_mode edid_cea_modes_193[] = {
1403 /* 193 - 5120x2160@120Hz 64:27 */
1404 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1405 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1407 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1408 /* 194 - 7680x4320@24Hz 16:9 */
1409 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1410 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1412 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1413 /* 195 - 7680x4320@25Hz 16:9 */
1414 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1415 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1417 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1418 /* 196 - 7680x4320@30Hz 16:9 */
1419 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1420 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1423 /* 197 - 7680x4320@48Hz 16:9 */
1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1428 /* 198 - 7680x4320@50Hz 16:9 */
1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1433 /* 199 - 7680x4320@60Hz 16:9 */
1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1438 /* 200 - 7680x4320@100Hz 16:9 */
1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1440 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1443 /* 201 - 7680x4320@120Hz 16:9 */
1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1445 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1448 /* 202 - 7680x4320@24Hz 64:27 */
1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1450 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1453 /* 203 - 7680x4320@25Hz 64:27 */
1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1455 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1458 /* 204 - 7680x4320@30Hz 64:27 */
1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1460 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1463 /* 205 - 7680x4320@48Hz 64:27 */
1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1468 /* 206 - 7680x4320@50Hz 64:27 */
1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1473 /* 207 - 7680x4320@60Hz 64:27 */
1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1478 /* 208 - 7680x4320@100Hz 64:27 */
1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1480 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1483 /* 209 - 7680x4320@120Hz 64:27 */
1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1485 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1488 /* 210 - 10240x4320@24Hz 64:27 */
1489 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1490 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1493 /* 211 - 10240x4320@25Hz 64:27 */
1494 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1495 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1498 /* 212 - 10240x4320@30Hz 64:27 */
1499 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1500 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1503 /* 213 - 10240x4320@48Hz 64:27 */
1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1508 /* 214 - 10240x4320@50Hz 64:27 */
1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1513 /* 215 - 10240x4320@60Hz 64:27 */
1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1518 /* 216 - 10240x4320@100Hz 64:27 */
1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1520 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1523 /* 217 - 10240x4320@120Hz 64:27 */
1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1525 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1528 /* 218 - 4096x2160@100Hz 256:135 */
1529 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1530 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1533 /* 219 - 4096x2160@120Hz 256:135 */
1534 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1535 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1541 * HDMI 1.4 4k modes. Index using the VIC.
1543 static const struct drm_display_mode edid_4k_modes[] = {
1544 /* 0 - dummy, VICs start at 1 */
1546 /* 1 - 3840x2160@30Hz */
1547 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1548 3840, 4016, 4104, 4400, 0,
1549 2160, 2168, 2178, 2250, 0,
1550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1551 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1552 /* 2 - 3840x2160@25Hz */
1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1554 3840, 4896, 4984, 5280, 0,
1555 2160, 2168, 2178, 2250, 0,
1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1558 /* 3 - 3840x2160@24Hz */
1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1560 3840, 5116, 5204, 5500, 0,
1561 2160, 2168, 2178, 2250, 0,
1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1564 /* 4 - 4096x2160@24Hz (SMPTE) */
1565 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1566 4096, 5116, 5204, 5500, 0,
1567 2160, 2168, 2178, 2250, 0,
1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1572 /*** DDC fetch and block validation ***/
1575 * The opaque EDID type, internal to drm_edid.c.
1578 /* Size allocated for edid */
1580 const struct edid *edid;
1583 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1585 static int edid_hfeeodb_block_count(const struct edid *edid)
1587 int eeodb = edid_hfeeodb_extension_block_count(edid);
1589 return eeodb ? eeodb + 1 : 0;
1592 static int edid_extension_block_count(const struct edid *edid)
1594 return edid->extensions;
1597 static int edid_block_count(const struct edid *edid)
1599 return edid_extension_block_count(edid) + 1;
1602 static int edid_size_by_blocks(int num_blocks)
1604 return num_blocks * EDID_LENGTH;
1607 static int edid_size(const struct edid *edid)
1609 return edid_size_by_blocks(edid_block_count(edid));
1612 static const void *edid_block_data(const struct edid *edid, int index)
1614 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1616 return edid + index;
1619 static const void *edid_extension_block_data(const struct edid *edid, int index)
1621 return edid_block_data(edid, index + 1);
1624 /* EDID block count indicated in EDID, may exceed allocated size */
1625 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1629 /* Starting point */
1630 num_blocks = edid_block_count(drm_edid->edid);
1632 /* HF-EEODB override */
1633 if (drm_edid->size >= edid_size_by_blocks(2)) {
1637 * Note: HF-EEODB may specify a smaller extension count than the
1638 * regular one. Unlike in buffer allocation, here we can use it.
1640 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1648 /* EDID block count, limited by allocated size */
1649 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1651 /* Limit by allocated size */
1652 return min(__drm_edid_block_count(drm_edid),
1653 (int)drm_edid->size / EDID_LENGTH);
1656 /* EDID extension block count, limited by allocated size */
1657 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1659 return drm_edid_block_count(drm_edid) - 1;
1662 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1664 return edid_block_data(drm_edid->edid, index);
1667 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1670 return edid_extension_block_data(drm_edid->edid, index);
1674 * Initializer helper for legacy interfaces, where we have no choice but to
1675 * trust edid size. Not for general purpose use.
1677 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1678 const struct edid *edid)
1683 memset(drm_edid, 0, sizeof(*drm_edid));
1685 drm_edid->edid = edid;
1686 drm_edid->size = edid_size(edid);
1692 * EDID base and extension block iterator.
1694 * struct drm_edid_iter iter;
1697 * drm_edid_iter_begin(drm_edid, &iter);
1698 * drm_edid_iter_for_each(block, &iter) {
1699 * // do stuff with block
1701 * drm_edid_iter_end(&iter);
1703 struct drm_edid_iter {
1704 const struct drm_edid *drm_edid;
1706 /* Current block index. */
1710 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1711 struct drm_edid_iter *iter)
1713 memset(iter, 0, sizeof(*iter));
1715 iter->drm_edid = drm_edid;
1718 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1720 const void *block = NULL;
1722 if (!iter->drm_edid)
1725 if (iter->index < drm_edid_block_count(iter->drm_edid))
1726 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1731 #define drm_edid_iter_for_each(__block, __iter) \
1732 while (((__block) = __drm_edid_iter_next(__iter)))
1734 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1736 memset(iter, 0, sizeof(*iter));
1739 static const u8 edid_header[] = {
1740 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1743 static void edid_header_fix(void *edid)
1745 memcpy(edid, edid_header, sizeof(edid_header));
1749 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1750 * @_edid: pointer to raw base EDID block
1752 * Sanity check the header of the base EDID block.
1754 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1756 int drm_edid_header_is_valid(const void *_edid)
1758 const struct edid *edid = _edid;
1761 for (i = 0; i < sizeof(edid_header); i++) {
1762 if (edid->header[i] == edid_header[i])
1768 EXPORT_SYMBOL(drm_edid_header_is_valid);
1770 static int edid_fixup __read_mostly = 6;
1771 module_param_named(edid_fixup, edid_fixup, int, 0400);
1772 MODULE_PARM_DESC(edid_fixup,
1773 "Minimum number of valid EDID header bytes (0-8, default 6)");
1775 static int edid_block_compute_checksum(const void *_block)
1777 const u8 *block = _block;
1779 u8 csum = 0, crc = 0;
1781 for (i = 0; i < EDID_LENGTH - 1; i++)
1789 static int edid_block_get_checksum(const void *_block)
1791 const struct edid *block = _block;
1793 return block->checksum;
1796 static int edid_block_tag(const void *_block)
1798 const u8 *block = _block;
1803 static bool edid_block_is_zero(const void *edid)
1805 return !memchr_inv(edid, 0, EDID_LENGTH);
1809 * drm_edid_are_equal - compare two edid blobs.
1810 * @edid1: pointer to first blob
1811 * @edid2: pointer to second blob
1812 * This helper can be used during probing to determine if
1815 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1817 int edid1_len, edid2_len;
1818 bool edid1_present = edid1 != NULL;
1819 bool edid2_present = edid2 != NULL;
1821 if (edid1_present != edid2_present)
1825 edid1_len = edid_size(edid1);
1826 edid2_len = edid_size(edid2);
1828 if (edid1_len != edid2_len)
1831 if (memcmp(edid1, edid2, edid1_len))
1837 EXPORT_SYMBOL(drm_edid_are_equal);
1839 enum edid_block_status {
1841 EDID_BLOCK_READ_FAIL,
1844 EDID_BLOCK_HEADER_CORRUPT,
1845 EDID_BLOCK_HEADER_REPAIR,
1846 EDID_BLOCK_HEADER_FIXED,
1847 EDID_BLOCK_CHECKSUM,
1851 static enum edid_block_status edid_block_check(const void *_block,
1854 const struct edid *block = _block;
1857 return EDID_BLOCK_NULL;
1859 if (is_base_block) {
1860 int score = drm_edid_header_is_valid(block);
1862 if (score < clamp(edid_fixup, 0, 8)) {
1863 if (edid_block_is_zero(block))
1864 return EDID_BLOCK_ZERO;
1866 return EDID_BLOCK_HEADER_CORRUPT;
1870 return EDID_BLOCK_HEADER_REPAIR;
1873 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1874 if (edid_block_is_zero(block))
1875 return EDID_BLOCK_ZERO;
1877 return EDID_BLOCK_CHECKSUM;
1880 if (is_base_block) {
1881 if (block->version != 1)
1882 return EDID_BLOCK_VERSION;
1885 return EDID_BLOCK_OK;
1888 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1890 return status == EDID_BLOCK_OK ||
1891 status == EDID_BLOCK_HEADER_FIXED ||
1892 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1895 static bool edid_block_valid(const void *block, bool base)
1897 return edid_block_status_valid(edid_block_check(block, base),
1898 edid_block_tag(block));
1901 static void edid_block_status_print(enum edid_block_status status,
1902 const struct edid *block,
1908 case EDID_BLOCK_READ_FAIL:
1909 pr_debug("EDID block %d read failed\n", block_num);
1911 case EDID_BLOCK_NULL:
1912 pr_debug("EDID block %d pointer is NULL\n", block_num);
1914 case EDID_BLOCK_ZERO:
1915 pr_notice("EDID block %d is all zeroes\n", block_num);
1917 case EDID_BLOCK_HEADER_CORRUPT:
1918 pr_notice("EDID has corrupt header\n");
1920 case EDID_BLOCK_HEADER_REPAIR:
1921 pr_debug("EDID corrupt header needs repair\n");
1923 case EDID_BLOCK_HEADER_FIXED:
1924 pr_debug("EDID corrupt header fixed\n");
1926 case EDID_BLOCK_CHECKSUM:
1927 if (edid_block_status_valid(status, edid_block_tag(block))) {
1928 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1929 block_num, edid_block_tag(block),
1930 edid_block_compute_checksum(block));
1932 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1933 block_num, edid_block_tag(block),
1934 edid_block_compute_checksum(block));
1937 case EDID_BLOCK_VERSION:
1938 pr_notice("EDID has major version %d, instead of 1\n",
1942 WARN(1, "EDID block %d unknown edid block status code %d\n",
1948 static void edid_block_dump(const char *level, const void *block, int block_num)
1950 enum edid_block_status status;
1953 status = edid_block_check(block, block_num == 0);
1954 if (status == EDID_BLOCK_ZERO)
1955 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1956 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1957 sprintf(prefix, "\t[%02x] BAD ", block_num);
1959 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1961 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1962 block, EDID_LENGTH, false);
1966 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1967 * @_block: pointer to raw EDID block
1968 * @block_num: type of block to validate (0 for base, extension otherwise)
1969 * @print_bad_edid: if true, dump bad EDID blocks to the console
1970 * @edid_corrupt: if true, the header or checksum is invalid
1972 * Validate a base or extension EDID block and optionally dump bad blocks to
1975 * Return: True if the block is valid, false otherwise.
1977 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1980 struct edid *block = (struct edid *)_block;
1981 enum edid_block_status status;
1982 bool is_base_block = block_num == 0;
1985 if (WARN_ON(!block))
1988 status = edid_block_check(block, is_base_block);
1989 if (status == EDID_BLOCK_HEADER_REPAIR) {
1990 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1991 edid_header_fix(block);
1993 /* Retry with fixed header, update status if that worked. */
1994 status = edid_block_check(block, is_base_block);
1995 if (status == EDID_BLOCK_OK)
1996 status = EDID_BLOCK_HEADER_FIXED;
2001 * Unknown major version isn't corrupt but we can't use it. Only
2002 * the base block can reset edid_corrupt to false.
2004 if (is_base_block &&
2005 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2006 *edid_corrupt = false;
2007 else if (status != EDID_BLOCK_OK)
2008 *edid_corrupt = true;
2011 edid_block_status_print(status, block, block_num);
2013 /* Determine whether we can use this block with this status. */
2014 valid = edid_block_status_valid(status, edid_block_tag(block));
2016 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2017 pr_notice("Raw EDID:\n");
2018 edid_block_dump(KERN_NOTICE, block, block_num);
2023 EXPORT_SYMBOL(drm_edid_block_valid);
2026 * drm_edid_is_valid - sanity check EDID data
2029 * Sanity-check an entire EDID record (including extensions)
2031 * Return: True if the EDID data is valid, false otherwise.
2033 bool drm_edid_is_valid(struct edid *edid)
2040 for (i = 0; i < edid_block_count(edid); i++) {
2041 void *block = (void *)edid_block_data(edid, i);
2043 if (!drm_edid_block_valid(block, i, true, NULL))
2049 EXPORT_SYMBOL(drm_edid_is_valid);
2052 * drm_edid_valid - sanity check EDID data
2053 * @drm_edid: EDID data
2055 * Sanity check an EDID. Cross check block count against allocated size and
2056 * checksum the blocks.
2058 * Return: True if the EDID data is valid, false otherwise.
2060 bool drm_edid_valid(const struct drm_edid *drm_edid)
2067 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2070 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2071 const void *block = drm_edid_block_data(drm_edid, i);
2073 if (!edid_block_valid(block, i == 0))
2079 EXPORT_SYMBOL(drm_edid_valid);
2081 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2085 int i, valid_blocks = 0;
2088 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2089 * back to regular extension count here. We don't want to start
2090 * modifying the HF-EEODB extension too.
2092 for (i = 0; i < edid_block_count(edid); i++) {
2093 const void *src_block = edid_block_data(edid, i);
2095 if (edid_block_valid(src_block, i == 0)) {
2096 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2098 memmove(dst_block, src_block, EDID_LENGTH);
2103 /* We already trusted the base block to be valid here... */
2104 if (WARN_ON(!valid_blocks)) {
2109 edid->extensions = valid_blocks - 1;
2110 edid->checksum = edid_block_compute_checksum(edid);
2112 *alloc_size = edid_size_by_blocks(valid_blocks);
2114 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2121 #define DDC_SEGMENT_ADDR 0x30
2123 * drm_do_probe_ddc_edid() - get EDID information via I2C
2124 * @data: I2C device adapter
2125 * @buf: EDID data buffer to be filled
2126 * @block: 128 byte EDID block to start fetching from
2127 * @len: EDID data buffer length to fetch
2129 * Try to fetch EDID information by calling I2C driver functions.
2131 * Return: 0 on success or -1 on failure.
2134 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2136 struct i2c_adapter *adapter = data;
2137 unsigned char start = block * EDID_LENGTH;
2138 unsigned char segment = block >> 1;
2139 unsigned char xfers = segment ? 3 : 2;
2140 int ret, retries = 5;
2143 * The core I2C driver will automatically retry the transfer if the
2144 * adapter reports EAGAIN. However, we find that bit-banging transfers
2145 * are susceptible to errors under a heavily loaded machine and
2146 * generate spurious NAKs and timeouts. Retrying the transfer
2147 * of the individual block a few times seems to overcome this.
2150 struct i2c_msg msgs[] = {
2152 .addr = DDC_SEGMENT_ADDR,
2170 * Avoid sending the segment addr to not upset non-compliant
2173 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2175 if (ret == -ENXIO) {
2176 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2180 } while (ret != xfers && --retries);
2182 return ret == xfers ? 0 : -1;
2185 static void connector_bad_edid(struct drm_connector *connector,
2186 const struct edid *edid, int num_blocks)
2192 * 0x7e in the EDID is the number of extension blocks. The EDID
2193 * is 1 (base block) + num_ext_blocks big. That means we can think
2194 * of 0x7e in the EDID of the _index_ of the last block in the
2195 * combined chunk of memory.
2197 last_block = edid->extensions;
2199 /* Calculate real checksum for the last edid extension block data */
2200 if (last_block < num_blocks)
2201 connector->real_edid_checksum =
2202 edid_block_compute_checksum(edid + last_block);
2204 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2207 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2208 connector->base.id, connector->name);
2209 for (i = 0; i < num_blocks; i++)
2210 edid_block_dump(KERN_DEBUG, edid + i, i);
2213 /* Get override or firmware EDID */
2214 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2216 const struct drm_edid *override = NULL;
2218 mutex_lock(&connector->edid_override_mutex);
2220 if (connector->edid_override)
2221 override = drm_edid_dup(connector->edid_override);
2223 mutex_unlock(&connector->edid_override_mutex);
2226 override = drm_edid_load_firmware(connector);
2228 return IS_ERR(override) ? NULL : override;
2231 /* For debugfs edid_override implementation */
2232 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2234 const struct drm_edid *drm_edid;
2236 mutex_lock(&connector->edid_override_mutex);
2238 drm_edid = connector->edid_override;
2240 seq_write(m, drm_edid->edid, drm_edid->size);
2242 mutex_unlock(&connector->edid_override_mutex);
2247 /* For debugfs edid_override implementation */
2248 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2251 const struct drm_edid *drm_edid;
2253 drm_edid = drm_edid_alloc(edid, size);
2254 if (!drm_edid_valid(drm_edid)) {
2255 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2256 connector->base.id, connector->name);
2257 drm_edid_free(drm_edid);
2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2262 connector->base.id, connector->name);
2264 mutex_lock(&connector->edid_override_mutex);
2266 drm_edid_free(connector->edid_override);
2267 connector->edid_override = drm_edid;
2269 mutex_unlock(&connector->edid_override_mutex);
2274 /* For debugfs edid_override implementation */
2275 int drm_edid_override_reset(struct drm_connector *connector)
2277 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2278 connector->base.id, connector->name);
2280 mutex_lock(&connector->edid_override_mutex);
2282 drm_edid_free(connector->edid_override);
2283 connector->edid_override = NULL;
2285 mutex_unlock(&connector->edid_override_mutex);
2291 * drm_edid_override_connector_update - add modes from override/firmware EDID
2292 * @connector: connector we're probing
2294 * Add modes from the override/firmware EDID, if available. Only to be used from
2295 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2296 * failed during drm_get_edid() and caused the override/firmware EDID to be
2299 * Return: The number of modes added or 0 if we couldn't find any.
2301 int drm_edid_override_connector_update(struct drm_connector *connector)
2303 const struct drm_edid *override;
2306 override = drm_edid_override_get(connector);
2308 num_modes = drm_edid_connector_update(connector, override);
2310 drm_edid_free(override);
2312 drm_dbg_kms(connector->dev,
2313 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2314 connector->base.id, connector->name, num_modes);
2319 EXPORT_SYMBOL(drm_edid_override_connector_update);
2321 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2323 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2324 read_block_fn read_block,
2327 enum edid_block_status status;
2328 bool is_base_block = block_num == 0;
2331 for (try = 0; try < 4; try++) {
2332 if (read_block(context, block, block_num, EDID_LENGTH))
2333 return EDID_BLOCK_READ_FAIL;
2335 status = edid_block_check(block, is_base_block);
2336 if (status == EDID_BLOCK_HEADER_REPAIR) {
2337 edid_header_fix(block);
2339 /* Retry with fixed header, update status if that worked. */
2340 status = edid_block_check(block, is_base_block);
2341 if (status == EDID_BLOCK_OK)
2342 status = EDID_BLOCK_HEADER_FIXED;
2345 if (edid_block_status_valid(status, edid_block_tag(block)))
2348 /* Fail early for unrepairable base block all zeros. */
2349 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2356 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2357 read_block_fn read_block, void *context,
2360 enum edid_block_status status;
2361 int i, num_blocks, invalid_blocks = 0;
2362 const struct drm_edid *override;
2363 struct edid *edid, *new;
2364 size_t alloc_size = EDID_LENGTH;
2366 override = drm_edid_override_get(connector);
2368 alloc_size = override->size;
2369 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2370 drm_edid_free(override);
2376 edid = kmalloc(alloc_size, GFP_KERNEL);
2380 status = edid_block_read(edid, 0, read_block, context);
2382 edid_block_status_print(status, edid, 0);
2384 if (status == EDID_BLOCK_READ_FAIL)
2387 /* FIXME: Clarify what a corrupt EDID actually means. */
2388 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2389 connector->edid_corrupt = false;
2391 connector->edid_corrupt = true;
2393 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2394 if (status == EDID_BLOCK_ZERO)
2395 connector->null_edid_counter++;
2397 connector_bad_edid(connector, edid, 1);
2401 if (!edid_extension_block_count(edid))
2404 alloc_size = edid_size(edid);
2405 new = krealloc(edid, alloc_size, GFP_KERNEL);
2410 num_blocks = edid_block_count(edid);
2411 for (i = 1; i < num_blocks; i++) {
2412 void *block = (void *)edid_block_data(edid, i);
2414 status = edid_block_read(block, i, read_block, context);
2416 edid_block_status_print(status, block, i);
2418 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2419 if (status == EDID_BLOCK_READ_FAIL)
2422 } else if (i == 1) {
2424 * If the first EDID extension is a CTA extension, and
2425 * the first Data Block is HF-EEODB, override the
2426 * extension block count.
2428 * Note: HF-EEODB could specify a smaller extension
2429 * count too, but we can't risk allocating a smaller
2432 int eeodb = edid_hfeeodb_block_count(edid);
2434 if (eeodb > num_blocks) {
2436 alloc_size = edid_size_by_blocks(num_blocks);
2437 new = krealloc(edid, alloc_size, GFP_KERNEL);
2445 if (invalid_blocks) {
2446 connector_bad_edid(connector, edid, num_blocks);
2448 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2463 * drm_do_get_edid - get EDID data using a custom EDID block read function
2464 * @connector: connector we're probing
2465 * @read_block: EDID block read function
2466 * @context: private data passed to the block read function
2468 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2469 * exposes a different interface to read EDID blocks this function can be used
2470 * to get EDID data using a custom block read function.
2472 * As in the general case the DDC bus is accessible by the kernel at the I2C
2473 * level, drivers must make all reasonable efforts to expose it as an I2C
2474 * adapter and use drm_get_edid() instead of abusing this function.
2476 * The EDID may be overridden using debugfs override_edid or firmware EDID
2477 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2478 * order. Having either of them bypasses actual EDID reads.
2480 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2482 struct edid *drm_do_get_edid(struct drm_connector *connector,
2483 read_block_fn read_block,
2486 return _drm_do_get_edid(connector, read_block, context, NULL);
2488 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2491 * drm_edid_raw - Get a pointer to the raw EDID data.
2492 * @drm_edid: drm_edid container
2494 * Get a pointer to the raw EDID data.
2496 * This is for transition only. Avoid using this like the plague.
2498 * Return: Pointer to raw EDID data.
2500 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2502 if (!drm_edid || !drm_edid->size)
2506 * Do not return pointers where relying on EDID extension count would
2507 * lead to buffer overflow.
2509 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2512 return drm_edid->edid;
2514 EXPORT_SYMBOL(drm_edid_raw);
2516 /* Allocate struct drm_edid container *without* duplicating the edid data */
2517 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2519 struct drm_edid *drm_edid;
2521 if (!edid || !size || size < EDID_LENGTH)
2524 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2526 drm_edid->edid = edid;
2527 drm_edid->size = size;
2534 * drm_edid_alloc - Allocate a new drm_edid container
2535 * @edid: Pointer to raw EDID data
2536 * @size: Size of memory allocated for EDID
2538 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2539 * the actual size that has been allocated for the data. There is no validation
2540 * of the raw EDID data against the size, but at least the EDID base block must
2541 * fit in the buffer.
2543 * The returned pointer must be freed using drm_edid_free().
2545 * Return: drm_edid container, or NULL on errors
2547 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2549 const struct drm_edid *drm_edid;
2551 if (!edid || !size || size < EDID_LENGTH)
2554 edid = kmemdup(edid, size, GFP_KERNEL);
2558 drm_edid = _drm_edid_alloc(edid, size);
2564 EXPORT_SYMBOL(drm_edid_alloc);
2567 * drm_edid_dup - Duplicate a drm_edid container
2568 * @drm_edid: EDID to duplicate
2570 * The returned pointer must be freed using drm_edid_free().
2572 * Returns: drm_edid container copy, or NULL on errors
2574 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2579 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2581 EXPORT_SYMBOL(drm_edid_dup);
2584 * drm_edid_free - Free the drm_edid container
2585 * @drm_edid: EDID to free
2587 void drm_edid_free(const struct drm_edid *drm_edid)
2592 kfree(drm_edid->edid);
2595 EXPORT_SYMBOL(drm_edid_free);
2598 * drm_probe_ddc() - probe DDC presence
2599 * @adapter: I2C adapter to probe
2601 * Return: True on success, false on failure.
2604 drm_probe_ddc(struct i2c_adapter *adapter)
2608 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2610 EXPORT_SYMBOL(drm_probe_ddc);
2613 * drm_get_edid - get EDID data, if available
2614 * @connector: connector we're probing
2615 * @adapter: I2C adapter to use for DDC
2617 * Poke the given I2C channel to grab EDID data if possible. If found,
2618 * attach it to the connector.
2620 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2622 struct edid *drm_get_edid(struct drm_connector *connector,
2623 struct i2c_adapter *adapter)
2627 if (connector->force == DRM_FORCE_OFF)
2630 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2633 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2634 drm_connector_update_edid_property(connector, edid);
2637 EXPORT_SYMBOL(drm_get_edid);
2640 * drm_edid_read_custom - Read EDID data using given EDID block read function
2641 * @connector: Connector to use
2642 * @read_block: EDID block read function
2643 * @context: Private data passed to the block read function
2645 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2646 * exposes a different interface to read EDID blocks this function can be used
2647 * to get EDID data using a custom block read function.
2649 * As in the general case the DDC bus is accessible by the kernel at the I2C
2650 * level, drivers must make all reasonable efforts to expose it as an I2C
2651 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2654 * The EDID may be overridden using debugfs override_edid or firmware EDID
2655 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2656 * order. Having either of them bypasses actual EDID reads.
2658 * The returned pointer must be freed using drm_edid_free().
2660 * Return: Pointer to EDID, or NULL if probe/read failed.
2662 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2663 read_block_fn read_block,
2666 const struct drm_edid *drm_edid;
2670 edid = _drm_do_get_edid(connector, read_block, context, &size);
2674 /* Sanity check for now */
2675 drm_WARN_ON(connector->dev, !size);
2677 drm_edid = _drm_edid_alloc(edid, size);
2683 EXPORT_SYMBOL(drm_edid_read_custom);
2686 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2687 * @connector: Connector to use
2688 * @adapter: I2C adapter to use for DDC
2690 * Read EDID using the given I2C adapter.
2692 * The EDID may be overridden using debugfs override_edid or firmware EDID
2693 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2694 * order. Having either of them bypasses actual EDID reads.
2696 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2697 * using drm_edid_read() instead of this function.
2699 * The returned pointer must be freed using drm_edid_free().
2701 * Return: Pointer to EDID, or NULL if probe/read failed.
2703 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2704 struct i2c_adapter *adapter)
2706 const struct drm_edid *drm_edid;
2708 if (connector->force == DRM_FORCE_OFF)
2711 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2714 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2716 /* Note: Do *not* call connector updates here. */
2720 EXPORT_SYMBOL(drm_edid_read_ddc);
2723 * drm_edid_read - Read EDID data using connector's I2C adapter
2724 * @connector: Connector to use
2726 * Read EDID using the connector's I2C adapter.
2728 * The EDID may be overridden using debugfs override_edid or firmware EDID
2729 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2730 * order. Having either of them bypasses actual EDID reads.
2732 * The returned pointer must be freed using drm_edid_free().
2734 * Return: Pointer to EDID, or NULL if probe/read failed.
2736 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2738 if (drm_WARN_ON(connector->dev, !connector->ddc))
2741 return drm_edid_read_ddc(connector, connector->ddc);
2743 EXPORT_SYMBOL(drm_edid_read);
2745 static u32 edid_extract_panel_id(const struct edid *edid)
2748 * We represent the ID as a 32-bit number so it can easily be compared
2751 * NOTE that we deal with endianness differently for the top half
2752 * of this ID than for the bottom half. The bottom half (the product
2753 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2754 * that's how everyone seems to interpret it. The top half (the mfg_id)
2755 * gets stored as big endian because that makes
2756 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2757 * to write (it's easier to extract the ASCII). It doesn't really
2758 * matter, though, as long as the number here is unique.
2760 return (u32)edid->mfg_id[0] << 24 |
2761 (u32)edid->mfg_id[1] << 16 |
2762 (u32)EDID_PRODUCT_ID(edid);
2766 * drm_edid_get_panel_id - Get a panel's ID through DDC
2767 * @adapter: I2C adapter to use for DDC
2769 * This function reads the first block of the EDID of a panel and (assuming
2770 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2771 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2772 * supposed to be different for each different modem of panel.
2774 * This function is intended to be used during early probing on devices where
2775 * more than one panel might be present. Because of its intended use it must
2776 * assume that the EDID of the panel is correct, at least as far as the ID
2777 * is concerned (in other words, we don't process any overrides here).
2779 * NOTE: it's expected that this function and drm_do_get_edid() will both
2780 * be read the EDID, but there is no caching between them. Since we're only
2781 * reading the first block, hopefully this extra overhead won't be too big.
2783 * Return: A 32-bit ID that should be different for each make/model of panel.
2784 * See the functions drm_edid_encode_panel_id() and
2785 * drm_edid_decode_panel_id() for some details on the structure of this
2789 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2791 enum edid_block_status status;
2796 * There are no manufacturer IDs of 0, so if there is a problem reading
2797 * the EDID then we'll just return 0.
2800 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2804 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2806 edid_block_status_print(status, base_block, 0);
2808 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2809 panel_id = edid_extract_panel_id(base_block);
2811 edid_block_dump(KERN_NOTICE, base_block, 0);
2817 EXPORT_SYMBOL(drm_edid_get_panel_id);
2820 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2821 * @connector: connector we're probing
2822 * @adapter: I2C adapter to use for DDC
2824 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2825 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2826 * switch DDC to the GPU which is retrieving EDID.
2828 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2830 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2831 struct i2c_adapter *adapter)
2833 struct drm_device *dev = connector->dev;
2834 struct pci_dev *pdev = to_pci_dev(dev->dev);
2837 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2840 vga_switcheroo_lock_ddc(pdev);
2841 edid = drm_get_edid(connector, adapter);
2842 vga_switcheroo_unlock_ddc(pdev);
2846 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2849 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2850 * @connector: connector we're probing
2851 * @adapter: I2C adapter to use for DDC
2853 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2854 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2855 * temporarily switch DDC to the GPU which is retrieving EDID.
2857 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2859 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2860 struct i2c_adapter *adapter)
2862 struct drm_device *dev = connector->dev;
2863 struct pci_dev *pdev = to_pci_dev(dev->dev);
2864 const struct drm_edid *drm_edid;
2866 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2869 vga_switcheroo_lock_ddc(pdev);
2870 drm_edid = drm_edid_read_ddc(connector, adapter);
2871 vga_switcheroo_unlock_ddc(pdev);
2875 EXPORT_SYMBOL(drm_edid_read_switcheroo);
2878 * drm_edid_duplicate - duplicate an EDID and the extensions
2879 * @edid: EDID to duplicate
2881 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2883 struct edid *drm_edid_duplicate(const struct edid *edid)
2888 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2890 EXPORT_SYMBOL(drm_edid_duplicate);
2892 /*** EDID parsing ***/
2895 * edid_get_quirks - return quirk flags for a given EDID
2896 * @drm_edid: EDID to process
2898 * This tells subsequent routines what fixes they need to apply.
2900 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2902 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2903 const struct edid_quirk *quirk;
2906 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2907 quirk = &edid_quirk_list[i];
2908 if (quirk->panel_id == panel_id)
2909 return quirk->quirks;
2915 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2916 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2919 * Walk the mode list for connector, clearing the preferred status on existing
2920 * modes and setting it anew for the right mode ala quirks.
2922 static void edid_fixup_preferred(struct drm_connector *connector)
2924 const struct drm_display_info *info = &connector->display_info;
2925 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2926 int target_refresh = 0;
2927 int cur_vrefresh, preferred_vrefresh;
2929 if (list_empty(&connector->probed_modes))
2932 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2933 target_refresh = 60;
2934 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2935 target_refresh = 75;
2937 preferred_mode = list_first_entry(&connector->probed_modes,
2938 struct drm_display_mode, head);
2940 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2941 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2943 if (cur_mode == preferred_mode)
2946 /* Largest mode is preferred */
2947 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2948 preferred_mode = cur_mode;
2950 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2951 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2952 /* At a given size, try to get closest to target refresh */
2953 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2954 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2955 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2956 preferred_mode = cur_mode;
2960 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2964 mode_is_rb(const struct drm_display_mode *mode)
2966 return (mode->htotal - mode->hdisplay == 160) &&
2967 (mode->hsync_end - mode->hdisplay == 80) &&
2968 (mode->hsync_end - mode->hsync_start == 32) &&
2969 (mode->vsync_start - mode->vdisplay == 3);
2973 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2974 * @dev: Device to duplicate against
2975 * @hsize: Mode width
2976 * @vsize: Mode height
2977 * @fresh: Mode refresh rate
2978 * @rb: Mode reduced-blanking-ness
2980 * Walk the DMT mode list looking for a match for the given parameters.
2982 * Return: A newly allocated copy of the mode, or NULL if not found.
2984 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2985 int hsize, int vsize, int fresh,
2990 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2991 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2993 if (hsize != ptr->hdisplay)
2995 if (vsize != ptr->vdisplay)
2997 if (fresh != drm_mode_vrefresh(ptr))
2999 if (rb != mode_is_rb(ptr))
3002 return drm_mode_duplicate(dev, ptr);
3007 EXPORT_SYMBOL(drm_mode_find_dmt);
3009 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3011 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3012 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3013 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3015 return descriptor->pixel_clock == 0 &&
3016 descriptor->data.other_data.pad1 == 0 &&
3017 descriptor->data.other_data.type == type;
3020 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3022 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3024 return descriptor->pixel_clock != 0;
3027 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3030 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3034 const u8 *det_base = ext + d;
3036 if (d < 4 || d > 127)
3040 for (i = 0; i < n; i++)
3041 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3045 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3047 unsigned int i, n = min((int)ext[0x02], 6);
3048 const u8 *det_base = ext + 5;
3051 return; /* unknown version */
3053 for (i = 0; i < n; i++)
3054 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3057 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3058 detailed_cb *cb, void *closure)
3060 struct drm_edid_iter edid_iter;
3067 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3068 cb(&drm_edid->edid->detailed_timings[i], closure);
3070 drm_edid_iter_begin(drm_edid, &edid_iter);
3071 drm_edid_iter_for_each(ext, &edid_iter) {
3074 cea_for_each_detailed_block(ext, cb, closure);
3077 vtb_for_each_detailed_block(ext, cb, closure);
3083 drm_edid_iter_end(&edid_iter);
3087 is_rb(const struct detailed_timing *descriptor, void *data)
3091 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3094 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3095 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3097 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3098 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3102 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3104 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3106 if (drm_edid->edid->revision >= 4) {
3109 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3113 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
3117 find_gtf2(const struct detailed_timing *descriptor, void *data)
3119 const struct detailed_timing **res = data;
3121 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3124 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3126 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3130 /* Secondary GTF curve kicks in above some break frequency */
3132 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3134 const struct detailed_timing *descriptor = NULL;
3136 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3138 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3140 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3144 drm_gtf2_2c(const struct drm_edid *drm_edid)
3146 const struct detailed_timing *descriptor = NULL;
3148 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3150 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3152 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3156 drm_gtf2_m(const struct drm_edid *drm_edid)
3158 const struct detailed_timing *descriptor = NULL;
3160 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3162 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3164 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3168 drm_gtf2_k(const struct drm_edid *drm_edid)
3170 const struct detailed_timing *descriptor = NULL;
3172 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3174 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3176 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3180 drm_gtf2_2j(const struct drm_edid *drm_edid)
3182 const struct detailed_timing *descriptor = NULL;
3184 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3186 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3188 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3192 get_timing_level(const struct detailed_timing *descriptor, void *data)
3196 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3199 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3201 switch (descriptor->data.other_data.data.range.flags) {
3202 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3205 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3208 case DRM_EDID_CVT_SUPPORT_FLAG:
3216 /* Get standard timing level (CVT/GTF/DMT). */
3217 static int standard_timing_level(const struct drm_edid *drm_edid)
3219 const struct edid *edid = drm_edid->edid;
3221 if (edid->revision >= 4) {
3223 * If the range descriptor doesn't
3224 * indicate otherwise default to CVT
3226 int ret = LEVEL_CVT;
3228 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3231 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3233 } else if (edid->revision >= 2) {
3241 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3242 * monitors fill with ascii space (0x20) instead.
3245 bad_std_timing(u8 a, u8 b)
3247 return (a == 0x00 && b == 0x00) ||
3248 (a == 0x01 && b == 0x01) ||
3249 (a == 0x20 && b == 0x20);
3252 static int drm_mode_hsync(const struct drm_display_mode *mode)
3254 if (mode->htotal <= 0)
3257 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3260 static struct drm_display_mode *
3261 drm_gtf2_mode(struct drm_device *dev,
3262 const struct drm_edid *drm_edid,
3263 int hsize, int vsize, int vrefresh_rate)
3265 struct drm_display_mode *mode;
3268 * This is potentially wrong if there's ever a monitor with
3269 * more than one ranges section, each claiming a different
3270 * secondary GTF curve. Please don't do that.
3272 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3276 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3277 drm_mode_destroy(dev, mode);
3278 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3279 vrefresh_rate, 0, 0,
3280 drm_gtf2_m(drm_edid),
3281 drm_gtf2_2c(drm_edid),
3282 drm_gtf2_k(drm_edid),
3283 drm_gtf2_2j(drm_edid));
3290 * Take the standard timing params (in this case width, aspect, and refresh)
3291 * and convert them into a real mode using CVT/GTF/DMT.
3293 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3294 const struct drm_edid *drm_edid,
3295 const struct std_timing *t)
3297 struct drm_device *dev = connector->dev;
3298 struct drm_display_mode *m, *mode = NULL;
3301 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3302 >> EDID_TIMING_ASPECT_SHIFT;
3303 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3304 >> EDID_TIMING_VFREQ_SHIFT;
3305 int timing_level = standard_timing_level(drm_edid);
3307 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3310 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3311 hsize = t->hsize * 8 + 248;
3312 /* vrefresh_rate = vfreq + 60 */
3313 vrefresh_rate = vfreq + 60;
3314 /* the vdisplay is calculated based on the aspect ratio */
3315 if (aspect_ratio == 0) {
3316 if (drm_edid->edid->revision < 3)
3319 vsize = (hsize * 10) / 16;
3320 } else if (aspect_ratio == 1)
3321 vsize = (hsize * 3) / 4;
3322 else if (aspect_ratio == 2)
3323 vsize = (hsize * 4) / 5;
3325 vsize = (hsize * 9) / 16;
3327 /* HDTV hack, part 1 */
3328 if (vrefresh_rate == 60 &&
3329 ((hsize == 1360 && vsize == 765) ||
3330 (hsize == 1368 && vsize == 769))) {
3336 * If this connector already has a mode for this size and refresh
3337 * rate (because it came from detailed or CVT info), use that
3338 * instead. This way we don't have to guess at interlace or
3341 list_for_each_entry(m, &connector->probed_modes, head)
3342 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3343 drm_mode_vrefresh(m) == vrefresh_rate)
3346 /* HDTV hack, part 2 */
3347 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3348 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3352 mode->hdisplay = 1366;
3353 mode->hsync_start = mode->hsync_start - 1;
3354 mode->hsync_end = mode->hsync_end - 1;
3358 /* check whether it can be found in default mode table */
3359 if (drm_monitor_supports_rb(drm_edid)) {
3360 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3365 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3369 /* okay, generate it */
3370 switch (timing_level) {
3374 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3377 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3380 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3388 * EDID is delightfully ambiguous about how interlaced modes are to be
3389 * encoded. Our internal representation is of frame height, but some
3390 * HDTV detailed timings are encoded as field height.
3392 * The format list here is from CEA, in frame size. Technically we
3393 * should be checking refresh rate too. Whatever.
3396 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3397 const struct detailed_pixel_timing *pt)
3400 static const struct {
3402 } cea_interlaced[] = {
3412 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3415 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3416 if ((mode->hdisplay == cea_interlaced[i].w) &&
3417 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3418 mode->vdisplay *= 2;
3419 mode->vsync_start *= 2;
3420 mode->vsync_end *= 2;
3426 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3430 * Create a new mode from an EDID detailed timing section. An EDID detailed
3431 * timing block contains enough info for us to create and return a new struct
3434 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3435 const struct drm_edid *drm_edid,
3436 const struct detailed_timing *timing)
3438 const struct drm_display_info *info = &connector->display_info;
3439 struct drm_device *dev = connector->dev;
3440 struct drm_display_mode *mode;
3441 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3442 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3443 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3444 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3445 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3446 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3447 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3448 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3449 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3451 /* ignore tiny modes */
3452 if (hactive < 64 || vactive < 64)
3455 if (pt->misc & DRM_EDID_PT_STEREO) {
3456 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3457 connector->base.id, connector->name);
3461 /* it is incorrect if hsync/vsync width is zero */
3462 if (!hsync_pulse_width || !vsync_pulse_width) {
3463 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3464 connector->base.id, connector->name);
3468 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3469 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3476 mode = drm_mode_create(dev);
3480 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3481 mode->clock = 1088 * 10;
3483 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3485 mode->hdisplay = hactive;
3486 mode->hsync_start = mode->hdisplay + hsync_offset;
3487 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3488 mode->htotal = mode->hdisplay + hblank;
3490 mode->vdisplay = vactive;
3491 mode->vsync_start = mode->vdisplay + vsync_offset;
3492 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3493 mode->vtotal = mode->vdisplay + vblank;
3495 /* Some EDIDs have bogus h/vtotal values */
3496 if (mode->hsync_end > mode->htotal)
3497 mode->htotal = mode->hsync_end + 1;
3498 if (mode->vsync_end > mode->vtotal)
3499 mode->vtotal = mode->vsync_end + 1;
3501 drm_mode_do_interlace_quirk(mode, pt);
3503 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3504 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3506 switch (pt->misc & DRM_EDID_PT_SYNC_MASK) {
3507 case DRM_EDID_PT_ANALOG_CSYNC:
3508 case DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC:
3509 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Analog composite sync!\n",
3510 connector->base.id, connector->name);
3511 mode->flags |= DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_NCSYNC;
3513 case DRM_EDID_PT_DIGITAL_CSYNC:
3514 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Digital composite sync!\n",
3515 connector->base.id, connector->name);
3516 mode->flags |= DRM_MODE_FLAG_CSYNC;
3517 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3518 DRM_MODE_FLAG_PCSYNC : DRM_MODE_FLAG_NCSYNC;
3520 case DRM_EDID_PT_DIGITAL_SEPARATE_SYNC:
3521 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3522 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3523 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3524 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3530 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3531 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3533 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3534 mode->width_mm *= 10;
3535 mode->height_mm *= 10;
3538 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3539 mode->width_mm = drm_edid->edid->width_cm * 10;
3540 mode->height_mm = drm_edid->edid->height_cm * 10;
3543 mode->type = DRM_MODE_TYPE_DRIVER;
3544 drm_mode_set_name(mode);
3550 mode_in_hsync_range(const struct drm_display_mode *mode,
3551 const struct edid *edid, const u8 *t)
3553 int hsync, hmin, hmax;
3556 if (edid->revision >= 4)
3557 hmin += ((t[4] & 0x04) ? 255 : 0);
3559 if (edid->revision >= 4)
3560 hmax += ((t[4] & 0x08) ? 255 : 0);
3561 hsync = drm_mode_hsync(mode);
3563 return (hsync <= hmax && hsync >= hmin);
3567 mode_in_vsync_range(const struct drm_display_mode *mode,
3568 const struct edid *edid, const u8 *t)
3570 int vsync, vmin, vmax;
3573 if (edid->revision >= 4)
3574 vmin += ((t[4] & 0x01) ? 255 : 0);
3576 if (edid->revision >= 4)
3577 vmax += ((t[4] & 0x02) ? 255 : 0);
3578 vsync = drm_mode_vrefresh(mode);
3580 return (vsync <= vmax && vsync >= vmin);
3584 range_pixel_clock(const struct edid *edid, const u8 *t)
3587 if (t[9] == 0 || t[9] == 255)
3590 /* 1.4 with CVT support gives us real precision, yay */
3591 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3592 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3594 /* 1.3 is pathetic, so fuzz up a bit */
3595 return t[9] * 10000 + 5001;
3598 static bool mode_in_range(const struct drm_display_mode *mode,
3599 const struct drm_edid *drm_edid,
3600 const struct detailed_timing *timing)
3602 const struct edid *edid = drm_edid->edid;
3604 const u8 *t = (const u8 *)timing;
3606 if (!mode_in_hsync_range(mode, edid, t))
3609 if (!mode_in_vsync_range(mode, edid, t))
3612 if ((max_clock = range_pixel_clock(edid, t)))
3613 if (mode->clock > max_clock)
3616 /* 1.4 max horizontal check */
3617 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3618 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3621 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3627 static bool valid_inferred_mode(const struct drm_connector *connector,
3628 const struct drm_display_mode *mode)
3630 const struct drm_display_mode *m;
3633 list_for_each_entry(m, &connector->probed_modes, head) {
3634 if (mode->hdisplay == m->hdisplay &&
3635 mode->vdisplay == m->vdisplay &&
3636 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3637 return false; /* duplicated */
3638 if (mode->hdisplay <= m->hdisplay &&
3639 mode->vdisplay <= m->vdisplay)
3645 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3646 const struct drm_edid *drm_edid,
3647 const struct detailed_timing *timing)
3650 struct drm_display_mode *newmode;
3651 struct drm_device *dev = connector->dev;
3653 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3654 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3655 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3656 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3658 drm_mode_probed_add(connector, newmode);
3667 /* fix up 1366x768 mode from 1368x768;
3668 * GFT/CVT can't express 1366 width which isn't dividable by 8
3670 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3672 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3673 mode->hdisplay = 1366;
3674 mode->hsync_start--;
3676 drm_mode_set_name(mode);
3680 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3681 const struct drm_edid *drm_edid,
3682 const struct detailed_timing *timing)
3685 struct drm_display_mode *newmode;
3686 struct drm_device *dev = connector->dev;
3688 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3689 const struct minimode *m = &extra_modes[i];
3691 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3695 drm_mode_fixup_1366x768(newmode);
3696 if (!mode_in_range(newmode, drm_edid, timing) ||
3697 !valid_inferred_mode(connector, newmode)) {
3698 drm_mode_destroy(dev, newmode);
3702 drm_mode_probed_add(connector, newmode);
3709 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3710 const struct drm_edid *drm_edid,
3711 const struct detailed_timing *timing)
3714 struct drm_display_mode *newmode;
3715 struct drm_device *dev = connector->dev;
3717 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3718 const struct minimode *m = &extra_modes[i];
3720 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3724 drm_mode_fixup_1366x768(newmode);
3725 if (!mode_in_range(newmode, drm_edid, timing) ||
3726 !valid_inferred_mode(connector, newmode)) {
3727 drm_mode_destroy(dev, newmode);
3731 drm_mode_probed_add(connector, newmode);
3738 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3739 const struct drm_edid *drm_edid,
3740 const struct detailed_timing *timing)
3743 struct drm_display_mode *newmode;
3744 struct drm_device *dev = connector->dev;
3745 bool rb = drm_monitor_supports_rb(drm_edid);
3747 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3748 const struct minimode *m = &extra_modes[i];
3750 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3754 drm_mode_fixup_1366x768(newmode);
3755 if (!mode_in_range(newmode, drm_edid, timing) ||
3756 !valid_inferred_mode(connector, newmode)) {
3757 drm_mode_destroy(dev, newmode);
3761 drm_mode_probed_add(connector, newmode);
3769 do_inferred_modes(const struct detailed_timing *timing, void *c)
3771 struct detailed_mode_closure *closure = c;
3772 const struct detailed_non_pixel *data = &timing->data.other_data;
3773 const struct detailed_data_monitor_range *range = &data->data.range;
3775 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3778 closure->modes += drm_dmt_modes_for_range(closure->connector,
3782 if (closure->drm_edid->edid->revision < 2)
3783 return; /* GTF not defined yet */
3785 switch (range->flags) {
3786 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3787 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3791 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3792 closure->modes += drm_gtf_modes_for_range(closure->connector,
3796 case DRM_EDID_CVT_SUPPORT_FLAG:
3797 if (closure->drm_edid->edid->revision < 4)
3800 closure->modes += drm_cvt_modes_for_range(closure->connector,
3804 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3810 static int add_inferred_modes(struct drm_connector *connector,
3811 const struct drm_edid *drm_edid)
3813 struct detailed_mode_closure closure = {
3814 .connector = connector,
3815 .drm_edid = drm_edid,
3818 if (drm_edid->edid->revision >= 1)
3819 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3821 return closure.modes;
3825 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3827 int i, j, m, modes = 0;
3828 struct drm_display_mode *mode;
3829 const u8 *est = ((const u8 *)timing) + 6;
3831 for (i = 0; i < 6; i++) {
3832 for (j = 7; j >= 0; j--) {
3833 m = (i * 8) + (7 - j);
3834 if (m >= ARRAY_SIZE(est3_modes))
3836 if (est[i] & (1 << j)) {
3837 mode = drm_mode_find_dmt(connector->dev,
3843 drm_mode_probed_add(connector, mode);
3854 do_established_modes(const struct detailed_timing *timing, void *c)
3856 struct detailed_mode_closure *closure = c;
3858 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3861 closure->modes += drm_est3_modes(closure->connector, timing);
3865 * Get established modes from EDID and add them. Each EDID block contains a
3866 * bitmap of the supported "established modes" list (defined above). Tease them
3867 * out and add them to the global modes list.
3869 static int add_established_modes(struct drm_connector *connector,
3870 const struct drm_edid *drm_edid)
3872 struct drm_device *dev = connector->dev;
3873 const struct edid *edid = drm_edid->edid;
3874 unsigned long est_bits = edid->established_timings.t1 |
3875 (edid->established_timings.t2 << 8) |
3876 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3878 struct detailed_mode_closure closure = {
3879 .connector = connector,
3880 .drm_edid = drm_edid,
3883 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3884 if (est_bits & (1<<i)) {
3885 struct drm_display_mode *newmode;
3887 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3889 drm_mode_probed_add(connector, newmode);
3895 if (edid->revision >= 1)
3896 drm_for_each_detailed_block(drm_edid, do_established_modes,
3899 return modes + closure.modes;
3903 do_standard_modes(const struct detailed_timing *timing, void *c)
3905 struct detailed_mode_closure *closure = c;
3906 const struct detailed_non_pixel *data = &timing->data.other_data;
3907 struct drm_connector *connector = closure->connector;
3910 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3913 for (i = 0; i < 6; i++) {
3914 const struct std_timing *std = &data->data.timings[i];
3915 struct drm_display_mode *newmode;
3917 newmode = drm_mode_std(connector, closure->drm_edid, std);
3919 drm_mode_probed_add(connector, newmode);
3926 * Get standard modes from EDID and add them. Standard modes can be calculated
3927 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3928 * add them to the list.
3930 static int add_standard_modes(struct drm_connector *connector,
3931 const struct drm_edid *drm_edid)
3934 struct detailed_mode_closure closure = {
3935 .connector = connector,
3936 .drm_edid = drm_edid,
3939 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3940 struct drm_display_mode *newmode;
3942 newmode = drm_mode_std(connector, drm_edid,
3943 &drm_edid->edid->standard_timings[i]);
3945 drm_mode_probed_add(connector, newmode);
3950 if (drm_edid->edid->revision >= 1)
3951 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3954 /* XXX should also look for standard codes in VTB blocks */
3956 return modes + closure.modes;
3959 static int drm_cvt_modes(struct drm_connector *connector,
3960 const struct detailed_timing *timing)
3962 int i, j, modes = 0;
3963 struct drm_display_mode *newmode;
3964 struct drm_device *dev = connector->dev;
3965 const struct cvt_timing *cvt;
3966 static const int rates[] = { 60, 85, 75, 60, 50 };
3967 const u8 empty[3] = { 0, 0, 0 };
3969 for (i = 0; i < 4; i++) {
3972 cvt = &(timing->data.other_data.data.cvt[i]);
3974 if (!memcmp(cvt->code, empty, 3))
3977 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3978 switch (cvt->code[1] & 0x0c) {
3979 /* default - because compiler doesn't see that we've enumerated all cases */
3982 width = height * 4 / 3;
3985 width = height * 16 / 9;
3988 width = height * 16 / 10;
3991 width = height * 15 / 9;
3995 for (j = 1; j < 5; j++) {
3996 if (cvt->code[2] & (1 << j)) {
3997 newmode = drm_cvt_mode(dev, width, height,
4001 drm_mode_probed_add(connector, newmode);
4012 do_cvt_mode(const struct detailed_timing *timing, void *c)
4014 struct detailed_mode_closure *closure = c;
4016 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4019 closure->modes += drm_cvt_modes(closure->connector, timing);
4023 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4025 struct detailed_mode_closure closure = {
4026 .connector = connector,
4027 .drm_edid = drm_edid,
4030 if (drm_edid->edid->revision >= 3)
4031 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4033 /* XXX should also look for CVT codes in VTB blocks */
4035 return closure.modes;
4038 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4039 struct drm_display_mode *mode);
4042 do_detailed_mode(const struct detailed_timing *timing, void *c)
4044 struct detailed_mode_closure *closure = c;
4045 struct drm_display_mode *newmode;
4047 if (!is_detailed_timing_descriptor(timing))
4050 newmode = drm_mode_detailed(closure->connector,
4051 closure->drm_edid, timing);
4055 if (closure->preferred)
4056 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4059 * Detailed modes are limited to 10kHz pixel clock resolution,
4060 * so fix up anything that looks like CEA/HDMI mode, but the clock
4061 * is just slightly off.
4063 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4065 drm_mode_probed_add(closure->connector, newmode);
4067 closure->preferred = false;
4071 * add_detailed_modes - Add modes from detailed timings
4072 * @connector: attached connector
4073 * @drm_edid: EDID block to scan
4075 static int add_detailed_modes(struct drm_connector *connector,
4076 const struct drm_edid *drm_edid)
4078 struct detailed_mode_closure closure = {
4079 .connector = connector,
4080 .drm_edid = drm_edid,
4083 if (drm_edid->edid->revision >= 4)
4084 closure.preferred = true; /* first detailed timing is always preferred */
4087 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4089 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4091 return closure.modes;
4094 /* CTA-861-H Table 60 - CTA Tag Codes */
4095 #define CTA_DB_AUDIO 1
4096 #define CTA_DB_VIDEO 2
4097 #define CTA_DB_VENDOR 3
4098 #define CTA_DB_SPEAKER 4
4099 #define CTA_DB_EXTENDED_TAG 7
4101 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4102 #define CTA_EXT_DB_VIDEO_CAP 0
4103 #define CTA_EXT_DB_VENDOR 1
4104 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4105 #define CTA_EXT_DB_420_VIDEO_DATA 14
4106 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4107 #define CTA_EXT_DB_HF_EEODB 0x78
4108 #define CTA_EXT_DB_HF_SCDB 0x79
4110 #define EDID_BASIC_AUDIO (1 << 6)
4111 #define EDID_CEA_YCRCB444 (1 << 5)
4112 #define EDID_CEA_YCRCB422 (1 << 4)
4113 #define EDID_CEA_VCDB_QS (1 << 6)
4116 * Search EDID for CEA extension block.
4118 * FIXME: Prefer not returning pointers to raw EDID data.
4120 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4121 int ext_id, int *ext_index)
4123 const u8 *edid_ext = NULL;
4126 /* No EDID or EDID extensions */
4127 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4130 /* Find CEA extension */
4131 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4132 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4133 if (edid_block_tag(edid_ext) == ext_id)
4137 if (i >= drm_edid_extension_block_count(drm_edid))
4145 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4146 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4148 const struct displayid_block *block;
4149 struct displayid_iter iter;
4153 /* Look for a top level CEA extension block */
4154 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4157 /* CEA blocks can also be found embedded in a DisplayID block */
4158 displayid_iter_edid_begin(drm_edid, &iter);
4159 displayid_iter_for_each(block, &iter) {
4160 if (block->tag == DATA_BLOCK_CTA) {
4165 displayid_iter_end(&iter);
4170 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4172 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4173 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4175 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4176 return &edid_cea_modes_1[vic - 1];
4177 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4178 return &edid_cea_modes_193[vic - 193];
4182 static u8 cea_num_vics(void)
4184 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4187 static u8 cea_next_vic(u8 vic)
4189 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4195 * Calculate the alternate clock for the CEA mode
4196 * (60Hz vs. 59.94Hz etc.)
4199 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4201 unsigned int clock = cea_mode->clock;
4203 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4207 * edid_cea_modes contains the 59.94Hz
4208 * variant for 240 and 480 line modes,
4209 * and the 60Hz variant otherwise.
4211 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4212 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4214 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4220 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4223 * For certain VICs the spec allows the vertical
4224 * front porch to vary by one or two lines.
4226 * cea_modes[] stores the variant with the shortest
4227 * vertical front porch. We can adjust the mode to
4228 * get the other variants by simply increasing the
4229 * vertical front porch length.
4231 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4232 cea_mode_for_vic(9)->vtotal != 262 ||
4233 cea_mode_for_vic(12)->vtotal != 262 ||
4234 cea_mode_for_vic(13)->vtotal != 262 ||
4235 cea_mode_for_vic(23)->vtotal != 312 ||
4236 cea_mode_for_vic(24)->vtotal != 312 ||
4237 cea_mode_for_vic(27)->vtotal != 312 ||
4238 cea_mode_for_vic(28)->vtotal != 312);
4240 if (((vic == 8 || vic == 9 ||
4241 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4242 ((vic == 23 || vic == 24 ||
4243 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4244 mode->vsync_start++;
4254 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4255 unsigned int clock_tolerance)
4257 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4260 if (!to_match->clock)
4263 if (to_match->picture_aspect_ratio)
4264 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4266 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4267 struct drm_display_mode cea_mode;
4268 unsigned int clock1, clock2;
4270 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4272 /* Check both 60Hz and 59.94Hz */
4273 clock1 = cea_mode.clock;
4274 clock2 = cea_mode_alternate_clock(&cea_mode);
4276 if (abs(to_match->clock - clock1) > clock_tolerance &&
4277 abs(to_match->clock - clock2) > clock_tolerance)
4281 if (drm_mode_match(to_match, &cea_mode, match_flags))
4283 } while (cea_mode_alternate_timings(vic, &cea_mode));
4290 * drm_match_cea_mode - look for a CEA mode matching given mode
4291 * @to_match: display mode
4293 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4296 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4298 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4301 if (!to_match->clock)
4304 if (to_match->picture_aspect_ratio)
4305 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4307 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4308 struct drm_display_mode cea_mode;
4309 unsigned int clock1, clock2;
4311 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4313 /* Check both 60Hz and 59.94Hz */
4314 clock1 = cea_mode.clock;
4315 clock2 = cea_mode_alternate_clock(&cea_mode);
4317 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4318 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4322 if (drm_mode_match(to_match, &cea_mode, match_flags))
4324 } while (cea_mode_alternate_timings(vic, &cea_mode));
4329 EXPORT_SYMBOL(drm_match_cea_mode);
4331 static bool drm_valid_cea_vic(u8 vic)
4333 return cea_mode_for_vic(vic) != NULL;
4336 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4338 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4341 return mode->picture_aspect_ratio;
4343 return HDMI_PICTURE_ASPECT_NONE;
4346 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4348 return edid_4k_modes[video_code].picture_aspect_ratio;
4352 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4356 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4358 return cea_mode_alternate_clock(hdmi_mode);
4361 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4362 unsigned int clock_tolerance)
4364 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4367 if (!to_match->clock)
4370 if (to_match->picture_aspect_ratio)
4371 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4373 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4374 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4375 unsigned int clock1, clock2;
4377 /* Make sure to also match alternate clocks */
4378 clock1 = hdmi_mode->clock;
4379 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4381 if (abs(to_match->clock - clock1) > clock_tolerance &&
4382 abs(to_match->clock - clock2) > clock_tolerance)
4385 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4393 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4394 * @to_match: display mode
4396 * An HDMI mode is one defined in the HDMI vendor specific block.
4398 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4400 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4402 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4405 if (!to_match->clock)
4408 if (to_match->picture_aspect_ratio)
4409 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4411 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4412 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4413 unsigned int clock1, clock2;
4415 /* Make sure to also match alternate clocks */
4416 clock1 = hdmi_mode->clock;
4417 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4419 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4420 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4421 drm_mode_match(to_match, hdmi_mode, match_flags))
4427 static bool drm_valid_hdmi_vic(u8 vic)
4429 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4432 static int add_alternate_cea_modes(struct drm_connector *connector,
4433 const struct drm_edid *drm_edid)
4435 struct drm_device *dev = connector->dev;
4436 struct drm_display_mode *mode, *tmp;
4440 /* Don't add CTA modes if the CTA extension block is missing */
4441 if (!drm_edid_has_cta_extension(drm_edid))
4445 * Go through all probed modes and create a new mode
4446 * with the alternate clock for certain CEA modes.
4448 list_for_each_entry(mode, &connector->probed_modes, head) {
4449 const struct drm_display_mode *cea_mode = NULL;
4450 struct drm_display_mode *newmode;
4451 u8 vic = drm_match_cea_mode(mode);
4452 unsigned int clock1, clock2;
4454 if (drm_valid_cea_vic(vic)) {
4455 cea_mode = cea_mode_for_vic(vic);
4456 clock2 = cea_mode_alternate_clock(cea_mode);
4458 vic = drm_match_hdmi_mode(mode);
4459 if (drm_valid_hdmi_vic(vic)) {
4460 cea_mode = &edid_4k_modes[vic];
4461 clock2 = hdmi_mode_alternate_clock(cea_mode);
4468 clock1 = cea_mode->clock;
4470 if (clock1 == clock2)
4473 if (mode->clock != clock1 && mode->clock != clock2)
4476 newmode = drm_mode_duplicate(dev, cea_mode);
4480 /* Carry over the stereo flags */
4481 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4484 * The current mode could be either variant. Make
4485 * sure to pick the "other" clock for the new mode.
4487 if (mode->clock != clock1)
4488 newmode->clock = clock1;
4490 newmode->clock = clock2;
4492 list_add_tail(&newmode->head, &list);
4495 list_for_each_entry_safe(mode, tmp, &list, head) {
4496 list_del(&mode->head);
4497 drm_mode_probed_add(connector, mode);
4504 static u8 svd_to_vic(u8 svd)
4506 /* 0-6 bit vic, 7th bit native mode indicator */
4507 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4514 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4515 * the EDID, or NULL on errors.
4517 static struct drm_display_mode *
4518 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4520 const struct drm_display_info *info = &connector->display_info;
4521 struct drm_device *dev = connector->dev;
4523 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4526 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4530 * do_y420vdb_modes - Parse YCBCR 420 only modes
4531 * @connector: connector corresponding to the HDMI sink
4532 * @svds: start of the data block of CEA YCBCR 420 VDB
4533 * @len: length of the CEA YCBCR 420 VDB
4535 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4536 * which contains modes which can be supported in YCBCR 420
4537 * output format only.
4539 static int do_y420vdb_modes(struct drm_connector *connector,
4540 const u8 *svds, u8 svds_len)
4542 struct drm_device *dev = connector->dev;
4545 for (i = 0; i < svds_len; i++) {
4546 u8 vic = svd_to_vic(svds[i]);
4547 struct drm_display_mode *newmode;
4549 if (!drm_valid_cea_vic(vic))
4552 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4555 drm_mode_probed_add(connector, newmode);
4563 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4565 * @video_code: CEA VIC of the mode
4567 * Creates a new mode matching the specified CEA VIC.
4569 * Returns: A new drm_display_mode on success or NULL on failure
4571 struct drm_display_mode *
4572 drm_display_mode_from_cea_vic(struct drm_device *dev,
4575 const struct drm_display_mode *cea_mode;
4576 struct drm_display_mode *newmode;
4578 cea_mode = cea_mode_for_vic(video_code);
4582 newmode = drm_mode_duplicate(dev, cea_mode);
4588 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4590 /* Add modes based on VICs parsed in parse_cta_vdb() */
4591 static int add_cta_vdb_modes(struct drm_connector *connector)
4593 const struct drm_display_info *info = &connector->display_info;
4599 for (i = 0; i < info->vics_len; i++) {
4600 struct drm_display_mode *mode;
4602 mode = drm_display_mode_from_vic_index(connector, i);
4604 drm_mode_probed_add(connector, mode);
4612 struct stereo_mandatory_mode {
4613 int width, height, vrefresh;
4617 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4618 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4619 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4621 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4623 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4624 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4625 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4626 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4627 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4631 stereo_match_mandatory(const struct drm_display_mode *mode,
4632 const struct stereo_mandatory_mode *stereo_mode)
4634 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4636 return mode->hdisplay == stereo_mode->width &&
4637 mode->vdisplay == stereo_mode->height &&
4638 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4639 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4642 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4644 struct drm_device *dev = connector->dev;
4645 const struct drm_display_mode *mode;
4646 struct list_head stereo_modes;
4649 INIT_LIST_HEAD(&stereo_modes);
4651 list_for_each_entry(mode, &connector->probed_modes, head) {
4652 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4653 const struct stereo_mandatory_mode *mandatory;
4654 struct drm_display_mode *new_mode;
4656 if (!stereo_match_mandatory(mode,
4657 &stereo_mandatory_modes[i]))
4660 mandatory = &stereo_mandatory_modes[i];
4661 new_mode = drm_mode_duplicate(dev, mode);
4665 new_mode->flags |= mandatory->flags;
4666 list_add_tail(&new_mode->head, &stereo_modes);
4671 list_splice_tail(&stereo_modes, &connector->probed_modes);
4676 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4678 struct drm_device *dev = connector->dev;
4679 struct drm_display_mode *newmode;
4681 if (!drm_valid_hdmi_vic(vic)) {
4682 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4683 connector->base.id, connector->name, vic);
4687 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4691 drm_mode_probed_add(connector, newmode);
4696 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4699 struct drm_display_mode *newmode;
4702 if (structure & (1 << 0)) {
4703 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4705 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4706 drm_mode_probed_add(connector, newmode);
4710 if (structure & (1 << 6)) {
4711 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4713 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4714 drm_mode_probed_add(connector, newmode);
4718 if (structure & (1 << 8)) {
4719 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4721 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4722 drm_mode_probed_add(connector, newmode);
4730 static bool hdmi_vsdb_latency_present(const u8 *db)
4732 return db[8] & BIT(7);
4735 static bool hdmi_vsdb_i_latency_present(const u8 *db)
4737 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4740 static int hdmi_vsdb_latency_length(const u8 *db)
4742 if (hdmi_vsdb_i_latency_present(db))
4744 else if (hdmi_vsdb_latency_present(db))
4751 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4752 * @connector: connector corresponding to the HDMI sink
4753 * @db: start of the CEA vendor specific block
4754 * @len: length of the CEA block payload, ie. one can access up to db[len]
4756 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4757 * also adds the stereo 3d modes when applicable.
4760 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4762 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4763 u8 vic_len, hdmi_3d_len = 0;
4770 /* no HDMI_Video_Present */
4771 if (!(db[8] & (1 << 5)))
4774 offset += hdmi_vsdb_latency_length(db);
4776 /* the declared length is not long enough for the 2 first bytes
4777 * of additional video format capabilities */
4778 if (len < (8 + offset + 2))
4783 if (db[8 + offset] & (1 << 7)) {
4784 modes += add_hdmi_mandatory_stereo_modes(connector);
4786 /* 3D_Multi_present */
4787 multi_present = (db[8 + offset] & 0x60) >> 5;
4791 vic_len = db[8 + offset] >> 5;
4792 hdmi_3d_len = db[8 + offset] & 0x1f;
4794 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4797 vic = db[9 + offset + i];
4798 modes += add_hdmi_mode(connector, vic);
4800 offset += 1 + vic_len;
4802 if (multi_present == 1)
4804 else if (multi_present == 2)
4809 if (len < (8 + offset + hdmi_3d_len - 1))
4812 if (hdmi_3d_len < multi_len)
4815 if (multi_present == 1 || multi_present == 2) {
4816 /* 3D_Structure_ALL */
4817 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4819 /* check if 3D_MASK is present */
4820 if (multi_present == 2)
4821 mask = (db[10 + offset] << 8) | db[11 + offset];
4825 for (i = 0; i < 16; i++) {
4826 if (mask & (1 << i))
4827 modes += add_3d_struct_modes(connector,
4832 offset += multi_len;
4834 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4836 struct drm_display_mode *newmode = NULL;
4837 unsigned int newflag = 0;
4838 bool detail_present;
4840 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4842 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4845 /* 2D_VIC_order_X */
4846 vic_index = db[8 + offset + i] >> 4;
4848 /* 3D_Structure_X */
4849 switch (db[8 + offset + i] & 0x0f) {
4851 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4854 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4858 if ((db[9 + offset + i] >> 4) == 1)
4859 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4864 newmode = drm_display_mode_from_vic_index(connector,
4868 newmode->flags |= newflag;
4869 drm_mode_probed_add(connector, newmode);
4883 cea_revision(const u8 *cea)
4886 * FIXME is this correct for the DispID variant?
4887 * The DispID spec doesn't really specify whether
4888 * this is the revision of the CEA extension or
4889 * the DispID CEA data block. And the only value
4890 * given as an example is 0.
4896 * CTA Data Block iterator.
4898 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4901 * struct cea_db *db:
4902 * struct cea_db_iter iter;
4904 * cea_db_iter_edid_begin(edid, &iter);
4905 * cea_db_iter_for_each(db, &iter) {
4906 * // do stuff with db
4908 * cea_db_iter_end(&iter);
4910 struct cea_db_iter {
4911 struct drm_edid_iter edid_iter;
4912 struct displayid_iter displayid_iter;
4914 /* Current Data Block Collection. */
4915 const u8 *collection;
4917 /* Current Data Block index in current collection. */
4920 /* End index in current collection. */
4924 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4930 static int cea_db_tag(const struct cea_db *db)
4932 return db->tag_length >> 5;
4935 static int cea_db_payload_len(const void *_db)
4937 /* FIXME: Transition to passing struct cea_db * everywhere. */
4938 const struct cea_db *db = _db;
4940 return db->tag_length & 0x1f;
4943 static const void *cea_db_data(const struct cea_db *db)
4948 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4950 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4951 cea_db_payload_len(db) >= 1 &&
4955 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4957 const u8 *data = cea_db_data(db);
4959 return cea_db_tag(db) == CTA_DB_VENDOR &&
4960 cea_db_payload_len(db) >= 3 &&
4961 oui(data[2], data[1], data[0]) == vendor_oui;
4964 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4965 struct cea_db_iter *iter)
4967 memset(iter, 0, sizeof(*iter));
4969 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4970 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4973 static const struct cea_db *
4974 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4976 const struct cea_db *db;
4978 if (!iter->collection)
4981 db = (const struct cea_db *)&iter->collection[iter->index];
4983 if (iter->index + sizeof(*db) <= iter->end &&
4984 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4992 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4994 static int cea_db_collection_size(const u8 *cta)
4998 if (d < 4 || d > 127)
5006 * - VESA E-EDID v1.4
5007 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5009 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5013 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5016 /* Only support CTA Extension revision 3+ */
5017 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5020 size = cea_db_collection_size(ext);
5025 iter->end = iter->index + size;
5035 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5036 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5038 * Note that the above do not specify any connection between DisplayID Data
5039 * Block revision and CTA Extension versions.
5041 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5043 const struct displayid_block *block;
5045 displayid_iter_for_each(block, &iter->displayid_iter) {
5046 if (block->tag != DATA_BLOCK_CTA)
5050 * The displayid iterator has already verified the block bounds
5051 * in displayid_iter_block().
5053 iter->index = sizeof(*block);
5054 iter->end = iter->index + block->num_bytes;
5062 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5064 const struct cea_db *db;
5066 if (iter->collection) {
5067 /* Current collection should always be valid. */
5068 db = __cea_db_iter_current_block(iter);
5070 iter->collection = NULL;
5074 /* Next block in CTA Data Block Collection */
5075 iter->index += sizeof(*db) + cea_db_payload_len(db);
5077 db = __cea_db_iter_current_block(iter);
5084 * Find the next CTA Data Block Collection. First iterate all
5085 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5087 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5088 * Extension, it's recommended that DisplayID extensions are
5089 * exposed after all of the CTA Extensions.
5091 iter->collection = __cea_db_iter_edid_next(iter);
5092 if (!iter->collection)
5093 iter->collection = __cea_db_iter_displayid_next(iter);
5095 if (!iter->collection)
5098 db = __cea_db_iter_current_block(iter);
5104 #define cea_db_iter_for_each(__db, __iter) \
5105 while (((__db) = __cea_db_iter_next(__iter)))
5107 static void cea_db_iter_end(struct cea_db_iter *iter)
5109 displayid_iter_end(&iter->displayid_iter);
5110 drm_edid_iter_end(&iter->edid_iter);
5112 memset(iter, 0, sizeof(*iter));
5115 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5117 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5118 cea_db_payload_len(db) >= 5;
5121 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5123 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5124 cea_db_payload_len(db) >= 7;
5127 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5129 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5130 cea_db_payload_len(db) >= 2;
5133 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5135 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5136 cea_db_payload_len(db) == 21;
5139 static bool cea_db_is_vcdb(const struct cea_db *db)
5141 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5142 cea_db_payload_len(db) == 2;
5145 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5147 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5148 cea_db_payload_len(db) >= 7;
5151 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5153 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5156 static bool cea_db_is_y420vdb(const struct cea_db *db)
5158 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5161 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5163 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5164 cea_db_payload_len(db) >= 3;
5168 * Get the HF-EEODB override extension block count from EDID.
5170 * The passed in EDID may be partially read, as long as it has at least two
5171 * blocks (base block and one extension block) if EDID extension count is > 0.
5173 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5174 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5175 * iterators instead.
5178 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5180 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5184 /* No extensions according to base block, no HF-EEODB. */
5185 if (!edid_extension_block_count(edid))
5188 /* HF-EEODB is always in the first EDID extension block only */
5189 cta = edid_extension_block_data(edid, 0);
5190 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5193 /* Need to have the data block collection, and at least 3 bytes. */
5194 if (cea_db_collection_size(cta) < 3)
5198 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5199 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5200 * through 6 of Block 1 of the E-EDID.
5202 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5209 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5211 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5212 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5213 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5214 * support YCBCR420 output too.
5216 static void parse_cta_y420cmdb(struct drm_connector *connector,
5217 const struct cea_db *db, u64 *y420cmdb_map)
5219 struct drm_display_info *info = &connector->display_info;
5220 int i, map_len = cea_db_payload_len(db) - 1;
5221 const u8 *data = cea_db_data(db) + 1;
5225 /* All CEA modes support ycbcr420 sampling also.*/
5231 * This map indicates which of the existing CEA block modes
5232 * from VDB can support YCBCR420 output too. So if bit=0 is
5233 * set, first mode from VDB can support YCBCR420 output too.
5234 * We will parse and keep this map, before parsing VDB itself
5235 * to avoid going through the same block again and again.
5237 * Spec is not clear about max possible size of this block.
5238 * Clamping max bitmap block size at 8 bytes. Every byte can
5239 * address 8 CEA modes, in this way this map can address
5240 * 8*8 = first 64 SVDs.
5242 if (WARN_ON_ONCE(map_len > 8))
5245 for (i = 0; i < map_len; i++)
5246 map |= (u64)data[i] << (8 * i);
5250 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5252 *y420cmdb_map = map;
5255 static int add_cea_modes(struct drm_connector *connector,
5256 const struct drm_edid *drm_edid)
5258 const struct cea_db *db;
5259 struct cea_db_iter iter;
5262 /* CTA VDB block VICs parsed earlier */
5263 modes = add_cta_vdb_modes(connector);
5265 cea_db_iter_edid_begin(drm_edid, &iter);
5266 cea_db_iter_for_each(db, &iter) {
5267 if (cea_db_is_hdmi_vsdb(db)) {
5268 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5269 cea_db_payload_len(db));
5270 } else if (cea_db_is_y420vdb(db)) {
5271 const u8 *vdb420 = cea_db_data(db) + 1;
5273 /* Add 4:2:0(only) modes present in EDID */
5274 modes += do_y420vdb_modes(connector, vdb420,
5275 cea_db_payload_len(db) - 1);
5278 cea_db_iter_end(&iter);
5283 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5284 struct drm_display_mode *mode)
5286 const struct drm_display_mode *cea_mode;
5287 int clock1, clock2, clock;
5292 * allow 5kHz clock difference either way to account for
5293 * the 10kHz clock resolution limit of detailed timings.
5295 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5296 if (drm_valid_cea_vic(vic)) {
5298 cea_mode = cea_mode_for_vic(vic);
5299 clock1 = cea_mode->clock;
5300 clock2 = cea_mode_alternate_clock(cea_mode);
5302 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5303 if (drm_valid_hdmi_vic(vic)) {
5305 cea_mode = &edid_4k_modes[vic];
5306 clock1 = cea_mode->clock;
5307 clock2 = hdmi_mode_alternate_clock(cea_mode);
5313 /* pick whichever is closest */
5314 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5319 if (mode->clock == clock)
5322 drm_dbg_kms(connector->dev,
5323 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5324 connector->base.id, connector->name,
5325 type, vic, mode->clock, clock);
5326 mode->clock = clock;
5329 static void drm_calculate_luminance_range(struct drm_connector *connector)
5331 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5332 struct drm_luminance_range_info *luminance_range =
5333 &connector->display_info.luminance_range;
5334 static const u8 pre_computed_values[] = {
5335 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5336 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5338 u32 max_avg, min_cll, max, min, q, r;
5340 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5343 max_avg = hdr_metadata->max_fall;
5344 min_cll = hdr_metadata->min_cll;
5347 * From the specification (CTA-861-G), for calculating the maximum
5348 * luminance we need to use:
5349 * Luminance = 50*2**(CV/32)
5350 * Where CV is a one-byte value.
5351 * For calculating this expression we may need float point precision;
5352 * to avoid this complexity level, we take advantage that CV is divided
5353 * by a constant. From the Euclids division algorithm, we know that CV
5354 * can be written as: CV = 32*q + r. Next, we replace CV in the
5355 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5356 * need to pre-compute the value of r/32. For pre-computing the values
5357 * We just used the following Ruby line:
5358 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5359 * The results of the above expressions can be verified at
5360 * pre_computed_values.
5364 max = (1 << q) * pre_computed_values[r];
5366 /* min luminance: maxLum * (CV/255)^2 / 100 */
5367 q = DIV_ROUND_CLOSEST(min_cll, 255);
5368 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5370 luminance_range->min_luminance = min;
5371 luminance_range->max_luminance = max;
5374 static uint8_t eotf_supported(const u8 *edid_ext)
5376 return edid_ext[2] &
5377 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5378 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5379 BIT(HDMI_EOTF_SMPTE_ST2084) |
5380 BIT(HDMI_EOTF_BT_2100_HLG));
5383 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5385 return edid_ext[3] &
5386 BIT(HDMI_STATIC_METADATA_TYPE1);
5390 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5394 len = cea_db_payload_len(db);
5396 connector->hdr_sink_metadata.hdmi_type1.eotf =
5398 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5399 hdr_metadata_type(db);
5402 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5404 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5406 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5408 /* Calculate only when all values are available */
5409 drm_calculate_luminance_range(connector);
5413 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5415 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5417 u8 len = cea_db_payload_len(db);
5419 if (len >= 6 && (db[6] & (1 << 7)))
5420 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5422 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5423 connector->latency_present[0] = true;
5424 connector->video_latency[0] = db[9];
5425 connector->audio_latency[0] = db[10];
5428 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5429 connector->latency_present[1] = true;
5430 connector->video_latency[1] = db[11];
5431 connector->audio_latency[1] = db[12];
5434 drm_dbg_kms(connector->dev,
5435 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5436 connector->base.id, connector->name,
5437 connector->latency_present[0], connector->latency_present[1],
5438 connector->video_latency[0], connector->video_latency[1],
5439 connector->audio_latency[0], connector->audio_latency[1]);
5443 monitor_name(const struct detailed_timing *timing, void *data)
5445 const char **res = data;
5447 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5450 *res = timing->data.other_data.data.str.str;
5453 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5455 const char *edid_name = NULL;
5458 if (!drm_edid || !name)
5461 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5462 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5463 if (edid_name[mnl] == 0x0a)
5466 name[mnl] = edid_name[mnl];
5473 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5474 * @edid: monitor EDID information
5475 * @name: pointer to a character array to hold the name of the monitor
5476 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5479 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5481 int name_length = 0;
5488 struct drm_edid drm_edid = {
5490 .size = edid_size(edid),
5493 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5494 memcpy(name, buf, name_length);
5497 name[name_length] = '\0';
5499 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5501 static void clear_eld(struct drm_connector *connector)
5503 memset(connector->eld, 0, sizeof(connector->eld));
5505 connector->latency_present[0] = false;
5506 connector->latency_present[1] = false;
5507 connector->video_latency[0] = 0;
5508 connector->audio_latency[0] = 0;
5509 connector->video_latency[1] = 0;
5510 connector->audio_latency[1] = 0;
5514 * drm_edid_to_eld - build ELD from EDID
5515 * @connector: connector corresponding to the HDMI/DP sink
5516 * @drm_edid: EDID to parse
5518 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5519 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5521 static void drm_edid_to_eld(struct drm_connector *connector,
5522 const struct drm_edid *drm_edid)
5524 const struct drm_display_info *info = &connector->display_info;
5525 const struct cea_db *db;
5526 struct cea_db_iter iter;
5527 uint8_t *eld = connector->eld;
5528 int total_sad_count = 0;
5534 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5535 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5536 connector->base.id, connector->name,
5537 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5539 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5540 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5542 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5544 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5545 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5546 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5547 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5549 cea_db_iter_edid_begin(drm_edid, &iter);
5550 cea_db_iter_for_each(db, &iter) {
5551 const u8 *data = cea_db_data(db);
5552 int len = cea_db_payload_len(db);
5555 switch (cea_db_tag(db)) {
5557 /* Audio Data Block, contains SADs */
5558 sad_count = min(len / 3, 15 - total_sad_count);
5560 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5561 data, sad_count * 3);
5562 total_sad_count += sad_count;
5564 case CTA_DB_SPEAKER:
5565 /* Speaker Allocation Data Block */
5567 eld[DRM_ELD_SPEAKER] = data[0];
5570 /* HDMI Vendor-Specific Data Block */
5571 if (cea_db_is_hdmi_vsdb(db))
5572 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5578 cea_db_iter_end(&iter);
5580 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5582 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5583 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5584 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5586 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5588 eld[DRM_ELD_BASELINE_ELD_LEN] =
5589 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5591 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5592 connector->base.id, connector->name,
5593 drm_eld_size(eld), total_sad_count);
5596 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5597 struct cea_sad **sads)
5599 const struct cea_db *db;
5600 struct cea_db_iter iter;
5603 cea_db_iter_edid_begin(drm_edid, &iter);
5604 cea_db_iter_for_each(db, &iter) {
5605 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5608 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5609 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5612 for (j = 0; j < count; j++) {
5613 const u8 *sad = &db->data[j * 3];
5615 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5616 (*sads)[j].channels = sad[0] & 0x7;
5617 (*sads)[j].freq = sad[1] & 0x7F;
5618 (*sads)[j].byte2 = sad[2];
5623 cea_db_iter_end(&iter);
5625 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5631 * drm_edid_to_sad - extracts SADs from EDID
5632 * @edid: EDID to parse
5633 * @sads: pointer that will be set to the extracted SADs
5635 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5637 * Note: The returned pointer needs to be freed using kfree().
5639 * Return: The number of found SADs or negative number on error.
5641 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5643 struct drm_edid drm_edid;
5645 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5647 EXPORT_SYMBOL(drm_edid_to_sad);
5649 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5652 const struct cea_db *db;
5653 struct cea_db_iter iter;
5656 cea_db_iter_edid_begin(drm_edid, &iter);
5657 cea_db_iter_for_each(db, &iter) {
5658 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5659 cea_db_payload_len(db) == 3) {
5660 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5664 count = cea_db_payload_len(db);
5668 cea_db_iter_end(&iter);
5670 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5676 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5677 * @edid: EDID to parse
5678 * @sadb: pointer to the speaker block
5680 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5682 * Note: The returned pointer needs to be freed using kfree().
5684 * Return: The number of found Speaker Allocation Blocks or negative number on
5687 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5689 struct drm_edid drm_edid;
5691 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5694 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5697 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5698 * @connector: connector associated with the HDMI/DP sink
5699 * @mode: the display mode
5701 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5702 * the sink doesn't support audio or video.
5704 int drm_av_sync_delay(struct drm_connector *connector,
5705 const struct drm_display_mode *mode)
5707 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5710 if (!connector->latency_present[0])
5712 if (!connector->latency_present[1])
5715 a = connector->audio_latency[i];
5716 v = connector->video_latency[i];
5719 * HDMI/DP sink doesn't support audio or video?
5721 if (a == 255 || v == 255)
5725 * Convert raw EDID values to millisecond.
5726 * Treat unknown latency as 0ms.
5729 a = min(2 * (a - 1), 500);
5731 v = min(2 * (v - 1), 500);
5733 return max(v - a, 0);
5735 EXPORT_SYMBOL(drm_av_sync_delay);
5737 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5739 const struct cea_db *db;
5740 struct cea_db_iter iter;
5744 * Because HDMI identifier is in Vendor Specific Block,
5745 * search it from all data blocks of CEA extension.
5747 cea_db_iter_edid_begin(drm_edid, &iter);
5748 cea_db_iter_for_each(db, &iter) {
5749 if (cea_db_is_hdmi_vsdb(db)) {
5754 cea_db_iter_end(&iter);
5760 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5761 * @edid: monitor EDID information
5763 * Parse the CEA extension according to CEA-861-B.
5765 * Drivers that have added the modes parsed from EDID to drm_display_info
5766 * should use &drm_display_info.is_hdmi instead of calling this function.
5768 * Return: True if the monitor is HDMI, false if not or unknown.
5770 bool drm_detect_hdmi_monitor(const struct edid *edid)
5772 struct drm_edid drm_edid;
5774 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5776 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5778 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5780 struct drm_edid_iter edid_iter;
5781 const struct cea_db *db;
5782 struct cea_db_iter iter;
5784 bool has_audio = false;
5786 drm_edid_iter_begin(drm_edid, &edid_iter);
5787 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5788 if (edid_ext[0] == CEA_EXT) {
5789 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5794 drm_edid_iter_end(&edid_iter);
5797 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5801 cea_db_iter_edid_begin(drm_edid, &iter);
5802 cea_db_iter_for_each(db, &iter) {
5803 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5804 const u8 *data = cea_db_data(db);
5807 for (i = 0; i < cea_db_payload_len(db); i += 3)
5808 DRM_DEBUG_KMS("CEA audio format %d\n",
5809 (data[i] >> 3) & 0xf);
5814 cea_db_iter_end(&iter);
5821 * drm_detect_monitor_audio - check monitor audio capability
5822 * @edid: EDID block to scan
5824 * Monitor should have CEA extension block.
5825 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5826 * audio' only. If there is any audio extension block and supported
5827 * audio format, assume at least 'basic audio' support, even if 'basic
5828 * audio' is not defined in EDID.
5830 * Return: True if the monitor supports audio, false otherwise.
5832 bool drm_detect_monitor_audio(const struct edid *edid)
5834 struct drm_edid drm_edid;
5836 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5838 EXPORT_SYMBOL(drm_detect_monitor_audio);
5842 * drm_default_rgb_quant_range - default RGB quantization range
5843 * @mode: display mode
5845 * Determine the default RGB quantization range for the mode,
5846 * as specified in CEA-861.
5848 * Return: The default RGB quantization range for the mode
5850 enum hdmi_quantization_range
5851 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5853 /* All CEA modes other than VIC 1 use limited quantization range. */
5854 return drm_match_cea_mode(mode) > 1 ?
5855 HDMI_QUANTIZATION_RANGE_LIMITED :
5856 HDMI_QUANTIZATION_RANGE_FULL;
5858 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5860 /* CTA-861 Video Data Block (CTA VDB) */
5861 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5863 struct drm_display_info *info = &connector->display_info;
5864 int i, vic_index, len = cea_db_payload_len(db);
5865 const u8 *svds = cea_db_data(db);
5871 /* Gracefully handle multiple VDBs, however unlikely that is */
5872 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5876 vic_index = info->vics_len;
5877 info->vics_len += len;
5880 for (i = 0; i < len; i++) {
5881 u8 vic = svd_to_vic(svds[i]);
5883 if (!drm_valid_cea_vic(vic))
5886 info->vics[vic_index++] = vic;
5891 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5893 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5894 * using the VICs themselves.
5896 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5898 struct drm_display_info *info = &connector->display_info;
5899 struct drm_hdmi_info *hdmi = &info->hdmi;
5900 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5902 for (i = 0; i < len; i++) {
5903 u8 vic = info->vics[i];
5905 if (vic && y420cmdb_map & BIT_ULL(i))
5906 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5910 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5912 const struct drm_display_info *info = &connector->display_info;
5915 if (!vic || !info->vics)
5918 for (i = 0; i < info->vics_len; i++) {
5919 if (info->vics[i] == vic)
5926 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5927 static void parse_cta_y420vdb(struct drm_connector *connector,
5928 const struct cea_db *db)
5930 struct drm_display_info *info = &connector->display_info;
5931 struct drm_hdmi_info *hdmi = &info->hdmi;
5932 const u8 *svds = cea_db_data(db) + 1;
5935 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5936 u8 vic = svd_to_vic(svds[i]);
5938 if (!drm_valid_cea_vic(vic))
5941 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5942 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5946 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5948 struct drm_display_info *info = &connector->display_info;
5950 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5951 connector->base.id, connector->name, db[2]);
5953 if (db[2] & EDID_CEA_VCDB_QS)
5954 info->rgb_quant_range_selectable = true;
5958 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5960 switch (max_frl_rate) {
5963 *max_rate_per_lane = 3;
5967 *max_rate_per_lane = 6;
5971 *max_rate_per_lane = 6;
5975 *max_rate_per_lane = 8;
5979 *max_rate_per_lane = 10;
5983 *max_rate_per_lane = 12;
5988 *max_rate_per_lane = 0;
5992 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5996 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5998 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5999 hdmi->y420_dc_modes = dc_mask;
6002 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6005 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6007 if (!hdmi_dsc->v_1p2)
6010 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6011 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6013 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6014 hdmi_dsc->bpc_supported = 16;
6015 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6016 hdmi_dsc->bpc_supported = 12;
6017 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6018 hdmi_dsc->bpc_supported = 10;
6020 /* Supports min 8 BPC if DSC 1.2 is supported*/
6021 hdmi_dsc->bpc_supported = 8;
6023 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6025 u8 dsc_max_frl_rate;
6027 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6028 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6029 &hdmi_dsc->max_frl_rate_per_lane);
6031 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6033 switch (dsc_max_slices) {
6035 hdmi_dsc->max_slices = 1;
6036 hdmi_dsc->clk_per_slice = 340;
6039 hdmi_dsc->max_slices = 2;
6040 hdmi_dsc->clk_per_slice = 340;
6043 hdmi_dsc->max_slices = 4;
6044 hdmi_dsc->clk_per_slice = 340;
6047 hdmi_dsc->max_slices = 8;
6048 hdmi_dsc->clk_per_slice = 340;
6051 hdmi_dsc->max_slices = 8;
6052 hdmi_dsc->clk_per_slice = 400;
6055 hdmi_dsc->max_slices = 12;
6056 hdmi_dsc->clk_per_slice = 400;
6059 hdmi_dsc->max_slices = 16;
6060 hdmi_dsc->clk_per_slice = 400;
6064 hdmi_dsc->max_slices = 0;
6065 hdmi_dsc->clk_per_slice = 0;
6069 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6070 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6073 /* Sink Capability Data Structure */
6074 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6077 struct drm_display_info *info = &connector->display_info;
6078 struct drm_hdmi_info *hdmi = &info->hdmi;
6079 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6080 int max_tmds_clock = 0;
6081 u8 max_frl_rate = 0;
6082 bool dsc_support = false;
6084 info->has_hdmi_infoframe = true;
6086 if (hf_scds[6] & 0x80) {
6087 hdmi->scdc.supported = true;
6088 if (hf_scds[6] & 0x40)
6089 hdmi->scdc.read_request = true;
6093 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6094 * And as per the spec, three factors confirm this:
6095 * * Availability of a HF-VSDB block in EDID (check)
6096 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6097 * * SCDC support available (let's check)
6098 * Lets check it out.
6102 struct drm_scdc *scdc = &hdmi->scdc;
6104 /* max clock is 5000 KHz times block value */
6105 max_tmds_clock = hf_scds[5] * 5000;
6107 if (max_tmds_clock > 340000) {
6108 info->max_tmds_clock = max_tmds_clock;
6111 if (scdc->supported) {
6112 scdc->scrambling.supported = true;
6114 /* Few sinks support scrambling for clocks < 340M */
6115 if ((hf_scds[6] & 0x8))
6116 scdc->scrambling.low_rates = true;
6121 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6122 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6123 &hdmi->max_frl_rate_per_lane);
6126 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6128 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6129 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6133 drm_dbg_kms(connector->dev,
6134 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6135 connector->base.id, connector->name,
6136 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6139 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6142 struct drm_display_info *info = &connector->display_info;
6143 unsigned int dc_bpc = 0;
6145 /* HDMI supports at least 8 bpc */
6148 if (cea_db_payload_len(hdmi) < 6)
6151 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6153 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6154 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6155 connector->base.id, connector->name);
6158 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6160 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6161 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6162 connector->base.id, connector->name);
6165 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6167 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6168 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6169 connector->base.id, connector->name);
6173 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6174 connector->base.id, connector->name);
6178 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6179 connector->base.id, connector->name, dc_bpc);
6182 /* YCRCB444 is optional according to spec. */
6183 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6184 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6185 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6186 connector->base.id, connector->name);
6190 * Spec says that if any deep color mode is supported at all,
6191 * then deep color 36 bit must be supported.
6193 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6194 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6195 connector->base.id, connector->name);
6199 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6201 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6203 struct drm_display_info *info = &connector->display_info;
6204 u8 len = cea_db_payload_len(db);
6206 info->is_hdmi = true;
6209 info->dvi_dual = db[6] & 1;
6211 info->max_tmds_clock = db[7] * 5000;
6214 * Try to infer whether the sink supports HDMI infoframes.
6216 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6217 * supports infoframes if HDMI_Video_present is set.
6219 if (len >= 8 && db[8] & BIT(5))
6220 info->has_hdmi_infoframe = true;
6222 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6223 connector->base.id, connector->name,
6224 info->dvi_dual, info->max_tmds_clock);
6226 drm_parse_hdmi_deep_color_info(connector, db);
6230 * See EDID extension for head-mounted and specialized monitors, specified at:
6231 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6233 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6236 struct drm_display_info *info = &connector->display_info;
6238 bool desktop_usage = db[5] & BIT(6);
6240 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6241 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6242 info->non_desktop = true;
6244 drm_dbg_kms(connector->dev,
6245 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6246 connector->base.id, connector->name, version, db[5]);
6249 static void drm_parse_cea_ext(struct drm_connector *connector,
6250 const struct drm_edid *drm_edid)
6252 struct drm_display_info *info = &connector->display_info;
6253 struct drm_edid_iter edid_iter;
6254 const struct cea_db *db;
6255 struct cea_db_iter iter;
6257 u64 y420cmdb_map = 0;
6259 drm_edid_iter_begin(drm_edid, &edid_iter);
6260 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6261 if (edid_ext[0] != CEA_EXT)
6265 info->cea_rev = edid_ext[1];
6267 if (info->cea_rev != edid_ext[1])
6268 drm_dbg_kms(connector->dev,
6269 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6270 connector->base.id, connector->name,
6271 info->cea_rev, edid_ext[1]);
6273 /* The existence of a CTA extension should imply RGB support */
6274 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6275 if (edid_ext[3] & EDID_CEA_YCRCB444)
6276 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6277 if (edid_ext[3] & EDID_CEA_YCRCB422)
6278 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6279 if (edid_ext[3] & EDID_BASIC_AUDIO)
6280 info->has_audio = true;
6283 drm_edid_iter_end(&edid_iter);
6285 cea_db_iter_edid_begin(drm_edid, &iter);
6286 cea_db_iter_for_each(db, &iter) {
6287 /* FIXME: convert parsers to use struct cea_db */
6288 const u8 *data = (const u8 *)db;
6290 if (cea_db_is_hdmi_vsdb(db))
6291 drm_parse_hdmi_vsdb_video(connector, data);
6292 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6293 cea_db_is_hdmi_forum_scdb(db))
6294 drm_parse_hdmi_forum_scds(connector, data);
6295 else if (cea_db_is_microsoft_vsdb(db))
6296 drm_parse_microsoft_vsdb(connector, data);
6297 else if (cea_db_is_y420cmdb(db))
6298 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6299 else if (cea_db_is_y420vdb(db))
6300 parse_cta_y420vdb(connector, db);
6301 else if (cea_db_is_vcdb(db))
6302 drm_parse_vcdb(connector, data);
6303 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6304 drm_parse_hdr_metadata_block(connector, data);
6305 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6306 parse_cta_vdb(connector, db);
6307 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6308 info->has_audio = true;
6310 cea_db_iter_end(&iter);
6313 update_cta_y420cmdb(connector, y420cmdb_map);
6317 void get_monitor_range(const struct detailed_timing *timing, void *c)
6319 struct detailed_mode_closure *closure = c;
6320 struct drm_display_info *info = &closure->connector->display_info;
6321 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6322 const struct detailed_non_pixel *data = &timing->data.other_data;
6323 const struct detailed_data_monitor_range *range = &data->data.range;
6324 const struct edid *edid = closure->drm_edid->edid;
6326 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6330 * These limits are used to determine the VRR refresh
6331 * rate range. Only the "range limits only" variant
6332 * of the range descriptor seems to guarantee that
6333 * any and all timings are accepted by the sink, as
6334 * opposed to just timings conforming to the indicated
6335 * formula (GTF/GTF2/CVT). Thus other variants of the
6336 * range descriptor are not accepted here.
6338 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6341 monitor_range->min_vfreq = range->min_vfreq;
6342 monitor_range->max_vfreq = range->max_vfreq;
6344 if (edid->revision >= 4) {
6345 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6346 monitor_range->min_vfreq += 255;
6347 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6348 monitor_range->max_vfreq += 255;
6352 static void drm_get_monitor_range(struct drm_connector *connector,
6353 const struct drm_edid *drm_edid)
6355 const struct drm_display_info *info = &connector->display_info;
6356 struct detailed_mode_closure closure = {
6357 .connector = connector,
6358 .drm_edid = drm_edid,
6361 if (drm_edid->edid->revision < 4)
6364 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6367 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6369 drm_dbg_kms(connector->dev,
6370 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6371 connector->base.id, connector->name,
6372 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6375 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6376 const struct displayid_block *block)
6378 struct displayid_vesa_vendor_specific_block *vesa =
6379 (struct displayid_vesa_vendor_specific_block *)block;
6380 struct drm_display_info *info = &connector->display_info;
6382 if (block->num_bytes < 3) {
6383 drm_dbg_kms(connector->dev,
6384 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6385 connector->base.id, connector->name, block->num_bytes);
6389 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6392 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6393 drm_dbg_kms(connector->dev,
6394 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6395 connector->base.id, connector->name);
6399 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6401 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6402 connector->base.id, connector->name);
6405 info->mso_stream_count = 0;
6408 info->mso_stream_count = 2; /* 2 or 4 links */
6411 info->mso_stream_count = 4; /* 4 links */
6415 if (!info->mso_stream_count) {
6416 info->mso_pixel_overlap = 0;
6420 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6421 if (info->mso_pixel_overlap > 8) {
6422 drm_dbg_kms(connector->dev,
6423 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6424 connector->base.id, connector->name,
6425 info->mso_pixel_overlap);
6426 info->mso_pixel_overlap = 8;
6429 drm_dbg_kms(connector->dev,
6430 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6431 connector->base.id, connector->name,
6432 info->mso_stream_count, info->mso_pixel_overlap);
6435 static void drm_update_mso(struct drm_connector *connector,
6436 const struct drm_edid *drm_edid)
6438 const struct displayid_block *block;
6439 struct displayid_iter iter;
6441 displayid_iter_edid_begin(drm_edid, &iter);
6442 displayid_iter_for_each(block, &iter) {
6443 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6444 drm_parse_vesa_mso_data(connector, block);
6446 displayid_iter_end(&iter);
6449 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6450 * all of the values which would have been set from EDID
6452 static void drm_reset_display_info(struct drm_connector *connector)
6454 struct drm_display_info *info = &connector->display_info;
6457 info->height_mm = 0;
6460 info->color_formats = 0;
6462 info->max_tmds_clock = 0;
6463 info->dvi_dual = false;
6464 info->is_hdmi = false;
6465 info->has_audio = false;
6466 info->has_hdmi_infoframe = false;
6467 info->rgb_quant_range_selectable = false;
6468 memset(&info->hdmi, 0, sizeof(info->hdmi));
6470 info->edid_hdmi_rgb444_dc_modes = 0;
6471 info->edid_hdmi_ycbcr444_dc_modes = 0;
6473 info->non_desktop = 0;
6474 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6475 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6477 info->mso_stream_count = 0;
6478 info->mso_pixel_overlap = 0;
6479 info->max_dsc_bpp = 0;
6488 static void update_displayid_info(struct drm_connector *connector,
6489 const struct drm_edid *drm_edid)
6491 struct drm_display_info *info = &connector->display_info;
6492 const struct displayid_block *block;
6493 struct displayid_iter iter;
6495 displayid_iter_edid_begin(drm_edid, &iter);
6496 displayid_iter_for_each(block, &iter) {
6497 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6498 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6499 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6500 info->non_desktop = true;
6503 * We're only interested in the base section here, no need to
6508 displayid_iter_end(&iter);
6511 static void update_display_info(struct drm_connector *connector,
6512 const struct drm_edid *drm_edid)
6514 struct drm_display_info *info = &connector->display_info;
6515 const struct edid *edid;
6517 drm_reset_display_info(connector);
6518 clear_eld(connector);
6523 edid = drm_edid->edid;
6525 info->quirks = edid_get_quirks(drm_edid);
6527 info->width_mm = edid->width_cm * 10;
6528 info->height_mm = edid->height_cm * 10;
6530 drm_get_monitor_range(connector, drm_edid);
6532 if (edid->revision < 3)
6535 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6538 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6539 drm_parse_cea_ext(connector, drm_edid);
6541 update_displayid_info(connector, drm_edid);
6544 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6546 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6547 * tells us to assume 8 bpc color depth if the EDID doesn't have
6548 * extensions which tell otherwise.
6550 if (info->bpc == 0 && edid->revision == 3 &&
6551 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6553 drm_dbg_kms(connector->dev,
6554 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6555 connector->base.id, connector->name, info->bpc);
6558 /* Only defined for 1.4 with digital displays */
6559 if (edid->revision < 4)
6562 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6563 case DRM_EDID_DIGITAL_DEPTH_6:
6566 case DRM_EDID_DIGITAL_DEPTH_8:
6569 case DRM_EDID_DIGITAL_DEPTH_10:
6572 case DRM_EDID_DIGITAL_DEPTH_12:
6575 case DRM_EDID_DIGITAL_DEPTH_14:
6578 case DRM_EDID_DIGITAL_DEPTH_16:
6581 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6587 drm_dbg_kms(connector->dev,
6588 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6589 connector->base.id, connector->name, info->bpc);
6591 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6592 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6593 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6594 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6596 drm_update_mso(connector, drm_edid);
6599 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6600 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6601 connector->base.id, connector->name,
6602 info->non_desktop ? " (redundant quirk)" : "");
6603 info->non_desktop = true;
6606 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6607 info->max_dsc_bpp = 15;
6609 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6612 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6615 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6618 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6621 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6622 drm_edid_to_eld(connector, drm_edid);
6625 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6626 struct displayid_detailed_timings_1 *timings,
6629 struct drm_display_mode *mode;
6630 unsigned pixel_clock = (timings->pixel_clock[0] |
6631 (timings->pixel_clock[1] << 8) |
6632 (timings->pixel_clock[2] << 16)) + 1;
6633 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6634 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6635 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6636 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6637 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6638 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6639 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6640 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6641 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6642 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6644 mode = drm_mode_create(dev);
6648 /* resolution is kHz for type VII, and 10 kHz for type I */
6649 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6650 mode->hdisplay = hactive;
6651 mode->hsync_start = mode->hdisplay + hsync;
6652 mode->hsync_end = mode->hsync_start + hsync_width;
6653 mode->htotal = mode->hdisplay + hblank;
6655 mode->vdisplay = vactive;
6656 mode->vsync_start = mode->vdisplay + vsync;
6657 mode->vsync_end = mode->vsync_start + vsync_width;
6658 mode->vtotal = mode->vdisplay + vblank;
6661 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6662 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6663 mode->type = DRM_MODE_TYPE_DRIVER;
6665 if (timings->flags & 0x80)
6666 mode->type |= DRM_MODE_TYPE_PREFERRED;
6667 drm_mode_set_name(mode);
6672 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6673 const struct displayid_block *block)
6675 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6678 struct drm_display_mode *newmode;
6680 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6681 /* blocks must be multiple of 20 bytes length */
6682 if (block->num_bytes % 20)
6685 num_timings = block->num_bytes / 20;
6686 for (i = 0; i < num_timings; i++) {
6687 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6689 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6693 drm_mode_probed_add(connector, newmode);
6699 static int add_displayid_detailed_modes(struct drm_connector *connector,
6700 const struct drm_edid *drm_edid)
6702 const struct displayid_block *block;
6703 struct displayid_iter iter;
6706 displayid_iter_edid_begin(drm_edid, &iter);
6707 displayid_iter_for_each(block, &iter) {
6708 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6709 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6710 num_modes += add_displayid_detailed_1_modes(connector, block);
6712 displayid_iter_end(&iter);
6717 static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6718 const struct drm_edid *drm_edid)
6720 const struct drm_display_info *info = &connector->display_info;
6727 * EDID spec says modes should be preferred in this order:
6728 * - preferred detailed mode
6729 * - other detailed modes from base block
6730 * - detailed modes from extension blocks
6731 * - CVT 3-byte code modes
6732 * - standard timing codes
6733 * - established timing codes
6734 * - modes inferred from GTF or CVT range information
6736 * We get this pretty much right.
6738 * XXX order for additional mode types in extension blocks?
6740 num_modes += add_detailed_modes(connector, drm_edid);
6741 num_modes += add_cvt_modes(connector, drm_edid);
6742 num_modes += add_standard_modes(connector, drm_edid);
6743 num_modes += add_established_modes(connector, drm_edid);
6744 num_modes += add_cea_modes(connector, drm_edid);
6745 num_modes += add_alternate_cea_modes(connector, drm_edid);
6746 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6747 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6748 num_modes += add_inferred_modes(connector, drm_edid);
6750 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6751 edid_fixup_preferred(connector);
6756 static void _drm_update_tile_info(struct drm_connector *connector,
6757 const struct drm_edid *drm_edid);
6759 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6760 const struct drm_edid *drm_edid)
6762 struct drm_device *dev = connector->dev;
6765 if (connector->edid_blob_ptr) {
6766 const struct edid *old_edid = connector->edid_blob_ptr->data;
6769 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6770 connector->epoch_counter++;
6771 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6772 connector->base.id, connector->name,
6773 connector->epoch_counter);
6778 ret = drm_property_replace_global_blob(dev,
6779 &connector->edid_blob_ptr,
6780 drm_edid ? drm_edid->size : 0,
6781 drm_edid ? drm_edid->edid : NULL,
6783 dev->mode_config.edid_property);
6785 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6786 connector->base.id, connector->name, ret);
6790 ret = drm_object_property_set_value(&connector->base,
6791 dev->mode_config.non_desktop_property,
6792 connector->display_info.non_desktop);
6794 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6795 connector->base.id, connector->name, ret);
6799 ret = drm_connector_set_tile_property(connector);
6801 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6802 connector->base.id, connector->name, ret);
6811 * drm_edid_connector_update - Update connector information from EDID
6812 * @connector: Connector
6815 * Update the connector display info, ELD, HDR metadata, relevant properties,
6816 * etc. from the passed in EDID.
6818 * If EDID is NULL, reset the information.
6820 * Must be called before calling drm_edid_connector_add_modes().
6822 * Return: 0 on success, negative error on errors.
6824 int drm_edid_connector_update(struct drm_connector *connector,
6825 const struct drm_edid *drm_edid)
6827 update_display_info(connector, drm_edid);
6829 _drm_update_tile_info(connector, drm_edid);
6831 return _drm_edid_connector_property_update(connector, drm_edid);
6833 EXPORT_SYMBOL(drm_edid_connector_update);
6836 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6837 * @connector: Connector
6839 * Add the modes from the previously updated EDID property to the connector
6840 * probed modes list.
6842 * drm_edid_connector_update() must have been called before this to update the
6845 * Return: The number of modes added, or 0 if we couldn't find any.
6847 int drm_edid_connector_add_modes(struct drm_connector *connector)
6849 const struct drm_edid *drm_edid = NULL;
6852 if (connector->edid_blob_ptr)
6853 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6854 connector->edid_blob_ptr->length);
6856 count = _drm_edid_connector_add_modes(connector, drm_edid);
6858 drm_edid_free(drm_edid);
6862 EXPORT_SYMBOL(drm_edid_connector_add_modes);
6865 * drm_connector_update_edid_property - update the edid property of a connector
6866 * @connector: drm connector
6867 * @edid: new value of the edid property
6869 * This function creates a new blob modeset object and assigns its id to the
6870 * connector's edid property.
6871 * Since we also parse tile information from EDID's displayID block, we also
6872 * set the connector's tile property here. See drm_connector_set_tile_property()
6875 * This function is deprecated. Use drm_edid_connector_update() instead.
6878 * Zero on success, negative errno on failure.
6880 int drm_connector_update_edid_property(struct drm_connector *connector,
6881 const struct edid *edid)
6883 struct drm_edid drm_edid;
6885 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6887 EXPORT_SYMBOL(drm_connector_update_edid_property);
6890 * drm_add_edid_modes - add modes from EDID data, if available
6891 * @connector: connector we're probing
6894 * Add the specified modes to the connector's mode list. Also fills out the
6895 * &drm_display_info structure and ELD in @connector with any information which
6896 * can be derived from the edid.
6898 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6900 * Return: The number of modes added or 0 if we couldn't find any.
6902 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6904 struct drm_edid _drm_edid;
6905 const struct drm_edid *drm_edid;
6907 if (edid && !drm_edid_is_valid(edid)) {
6908 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6909 connector->base.id, connector->name);
6913 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6915 update_display_info(connector, drm_edid);
6917 return _drm_edid_connector_add_modes(connector, drm_edid);
6919 EXPORT_SYMBOL(drm_add_edid_modes);
6922 * drm_add_modes_noedid - add modes for the connectors without EDID
6923 * @connector: connector we're probing
6924 * @hdisplay: the horizontal display limit
6925 * @vdisplay: the vertical display limit
6927 * Add the specified modes to the connector's mode list. Only when the
6928 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6930 * Return: The number of modes added or 0 if we couldn't find any.
6932 int drm_add_modes_noedid(struct drm_connector *connector,
6933 int hdisplay, int vdisplay)
6935 int i, count, num_modes = 0;
6936 struct drm_display_mode *mode;
6937 struct drm_device *dev = connector->dev;
6939 count = ARRAY_SIZE(drm_dmt_modes);
6945 for (i = 0; i < count; i++) {
6946 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6948 if (hdisplay && vdisplay) {
6950 * Only when two are valid, they will be used to check
6951 * whether the mode should be added to the mode list of
6954 if (ptr->hdisplay > hdisplay ||
6955 ptr->vdisplay > vdisplay)
6958 if (drm_mode_vrefresh(ptr) > 61)
6960 mode = drm_mode_duplicate(dev, ptr);
6962 drm_mode_probed_add(connector, mode);
6968 EXPORT_SYMBOL(drm_add_modes_noedid);
6971 * drm_set_preferred_mode - Sets the preferred mode of a connector
6972 * @connector: connector whose mode list should be processed
6973 * @hpref: horizontal resolution of preferred mode
6974 * @vpref: vertical resolution of preferred mode
6976 * Marks a mode as preferred if it matches the resolution specified by @hpref
6979 void drm_set_preferred_mode(struct drm_connector *connector,
6980 int hpref, int vpref)
6982 struct drm_display_mode *mode;
6984 list_for_each_entry(mode, &connector->probed_modes, head) {
6985 if (mode->hdisplay == hpref &&
6986 mode->vdisplay == vpref)
6987 mode->type |= DRM_MODE_TYPE_PREFERRED;
6990 EXPORT_SYMBOL(drm_set_preferred_mode);
6992 static bool is_hdmi2_sink(const struct drm_connector *connector)
6995 * FIXME: sil-sii8620 doesn't have a connector around when
6996 * we need one, so we have to be prepared for a NULL connector.
7001 return connector->display_info.hdmi.scdc.supported ||
7002 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7005 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7006 const struct drm_display_mode *mode)
7008 bool has_hdmi_infoframe = connector ?
7009 connector->display_info.has_hdmi_infoframe : false;
7011 if (!has_hdmi_infoframe)
7014 /* No HDMI VIC when signalling 3D video format */
7015 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7018 return drm_match_hdmi_mode(mode);
7021 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7022 const struct drm_display_mode *mode)
7025 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7026 * we should send its VIC in vendor infoframes, else send the
7027 * VIC in AVI infoframes. Lets check if this mode is present in
7028 * HDMI 1.4b 4K modes
7030 if (drm_mode_hdmi_vic(connector, mode))
7033 return drm_match_cea_mode(mode);
7037 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7038 * conform to HDMI 1.4.
7040 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7041 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7043 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7046 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7048 if (!is_hdmi2_sink(connector) && vic > 64 &&
7049 !cta_vdb_has_vic(connector, vic))
7056 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7057 * data from a DRM display mode
7058 * @frame: HDMI AVI infoframe
7059 * @connector: the connector
7060 * @mode: DRM display mode
7062 * Return: 0 on success or a negative error code on failure.
7065 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7066 const struct drm_connector *connector,
7067 const struct drm_display_mode *mode)
7069 enum hdmi_picture_aspect picture_aspect;
7072 if (!frame || !mode)
7075 hdmi_avi_infoframe_init(frame);
7077 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7078 frame->pixel_repeat = 1;
7080 vic = drm_mode_cea_vic(connector, mode);
7081 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7083 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7086 * As some drivers don't support atomic, we can't use connector state.
7087 * So just initialize the frame with default values, just the same way
7088 * as it's done with other properties here.
7090 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7094 * Populate picture aspect ratio from either
7095 * user input (if specified) or from the CEA/HDMI mode lists.
7097 picture_aspect = mode->picture_aspect_ratio;
7098 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7100 picture_aspect = drm_get_cea_aspect_ratio(vic);
7102 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7106 * The infoframe can't convey anything but none, 4:3
7107 * and 16:9, so if the user has asked for anything else
7108 * we can only satisfy it by specifying the right VIC.
7110 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7112 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7114 } else if (hdmi_vic) {
7115 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7121 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7124 frame->video_code = vic_for_avi_infoframe(connector, vic);
7125 frame->picture_aspect = picture_aspect;
7126 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7127 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7131 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7134 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7135 * quantization range information
7136 * @frame: HDMI AVI infoframe
7137 * @connector: the connector
7138 * @mode: DRM display mode
7139 * @rgb_quant_range: RGB quantization range (Q)
7142 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7143 const struct drm_connector *connector,
7144 const struct drm_display_mode *mode,
7145 enum hdmi_quantization_range rgb_quant_range)
7147 const struct drm_display_info *info = &connector->display_info;
7151 * "A Source shall not send a non-zero Q value that does not correspond
7152 * to the default RGB Quantization Range for the transmitted Picture
7153 * unless the Sink indicates support for the Q bit in a Video
7154 * Capabilities Data Block."
7156 * HDMI 2.0 recommends sending non-zero Q when it does match the
7157 * default RGB quantization range for the mode, even when QS=0.
7159 if (info->rgb_quant_range_selectable ||
7160 rgb_quant_range == drm_default_rgb_quant_range(mode))
7161 frame->quantization_range = rgb_quant_range;
7163 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7167 * "When transmitting any RGB colorimetry, the Source should set the
7168 * YQ-field to match the RGB Quantization Range being transmitted
7169 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7170 * set YQ=1) and the Sink shall ignore the YQ-field."
7172 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7173 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7174 * good way to tell which version of CEA-861 the sink supports, so
7175 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7178 if (!is_hdmi2_sink(connector) ||
7179 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7180 frame->ycc_quantization_range =
7181 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7183 frame->ycc_quantization_range =
7184 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7186 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7188 static enum hdmi_3d_structure
7189 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7191 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7194 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7195 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7196 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7197 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7198 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7199 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7200 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7201 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7202 case DRM_MODE_FLAG_3D_L_DEPTH:
7203 return HDMI_3D_STRUCTURE_L_DEPTH;
7204 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7205 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7206 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7207 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7208 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7209 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7211 return HDMI_3D_STRUCTURE_INVALID;
7216 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7217 * data from a DRM display mode
7218 * @frame: HDMI vendor infoframe
7219 * @connector: the connector
7220 * @mode: DRM display mode
7222 * Note that there's is a need to send HDMI vendor infoframes only when using a
7223 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7224 * function will return -EINVAL, error that can be safely ignored.
7226 * Return: 0 on success or a negative error code on failure.
7229 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7230 const struct drm_connector *connector,
7231 const struct drm_display_mode *mode)
7234 * FIXME: sil-sii8620 doesn't have a connector around when
7235 * we need one, so we have to be prepared for a NULL connector.
7237 bool has_hdmi_infoframe = connector ?
7238 connector->display_info.has_hdmi_infoframe : false;
7241 if (!frame || !mode)
7244 if (!has_hdmi_infoframe)
7247 err = hdmi_vendor_infoframe_init(frame);
7252 * Even if it's not absolutely necessary to send the infoframe
7253 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7254 * know that the sink can handle it. This is based on a
7255 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7256 * have trouble realizing that they should switch from 3D to 2D
7257 * mode if the source simply stops sending the infoframe when
7258 * it wants to switch from 3D to 2D.
7260 frame->vic = drm_mode_hdmi_vic(connector, mode);
7261 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7265 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7267 static void drm_parse_tiled_block(struct drm_connector *connector,
7268 const struct displayid_block *block)
7270 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7272 u8 tile_v_loc, tile_h_loc;
7273 u8 num_v_tile, num_h_tile;
7274 struct drm_tile_group *tg;
7276 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7277 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7279 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7280 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7281 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7282 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7284 connector->has_tile = true;
7285 if (tile->tile_cap & 0x80)
7286 connector->tile_is_single_monitor = true;
7288 connector->num_h_tile = num_h_tile + 1;
7289 connector->num_v_tile = num_v_tile + 1;
7290 connector->tile_h_loc = tile_h_loc;
7291 connector->tile_v_loc = tile_v_loc;
7292 connector->tile_h_size = w + 1;
7293 connector->tile_v_size = h + 1;
7295 drm_dbg_kms(connector->dev,
7296 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7297 connector->base.id, connector->name,
7299 connector->tile_h_size, connector->tile_v_size,
7300 connector->num_h_tile, connector->num_v_tile,
7301 connector->tile_h_loc, connector->tile_v_loc,
7302 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7304 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7306 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7310 if (connector->tile_group != tg) {
7311 /* if we haven't got a pointer,
7312 take the reference, drop ref to old tile group */
7313 if (connector->tile_group)
7314 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7315 connector->tile_group = tg;
7317 /* if same tile group, then release the ref we just took. */
7318 drm_mode_put_tile_group(connector->dev, tg);
7322 static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7323 const struct displayid_block *block)
7325 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 &&
7326 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7327 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7328 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7331 static void _drm_update_tile_info(struct drm_connector *connector,
7332 const struct drm_edid *drm_edid)
7334 const struct displayid_block *block;
7335 struct displayid_iter iter;
7337 connector->has_tile = false;
7339 displayid_iter_edid_begin(drm_edid, &iter);
7340 displayid_iter_for_each(block, &iter) {
7341 if (displayid_is_tiled_block(&iter, block))
7342 drm_parse_tiled_block(connector, block);
7344 displayid_iter_end(&iter);
7346 if (!connector->has_tile && connector->tile_group) {
7347 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7348 connector->tile_group = NULL;
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