drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include <linux/vmalloc.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v13_0.h"
  30
  31 #include "mp/mp_13_0_2_offset.h"
  32 #include "mp/mp_13_0_2_sh_mask.h"
  33
  34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
  48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
  49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
  50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
  51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
  52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
  53 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
  54 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
  55
  56 /* For large FW files the time to complete can be very long */
  57 #define USBC_PD_POLLING_LIMIT_S 240
  58
  59 /* Read USB-PD from LFB */
  60 #define GFX_CMD_USB_PD_USE_LFB 0x480
  61
  62 /* VBIOS gfl defines */
  63 #define MBOX_READY_MASK 0x80000000
  64 #define MBOX_STATUS_MASK 0x0000FFFF
  65 #define MBOX_COMMAND_MASK 0x00FF0000
  66 #define MBOX_READY_FLAG 0x80000000
  67 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  68 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  69 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  70
  71 /* memory training timeout define */
  72 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  73
  74 static int psp_v13_0_init_microcode(struct psp_context *psp)
  75 {
  76         struct amdgpu_device *adev = psp->adev;
  77         char ucode_prefix[30];
  78         int err = 0;
  79
  80         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  81
  82         switch (adev->ip_versions[MP0_HWIP][0]) {
  83         case IP_VERSION(13, 0, 2):
  84                 err = psp_init_sos_microcode(psp, ucode_prefix);
  85                 if (err)
  86                         return err;
  87                 /* It's not necessary to load ras ta on Guest side */
  88                 if (!amdgpu_sriov_vf(adev)) {
  89                         err = psp_init_ta_microcode(psp, ucode_prefix);
  90                         if (err)
  91                                 return err;
  92                 }
  93                 break;
  94         case IP_VERSION(13, 0, 1):
  95         case IP_VERSION(13, 0, 3):
  96         case IP_VERSION(13, 0, 5):
  97         case IP_VERSION(13, 0, 8):
  98         case IP_VERSION(13, 0, 11):
  99         case IP_VERSION(14, 0, 0):
 100                 err = psp_init_toc_microcode(psp, ucode_prefix);
 101                 if (err)
 102                         return err;
 103                 err = psp_init_ta_microcode(psp, ucode_prefix);
 104                 if (err)
 105                         return err;
 106                 break;
 107         case IP_VERSION(13, 0, 0):
 108         case IP_VERSION(13, 0, 6):
 109         case IP_VERSION(13, 0, 7):
 110         case IP_VERSION(13, 0, 10):
 111                 err = psp_init_sos_microcode(psp, ucode_prefix);
 112                 if (err)
 113                         return err;
 114                 /* It's not necessary to load ras ta on Guest side */
 115                 err = psp_init_ta_microcode(psp, ucode_prefix);
 116                 if (err)
 117                         return err;
 118                 break;
 119         default:
 120                 BUG();
 121         }
 122
 123         return 0;
 124 }
 125
 126 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         uint32_t sol_reg;
 130
 131         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 132
 133         return sol_reg != 0x0;
 134 }
 135
 136 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 137 {
 138         struct amdgpu_device *adev = psp->adev;
 139
 140         int ret;
 141         int retry_loop;
 142
 143         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 144                 /* Wait for bootloader to signify that is
 145                     ready having bit 31 of C2PMSG_35 set to 1 */
 146                 ret = psp_wait_for(psp,
 147                                    SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 148                                    0x80000000,
 149                                    0x80000000,
 150                                    false);
 151
 152                 if (ret == 0)
 153                         return 0;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 160                                                struct psp_bin_desc      *bin_desc,
 161                                                enum psp_bootloader_cmd  bl_cmd)
 162 {
 163         int ret;
 164         uint32_t psp_gfxdrv_command_reg = 0;
 165         struct amdgpu_device *adev = psp->adev;
 166
 167         /* Check tOS sign of life register to confirm sys driver and sOS
 168          * are already been loaded.
 169          */
 170         if (psp_v13_0_is_sos_alive(psp))
 171                 return 0;
 172
 173         ret = psp_v13_0_wait_for_bootloader(psp);
 174         if (ret)
 175                 return ret;
 176
 177         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 178
 179         /* Copy PSP KDB binary to memory */
 180         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 181
 182         /* Provide the PSP KDB to bootloader */
 183         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 184                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 185         psp_gfxdrv_command_reg = bl_cmd;
 186         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 187                psp_gfxdrv_command_reg);
 188
 189         ret = psp_v13_0_wait_for_bootloader(psp);
 190
 191         return ret;
 192 }
 193
 194 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 195 {
 196         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 197 }
 198
 199 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 200 {
 201         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 202 }
 203
 204 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 205 {
 206         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 207 }
 208
 209 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 210 {
 211         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 212 }
 213
 214 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 215 {
 216         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 217 }
 218
 219 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 220 {
 221         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 222 }
 223
 224 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
 225 {
 226         return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
 227 }
 228
 229
 230 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 231 {
 232         int ret;
 233         unsigned int psp_gfxdrv_command_reg = 0;
 234         struct amdgpu_device *adev = psp->adev;
 235
 236         /* Check sOS sign of life register to confirm sys driver and sOS
 237          * are already been loaded.
 238          */
 239         if (psp_v13_0_is_sos_alive(psp))
 240                 return 0;
 241
 242         ret = psp_v13_0_wait_for_bootloader(psp);
 243         if (ret)
 244                 return ret;
 245
 246         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 247
 248         /* Copy Secure OS binary to PSP memory */
 249         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 250
 251         /* Provide the PSP secure OS to bootloader */
 252         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 253                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 254         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 255         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 256                psp_gfxdrv_command_reg);
 257
 258         /* there might be handshake issue with hardware which needs delay */
 259         mdelay(20);
 260         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 261                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 262                            0, true);
 263
 264         return ret;
 265 }
 266
 267 static int psp_v13_0_ring_stop(struct psp_context *psp,
 268                                enum psp_ring_type ring_type)
 269 {
 270         int ret = 0;
 271         struct amdgpu_device *adev = psp->adev;
 272
 273         if (amdgpu_sriov_vf(adev)) {
 274                 /* Write the ring destroy command*/
 275                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 276                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 277                 /* there might be handshake issue with hardware which needs delay */
 278                 mdelay(20);
 279                 /* Wait for response flag (bit 31) */
 280                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 281                                    0x80000000, 0x80000000, false);
 282         } else {
 283                 /* Write the ring destroy command*/
 284                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 285                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 286                 /* there might be handshake issue with hardware which needs delay */
 287                 mdelay(20);
 288                 /* Wait for response flag (bit 31) */
 289                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 290                                    0x80000000, 0x80000000, false);
 291         }
 292
 293         return ret;
 294 }
 295
 296 static int psp_v13_0_ring_create(struct psp_context *psp,
 297                                  enum psp_ring_type ring_type)
 298 {
 299         int ret = 0;
 300         unsigned int psp_ring_reg = 0;
 301         struct psp_ring *ring = &psp->km_ring;
 302         struct amdgpu_device *adev = psp->adev;
 303
 304         if (amdgpu_sriov_vf(adev)) {
 305                 ret = psp_v13_0_ring_stop(psp, ring_type);
 306                 if (ret) {
 307                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 308                         return ret;
 309                 }
 310
 311                 /* Write low address of the ring to C2PMSG_102 */
 312                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 313                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 314                 /* Write high address of the ring to C2PMSG_103 */
 315                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 316                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 317
 318                 /* Write the ring initialization command to C2PMSG_101 */
 319                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 320                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 321
 322                 /* there might be handshake issue with hardware which needs delay */
 323                 mdelay(20);
 324
 325                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 326                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 327                                    0x80000000, 0x8000FFFF, false);
 328
 329         } else {
 330                 /* Wait for sOS ready for ring creation */
 331                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 332                                    0x80000000, 0x80000000, false);
 333                 if (ret) {
 334                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 335                         return ret;
 336                 }
 337
 338                 /* Write low address of the ring to C2PMSG_69 */
 339                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 340                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 341                 /* Write high address of the ring to C2PMSG_70 */
 342                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 343                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 344                 /* Write size of ring to C2PMSG_71 */
 345                 psp_ring_reg = ring->ring_size;
 346                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 347                 /* Write the ring initialization command to C2PMSG_64 */
 348                 psp_ring_reg = ring_type;
 349                 psp_ring_reg = psp_ring_reg << 16;
 350                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 351
 352                 /* there might be handshake issue with hardware which needs delay */
 353                 mdelay(20);
 354
 355                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 356                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 357                                    0x80000000, 0x8000FFFF, false);
 358         }
 359
 360         return ret;
 361 }
 362
 363 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 364                                   enum psp_ring_type ring_type)
 365 {
 366         int ret = 0;
 367         struct psp_ring *ring = &psp->km_ring;
 368         struct amdgpu_device *adev = psp->adev;
 369
 370         ret = psp_v13_0_ring_stop(psp, ring_type);
 371         if (ret)
 372                 DRM_ERROR("Fail to stop psp ring\n");
 373
 374         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 375                               &ring->ring_mem_mc_addr,
 376                               (void **)&ring->ring_mem);
 377
 378         return ret;
 379 }
 380
 381 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 382 {
 383         uint32_t data;
 384         struct amdgpu_device *adev = psp->adev;
 385
 386         if (amdgpu_sriov_vf(adev))
 387                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 388         else
 389                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 390
 391         return data;
 392 }
 393
 394 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 395 {
 396         struct amdgpu_device *adev = psp->adev;
 397
 398         if (amdgpu_sriov_vf(adev)) {
 399                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 400                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 401                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 402         } else
 403                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 404 }
 405
 406 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 407 {
 408         int ret;
 409         int i;
 410         uint32_t data_32;
 411         int max_wait;
 412         struct amdgpu_device *adev = psp->adev;
 413
 414         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 415         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
 416         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
 417
 418         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 419         for (i = 0; i < max_wait; i++) {
 420                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 421                                    0x80000000, 0x80000000, false);
 422                 if (ret == 0)
 423                         break;
 424         }
 425         if (i < max_wait)
 426                 ret = 0;
 427         else
 428                 ret = -ETIME;
 429
 430         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 431                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 432                   (ret == 0) ? "succeed" : "failed",
 433                   i, adev->usec_timeout/1000);
 434         return ret;
 435 }
 436
 437
 438 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
 439 {
 440         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 441         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 442         struct amdgpu_device *adev = psp->adev;
 443         uint32_t p2c_header[4];
 444         uint32_t sz;
 445         void *buf;
 446         int ret, idx;
 447
 448         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 449                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 450                 return 0;
 451         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 452                 dev_err(adev->dev, "Memory training initialization failure.\n");
 453                 return -EINVAL;
 454         }
 455
 456         if (psp_v13_0_is_sos_alive(psp)) {
 457                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 458                 return 0;
 459         }
 460
 461         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 462         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 463                   pcache[0], pcache[1], pcache[2], pcache[3],
 464                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 465
 466         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 467                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 468                 ops |= PSP_MEM_TRAIN_RESTORE;
 469         }
 470
 471         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 472             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 473                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 474                 ops |= PSP_MEM_TRAIN_SAVE;
 475         }
 476
 477         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 478             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 479               pcache[3] == p2c_header[3])) {
 480                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 481                 ops |= PSP_MEM_TRAIN_SAVE;
 482         }
 483
 484         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 485             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 486                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 487                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 488         }
 489
 490         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 491                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 492                 ops |= PSP_MEM_TRAIN_SAVE;
 493         }
 494
 495         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 496
 497         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 498                 /*
 499                  * Long training will encroach a certain amount on the bottom of VRAM;
 500                  * save the content from the bottom of VRAM to system memory
 501                  * before training, and restore it after training to avoid
 502                  * VRAM corruption.
 503                  */
 504                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 505
 506                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 507                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 508                                   adev->gmc.visible_vram_size,
 509                                   adev->mman.aper_base_kaddr);
 510                         return -EINVAL;
 511                 }
 512
 513                 buf = vmalloc(sz);
 514                 if (!buf) {
 515                         dev_err(adev->dev, "failed to allocate system memory.\n");
 516                         return -ENOMEM;
 517                 }
 518
 519                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 520                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 521                         ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 522                         if (ret) {
 523                                 DRM_ERROR("Send long training msg failed.\n");
 524                                 vfree(buf);
 525                                 drm_dev_exit(idx);
 526                                 return ret;
 527                         }
 528
 529                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 530                         adev->hdp.funcs->flush_hdp(adev, NULL);
 531                         vfree(buf);
 532                         drm_dev_exit(idx);
 533                 } else {
 534                         vfree(buf);
 535                         return -ENODEV;
 536                 }
 537         }
 538
 539         if (ops & PSP_MEM_TRAIN_SAVE) {
 540                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 541         }
 542
 543         if (ops & PSP_MEM_TRAIN_RESTORE) {
 544                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 545         }
 546
 547         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 548                 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 549                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 550                 if (ret) {
 551                         dev_err(adev->dev, "send training msg failed.\n");
 552                         return ret;
 553                 }
 554         }
 555         ctx->training_cnt++;
 556         return 0;
 557 }
 558
 559 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 560 {
 561         struct amdgpu_device *adev = psp->adev;
 562         uint32_t reg_status;
 563         int ret, i = 0;
 564
 565         /*
 566          * LFB address which is aligned to 1MB address and has to be
 567          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 568          * register
 569          */
 570         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 571
 572         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 573                              0x80000000, 0x80000000, false);
 574         if (ret)
 575                 return ret;
 576
 577         /* Fireup interrupt so PSP can pick up the address */
 578         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 579
 580         /* FW load takes very long time */
 581         do {
 582                 msleep(1000);
 583                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 584
 585                 if (reg_status & 0x80000000)
 586                         goto done;
 587
 588         } while (++i < USBC_PD_POLLING_LIMIT_S);
 589
 590         return -ETIME;
 591 done:
 592
 593         if ((reg_status & 0xFFFF) != 0) {
 594                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 595                                 reg_status & 0xFFFF);
 596                 return -EIO;
 597         }
 598
 599         return 0;
 600 }
 601
 602 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 603 {
 604         struct amdgpu_device *adev = psp->adev;
 605         int ret;
 606
 607         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 608
 609         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 610                                      0x80000000, 0x80000000, false);
 611         if (!ret)
 612                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 613
 614         return ret;
 615 }
 616
 617 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 618 {
 619         uint32_t reg_status = 0, reg_val = 0;
 620         struct amdgpu_device *adev = psp->adev;
 621         int ret;
 622
 623         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 624         reg_val |= (cmd << 16);
 625         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 626
 627         /* Ring the doorbell */
 628         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 629
 630         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 631                 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 632                                                  MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
 633         else
 634                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 635                                    MBOX_READY_FLAG, MBOX_READY_MASK, false);
 636         if (ret) {
 637                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 638                 return ret;
 639         }
 640
 641         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 642         if ((reg_status & 0xFFFF) != 0) {
 643                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 644                                 cmd, reg_status & 0xFFFF);
 645                 return -EIO;
 646         }
 647
 648         return 0;
 649 }
 650
 651 static int psp_v13_0_update_spirom(struct psp_context *psp,
 652                                    uint64_t fw_pri_mc_addr)
 653 {
 654         struct amdgpu_device *adev = psp->adev;
 655         int ret;
 656
 657         /* Confirm PSP is ready to start */
 658         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 659                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 660         if (ret) {
 661                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 662                 return ret;
 663         }
 664
 665         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 666
 667         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 668         if (ret)
 669                 return ret;
 670
 671         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 672
 673         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 674         if (ret)
 675                 return ret;
 676
 677         psp->vbflash_done = true;
 678
 679         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 680         if (ret)
 681                 return ret;
 682
 683         return 0;
 684 }
 685
 686 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 687 {
 688         struct amdgpu_device *adev = psp->adev;
 689
 690         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 691 }
 692
 693 static const struct psp_funcs psp_v13_0_funcs = {
 694         .init_microcode = psp_v13_0_init_microcode,
 695         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 696         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 697         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 698         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 699         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 700         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 701         .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
 702         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 703         .ring_create = psp_v13_0_ring_create,
 704         .ring_stop = psp_v13_0_ring_stop,
 705         .ring_destroy = psp_v13_0_ring_destroy,
 706         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 707         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 708         .mem_training = psp_v13_0_memory_training,
 709         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 710         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 711         .update_spirom = psp_v13_0_update_spirom,
 712         .vbflash_stat = psp_v13_0_vbflash_status
 713 };
 714
 715 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 716 {
 717         psp->funcs = &psp_v13_0_funcs;
 718 }