drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "uvd/uvd_7_0_offset.h"
  38 #include "gc/gc_9_0_offset.h"
  39 #include "gc/gc_9_0_sh_mask.h"
  40 #include "sdma0/sdma0_4_0_offset.h"
  41 #include "sdma1/sdma1_4_0_offset.h"
  42 #include "hdp/hdp_4_0_offset.h"
  43 #include "hdp/hdp_4_0_sh_mask.h"
  44 #include "mp/mp_9_0_offset.h"
  45 #include "mp/mp_9_0_sh_mask.h"
  46 #include "smuio/smuio_9_0_offset.h"
  47 #include "smuio/smuio_9_0_sh_mask.h"
  48
  49 #include "soc15.h"
  50 #include "soc15_common.h"
  51 #include "gfx_v9_0.h"
  52 #include "gmc_v9_0.h"
  53 #include "gfxhub_v1_0.h"
  54 #include "mmhub_v1_0.h"
  55 #include "df_v1_7.h"
  56 #include "vega10_ih.h"
  57 #include "sdma_v4_0.h"
  58 #include "uvd_v7_0.h"
  59 #include "vce_v4_0.h"
  60 #include "vcn_v1_0.h"
  61 #include "dce_virtual.h"
  62 #include "mxgpu_ai.h"
  63
  64 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  65 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  66 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  67 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  68
  69 /*
  70  * Indirect registers accessor
  71  */
  72 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  73 {
  74         unsigned long flags, address, data;
  75         u32 r;
  76         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  77         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  78
  79         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  80         WREG32(address, reg);
  81         (void)RREG32(address);
  82         r = RREG32(data);
  83         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  84         return r;
  85 }
  86
  87 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  88 {
  89         unsigned long flags, address, data;
  90
  91         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  92         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  93
  94         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  95         WREG32(address, reg);
  96         (void)RREG32(address);
  97         WREG32(data, v);
  98         (void)RREG32(data);
  99         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 100 }
 101
 102 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 103 {
 104         unsigned long flags, address, data;
 105         u32 r;
 106
 107         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 108         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 109
 110         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 111         WREG32(address, ((reg) & 0x1ff));
 112         r = RREG32(data);
 113         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 114         return r;
 115 }
 116
 117 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 118 {
 119         unsigned long flags, address, data;
 120
 121         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 122         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 123
 124         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 125         WREG32(address, ((reg) & 0x1ff));
 126         WREG32(data, (v));
 127         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 128 }
 129
 130 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 131 {
 132         unsigned long flags, address, data;
 133         u32 r;
 134
 135         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 136         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 137
 138         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 139         WREG32(address, (reg));
 140         r = RREG32(data);
 141         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 142         return r;
 143 }
 144
 145 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 146 {
 147         unsigned long flags, address, data;
 148
 149         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 150         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 151
 152         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 153         WREG32(address, (reg));
 154         WREG32(data, (v));
 155         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 156 }
 157
 158 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 159 {
 160         unsigned long flags;
 161         u32 r;
 162
 163         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 164         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 165         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 166         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 167         return r;
 168 }
 169
 170 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 171 {
 172         unsigned long flags;
 173
 174         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 175         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 176         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 177         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 178 }
 179
 180 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 181 {
 182         unsigned long flags;
 183         u32 r;
 184
 185         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 186         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 187         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 188         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 189         return r;
 190 }
 191
 192 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 193 {
 194         unsigned long flags;
 195
 196         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 197         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 198         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 199         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 200 }
 201
 202 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 203 {
 204         return adev->nbio_funcs->get_memsize(adev);
 205 }
 206
 207 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 208 {
 209         return adev->clock.spll.reference_freq;
 210 }
 211
 212
 213 void soc15_grbm_select(struct amdgpu_device *adev,
 214                      u32 me, u32 pipe, u32 queue, u32 vmid)
 215 {
 216         u32 grbm_gfx_cntl = 0;
 217         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 218         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 219         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 220         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 221
 222         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 223 }
 224
 225 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 226 {
 227         /* todo */
 228 }
 229
 230 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 231 {
 232         /* todo */
 233         return false;
 234 }
 235
 236 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 237                                      u8 *bios, u32 length_bytes)
 238 {
 239         u32 *dw_ptr;
 240         u32 i, length_dw;
 241
 242         if (bios == NULL)
 243                 return false;
 244         if (length_bytes == 0)
 245                 return false;
 246         /* APU vbios image is part of sbios image */
 247         if (adev->flags & AMD_IS_APU)
 248                 return false;
 249
 250         dw_ptr = (u32 *)bios;
 251         length_dw = ALIGN(length_bytes, 4) / 4;
 252
 253         /* set rom index to 0 */
 254         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 255         /* read out the rom data */
 256         for (i = 0; i < length_dw; i++)
 257                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 258
 259         return true;
 260 }
 261
 262 struct soc15_allowed_register_entry {
 263         uint32_t hwip;
 264         uint32_t inst;
 265         uint32_t seg;
 266         uint32_t reg_offset;
 267         bool grbm_indexed;
 268 };
 269
 270
 271 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 272         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 273         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 274         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 275         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 276         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 277         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 278         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 279         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 280         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 281         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 282         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 283         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 284         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 285         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 286         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 287         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 288         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 289         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 290         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 291 };
 292
 293 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 294                                          u32 sh_num, u32 reg_offset)
 295 {
 296         uint32_t val;
 297
 298         mutex_lock(&adev->grbm_idx_mutex);
 299         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 300                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 301
 302         val = RREG32(reg_offset);
 303
 304         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 305                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 306         mutex_unlock(&adev->grbm_idx_mutex);
 307         return val;
 308 }
 309
 310 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 311                                          bool indexed, u32 se_num,
 312                                          u32 sh_num, u32 reg_offset)
 313 {
 314         if (indexed) {
 315                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 316         } else {
 317                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 318                         return adev->gfx.config.gb_addr_config;
 319                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 320                         return adev->gfx.config.db_debug2;
 321                 return RREG32(reg_offset);
 322         }
 323 }
 324
 325 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 326                             u32 sh_num, u32 reg_offset, u32 *value)
 327 {
 328         uint32_t i;
 329         struct soc15_allowed_register_entry  *en;
 330
 331         *value = 0;
 332         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 333                 en = &soc15_allowed_read_registers[i];
 334                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 335                                         + en->reg_offset))
 336                         continue;
 337
 338                 *value = soc15_get_register_value(adev,
 339                                                   soc15_allowed_read_registers[i].grbm_indexed,
 340                                                   se_num, sh_num, reg_offset);
 341                 return 0;
 342         }
 343         return -EINVAL;
 344 }
 345
 346
 347 /**
 348  * soc15_program_register_sequence - program an array of registers.
 349  *
 350  * @adev: amdgpu_device pointer
 351  * @regs: pointer to the register array
 352  * @array_size: size of the register array
 353  *
 354  * Programs an array or registers with and and or masks.
 355  * This is a helper for setting golden registers.
 356  */
 357
 358 void soc15_program_register_sequence(struct amdgpu_device *adev,
 359                                              const struct soc15_reg_golden *regs,
 360                                              const u32 array_size)
 361 {
 362         const struct soc15_reg_golden *entry;
 363         u32 tmp, reg;
 364         int i;
 365
 366         for (i = 0; i < array_size; ++i) {
 367                 entry = &regs[i];
 368                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 369
 370                 if (entry->and_mask == 0xffffffff) {
 371                         tmp = entry->or_mask;
 372                 } else {
 373                         tmp = RREG32(reg);
 374                         tmp &= ~(entry->and_mask);
 375                         tmp |= entry->or_mask;
 376                 }
 377                 WREG32(reg, tmp);
 378         }
 379
 380 }
 381
 382
 383 static int soc15_asic_reset(struct amdgpu_device *adev)
 384 {
 385         u32 i;
 386
 387         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 388
 389         dev_info(adev->dev, "GPU reset\n");
 390
 391         /* disable BM */
 392         pci_clear_master(adev->pdev);
 393
 394         pci_save_state(adev->pdev);
 395
 396         psp_gpu_reset(adev);
 397
 398         pci_restore_state(adev->pdev);
 399
 400         /* wait for asic to come out of reset */
 401         for (i = 0; i < adev->usec_timeout; i++) {
 402                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 403
 404                 if (memsize != 0xffffffff)
 405                         break;
 406                 udelay(1);
 407         }
 408
 409         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 410
 411         return 0;
 412 }
 413
 414 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 415                         u32 cntl_reg, u32 status_reg)
 416 {
 417         return 0;
 418 }*/
 419
 420 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 421 {
 422         /*int r;
 423
 424         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 425         if (r)
 426                 return r;
 427
 428         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 429         */
 430         return 0;
 431 }
 432
 433 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 434 {
 435         /* todo */
 436
 437         return 0;
 438 }
 439
 440 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 441 {
 442         if (pci_is_root_bus(adev->pdev->bus))
 443                 return;
 444
 445         if (amdgpu_pcie_gen2 == 0)
 446                 return;
 447
 448         if (adev->flags & AMD_IS_APU)
 449                 return;
 450
 451         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 452                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 453                 return;
 454
 455         /* todo */
 456 }
 457
 458 static void soc15_program_aspm(struct amdgpu_device *adev)
 459 {
 460
 461         if (amdgpu_aspm == 0)
 462                 return;
 463
 464         /* todo */
 465 }
 466
 467 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 468                                            bool enable)
 469 {
 470         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 471         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 472 }
 473
 474 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 475 {
 476         .type = AMD_IP_BLOCK_TYPE_COMMON,
 477         .major = 2,
 478         .minor = 0,
 479         .rev = 0,
 480         .funcs = &soc15_common_ip_funcs,
 481 };
 482
 483 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 484 {
 485         /* Set IP register base before any HW register access */
 486         switch (adev->asic_type) {
 487         case CHIP_VEGA10:
 488         case CHIP_VEGA12:
 489         case CHIP_RAVEN:
 490                 vega10_reg_base_init(adev);
 491                 break;
 492         default:
 493                 return -EINVAL;
 494         }
 495
 496         if (adev->flags & AMD_IS_APU)
 497                 adev->nbio_funcs = &nbio_v7_0_funcs;
 498         else
 499                 adev->nbio_funcs = &nbio_v6_1_funcs;
 500
 501         adev->df_funcs = &df_v1_7_funcs;
 502         adev->nbio_funcs->detect_hw_virt(adev);
 503
 504         if (amdgpu_sriov_vf(adev))
 505                 adev->virt.ops = &xgpu_ai_virt_ops;
 506
 507         switch (adev->asic_type) {
 508         case CHIP_VEGA10:
 509         case CHIP_VEGA12:
 510                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 511                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 512                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 513                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 514                 if (!amdgpu_sriov_vf(adev))
 515                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 516                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 517                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 518 #if defined(CONFIG_DRM_AMD_DC)
 519                 else if (amdgpu_device_has_dc_support(adev))
 520                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 521 #else
 522 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 523 #endif
 524                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 525                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 526                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 527                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 528                 break;
 529         case CHIP_RAVEN:
 530                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 531                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 532                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 533                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 534                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 535                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 536                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 537 #if defined(CONFIG_DRM_AMD_DC)
 538                 else if (amdgpu_device_has_dc_support(adev))
 539                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 540 #else
 541 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 542 #endif
 543                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 544                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 545                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 546                 break;
 547         default:
 548                 return -EINVAL;
 549         }
 550
 551         return 0;
 552 }
 553
 554 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 555 {
 556         return adev->nbio_funcs->get_rev_id(adev);
 557 }
 558
 559 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 560 {
 561         adev->nbio_funcs->hdp_flush(adev, ring);
 562 }
 563
 564 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 565                                  struct amdgpu_ring *ring)
 566 {
 567         if (!ring || !ring->funcs->emit_wreg)
 568                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 569         else
 570                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 571                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 572 }
 573
 574 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 575 {
 576         /* change this when we implement soft reset */
 577         return true;
 578 }
 579
 580 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 581 {
 582         .read_disabled_bios = &soc15_read_disabled_bios,
 583         .read_bios_from_rom = &soc15_read_bios_from_rom,
 584         .read_register = &soc15_read_register,
 585         .reset = &soc15_asic_reset,
 586         .set_vga_state = &soc15_vga_set_state,
 587         .get_xclk = &soc15_get_xclk,
 588         .set_uvd_clocks = &soc15_set_uvd_clocks,
 589         .set_vce_clocks = &soc15_set_vce_clocks,
 590         .get_config_memsize = &soc15_get_config_memsize,
 591         .flush_hdp = &soc15_flush_hdp,
 592         .invalidate_hdp = &soc15_invalidate_hdp,
 593         .need_full_reset = &soc15_need_full_reset,
 594 };
 595
 596 static int soc15_common_early_init(void *handle)
 597 {
 598         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 599
 600         adev->smc_rreg = NULL;
 601         adev->smc_wreg = NULL;
 602         adev->pcie_rreg = &soc15_pcie_rreg;
 603         adev->pcie_wreg = &soc15_pcie_wreg;
 604         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 605         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 606         adev->didt_rreg = &soc15_didt_rreg;
 607         adev->didt_wreg = &soc15_didt_wreg;
 608         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 609         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 610         adev->se_cac_rreg = &soc15_se_cac_rreg;
 611         adev->se_cac_wreg = &soc15_se_cac_wreg;
 612
 613         adev->asic_funcs = &soc15_asic_funcs;
 614
 615         adev->rev_id = soc15_get_rev_id(adev);
 616         adev->external_rev_id = 0xFF;
 617         switch (adev->asic_type) {
 618         case CHIP_VEGA10:
 619                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 620                         AMD_CG_SUPPORT_GFX_MGLS |
 621                         AMD_CG_SUPPORT_GFX_RLC_LS |
 622                         AMD_CG_SUPPORT_GFX_CP_LS |
 623                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 624                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 625                         AMD_CG_SUPPORT_GFX_CGCG |
 626                         AMD_CG_SUPPORT_GFX_CGLS |
 627                         AMD_CG_SUPPORT_BIF_MGCG |
 628                         AMD_CG_SUPPORT_BIF_LS |
 629                         AMD_CG_SUPPORT_HDP_LS |
 630                         AMD_CG_SUPPORT_DRM_MGCG |
 631                         AMD_CG_SUPPORT_DRM_LS |
 632                         AMD_CG_SUPPORT_ROM_MGCG |
 633                         AMD_CG_SUPPORT_DF_MGCG |
 634                         AMD_CG_SUPPORT_SDMA_MGCG |
 635                         AMD_CG_SUPPORT_SDMA_LS |
 636                         AMD_CG_SUPPORT_MC_MGCG |
 637                         AMD_CG_SUPPORT_MC_LS;
 638                 adev->pg_flags = 0;
 639                 adev->external_rev_id = 0x1;
 640                 break;
 641         case CHIP_VEGA12:
 642                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 643                         AMD_CG_SUPPORT_GFX_MGLS |
 644                         AMD_CG_SUPPORT_GFX_CGCG |
 645                         AMD_CG_SUPPORT_GFX_CGLS |
 646                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 647                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 648                         AMD_CG_SUPPORT_GFX_CP_LS |
 649                         AMD_CG_SUPPORT_MC_LS |
 650                         AMD_CG_SUPPORT_MC_MGCG |
 651                         AMD_CG_SUPPORT_SDMA_MGCG |
 652                         AMD_CG_SUPPORT_SDMA_LS |
 653                         AMD_CG_SUPPORT_BIF_MGCG |
 654                         AMD_CG_SUPPORT_BIF_LS |
 655                         AMD_CG_SUPPORT_HDP_MGCG |
 656                         AMD_CG_SUPPORT_HDP_LS |
 657                         AMD_CG_SUPPORT_ROM_MGCG |
 658                         AMD_CG_SUPPORT_VCE_MGCG |
 659                         AMD_CG_SUPPORT_UVD_MGCG;
 660                 adev->pg_flags = 0;
 661                 adev->external_rev_id = adev->rev_id + 0x14;
 662                 break;
 663         case CHIP_RAVEN:
 664                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 665                         AMD_CG_SUPPORT_GFX_MGLS |
 666                         AMD_CG_SUPPORT_GFX_RLC_LS |
 667                         AMD_CG_SUPPORT_GFX_CP_LS |
 668                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 669                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 670                         AMD_CG_SUPPORT_GFX_CGCG |
 671                         AMD_CG_SUPPORT_GFX_CGLS |
 672                         AMD_CG_SUPPORT_BIF_MGCG |
 673                         AMD_CG_SUPPORT_BIF_LS |
 674                         AMD_CG_SUPPORT_HDP_MGCG |
 675                         AMD_CG_SUPPORT_HDP_LS |
 676                         AMD_CG_SUPPORT_DRM_MGCG |
 677                         AMD_CG_SUPPORT_DRM_LS |
 678                         AMD_CG_SUPPORT_ROM_MGCG |
 679                         AMD_CG_SUPPORT_MC_MGCG |
 680                         AMD_CG_SUPPORT_MC_LS |
 681                         AMD_CG_SUPPORT_SDMA_MGCG |
 682                         AMD_CG_SUPPORT_SDMA_LS;
 683                 adev->pg_flags = AMD_PG_SUPPORT_SDMA;
 684
 685                 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
 686                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 687                                 AMD_PG_SUPPORT_CP |
 688                                 AMD_PG_SUPPORT_RLC_SMU_HS;
 689
 690                 adev->external_rev_id = 0x1;
 691                 break;
 692         default:
 693                 /* FIXME: not supported yet */
 694                 return -EINVAL;
 695         }
 696
 697         if (amdgpu_sriov_vf(adev)) {
 698                 amdgpu_virt_init_setting(adev);
 699                 xgpu_ai_mailbox_set_irq_funcs(adev);
 700         }
 701
 702         return 0;
 703 }
 704
 705 static int soc15_common_late_init(void *handle)
 706 {
 707         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 708
 709         if (amdgpu_sriov_vf(adev))
 710                 xgpu_ai_mailbox_get_irq(adev);
 711
 712         return 0;
 713 }
 714
 715 static int soc15_common_sw_init(void *handle)
 716 {
 717         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 718
 719         if (amdgpu_sriov_vf(adev))
 720                 xgpu_ai_mailbox_add_irq_id(adev);
 721
 722         return 0;
 723 }
 724
 725 static int soc15_common_sw_fini(void *handle)
 726 {
 727         return 0;
 728 }
 729
 730 static int soc15_common_hw_init(void *handle)
 731 {
 732         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 733
 734         /* enable pcie gen2/3 link */
 735         soc15_pcie_gen3_enable(adev);
 736         /* enable aspm */
 737         soc15_program_aspm(adev);
 738         /* setup nbio registers */
 739         adev->nbio_funcs->init_registers(adev);
 740         /* enable the doorbell aperture */
 741         soc15_enable_doorbell_aperture(adev, true);
 742
 743         return 0;
 744 }
 745
 746 static int soc15_common_hw_fini(void *handle)
 747 {
 748         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 749
 750         /* disable the doorbell aperture */
 751         soc15_enable_doorbell_aperture(adev, false);
 752         if (amdgpu_sriov_vf(adev))
 753                 xgpu_ai_mailbox_put_irq(adev);
 754
 755         return 0;
 756 }
 757
 758 static int soc15_common_suspend(void *handle)
 759 {
 760         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 761
 762         return soc15_common_hw_fini(adev);
 763 }
 764
 765 static int soc15_common_resume(void *handle)
 766 {
 767         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 768
 769         return soc15_common_hw_init(adev);
 770 }
 771
 772 static bool soc15_common_is_idle(void *handle)
 773 {
 774         return true;
 775 }
 776
 777 static int soc15_common_wait_for_idle(void *handle)
 778 {
 779         return 0;
 780 }
 781
 782 static int soc15_common_soft_reset(void *handle)
 783 {
 784         return 0;
 785 }
 786
 787 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
 788 {
 789         uint32_t def, data;
 790
 791         def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 792
 793         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 794                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 795         else
 796                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 797
 798         if (def != data)
 799                 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
 800 }
 801
 802 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
 803 {
 804         uint32_t def, data;
 805
 806         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 807
 808         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
 809                 data &= ~(0x01000000 |
 810                           0x02000000 |
 811                           0x04000000 |
 812                           0x08000000 |
 813                           0x10000000 |
 814                           0x20000000 |
 815                           0x40000000 |
 816                           0x80000000);
 817         else
 818                 data |= (0x01000000 |
 819                          0x02000000 |
 820                          0x04000000 |
 821                          0x08000000 |
 822                          0x10000000 |
 823                          0x20000000 |
 824                          0x40000000 |
 825                          0x80000000);
 826
 827         if (def != data)
 828                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
 829 }
 830
 831 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
 832 {
 833         uint32_t def, data;
 834
 835         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 836
 837         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
 838                 data |= 1;
 839         else
 840                 data &= ~1;
 841
 842         if (def != data)
 843                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
 844 }
 845
 846 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 847                                                        bool enable)
 848 {
 849         uint32_t def, data;
 850
 851         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 852
 853         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
 854                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 855                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
 856         else
 857                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 858                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
 859
 860         if (def != data)
 861                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 862 }
 863
 864 static int soc15_common_set_clockgating_state(void *handle,
 865                                             enum amd_clockgating_state state)
 866 {
 867         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 868
 869         if (amdgpu_sriov_vf(adev))
 870                 return 0;
 871
 872         switch (adev->asic_type) {
 873         case CHIP_VEGA10:
 874         case CHIP_VEGA12:
 875                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
 876                                 state == AMD_CG_STATE_GATE ? true : false);
 877                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
 878                                 state == AMD_CG_STATE_GATE ? true : false);
 879                 soc15_update_hdp_light_sleep(adev,
 880                                 state == AMD_CG_STATE_GATE ? true : false);
 881                 soc15_update_drm_clock_gating(adev,
 882                                 state == AMD_CG_STATE_GATE ? true : false);
 883                 soc15_update_drm_light_sleep(adev,
 884                                 state == AMD_CG_STATE_GATE ? true : false);
 885                 soc15_update_rom_medium_grain_clock_gating(adev,
 886                                 state == AMD_CG_STATE_GATE ? true : false);
 887                 adev->df_funcs->update_medium_grain_clock_gating(adev,
 888                                 state == AMD_CG_STATE_GATE ? true : false);
 889                 break;
 890         case CHIP_RAVEN:
 891                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
 892                                 state == AMD_CG_STATE_GATE ? true : false);
 893                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
 894                                 state == AMD_CG_STATE_GATE ? true : false);
 895                 soc15_update_hdp_light_sleep(adev,
 896                                 state == AMD_CG_STATE_GATE ? true : false);
 897                 soc15_update_drm_clock_gating(adev,
 898                                 state == AMD_CG_STATE_GATE ? true : false);
 899                 soc15_update_drm_light_sleep(adev,
 900                                 state == AMD_CG_STATE_GATE ? true : false);
 901                 soc15_update_rom_medium_grain_clock_gating(adev,
 902                                 state == AMD_CG_STATE_GATE ? true : false);
 903                 break;
 904         default:
 905                 break;
 906         }
 907         return 0;
 908 }
 909
 910 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
 911 {
 912         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 913         int data;
 914
 915         if (amdgpu_sriov_vf(adev))
 916                 *flags = 0;
 917
 918         adev->nbio_funcs->get_clockgating_state(adev, flags);
 919
 920         /* AMD_CG_SUPPORT_HDP_LS */
 921         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 922         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 923                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 924
 925         /* AMD_CG_SUPPORT_DRM_MGCG */
 926         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 927         if (!(data & 0x01000000))
 928                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
 929
 930         /* AMD_CG_SUPPORT_DRM_LS */
 931         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 932         if (data & 0x1)
 933                 *flags |= AMD_CG_SUPPORT_DRM_LS;
 934
 935         /* AMD_CG_SUPPORT_ROM_MGCG */
 936         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 937         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
 938                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
 939
 940         adev->df_funcs->get_clockgating_state(adev, flags);
 941 }
 942
 943 static int soc15_common_set_powergating_state(void *handle,
 944                                             enum amd_powergating_state state)
 945 {
 946         /* todo */
 947         return 0;
 948 }
 949
 950 const struct amd_ip_funcs soc15_common_ip_funcs = {
 951         .name = "soc15_common",
 952         .early_init = soc15_common_early_init,
 953         .late_init = soc15_common_late_init,
 954         .sw_init = soc15_common_sw_init,
 955         .sw_fini = soc15_common_sw_fini,
 956         .hw_init = soc15_common_hw_init,
 957         .hw_fini = soc15_common_hw_fini,
 958         .suspend = soc15_common_suspend,
 959         .resume = soc15_common_resume,
 960         .is_idle = soc15_common_is_idle,
 961         .wait_for_idle = soc15_common_wait_for_idle,
 962         .soft_reset = soc15_common_soft_reset,
 963         .set_clockgating_state = soc15_common_set_clockgating_state,
 964         .set_powergating_state = soc15_common_set_powergating_state,
 965         .get_clockgating_state= soc15_common_get_clockgating_state,
 966 };