drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_object.h"
  48 #include "amdgpu_trace.h"
  49 #include "amdgpu_amdkfd.h"
  50 #include "bif/bif_4_1_d.h"
  51
  52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  53
  54 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  55                              struct ttm_mem_reg *mem, unsigned num_pages,
  56                              uint64_t offset, unsigned window,
  57                              struct amdgpu_ring *ring,
  58                              uint64_t *addr);
  59
  60 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  61 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  62
  63 /*
  64  * Global memory.
  65  */
  66 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  67 {
  68         return ttm_mem_global_init(ref->object);
  69 }
  70
  71 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  72 {
  73         ttm_mem_global_release(ref->object);
  74 }
  75
  76 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  77 {
  78         struct drm_global_reference *global_ref;
  79         struct amdgpu_ring *ring;
  80         struct drm_sched_rq *rq;
  81         int r;
  82
  83         adev->mman.mem_global_referenced = false;
  84         global_ref = &adev->mman.mem_global_ref;
  85         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  86         global_ref->size = sizeof(struct ttm_mem_global);
  87         global_ref->init = &amdgpu_ttm_mem_global_init;
  88         global_ref->release = &amdgpu_ttm_mem_global_release;
  89         r = drm_global_item_ref(global_ref);
  90         if (r) {
  91                 DRM_ERROR("Failed setting up TTM memory accounting "
  92                           "subsystem.\n");
  93                 goto error_mem;
  94         }
  95
  96         adev->mman.bo_global_ref.mem_glob =
  97                 adev->mman.mem_global_ref.object;
  98         global_ref = &adev->mman.bo_global_ref.ref;
  99         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 100         global_ref->size = sizeof(struct ttm_bo_global);
 101         global_ref->init = &ttm_bo_global_init;
 102         global_ref->release = &ttm_bo_global_release;
 103         r = drm_global_item_ref(global_ref);
 104         if (r) {
 105                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 106                 goto error_bo;
 107         }
 108
 109         mutex_init(&adev->mman.gtt_window_lock);
 110
 111         ring = adev->mman.buffer_funcs_ring;
 112         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
 113         r = drm_sched_entity_init(&ring->sched, &adev->mman.entity,
 114                                   rq, NULL);
 115         if (r) {
 116                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 117                 goto error_entity;
 118         }
 119
 120         adev->mman.mem_global_referenced = true;
 121
 122         return 0;
 123
 124 error_entity:
 125         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 126 error_bo:
 127         drm_global_item_unref(&adev->mman.mem_global_ref);
 128 error_mem:
 129         return r;
 130 }
 131
 132 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 133 {
 134         if (adev->mman.mem_global_referenced) {
 135                 drm_sched_entity_fini(adev->mman.entity.sched,
 136                                       &adev->mman.entity);
 137                 mutex_destroy(&adev->mman.gtt_window_lock);
 138                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 139                 drm_global_item_unref(&adev->mman.mem_global_ref);
 140                 adev->mman.mem_global_referenced = false;
 141         }
 142 }
 143
 144 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 145 {
 146         return 0;
 147 }
 148
 149 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 150                                 struct ttm_mem_type_manager *man)
 151 {
 152         struct amdgpu_device *adev;
 153
 154         adev = amdgpu_ttm_adev(bdev);
 155
 156         switch (type) {
 157         case TTM_PL_SYSTEM:
 158                 /* System memory */
 159                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 160                 man->available_caching = TTM_PL_MASK_CACHING;
 161                 man->default_caching = TTM_PL_FLAG_CACHED;
 162                 break;
 163         case TTM_PL_TT:
 164                 man->func = &amdgpu_gtt_mgr_func;
 165                 man->gpu_offset = adev->gmc.gart_start;
 166                 man->available_caching = TTM_PL_MASK_CACHING;
 167                 man->default_caching = TTM_PL_FLAG_CACHED;
 168                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 169                 break;
 170         case TTM_PL_VRAM:
 171                 /* "On-card" video ram */
 172                 man->func = &amdgpu_vram_mgr_func;
 173                 man->gpu_offset = adev->gmc.vram_start;
 174                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 175                              TTM_MEMTYPE_FLAG_MAPPABLE;
 176                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 177                 man->default_caching = TTM_PL_FLAG_WC;
 178                 break;
 179         case AMDGPU_PL_GDS:
 180         case AMDGPU_PL_GWS:
 181         case AMDGPU_PL_OA:
 182                 /* On-chip GDS memory*/
 183                 man->func = &ttm_bo_manager_func;
 184                 man->gpu_offset = 0;
 185                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 186                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 187                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 188                 break;
 189         default:
 190                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 191                 return -EINVAL;
 192         }
 193         return 0;
 194 }
 195
 196 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 197                                 struct ttm_placement *placement)
 198 {
 199         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 200         struct amdgpu_bo *abo;
 201         static const struct ttm_place placements = {
 202                 .fpfn = 0,
 203                 .lpfn = 0,
 204                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 205         };
 206
 207         if (bo->type == ttm_bo_type_sg) {
 208                 placement->num_placement = 0;
 209                 placement->num_busy_placement = 0;
 210                 return;
 211         }
 212
 213         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 214                 placement->placement = &placements;
 215                 placement->busy_placement = &placements;
 216                 placement->num_placement = 1;
 217                 placement->num_busy_placement = 1;
 218                 return;
 219         }
 220         abo = ttm_to_amdgpu_bo(bo);
 221         switch (bo->mem.mem_type) {
 222         case TTM_PL_VRAM:
 223                 if (!adev->mman.buffer_funcs_enabled) {
 224                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 225                 } else if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 226                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 227                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 228
 229                         /* Try evicting to the CPU inaccessible part of VRAM
 230                          * first, but only set GTT as busy placement, so this
 231                          * BO will be evicted to GTT rather than causing other
 232                          * BOs to be evicted from VRAM
 233                          */
 234                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 235                                                          AMDGPU_GEM_DOMAIN_GTT);
 236                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 237                         abo->placements[0].lpfn = 0;
 238                         abo->placement.busy_placement = &abo->placements[1];
 239                         abo->placement.num_busy_placement = 1;
 240                 } else {
 241                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 242                 }
 243                 break;
 244         case TTM_PL_TT:
 245         default:
 246                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 247         }
 248         *placement = abo->placement;
 249 }
 250
 251 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 252 {
 253         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 254
 255         /*
 256          * Don't verify access for KFD BOs. They don't have a GEM
 257          * object associated with them.
 258          */
 259         if (abo->kfd_bo)
 260                 return 0;
 261
 262         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 263                 return -EPERM;
 264         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 265                                           filp->private_data);
 266 }
 267
 268 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 269                              struct ttm_mem_reg *new_mem)
 270 {
 271         struct ttm_mem_reg *old_mem = &bo->mem;
 272
 273         BUG_ON(old_mem->mm_node != NULL);
 274         *old_mem = *new_mem;
 275         new_mem->mm_node = NULL;
 276 }
 277
 278 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 279                                     struct drm_mm_node *mm_node,
 280                                     struct ttm_mem_reg *mem)
 281 {
 282         uint64_t addr = 0;
 283
 284         if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
 285                 addr = mm_node->start << PAGE_SHIFT;
 286                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 287         }
 288         return addr;
 289 }
 290
 291 /**
 292  * amdgpu_find_mm_node - Helper function finds the drm_mm_node
 293  *  corresponding to @offset. It also modifies the offset to be
 294  *  within the drm_mm_node returned
 295  */
 296 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 297                                                unsigned long *offset)
 298 {
 299         struct drm_mm_node *mm_node = mem->mm_node;
 300
 301         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 302                 *offset -= (mm_node->size << PAGE_SHIFT);
 303                 ++mm_node;
 304         }
 305         return mm_node;
 306 }
 307
 308 /**
 309  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 310  *
 311  * The function copies @size bytes from {src->mem + src->offset} to
 312  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 313  * move and different for a BO to BO copy.
 314  *
 315  * @f: Returns the last fence if multiple jobs are submitted.
 316  */
 317 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 318                                struct amdgpu_copy_mem *src,
 319                                struct amdgpu_copy_mem *dst,
 320                                uint64_t size,
 321                                struct reservation_object *resv,
 322                                struct dma_fence **f)
 323 {
 324         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 325         struct drm_mm_node *src_mm, *dst_mm;
 326         uint64_t src_node_start, dst_node_start, src_node_size,
 327                  dst_node_size, src_page_offset, dst_page_offset;
 328         struct dma_fence *fence = NULL;
 329         int r = 0;
 330         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 331                                         AMDGPU_GPU_PAGE_SIZE);
 332
 333         if (!adev->mman.buffer_funcs_enabled) {
 334                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 335                 return -EINVAL;
 336         }
 337
 338         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 339         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 340                                              src->offset;
 341         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 342         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 343
 344         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 345         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 346                                              dst->offset;
 347         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 348         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 349
 350         mutex_lock(&adev->mman.gtt_window_lock);
 351
 352         while (size) {
 353                 unsigned long cur_size;
 354                 uint64_t from = src_node_start, to = dst_node_start;
 355                 struct dma_fence *next;
 356
 357                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 358                  * begins at an offset, then adjust the size accordingly
 359                  */
 360                 cur_size = min3(min(src_node_size, dst_node_size), size,
 361                                 GTT_MAX_BYTES);
 362                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 363                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 364                         cur_size -= max(src_page_offset, dst_page_offset);
 365
 366                 /* Map only what needs to be accessed. Map src to window 0 and
 367                  * dst to window 1
 368                  */
 369                 if (src->mem->mem_type == TTM_PL_TT &&
 370                     !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
 371                         r = amdgpu_map_buffer(src->bo, src->mem,
 372                                         PFN_UP(cur_size + src_page_offset),
 373                                         src_node_start, 0, ring,
 374                                         &from);
 375                         if (r)
 376                                 goto error;
 377                         /* Adjust the offset because amdgpu_map_buffer returns
 378                          * start of mapped page
 379                          */
 380                         from += src_page_offset;
 381                 }
 382
 383                 if (dst->mem->mem_type == TTM_PL_TT &&
 384                     !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
 385                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 386                                         PFN_UP(cur_size + dst_page_offset),
 387                                         dst_node_start, 1, ring,
 388                                         &to);
 389                         if (r)
 390                                 goto error;
 391                         to += dst_page_offset;
 392                 }
 393
 394                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 395                                        resv, &next, false, true);
 396                 if (r)
 397                         goto error;
 398
 399                 dma_fence_put(fence);
 400                 fence = next;
 401
 402                 size -= cur_size;
 403                 if (!size)
 404                         break;
 405
 406                 src_node_size -= cur_size;
 407                 if (!src_node_size) {
 408                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 409                                                              src->mem);
 410                         src_node_size = (src_mm->size << PAGE_SHIFT);
 411                 } else {
 412                         src_node_start += cur_size;
 413                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 414                 }
 415                 dst_node_size -= cur_size;
 416                 if (!dst_node_size) {
 417                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 418                                                              dst->mem);
 419                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 420                 } else {
 421                         dst_node_start += cur_size;
 422                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 423                 }
 424         }
 425 error:
 426         mutex_unlock(&adev->mman.gtt_window_lock);
 427         if (f)
 428                 *f = dma_fence_get(fence);
 429         dma_fence_put(fence);
 430         return r;
 431 }
 432
 433
 434 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 435                             bool evict, bool no_wait_gpu,
 436                             struct ttm_mem_reg *new_mem,
 437                             struct ttm_mem_reg *old_mem)
 438 {
 439         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 440         struct amdgpu_copy_mem src, dst;
 441         struct dma_fence *fence = NULL;
 442         int r;
 443
 444         src.bo = bo;
 445         dst.bo = bo;
 446         src.mem = old_mem;
 447         dst.mem = new_mem;
 448         src.offset = 0;
 449         dst.offset = 0;
 450
 451         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 452                                        new_mem->num_pages << PAGE_SHIFT,
 453                                        bo->resv, &fence);
 454         if (r)
 455                 goto error;
 456
 457         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 458         dma_fence_put(fence);
 459         return r;
 460
 461 error:
 462         if (fence)
 463                 dma_fence_wait(fence, false);
 464         dma_fence_put(fence);
 465         return r;
 466 }
 467
 468 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 469                                 struct ttm_operation_ctx *ctx,
 470                                 struct ttm_mem_reg *new_mem)
 471 {
 472         struct amdgpu_device *adev;
 473         struct ttm_mem_reg *old_mem = &bo->mem;
 474         struct ttm_mem_reg tmp_mem;
 475         struct ttm_place placements;
 476         struct ttm_placement placement;
 477         int r;
 478
 479         adev = amdgpu_ttm_adev(bo->bdev);
 480         tmp_mem = *new_mem;
 481         tmp_mem.mm_node = NULL;
 482         placement.num_placement = 1;
 483         placement.placement = &placements;
 484         placement.num_busy_placement = 1;
 485         placement.busy_placement = &placements;
 486         placements.fpfn = 0;
 487         placements.lpfn = 0;
 488         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 489         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 490         if (unlikely(r)) {
 491                 return r;
 492         }
 493
 494         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 495         if (unlikely(r)) {
 496                 goto out_cleanup;
 497         }
 498
 499         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 500         if (unlikely(r)) {
 501                 goto out_cleanup;
 502         }
 503         r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, &tmp_mem, old_mem);
 504         if (unlikely(r)) {
 505                 goto out_cleanup;
 506         }
 507         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 508 out_cleanup:
 509         ttm_bo_mem_put(bo, &tmp_mem);
 510         return r;
 511 }
 512
 513 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 514                                 struct ttm_operation_ctx *ctx,
 515                                 struct ttm_mem_reg *new_mem)
 516 {
 517         struct amdgpu_device *adev;
 518         struct ttm_mem_reg *old_mem = &bo->mem;
 519         struct ttm_mem_reg tmp_mem;
 520         struct ttm_placement placement;
 521         struct ttm_place placements;
 522         int r;
 523
 524         adev = amdgpu_ttm_adev(bo->bdev);
 525         tmp_mem = *new_mem;
 526         tmp_mem.mm_node = NULL;
 527         placement.num_placement = 1;
 528         placement.placement = &placements;
 529         placement.num_busy_placement = 1;
 530         placement.busy_placement = &placements;
 531         placements.fpfn = 0;
 532         placements.lpfn = 0;
 533         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 534         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 535         if (unlikely(r)) {
 536                 return r;
 537         }
 538         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 539         if (unlikely(r)) {
 540                 goto out_cleanup;
 541         }
 542         r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, new_mem, old_mem);
 543         if (unlikely(r)) {
 544                 goto out_cleanup;
 545         }
 546 out_cleanup:
 547         ttm_bo_mem_put(bo, &tmp_mem);
 548         return r;
 549 }
 550
 551 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 552                           struct ttm_operation_ctx *ctx,
 553                           struct ttm_mem_reg *new_mem)
 554 {
 555         struct amdgpu_device *adev;
 556         struct amdgpu_bo *abo;
 557         struct ttm_mem_reg *old_mem = &bo->mem;
 558         int r;
 559
 560         /* Can't move a pinned BO */
 561         abo = ttm_to_amdgpu_bo(bo);
 562         if (WARN_ON_ONCE(abo->pin_count > 0))
 563                 return -EINVAL;
 564
 565         adev = amdgpu_ttm_adev(bo->bdev);
 566
 567         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 568                 amdgpu_move_null(bo, new_mem);
 569                 return 0;
 570         }
 571         if ((old_mem->mem_type == TTM_PL_TT &&
 572              new_mem->mem_type == TTM_PL_SYSTEM) ||
 573             (old_mem->mem_type == TTM_PL_SYSTEM &&
 574              new_mem->mem_type == TTM_PL_TT)) {
 575                 /* bind is enough */
 576                 amdgpu_move_null(bo, new_mem);
 577                 return 0;
 578         }
 579
 580         if (!adev->mman.buffer_funcs_enabled)
 581                 goto memcpy;
 582
 583         if (old_mem->mem_type == TTM_PL_VRAM &&
 584             new_mem->mem_type == TTM_PL_SYSTEM) {
 585                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 586         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 587                    new_mem->mem_type == TTM_PL_VRAM) {
 588                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 589         } else {
 590                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 591                                      new_mem, old_mem);
 592         }
 593
 594         if (r) {
 595 memcpy:
 596                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 597                 if (r) {
 598                         return r;
 599                 }
 600         }
 601
 602         if (bo->type == ttm_bo_type_device &&
 603             new_mem->mem_type == TTM_PL_VRAM &&
 604             old_mem->mem_type != TTM_PL_VRAM) {
 605                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 606                  * accesses the BO after it's moved.
 607                  */
 608                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 609         }
 610
 611         /* update statistics */
 612         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 613         return 0;
 614 }
 615
 616 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 617 {
 618         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 619         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 620         struct drm_mm_node *mm_node = mem->mm_node;
 621
 622         mem->bus.addr = NULL;
 623         mem->bus.offset = 0;
 624         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 625         mem->bus.base = 0;
 626         mem->bus.is_iomem = false;
 627         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 628                 return -EINVAL;
 629         switch (mem->mem_type) {
 630         case TTM_PL_SYSTEM:
 631                 /* system memory */
 632                 return 0;
 633         case TTM_PL_TT:
 634                 break;
 635         case TTM_PL_VRAM:
 636                 mem->bus.offset = mem->start << PAGE_SHIFT;
 637                 /* check if it's visible */
 638                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 639                         return -EINVAL;
 640                 /* Only physically contiguous buffers apply. In a contiguous
 641                  * buffer, size of the first mm_node would match the number of
 642                  * pages in ttm_mem_reg.
 643                  */
 644                 if (adev->mman.aper_base_kaddr &&
 645                     (mm_node->size == mem->num_pages))
 646                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 647                                         mem->bus.offset;
 648
 649                 mem->bus.base = adev->gmc.aper_base;
 650                 mem->bus.is_iomem = true;
 651                 break;
 652         default:
 653                 return -EINVAL;
 654         }
 655         return 0;
 656 }
 657
 658 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 659 {
 660 }
 661
 662 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 663                                            unsigned long page_offset)
 664 {
 665         struct drm_mm_node *mm;
 666         unsigned long offset = (page_offset << PAGE_SHIFT);
 667
 668         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 669         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 670                 (offset >> PAGE_SHIFT);
 671 }
 672
 673 /*
 674  * TTM backend functions.
 675  */
 676 struct amdgpu_ttm_gup_task_list {
 677         struct list_head        list;
 678         struct task_struct      *task;
 679 };
 680
 681 struct amdgpu_ttm_tt {
 682         struct ttm_dma_tt       ttm;
 683         u64                     offset;
 684         uint64_t                userptr;
 685         struct task_struct      *usertask;
 686         uint32_t                userflags;
 687         spinlock_t              guptasklock;
 688         struct list_head        guptasks;
 689         atomic_t                mmu_invalidations;
 690         uint32_t                last_set_pages;
 691 };
 692
 693 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 694 {
 695         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 696         struct mm_struct *mm = gtt->usertask->mm;
 697         unsigned int flags = 0;
 698         unsigned pinned = 0;
 699         int r;
 700
 701         if (!mm) /* Happens during process shutdown */
 702                 return -ESRCH;
 703
 704         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 705                 flags |= FOLL_WRITE;
 706
 707         down_read(&mm->mmap_sem);
 708
 709         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 710                 /* check that we only use anonymous memory
 711                    to prevent problems with writeback */
 712                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 713                 struct vm_area_struct *vma;
 714
 715                 vma = find_vma(mm, gtt->userptr);
 716                 if (!vma || vma->vm_file || vma->vm_end < end) {
 717                         up_read(&mm->mmap_sem);
 718                         return -EPERM;
 719                 }
 720         }
 721
 722         do {
 723                 unsigned num_pages = ttm->num_pages - pinned;
 724                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 725                 struct page **p = pages + pinned;
 726                 struct amdgpu_ttm_gup_task_list guptask;
 727
 728                 guptask.task = current;
 729                 spin_lock(&gtt->guptasklock);
 730                 list_add(&guptask.list, &gtt->guptasks);
 731                 spin_unlock(&gtt->guptasklock);
 732
 733                 if (mm == current->mm)
 734                         r = get_user_pages(userptr, num_pages, flags, p, NULL);
 735                 else
 736                         r = get_user_pages_remote(gtt->usertask,
 737                                         mm, userptr, num_pages,
 738                                         flags, p, NULL, NULL);
 739
 740                 spin_lock(&gtt->guptasklock);
 741                 list_del(&guptask.list);
 742                 spin_unlock(&gtt->guptasklock);
 743
 744                 if (r < 0)
 745                         goto release_pages;
 746
 747                 pinned += r;
 748
 749         } while (pinned < ttm->num_pages);
 750
 751         up_read(&mm->mmap_sem);
 752         return 0;
 753
 754 release_pages:
 755         release_pages(pages, pinned);
 756         up_read(&mm->mmap_sem);
 757         return r;
 758 }
 759
 760 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 761 {
 762         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 763         unsigned i;
 764
 765         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 766         for (i = 0; i < ttm->num_pages; ++i) {
 767                 if (ttm->pages[i])
 768                         put_page(ttm->pages[i]);
 769
 770                 ttm->pages[i] = pages ? pages[i] : NULL;
 771         }
 772 }
 773
 774 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 775 {
 776         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 777         unsigned i;
 778
 779         for (i = 0; i < ttm->num_pages; ++i) {
 780                 struct page *page = ttm->pages[i];
 781
 782                 if (!page)
 783                         continue;
 784
 785                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 786                         set_page_dirty(page);
 787
 788                 mark_page_accessed(page);
 789         }
 790 }
 791
 792 /* prepare the sg table with the user pages */
 793 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 794 {
 795         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 796         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 797         unsigned nents;
 798         int r;
 799
 800         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 801         enum dma_data_direction direction = write ?
 802                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 803
 804         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 805                                       ttm->num_pages << PAGE_SHIFT,
 806                                       GFP_KERNEL);
 807         if (r)
 808                 goto release_sg;
 809
 810         r = -ENOMEM;
 811         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 812         if (nents != ttm->sg->nents)
 813                 goto release_sg;
 814
 815         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 816                                          gtt->ttm.dma_address, ttm->num_pages);
 817
 818         return 0;
 819
 820 release_sg:
 821         kfree(ttm->sg);
 822         return r;
 823 }
 824
 825 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 826 {
 827         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 828         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 829
 830         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 831         enum dma_data_direction direction = write ?
 832                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 833
 834         /* double check that we don't free the table twice */
 835         if (!ttm->sg->sgl)
 836                 return;
 837
 838         /* free the sg table and pages again */
 839         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 840
 841         amdgpu_ttm_tt_mark_user_pages(ttm);
 842
 843         sg_free_table(ttm->sg);
 844 }
 845
 846 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 847                                 struct ttm_buffer_object *tbo,
 848                                 uint64_t flags)
 849 {
 850         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 851         struct ttm_tt *ttm = tbo->ttm;
 852         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 853         int r;
 854
 855         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
 856                 uint64_t page_idx = 1;
 857
 858                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 859                                 ttm->pages, gtt->ttm.dma_address, flags);
 860                 if (r)
 861                         goto gart_bind_fail;
 862
 863                 /* Patch mtype of the second part BO */
 864                 flags &=  ~AMDGPU_PTE_MTYPE_MASK;
 865                 flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
 866
 867                 r = amdgpu_gart_bind(adev,
 868                                 gtt->offset + (page_idx << PAGE_SHIFT),
 869                                 ttm->num_pages - page_idx,
 870                                 &ttm->pages[page_idx],
 871                                 &(gtt->ttm.dma_address[page_idx]), flags);
 872         } else {
 873                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 874                                      ttm->pages, gtt->ttm.dma_address, flags);
 875         }
 876
 877 gart_bind_fail:
 878         if (r)
 879                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 880                           ttm->num_pages, gtt->offset);
 881
 882         return r;
 883 }
 884
 885 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 886                                    struct ttm_mem_reg *bo_mem)
 887 {
 888         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 889         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 890         uint64_t flags;
 891         int r = 0;
 892
 893         if (gtt->userptr) {
 894                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 895                 if (r) {
 896                         DRM_ERROR("failed to pin userptr\n");
 897                         return r;
 898                 }
 899         }
 900         if (!ttm->num_pages) {
 901                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 902                      ttm->num_pages, bo_mem, ttm);
 903         }
 904
 905         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 906             bo_mem->mem_type == AMDGPU_PL_GWS ||
 907             bo_mem->mem_type == AMDGPU_PL_OA)
 908                 return -EINVAL;
 909
 910         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 911                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 912                 return 0;
 913         }
 914
 915         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 916         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 917         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 918                 ttm->pages, gtt->ttm.dma_address, flags);
 919
 920         if (r)
 921                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 922                           ttm->num_pages, gtt->offset);
 923         return r;
 924 }
 925
 926 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 927 {
 928         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 929         struct ttm_operation_ctx ctx = { false, false };
 930         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
 931         struct ttm_mem_reg tmp;
 932         struct ttm_placement placement;
 933         struct ttm_place placements;
 934         uint64_t flags;
 935         int r;
 936
 937         if (bo->mem.mem_type != TTM_PL_TT ||
 938             amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
 939                 return 0;
 940
 941         tmp = bo->mem;
 942         tmp.mm_node = NULL;
 943         placement.num_placement = 1;
 944         placement.placement = &placements;
 945         placement.num_busy_placement = 1;
 946         placement.busy_placement = &placements;
 947         placements.fpfn = 0;
 948         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 949         placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
 950                 TTM_PL_FLAG_TT;
 951
 952         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 953         if (unlikely(r))
 954                 return r;
 955
 956         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
 957         gtt->offset = (u64)tmp.start << PAGE_SHIFT;
 958         r = amdgpu_ttm_gart_bind(adev, bo, flags);
 959         if (unlikely(r)) {
 960                 ttm_bo_mem_put(bo, &tmp);
 961                 return r;
 962         }
 963
 964         ttm_bo_mem_put(bo, &bo->mem);
 965         bo->mem = tmp;
 966         bo->offset = (bo->mem.start << PAGE_SHIFT) +
 967                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
 968
 969         return 0;
 970 }
 971
 972 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
 973 {
 974         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
 975         uint64_t flags;
 976         int r;
 977
 978         if (!tbo->ttm)
 979                 return 0;
 980
 981         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
 982         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
 983
 984         return r;
 985 }
 986
 987 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 988 {
 989         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 990         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 991         int r;
 992
 993         if (gtt->userptr)
 994                 amdgpu_ttm_tt_unpin_userptr(ttm);
 995
 996         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
 997                 return 0;
 998
 999         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1000         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1001         if (r)
1002                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1003                           gtt->ttm.ttm.num_pages, gtt->offset);
1004         return r;
1005 }
1006
1007 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1008 {
1009         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1010
1011         if (gtt->usertask)
1012                 put_task_struct(gtt->usertask);
1013
1014         ttm_dma_tt_fini(&gtt->ttm);
1015         kfree(gtt);
1016 }
1017
1018 static struct ttm_backend_func amdgpu_backend_func = {
1019         .bind = &amdgpu_ttm_backend_bind,
1020         .unbind = &amdgpu_ttm_backend_unbind,
1021         .destroy = &amdgpu_ttm_backend_destroy,
1022 };
1023
1024 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1025                                            uint32_t page_flags)
1026 {
1027         struct amdgpu_device *adev;
1028         struct amdgpu_ttm_tt *gtt;
1029
1030         adev = amdgpu_ttm_adev(bo->bdev);
1031
1032         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1033         if (gtt == NULL) {
1034                 return NULL;
1035         }
1036         gtt->ttm.ttm.func = &amdgpu_backend_func;
1037         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1038                 kfree(gtt);
1039                 return NULL;
1040         }
1041         return &gtt->ttm.ttm;
1042 }
1043
1044 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1045                         struct ttm_operation_ctx *ctx)
1046 {
1047         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1048         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1049         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1050
1051         if (gtt && gtt->userptr) {
1052                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1053                 if (!ttm->sg)
1054                         return -ENOMEM;
1055
1056                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1057                 ttm->state = tt_unbound;
1058                 return 0;
1059         }
1060
1061         if (slave && ttm->sg) {
1062                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1063                                                  gtt->ttm.dma_address,
1064                                                  ttm->num_pages);
1065                 ttm->state = tt_unbound;
1066                 return 0;
1067         }
1068
1069 #ifdef CONFIG_SWIOTLB
1070         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1071                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1072         }
1073 #endif
1074
1075         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1076 }
1077
1078 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1079 {
1080         struct amdgpu_device *adev;
1081         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1082         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1083
1084         if (gtt && gtt->userptr) {
1085                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1086                 kfree(ttm->sg);
1087                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1088                 return;
1089         }
1090
1091         if (slave)
1092                 return;
1093
1094         adev = amdgpu_ttm_adev(ttm->bdev);
1095
1096 #ifdef CONFIG_SWIOTLB
1097         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1098                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1099                 return;
1100         }
1101 #endif
1102
1103         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1104 }
1105
1106 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1107                               uint32_t flags)
1108 {
1109         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1110
1111         if (gtt == NULL)
1112                 return -EINVAL;
1113
1114         gtt->userptr = addr;
1115         gtt->userflags = flags;
1116
1117         if (gtt->usertask)
1118                 put_task_struct(gtt->usertask);
1119         gtt->usertask = current->group_leader;
1120         get_task_struct(gtt->usertask);
1121
1122         spin_lock_init(&gtt->guptasklock);
1123         INIT_LIST_HEAD(&gtt->guptasks);
1124         atomic_set(&gtt->mmu_invalidations, 0);
1125         gtt->last_set_pages = 0;
1126
1127         return 0;
1128 }
1129
1130 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1131 {
1132         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1133
1134         if (gtt == NULL)
1135                 return NULL;
1136
1137         if (gtt->usertask == NULL)
1138                 return NULL;
1139
1140         return gtt->usertask->mm;
1141 }
1142
1143 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1144                                   unsigned long end)
1145 {
1146         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1147         struct amdgpu_ttm_gup_task_list *entry;
1148         unsigned long size;
1149
1150         if (gtt == NULL || !gtt->userptr)
1151                 return false;
1152
1153         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1154         if (gtt->userptr > end || gtt->userptr + size <= start)
1155                 return false;
1156
1157         spin_lock(&gtt->guptasklock);
1158         list_for_each_entry(entry, &gtt->guptasks, list) {
1159                 if (entry->task == current) {
1160                         spin_unlock(&gtt->guptasklock);
1161                         return false;
1162                 }
1163         }
1164         spin_unlock(&gtt->guptasklock);
1165
1166         atomic_inc(&gtt->mmu_invalidations);
1167
1168         return true;
1169 }
1170
1171 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1172                                        int *last_invalidated)
1173 {
1174         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1175         int prev_invalidated = *last_invalidated;
1176
1177         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1178         return prev_invalidated != *last_invalidated;
1179 }
1180
1181 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1182 {
1183         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1184
1185         if (gtt == NULL || !gtt->userptr)
1186                 return false;
1187
1188         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1189 }
1190
1191 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1192 {
1193         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1194
1195         if (gtt == NULL)
1196                 return false;
1197
1198         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1199 }
1200
1201 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1202                                  struct ttm_mem_reg *mem)
1203 {
1204         uint64_t flags = 0;
1205
1206         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1207                 flags |= AMDGPU_PTE_VALID;
1208
1209         if (mem && mem->mem_type == TTM_PL_TT) {
1210                 flags |= AMDGPU_PTE_SYSTEM;
1211
1212                 if (ttm->caching_state == tt_cached)
1213                         flags |= AMDGPU_PTE_SNOOPED;
1214         }
1215
1216         flags |= adev->gart.gart_pte_flags;
1217         flags |= AMDGPU_PTE_READABLE;
1218
1219         if (!amdgpu_ttm_tt_is_readonly(ttm))
1220                 flags |= AMDGPU_PTE_WRITEABLE;
1221
1222         return flags;
1223 }
1224
1225 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1226                                             const struct ttm_place *place)
1227 {
1228         unsigned long num_pages = bo->mem.num_pages;
1229         struct drm_mm_node *node = bo->mem.mm_node;
1230         struct reservation_object_list *flist;
1231         struct dma_fence *f;
1232         int i;
1233
1234         /* If bo is a KFD BO, check if the bo belongs to the current process.
1235          * If true, then return false as any KFD process needs all its BOs to
1236          * be resident to run successfully
1237          */
1238         flist = reservation_object_get_list(bo->resv);
1239         if (flist) {
1240                 for (i = 0; i < flist->shared_count; ++i) {
1241                         f = rcu_dereference_protected(flist->shared[i],
1242                                 reservation_object_held(bo->resv));
1243                         if (amdkfd_fence_check_mm(f, current->mm))
1244                                 return false;
1245                 }
1246         }
1247
1248         switch (bo->mem.mem_type) {
1249         case TTM_PL_TT:
1250                 return true;
1251
1252         case TTM_PL_VRAM:
1253                 /* Check each drm MM node individually */
1254                 while (num_pages) {
1255                         if (place->fpfn < (node->start + node->size) &&
1256                             !(place->lpfn && place->lpfn <= node->start))
1257                                 return true;
1258
1259                         num_pages -= node->size;
1260                         ++node;
1261                 }
1262                 return false;
1263
1264         default:
1265                 break;
1266         }
1267
1268         return ttm_bo_eviction_valuable(bo, place);
1269 }
1270
1271 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1272                                     unsigned long offset,
1273                                     void *buf, int len, int write)
1274 {
1275         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1276         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1277         struct drm_mm_node *nodes;
1278         uint32_t value = 0;
1279         int ret = 0;
1280         uint64_t pos;
1281         unsigned long flags;
1282
1283         if (bo->mem.mem_type != TTM_PL_VRAM)
1284                 return -EIO;
1285
1286         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1287         pos = (nodes->start << PAGE_SHIFT) + offset;
1288
1289         while (len && pos < adev->gmc.mc_vram_size) {
1290                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1291                 uint32_t bytes = 4 - (pos & 3);
1292                 uint32_t shift = (pos & 3) * 8;
1293                 uint32_t mask = 0xffffffff << shift;
1294
1295                 if (len < bytes) {
1296                         mask &= 0xffffffff >> (bytes - len) * 8;
1297                         bytes = len;
1298                 }
1299
1300                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1301                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1302                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1303                 if (!write || mask != 0xffffffff)
1304                         value = RREG32_NO_KIQ(mmMM_DATA);
1305                 if (write) {
1306                         value &= ~mask;
1307                         value |= (*(uint32_t *)buf << shift) & mask;
1308                         WREG32_NO_KIQ(mmMM_DATA, value);
1309                 }
1310                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1311                 if (!write) {
1312                         value = (value & mask) >> shift;
1313                         memcpy(buf, &value, bytes);
1314                 }
1315
1316                 ret += bytes;
1317                 buf = (uint8_t *)buf + bytes;
1318                 pos += bytes;
1319                 len -= bytes;
1320                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1321                         ++nodes;
1322                         pos = (nodes->start << PAGE_SHIFT);
1323                 }
1324         }
1325
1326         return ret;
1327 }
1328
1329 static struct ttm_bo_driver amdgpu_bo_driver = {
1330         .ttm_tt_create = &amdgpu_ttm_tt_create,
1331         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1332         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1333         .invalidate_caches = &amdgpu_invalidate_caches,
1334         .init_mem_type = &amdgpu_init_mem_type,
1335         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1336         .evict_flags = &amdgpu_evict_flags,
1337         .move = &amdgpu_bo_move,
1338         .verify_access = &amdgpu_verify_access,
1339         .move_notify = &amdgpu_bo_move_notify,
1340         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1341         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1342         .io_mem_free = &amdgpu_ttm_io_mem_free,
1343         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1344         .access_memory = &amdgpu_ttm_access_memory
1345 };
1346
1347 /*
1348  * Firmware Reservation functions
1349  */
1350 /**
1351  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1352  *
1353  * @adev: amdgpu_device pointer
1354  *
1355  * free fw reserved vram if it has been reserved.
1356  */
1357 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1358 {
1359         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1360                 NULL, &adev->fw_vram_usage.va);
1361 }
1362
1363 /**
1364  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1365  *
1366  * @adev: amdgpu_device pointer
1367  *
1368  * create bo vram reservation from fw.
1369  */
1370 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1371 {
1372         struct ttm_operation_ctx ctx = { false, false };
1373         struct amdgpu_bo_param bp;
1374         int r = 0;
1375         int i;
1376         u64 vram_size = adev->gmc.visible_vram_size;
1377         u64 offset = adev->fw_vram_usage.start_offset;
1378         u64 size = adev->fw_vram_usage.size;
1379         struct amdgpu_bo *bo;
1380
1381         memset(&bp, 0, sizeof(bp));
1382         bp.size = adev->fw_vram_usage.size;
1383         bp.byte_align = PAGE_SIZE;
1384         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1385         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1386                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1387         bp.type = ttm_bo_type_kernel;
1388         bp.resv = NULL;
1389         adev->fw_vram_usage.va = NULL;
1390         adev->fw_vram_usage.reserved_bo = NULL;
1391
1392         if (adev->fw_vram_usage.size > 0 &&
1393                 adev->fw_vram_usage.size <= vram_size) {
1394
1395                 r = amdgpu_bo_create(adev, &bp,
1396                                      &adev->fw_vram_usage.reserved_bo);
1397                 if (r)
1398                         goto error_create;
1399
1400                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1401                 if (r)
1402                         goto error_reserve;
1403
1404                 /* remove the original mem node and create a new one at the
1405                  * request position
1406                  */
1407                 bo = adev->fw_vram_usage.reserved_bo;
1408                 offset = ALIGN(offset, PAGE_SIZE);
1409                 for (i = 0; i < bo->placement.num_placement; ++i) {
1410                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1411                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1412                 }
1413
1414                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1415                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1416                                      &bo->tbo.mem, &ctx);
1417                 if (r)
1418                         goto error_pin;
1419
1420                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1421                         AMDGPU_GEM_DOMAIN_VRAM,
1422                         adev->fw_vram_usage.start_offset,
1423                         (adev->fw_vram_usage.start_offset +
1424                         adev->fw_vram_usage.size), NULL);
1425                 if (r)
1426                         goto error_pin;
1427                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1428                         &adev->fw_vram_usage.va);
1429                 if (r)
1430                         goto error_kmap;
1431
1432                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1433         }
1434         return r;
1435
1436 error_kmap:
1437         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1438 error_pin:
1439         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1440 error_reserve:
1441         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1442 error_create:
1443         adev->fw_vram_usage.va = NULL;
1444         adev->fw_vram_usage.reserved_bo = NULL;
1445         return r;
1446 }
1447
1448 int amdgpu_ttm_init(struct amdgpu_device *adev)
1449 {
1450         uint64_t gtt_size;
1451         int r;
1452         u64 vis_vram_limit;
1453
1454         r = amdgpu_ttm_global_init(adev);
1455         if (r) {
1456                 return r;
1457         }
1458         /* No others user of address space so set it to 0 */
1459         r = ttm_bo_device_init(&adev->mman.bdev,
1460                                adev->mman.bo_global_ref.ref.object,
1461                                &amdgpu_bo_driver,
1462                                adev->ddev->anon_inode->i_mapping,
1463                                DRM_FILE_PAGE_OFFSET,
1464                                adev->need_dma32);
1465         if (r) {
1466                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1467                 return r;
1468         }
1469         adev->mman.initialized = true;
1470
1471         /* We opt to avoid OOM on system pages allocations */
1472         adev->mman.bdev.no_retry = true;
1473
1474         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1475                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1476         if (r) {
1477                 DRM_ERROR("Failed initializing VRAM heap.\n");
1478                 return r;
1479         }
1480
1481         /* Reduce size of CPU-visible VRAM if requested */
1482         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1483         if (amdgpu_vis_vram_limit > 0 &&
1484             vis_vram_limit <= adev->gmc.visible_vram_size)
1485                 adev->gmc.visible_vram_size = vis_vram_limit;
1486
1487         /* Change the size here instead of the init above so only lpfn is affected */
1488         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1489 #ifdef CONFIG_64BIT
1490         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1491                                                 adev->gmc.visible_vram_size);
1492 #endif
1493
1494         /*
1495          *The reserved vram for firmware must be pinned to the specified
1496          *place on the VRAM, so reserve it early.
1497          */
1498         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1499         if (r) {
1500                 return r;
1501         }
1502
1503         if (adev->gmc.stolen_size) {
1504                 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1505                                             AMDGPU_GEM_DOMAIN_VRAM,
1506                                             &adev->stolen_vga_memory,
1507                                             NULL, NULL);
1508                 if (r)
1509                         return r;
1510         }
1511         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1512                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1513
1514         if (amdgpu_gtt_size == -1) {
1515                 struct sysinfo si;
1516
1517                 si_meminfo(&si);
1518                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1519                                adev->gmc.mc_vram_size),
1520                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1521         }
1522         else
1523                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1524         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1525         if (r) {
1526                 DRM_ERROR("Failed initializing GTT heap.\n");
1527                 return r;
1528         }
1529         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1530                  (unsigned)(gtt_size / (1024 * 1024)));
1531
1532         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1533         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1534         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1535         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1536         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1537         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1538         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1539         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1540         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1541         /* GDS Memory */
1542         if (adev->gds.mem.total_size) {
1543                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1544                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1545                 if (r) {
1546                         DRM_ERROR("Failed initializing GDS heap.\n");
1547                         return r;
1548                 }
1549         }
1550
1551         /* GWS */
1552         if (adev->gds.gws.total_size) {
1553                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1554                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1555                 if (r) {
1556                         DRM_ERROR("Failed initializing gws heap.\n");
1557                         return r;
1558                 }
1559         }
1560
1561         /* OA */
1562         if (adev->gds.oa.total_size) {
1563                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1564                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1565                 if (r) {
1566                         DRM_ERROR("Failed initializing oa heap.\n");
1567                         return r;
1568                 }
1569         }
1570
1571         r = amdgpu_ttm_debugfs_init(adev);
1572         if (r) {
1573                 DRM_ERROR("Failed to init debugfs\n");
1574                 return r;
1575         }
1576         return 0;
1577 }
1578
1579 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1580 {
1581         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1582 }
1583
1584 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1585 {
1586         if (!adev->mman.initialized)
1587                 return;
1588
1589         amdgpu_ttm_debugfs_fini(adev);
1590         amdgpu_ttm_fw_reserve_vram_fini(adev);
1591         if (adev->mman.aper_base_kaddr)
1592                 iounmap(adev->mman.aper_base_kaddr);
1593         adev->mman.aper_base_kaddr = NULL;
1594
1595         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1596         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1597         if (adev->gds.mem.total_size)
1598                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1599         if (adev->gds.gws.total_size)
1600                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1601         if (adev->gds.oa.total_size)
1602                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1603         ttm_bo_device_release(&adev->mman.bdev);
1604         amdgpu_ttm_global_fini(adev);
1605         adev->mman.initialized = false;
1606         DRM_INFO("amdgpu: ttm finalized\n");
1607 }
1608
1609 /**
1610  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1611  *
1612  * @adev: amdgpu_device pointer
1613  * @enable: true when we can use buffer functions.
1614  *
1615  * Enable/disable use of buffer functions during suspend/resume. This should
1616  * only be called at bootup or when userspace isn't running.
1617  */
1618 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1619 {
1620         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1621         uint64_t size;
1622
1623         if (!adev->mman.initialized || adev->in_gpu_reset)
1624                 return;
1625
1626         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1627         if (enable)
1628                 size = adev->gmc.real_vram_size;
1629         else
1630                 size = adev->gmc.visible_vram_size;
1631         man->size = size >> PAGE_SHIFT;
1632         adev->mman.buffer_funcs_enabled = enable;
1633 }
1634
1635 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1636 {
1637         struct drm_file *file_priv;
1638         struct amdgpu_device *adev;
1639
1640         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1641                 return -EINVAL;
1642
1643         file_priv = filp->private_data;
1644         adev = file_priv->minor->dev->dev_private;
1645         if (adev == NULL)
1646                 return -EINVAL;
1647
1648         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1649 }
1650
1651 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1652                              struct ttm_mem_reg *mem, unsigned num_pages,
1653                              uint64_t offset, unsigned window,
1654                              struct amdgpu_ring *ring,
1655                              uint64_t *addr)
1656 {
1657         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1658         struct amdgpu_device *adev = ring->adev;
1659         struct ttm_tt *ttm = bo->ttm;
1660         struct amdgpu_job *job;
1661         unsigned num_dw, num_bytes;
1662         dma_addr_t *dma_address;
1663         struct dma_fence *fence;
1664         uint64_t src_addr, dst_addr;
1665         uint64_t flags;
1666         int r;
1667
1668         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1669                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1670
1671         *addr = adev->gmc.gart_start;
1672         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1673                 AMDGPU_GPU_PAGE_SIZE;
1674
1675         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1676         while (num_dw & 0x7)
1677                 num_dw++;
1678
1679         num_bytes = num_pages * 8;
1680
1681         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1682         if (r)
1683                 return r;
1684
1685         src_addr = num_dw * 4;
1686         src_addr += job->ibs[0].gpu_addr;
1687
1688         dst_addr = adev->gart.table_addr;
1689         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1690         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1691                                 dst_addr, num_bytes);
1692
1693         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1694         WARN_ON(job->ibs[0].length_dw > num_dw);
1695
1696         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1697         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1698         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1699                             &job->ibs[0].ptr[num_dw]);
1700         if (r)
1701                 goto error_free;
1702
1703         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1704                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1705         if (r)
1706                 goto error_free;
1707
1708         dma_fence_put(fence);
1709
1710         return r;
1711
1712 error_free:
1713         amdgpu_job_free(job);
1714         return r;
1715 }
1716
1717 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1718                        uint64_t dst_offset, uint32_t byte_count,
1719                        struct reservation_object *resv,
1720                        struct dma_fence **fence, bool direct_submit,
1721                        bool vm_needs_flush)
1722 {
1723         struct amdgpu_device *adev = ring->adev;
1724         struct amdgpu_job *job;
1725
1726         uint32_t max_bytes;
1727         unsigned num_loops, num_dw;
1728         unsigned i;
1729         int r;
1730
1731         if (direct_submit && !ring->ready) {
1732                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1733                 return -EINVAL;
1734         }
1735
1736         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1737         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1738         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1739
1740         /* for IB padding */
1741         while (num_dw & 0x7)
1742                 num_dw++;
1743
1744         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1745         if (r)
1746                 return r;
1747
1748         job->vm_needs_flush = vm_needs_flush;
1749         if (resv) {
1750                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1751                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1752                                      false);
1753                 if (r) {
1754                         DRM_ERROR("sync failed (%d).\n", r);
1755                         goto error_free;
1756                 }
1757         }
1758
1759         for (i = 0; i < num_loops; i++) {
1760                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1761
1762                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1763                                         dst_offset, cur_size_in_bytes);
1764
1765                 src_offset += cur_size_in_bytes;
1766                 dst_offset += cur_size_in_bytes;
1767                 byte_count -= cur_size_in_bytes;
1768         }
1769
1770         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1771         WARN_ON(job->ibs[0].length_dw > num_dw);
1772         if (direct_submit) {
1773                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1774                                        NULL, fence);
1775                 job->fence = dma_fence_get(*fence);
1776                 if (r)
1777                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1778                 amdgpu_job_free(job);
1779         } else {
1780                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1781                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1782                 if (r)
1783                         goto error_free;
1784         }
1785
1786         return r;
1787
1788 error_free:
1789         amdgpu_job_free(job);
1790         return r;
1791 }
1792
1793 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1794                        uint32_t src_data,
1795                        struct reservation_object *resv,
1796                        struct dma_fence **fence)
1797 {
1798         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1799         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1800         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1801
1802         struct drm_mm_node *mm_node;
1803         unsigned long num_pages;
1804         unsigned int num_loops, num_dw;
1805
1806         struct amdgpu_job *job;
1807         int r;
1808
1809         if (!adev->mman.buffer_funcs_enabled) {
1810                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1811                 return -EINVAL;
1812         }
1813
1814         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1815                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1816                 if (r)
1817                         return r;
1818         }
1819
1820         num_pages = bo->tbo.num_pages;
1821         mm_node = bo->tbo.mem.mm_node;
1822         num_loops = 0;
1823         while (num_pages) {
1824                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1825
1826                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1827                 num_pages -= mm_node->size;
1828                 ++mm_node;
1829         }
1830         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1831
1832         /* for IB padding */
1833         num_dw += 64;
1834
1835         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1836         if (r)
1837                 return r;
1838
1839         if (resv) {
1840                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1841                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
1842                 if (r) {
1843                         DRM_ERROR("sync failed (%d).\n", r);
1844                         goto error_free;
1845                 }
1846         }
1847
1848         num_pages = bo->tbo.num_pages;
1849         mm_node = bo->tbo.mem.mm_node;
1850
1851         while (num_pages) {
1852                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1853                 uint64_t dst_addr;
1854
1855                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1856                 while (byte_count) {
1857                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1858
1859                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1860                                                 dst_addr, cur_size_in_bytes);
1861
1862                         dst_addr += cur_size_in_bytes;
1863                         byte_count -= cur_size_in_bytes;
1864                 }
1865
1866                 num_pages -= mm_node->size;
1867                 ++mm_node;
1868         }
1869
1870         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1871         WARN_ON(job->ibs[0].length_dw > num_dw);
1872         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1873                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1874         if (r)
1875                 goto error_free;
1876
1877         return 0;
1878
1879 error_free:
1880         amdgpu_job_free(job);
1881         return r;
1882 }
1883
1884 #if defined(CONFIG_DEBUG_FS)
1885
1886 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1887 {
1888         struct drm_info_node *node = (struct drm_info_node *)m->private;
1889         unsigned ttm_pl = *(int *)node->info_ent->data;
1890         struct drm_device *dev = node->minor->dev;
1891         struct amdgpu_device *adev = dev->dev_private;
1892         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
1893         struct drm_printer p = drm_seq_file_printer(m);
1894
1895         man->func->debug(man, &p);
1896         return 0;
1897 }
1898
1899 static int ttm_pl_vram = TTM_PL_VRAM;
1900 static int ttm_pl_tt = TTM_PL_TT;
1901
1902 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1903         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1904         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1905         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1906 #ifdef CONFIG_SWIOTLB
1907         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1908 #endif
1909 };
1910
1911 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1912                                     size_t size, loff_t *pos)
1913 {
1914         struct amdgpu_device *adev = file_inode(f)->i_private;
1915         ssize_t result = 0;
1916         int r;
1917
1918         if (size & 0x3 || *pos & 0x3)
1919                 return -EINVAL;
1920
1921         if (*pos >= adev->gmc.mc_vram_size)
1922                 return -ENXIO;
1923
1924         while (size) {
1925                 unsigned long flags;
1926                 uint32_t value;
1927
1928                 if (*pos >= adev->gmc.mc_vram_size)
1929                         return result;
1930
1931                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1932                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1933                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1934                 value = RREG32_NO_KIQ(mmMM_DATA);
1935                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1936
1937                 r = put_user(value, (uint32_t *)buf);
1938                 if (r)
1939                         return r;
1940
1941                 result += 4;
1942                 buf += 4;
1943                 *pos += 4;
1944                 size -= 4;
1945         }
1946
1947         return result;
1948 }
1949
1950 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
1951                                     size_t size, loff_t *pos)
1952 {
1953         struct amdgpu_device *adev = file_inode(f)->i_private;
1954         ssize_t result = 0;
1955         int r;
1956
1957         if (size & 0x3 || *pos & 0x3)
1958                 return -EINVAL;
1959
1960         if (*pos >= adev->gmc.mc_vram_size)
1961                 return -ENXIO;
1962
1963         while (size) {
1964                 unsigned long flags;
1965                 uint32_t value;
1966
1967                 if (*pos >= adev->gmc.mc_vram_size)
1968                         return result;
1969
1970                 r = get_user(value, (uint32_t *)buf);
1971                 if (r)
1972                         return r;
1973
1974                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1975                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1976                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1977                 WREG32_NO_KIQ(mmMM_DATA, value);
1978                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1979
1980                 result += 4;
1981                 buf += 4;
1982                 *pos += 4;
1983                 size -= 4;
1984         }
1985
1986         return result;
1987 }
1988
1989 static const struct file_operations amdgpu_ttm_vram_fops = {
1990         .owner = THIS_MODULE,
1991         .read = amdgpu_ttm_vram_read,
1992         .write = amdgpu_ttm_vram_write,
1993         .llseek = default_llseek,
1994 };
1995
1996 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1997
1998 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1999                                    size_t size, loff_t *pos)
2000 {
2001         struct amdgpu_device *adev = file_inode(f)->i_private;
2002         ssize_t result = 0;
2003         int r;
2004
2005         while (size) {
2006                 loff_t p = *pos / PAGE_SIZE;
2007                 unsigned off = *pos & ~PAGE_MASK;
2008                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2009                 struct page *page;
2010                 void *ptr;
2011
2012                 if (p >= adev->gart.num_cpu_pages)
2013                         return result;
2014
2015                 page = adev->gart.pages[p];
2016                 if (page) {
2017                         ptr = kmap(page);
2018                         ptr += off;
2019
2020                         r = copy_to_user(buf, ptr, cur_size);
2021                         kunmap(adev->gart.pages[p]);
2022                 } else
2023                         r = clear_user(buf, cur_size);
2024
2025                 if (r)
2026                         return -EFAULT;
2027
2028                 result += cur_size;
2029                 buf += cur_size;
2030                 *pos += cur_size;
2031                 size -= cur_size;
2032         }
2033
2034         return result;
2035 }
2036
2037 static const struct file_operations amdgpu_ttm_gtt_fops = {
2038         .owner = THIS_MODULE,
2039         .read = amdgpu_ttm_gtt_read,
2040         .llseek = default_llseek
2041 };
2042
2043 #endif
2044
2045 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2046                                  size_t size, loff_t *pos)
2047 {
2048         struct amdgpu_device *adev = file_inode(f)->i_private;
2049         struct iommu_domain *dom;
2050         ssize_t result = 0;
2051         int r;
2052
2053         dom = iommu_get_domain_for_dev(adev->dev);
2054
2055         while (size) {
2056                 phys_addr_t addr = *pos & PAGE_MASK;
2057                 loff_t off = *pos & ~PAGE_MASK;
2058                 size_t bytes = PAGE_SIZE - off;
2059                 unsigned long pfn;
2060                 struct page *p;
2061                 void *ptr;
2062
2063                 bytes = bytes < size ? bytes : size;
2064
2065                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2066
2067                 pfn = addr >> PAGE_SHIFT;
2068                 if (!pfn_valid(pfn))
2069                         return -EPERM;
2070
2071                 p = pfn_to_page(pfn);
2072                 if (p->mapping != adev->mman.bdev.dev_mapping)
2073                         return -EPERM;
2074
2075                 ptr = kmap(p);
2076                 r = copy_to_user(buf, ptr + off, bytes);
2077                 kunmap(p);
2078                 if (r)
2079                         return -EFAULT;
2080
2081                 size -= bytes;
2082                 *pos += bytes;
2083                 result += bytes;
2084         }
2085
2086         return result;
2087 }
2088
2089 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2090                                  size_t size, loff_t *pos)
2091 {
2092         struct amdgpu_device *adev = file_inode(f)->i_private;
2093         struct iommu_domain *dom;
2094         ssize_t result = 0;
2095         int r;
2096
2097         dom = iommu_get_domain_for_dev(adev->dev);
2098
2099         while (size) {
2100                 phys_addr_t addr = *pos & PAGE_MASK;
2101                 loff_t off = *pos & ~PAGE_MASK;
2102                 size_t bytes = PAGE_SIZE - off;
2103                 unsigned long pfn;
2104                 struct page *p;
2105                 void *ptr;
2106
2107                 bytes = bytes < size ? bytes : size;
2108
2109                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2110
2111                 pfn = addr >> PAGE_SHIFT;
2112                 if (!pfn_valid(pfn))
2113                         return -EPERM;
2114
2115                 p = pfn_to_page(pfn);
2116                 if (p->mapping != adev->mman.bdev.dev_mapping)
2117                         return -EPERM;
2118
2119                 ptr = kmap(p);
2120                 r = copy_from_user(ptr + off, buf, bytes);
2121                 kunmap(p);
2122                 if (r)
2123                         return -EFAULT;
2124
2125                 size -= bytes;
2126                 *pos += bytes;
2127                 result += bytes;
2128         }
2129
2130         return result;
2131 }
2132
2133 static const struct file_operations amdgpu_ttm_iomem_fops = {
2134         .owner = THIS_MODULE,
2135         .read = amdgpu_iomem_read,
2136         .write = amdgpu_iomem_write,
2137         .llseek = default_llseek
2138 };
2139
2140 static const struct {
2141         char *name;
2142         const struct file_operations *fops;
2143         int domain;
2144 } ttm_debugfs_entries[] = {
2145         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2146 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2147         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2148 #endif
2149         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2150 };
2151
2152 #endif
2153
2154 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2155 {
2156 #if defined(CONFIG_DEBUG_FS)
2157         unsigned count;
2158
2159         struct drm_minor *minor = adev->ddev->primary;
2160         struct dentry *ent, *root = minor->debugfs_root;
2161
2162         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2163                 ent = debugfs_create_file(
2164                                 ttm_debugfs_entries[count].name,
2165                                 S_IFREG | S_IRUGO, root,
2166                                 adev,
2167                                 ttm_debugfs_entries[count].fops);
2168                 if (IS_ERR(ent))
2169                         return PTR_ERR(ent);
2170                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2171                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2172                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2173                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2174                 adev->mman.debugfs_entries[count] = ent;
2175         }
2176
2177         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2178
2179 #ifdef CONFIG_SWIOTLB
2180         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2181                 --count;
2182 #endif
2183
2184         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2185 #else
2186         return 0;
2187 #endif
2188 }
2189
2190 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2191 {
2192 #if defined(CONFIG_DEBUG_FS)
2193         unsigned i;
2194
2195         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2196                 debugfs_remove(adev->mman.debugfs_entries[i]);
2197 #endif
2198 }