2 * Copyright 2021 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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24 #include "amdgpu_reset.h"
25 #include "aldebaran.h"
26 #include "sienna_cichlid.h"
27 #include "smu_v13_0_10.h"
29 int amdgpu_reset_init(struct amdgpu_device *adev)
33 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
34 case IP_VERSION(13, 0, 2):
35 case IP_VERSION(13, 0, 6):
36 case IP_VERSION(13, 0, 14):
37 ret = aldebaran_reset_init(adev);
39 case IP_VERSION(11, 0, 7):
40 ret = sienna_cichlid_reset_init(adev);
42 case IP_VERSION(13, 0, 10):
43 ret = smu_v13_0_10_reset_init(adev);
52 int amdgpu_reset_fini(struct amdgpu_device *adev)
56 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
57 case IP_VERSION(13, 0, 2):
58 case IP_VERSION(13, 0, 6):
59 case IP_VERSION(13, 0, 14):
60 ret = aldebaran_reset_fini(adev);
62 case IP_VERSION(11, 0, 7):
63 ret = sienna_cichlid_reset_fini(adev);
65 case IP_VERSION(13, 0, 10):
66 ret = smu_v13_0_10_reset_fini(adev);
75 int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
76 struct amdgpu_reset_context *reset_context)
78 struct amdgpu_reset_handler *reset_handler = NULL;
80 if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
81 reset_handler = adev->reset_cntl->get_reset_handler(
82 adev->reset_cntl, reset_context);
86 return reset_handler->prepare_hwcontext(adev->reset_cntl,
90 int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
91 struct amdgpu_reset_context *reset_context)
94 struct amdgpu_reset_handler *reset_handler = NULL;
97 reset_handler = adev->reset_cntl->get_reset_handler(
98 adev->reset_cntl, reset_context);
102 ret = reset_handler->perform_reset(adev->reset_cntl, reset_context);
106 return reset_handler->restore_hwcontext(adev->reset_cntl,
111 void amdgpu_reset_destroy_reset_domain(struct kref *ref)
113 struct amdgpu_reset_domain *reset_domain = container_of(ref,
114 struct amdgpu_reset_domain,
116 if (reset_domain->wq)
117 destroy_workqueue(reset_domain->wq);
119 kvfree(reset_domain);
122 struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
125 struct amdgpu_reset_domain *reset_domain;
127 reset_domain = kvzalloc(sizeof(struct amdgpu_reset_domain), GFP_KERNEL);
129 DRM_ERROR("Failed to allocate amdgpu_reset_domain!");
133 reset_domain->type = type;
134 kref_init(&reset_domain->refcount);
136 reset_domain->wq = create_singlethread_workqueue(wq_name);
137 if (!reset_domain->wq) {
138 DRM_ERROR("Failed to allocate wq for amdgpu_reset_domain!");
139 amdgpu_reset_put_reset_domain(reset_domain);
144 atomic_set(&reset_domain->in_gpu_reset, 0);
145 atomic_set(&reset_domain->reset_res, 0);
146 init_rwsem(&reset_domain->sem);
151 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain)
153 atomic_set(&reset_domain->in_gpu_reset, 1);
154 down_write(&reset_domain->sem);
158 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain)
160 atomic_set(&reset_domain->in_gpu_reset, 0);
161 up_write(&reset_domain->sem);
164 void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf,
170 switch (rst_ctxt->src) {
171 case AMDGPU_RESET_SRC_JOB:
173 snprintf(buf, len, "job hang on ring:%s",
174 rst_ctxt->job->base.sched->name);
176 strscpy(buf, "job hang", len);
179 case AMDGPU_RESET_SRC_RAS:
180 strscpy(buf, "RAS error", len);
182 case AMDGPU_RESET_SRC_MES:
183 strscpy(buf, "MES hang", len);
185 case AMDGPU_RESET_SRC_HWS:
186 strscpy(buf, "HWS hang", len);
188 case AMDGPU_RESET_SRC_USER:
189 strscpy(buf, "user trigger", len);
192 strscpy(buf, "unknown", len);