drivers/gpu/drm/i2c/tda998x_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <[email protected]>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/component.h>
  19 #include <linux/gpio/consumer.h>
  20 #include <linux/hdmi.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_data/tda9950.h>
  23 #include <linux/irq.h>
  24 #include <sound/asoundef.h>
  25 #include <sound/hdmi-codec.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_of.h>
  32 #include <drm/i2c/tda998x.h>
  33
  34 #include <media/cec-notifier.h>
  35
  36 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  37
  38 struct tda998x_audio_port {
  39         u8 format;              /* AFMT_xxx */
  40         u8 config;              /* AP value */
  41 };
  42
  43 struct tda998x_priv {
  44         struct i2c_client *cec;
  45         struct i2c_client *hdmi;
  46         struct mutex mutex;
  47         u16 rev;
  48         u8 cec_addr;
  49         u8 current_page;
  50         bool is_on;
  51         bool supports_infoframes;
  52         bool sink_has_audio;
  53         u8 vip_cntrl_0;
  54         u8 vip_cntrl_1;
  55         u8 vip_cntrl_2;
  56         unsigned long tmds_clock;
  57         struct tda998x_audio_params audio_params;
  58
  59         struct platform_device *audio_pdev;
  60         struct mutex audio_mutex;
  61
  62         struct mutex edid_mutex;
  63         wait_queue_head_t wq_edid;
  64         volatile int wq_edid_wait;
  65
  66         struct work_struct detect_work;
  67         struct timer_list edid_delay_timer;
  68         wait_queue_head_t edid_delay_waitq;
  69         bool edid_delay_active;
  70
  71         struct drm_encoder encoder;
  72         struct drm_connector connector;
  73
  74         struct tda998x_audio_port audio_port[2];
  75         struct tda9950_glue cec_glue;
  76         struct gpio_desc *calib;
  77         struct cec_notifier *cec_notify;
  78 };
  79
  80 #define conn_to_tda998x_priv(x) \
  81         container_of(x, struct tda998x_priv, connector)
  82
  83 #define enc_to_tda998x_priv(x) \
  84         container_of(x, struct tda998x_priv, encoder)
  85
  86 /* The TDA9988 series of devices use a paged register scheme.. to simplify
  87  * things we encode the page # in upper bits of the register #.  To read/
  88  * write a given register, we need to make sure CURPAGE register is set
  89  * appropriately.  Which implies reads/writes are not atomic.  Fun!
  90  */
  91
  92 #define REG(page, addr) (((page) << 8) | (addr))
  93 #define REG2ADDR(reg)   ((reg) & 0xff)
  94 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
  95
  96 #define REG_CURPAGE               0xff                /* write */
  97
  98
  99 /* Page 00h: General Control */
 100 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
 101 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
 102 # define MAIN_CNTRL0_SR           (1 << 0)
 103 # define MAIN_CNTRL0_DECS         (1 << 1)
 104 # define MAIN_CNTRL0_DEHS         (1 << 2)
 105 # define MAIN_CNTRL0_CECS         (1 << 3)
 106 # define MAIN_CNTRL0_CEHS         (1 << 4)
 107 # define MAIN_CNTRL0_SCALER       (1 << 7)
 108 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
 109 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
 110 # define SOFTRESET_AUDIO          (1 << 0)
 111 # define SOFTRESET_I2C_MASTER     (1 << 1)
 112 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
 113 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
 114 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
 115 # define I2C_MASTER_DIS_MM        (1 << 0)
 116 # define I2C_MASTER_DIS_FILT      (1 << 1)
 117 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
 118 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
 119 # define FEAT_POWERDOWN_PREFILT   BIT(0)
 120 # define FEAT_POWERDOWN_CSC       BIT(1)
 121 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
 122 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
 123 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
 124 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
 125 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
 126 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
 127 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
 128 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
 129 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
 130 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 131 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 132 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
 133 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 134 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 135 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 136 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 137 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 138 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 139 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 140 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 141 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 142 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 143 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 144 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 145 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 146 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 147 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 148 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 149 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 150 # define VIP_CNTRL_3_EMB          (1 << 3)
 151 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 152 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 153 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 154 # define VIP_CNTRL_3_EDGE         (1 << 7)
 155 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 156 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 157 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 158 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 159 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 160 # define VIP_CNTRL_4_TST_656      (1 << 6)
 161 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 162 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 163 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 164 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 165 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 166 # define MUX_AP_SELECT_I2S        0x64
 167 # define MUX_AP_SELECT_SPDIF      0x40
 168 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 169 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 170 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 171 # define MAT_CONTRL_MAT_BP        (1 << 2)
 172 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 173 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 174 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 175 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 176 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 177 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 178 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 179 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 180 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 181 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 182 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 183 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 184 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 185 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 186 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 187 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 188 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 189 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 190 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 191 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 192 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 193 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 194 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 195 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 196 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 197 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 198 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 199 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 200 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 201 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 202 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 203 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 204 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 205 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 206 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 207 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 208 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 209 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 210 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 211 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 212 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 213 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 214 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 215 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 216 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 217 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 218 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 219 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 220 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 221 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 222 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 223 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 224 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 225 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 226 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 227 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 228 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 229 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 230 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 231 # define HVF_CNTRL_0_SM           (1 << 7)
 232 # define HVF_CNTRL_0_RWB          (1 << 6)
 233 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 234 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 235 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 236 # define HVF_CNTRL_1_FOR          (1 << 0)
 237 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 238 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 239 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 240 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 241 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 242 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 243 # define I2S_FORMAT(x)            (((x) & 3) << 0)
 244 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 245 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 246 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 247 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 248 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 249 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 250
 251 /* Page 02h: PLL settings */
 252 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 253 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 254 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 255 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 256 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 257 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 258 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 259 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 260 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 261 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 262 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 263 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 264 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 265 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 266 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 267 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 268 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 269 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 270 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 271 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 272 # define AUDIO_DIV_SERCLK_1       0
 273 # define AUDIO_DIV_SERCLK_2       1
 274 # define AUDIO_DIV_SERCLK_4       2
 275 # define AUDIO_DIV_SERCLK_8       3
 276 # define AUDIO_DIV_SERCLK_16      4
 277 # define AUDIO_DIV_SERCLK_32      5
 278 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 279 # define SEL_CLK_SEL_CLK1         (1 << 0)
 280 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 281 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 282 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 283
 284
 285 /* Page 09h: EDID Control */
 286 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 287 /* next 127 successive registers are the EDID block */
 288 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 289 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 290 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 291 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 292 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 293
 294
 295 /* Page 10h: information frames and packets */
 296 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 297 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 298 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 299 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 300 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 301
 302
 303 /* Page 11h: audio settings and content info packets */
 304 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 305 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 306 # define AIP_CNTRL_0_SWAP         (1 << 1)
 307 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 308 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 309 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 310 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 311 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 312 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 313 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 314 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 315 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 316 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 317 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 318 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 319 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 320 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 321 # define CTS_N_K(x)               (((x) & 7) << 0)
 322 # define CTS_N_M(x)               (((x) & 3) << 4)
 323 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 324 # define ENC_CNTRL_RST_ENC        (1 << 0)
 325 # define ENC_CNTRL_RST_SEL        (1 << 1)
 326 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 327 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 328 # define DIP_FLAGS_ACR            (1 << 0)
 329 # define DIP_FLAGS_GC             (1 << 1)
 330 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 331 # define DIP_IF_FLAGS_IF1         (1 << 1)
 332 # define DIP_IF_FLAGS_IF2         (1 << 2)
 333 # define DIP_IF_FLAGS_IF3         (1 << 3)
 334 # define DIP_IF_FLAGS_IF4         (1 << 4)
 335 # define DIP_IF_FLAGS_IF5         (1 << 5)
 336 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 337
 338
 339 /* Page 12h: HDCP and OTP */
 340 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 341 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 342 # define TX4_PD_RAM               (1 << 1)
 343 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 344 # define TX33_HDMI                (1 << 1)
 345
 346
 347 /* Page 13h: Gamut related metadata packets */
 348
 349
 350
 351 /* CEC registers: (not paged)
 352  */
 353 #define REG_CEC_INTSTATUS         0xee                /* read */
 354 # define CEC_INTSTATUS_CEC        (1 << 0)
 355 # define CEC_INTSTATUS_HDMI       (1 << 1)
 356 #define REG_CEC_CAL_XOSC_CTRL1    0xf2
 357 # define CEC_CAL_XOSC_CTRL1_ENA_CAL     BIT(0)
 358 #define REG_CEC_DES_FREQ2         0xf5
 359 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
 360 #define REG_CEC_CLK               0xf6
 361 # define CEC_CLK_FRO              0x11
 362 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 363 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 364 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 365 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 366 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 367 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 368 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 369 # define CEC_RXSHPDINT_RXSENS     BIT(0)
 370 # define CEC_RXSHPDINT_HPD        BIT(1)
 371 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 372 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 373 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 374
 375 #define REG_CEC_ENAMODS           0xff                /* read/write */
 376 # define CEC_ENAMODS_EN_CEC_CLK   (1 << 7)
 377 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 378 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 379 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 380 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 381 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 382
 383
 384 /* Device versions: */
 385 #define TDA9989N2                 0x0101
 386 #define TDA19989                  0x0201
 387 #define TDA19989N2                0x0202
 388 #define TDA19988                  0x0301
 389
 390 static void
 391 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 392 {
 393         u8 buf[] = {addr, val};
 394         struct i2c_msg msg = {
 395                 .addr = priv->cec_addr,
 396                 .len = 2,
 397                 .buf = buf,
 398         };
 399         int ret;
 400
 401         ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
 402         if (ret < 0)
 403                 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
 404                         ret, addr);
 405 }
 406
 407 static u8
 408 cec_read(struct tda998x_priv *priv, u8 addr)
 409 {
 410         u8 val;
 411         struct i2c_msg msg[2] = {
 412                 {
 413                         .addr = priv->cec_addr,
 414                         .len = 1,
 415                         .buf = &addr,
 416                 }, {
 417                         .addr = priv->cec_addr,
 418                         .flags = I2C_M_RD,
 419                         .len = 1,
 420                         .buf = &val,
 421                 },
 422         };
 423         int ret;
 424
 425         ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
 426         if (ret < 0) {
 427                 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
 428                         ret, addr);
 429                 val = 0;
 430         }
 431
 432         return val;
 433 }
 434
 435 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
 436 {
 437         int val = cec_read(priv, REG_CEC_ENAMODS);
 438
 439         if (val < 0)
 440                 return;
 441
 442         if (enable)
 443                 val |= mods;
 444         else
 445                 val &= ~mods;
 446
 447         cec_write(priv, REG_CEC_ENAMODS, val);
 448 }
 449
 450 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
 451 {
 452         if (enable) {
 453                 u8 val;
 454
 455                 cec_write(priv, 0xf3, 0xc0);
 456                 cec_write(priv, 0xf4, 0xd4);
 457
 458                 /* Enable automatic calibration mode */
 459                 val = cec_read(priv, REG_CEC_DES_FREQ2);
 460                 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
 461                 cec_write(priv, REG_CEC_DES_FREQ2, val);
 462
 463                 /* Enable free running oscillator */
 464                 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
 465                 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
 466
 467                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
 468                           CEC_CAL_XOSC_CTRL1_ENA_CAL);
 469         } else {
 470                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
 471         }
 472 }
 473
 474 /*
 475  * Calibration for the internal oscillator: we need to set calibration mode,
 476  * and then pulse the IRQ line low for a 10ms ± 1% period.
 477  */
 478 static void tda998x_cec_calibration(struct tda998x_priv *priv)
 479 {
 480         struct gpio_desc *calib = priv->calib;
 481
 482         mutex_lock(&priv->edid_mutex);
 483         if (priv->hdmi->irq > 0)
 484                 disable_irq(priv->hdmi->irq);
 485         gpiod_direction_output(calib, 1);
 486         tda998x_cec_set_calibration(priv, true);
 487
 488         local_irq_disable();
 489         gpiod_set_value(calib, 0);
 490         mdelay(10);
 491         gpiod_set_value(calib, 1);
 492         local_irq_enable();
 493
 494         tda998x_cec_set_calibration(priv, false);
 495         gpiod_direction_input(calib);
 496         if (priv->hdmi->irq > 0)
 497                 enable_irq(priv->hdmi->irq);
 498         mutex_unlock(&priv->edid_mutex);
 499 }
 500
 501 static int tda998x_cec_hook_init(void *data)
 502 {
 503         struct tda998x_priv *priv = data;
 504         struct gpio_desc *calib;
 505
 506         calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
 507         if (IS_ERR(calib)) {
 508                 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
 509                          PTR_ERR(calib));
 510                 return PTR_ERR(calib);
 511         }
 512
 513         priv->calib = calib;
 514
 515         return 0;
 516 }
 517
 518 static void tda998x_cec_hook_exit(void *data)
 519 {
 520         struct tda998x_priv *priv = data;
 521
 522         gpiod_put(priv->calib);
 523         priv->calib = NULL;
 524 }
 525
 526 static int tda998x_cec_hook_open(void *data)
 527 {
 528         struct tda998x_priv *priv = data;
 529
 530         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
 531         tda998x_cec_calibration(priv);
 532
 533         return 0;
 534 }
 535
 536 static void tda998x_cec_hook_release(void *data)
 537 {
 538         struct tda998x_priv *priv = data;
 539
 540         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
 541 }
 542
 543 static int
 544 set_page(struct tda998x_priv *priv, u16 reg)
 545 {
 546         if (REG2PAGE(reg) != priv->current_page) {
 547                 struct i2c_client *client = priv->hdmi;
 548                 u8 buf[] = {
 549                                 REG_CURPAGE, REG2PAGE(reg)
 550                 };
 551                 int ret = i2c_master_send(client, buf, sizeof(buf));
 552                 if (ret < 0) {
 553                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 554                                         reg, ret);
 555                         return ret;
 556                 }
 557
 558                 priv->current_page = REG2PAGE(reg);
 559         }
 560         return 0;
 561 }
 562
 563 static int
 564 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 565 {
 566         struct i2c_client *client = priv->hdmi;
 567         u8 addr = REG2ADDR(reg);
 568         int ret;
 569
 570         mutex_lock(&priv->mutex);
 571         ret = set_page(priv, reg);
 572         if (ret < 0)
 573                 goto out;
 574
 575         ret = i2c_master_send(client, &addr, sizeof(addr));
 576         if (ret < 0)
 577                 goto fail;
 578
 579         ret = i2c_master_recv(client, buf, cnt);
 580         if (ret < 0)
 581                 goto fail;
 582
 583         goto out;
 584
 585 fail:
 586         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 587 out:
 588         mutex_unlock(&priv->mutex);
 589         return ret;
 590 }
 591
 592 #define MAX_WRITE_RANGE_BUF 32
 593
 594 static void
 595 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 596 {
 597         struct i2c_client *client = priv->hdmi;
 598         /* This is the maximum size of the buffer passed in */
 599         u8 buf[MAX_WRITE_RANGE_BUF + 1];
 600         int ret;
 601
 602         if (cnt > MAX_WRITE_RANGE_BUF) {
 603                 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
 604                                 MAX_WRITE_RANGE_BUF);
 605                 return;
 606         }
 607
 608         buf[0] = REG2ADDR(reg);
 609         memcpy(&buf[1], p, cnt);
 610
 611         mutex_lock(&priv->mutex);
 612         ret = set_page(priv, reg);
 613         if (ret < 0)
 614                 goto out;
 615
 616         ret = i2c_master_send(client, buf, cnt + 1);
 617         if (ret < 0)
 618                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 619 out:
 620         mutex_unlock(&priv->mutex);
 621 }
 622
 623 static int
 624 reg_read(struct tda998x_priv *priv, u16 reg)
 625 {
 626         u8 val = 0;
 627         int ret;
 628
 629         ret = reg_read_range(priv, reg, &val, sizeof(val));
 630         if (ret < 0)
 631                 return ret;
 632         return val;
 633 }
 634
 635 static void
 636 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 637 {
 638         struct i2c_client *client = priv->hdmi;
 639         u8 buf[] = {REG2ADDR(reg), val};
 640         int ret;
 641
 642         mutex_lock(&priv->mutex);
 643         ret = set_page(priv, reg);
 644         if (ret < 0)
 645                 goto out;
 646
 647         ret = i2c_master_send(client, buf, sizeof(buf));
 648         if (ret < 0)
 649                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 650 out:
 651         mutex_unlock(&priv->mutex);
 652 }
 653
 654 static void
 655 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 656 {
 657         struct i2c_client *client = priv->hdmi;
 658         u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 659         int ret;
 660
 661         mutex_lock(&priv->mutex);
 662         ret = set_page(priv, reg);
 663         if (ret < 0)
 664                 goto out;
 665
 666         ret = i2c_master_send(client, buf, sizeof(buf));
 667         if (ret < 0)
 668                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 669 out:
 670         mutex_unlock(&priv->mutex);
 671 }
 672
 673 static void
 674 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 675 {
 676         int old_val;
 677
 678         old_val = reg_read(priv, reg);
 679         if (old_val >= 0)
 680                 reg_write(priv, reg, old_val | val);
 681 }
 682
 683 static void
 684 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 685 {
 686         int old_val;
 687
 688         old_val = reg_read(priv, reg);
 689         if (old_val >= 0)
 690                 reg_write(priv, reg, old_val & ~val);
 691 }
 692
 693 static void
 694 tda998x_reset(struct tda998x_priv *priv)
 695 {
 696         /* reset audio and i2c master: */
 697         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 698         msleep(50);
 699         reg_write(priv, REG_SOFTRESET, 0);
 700         msleep(50);
 701
 702         /* reset transmitter: */
 703         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 704         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 705
 706         /* PLL registers common configuration */
 707         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 708         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 709         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 710         reg_write(priv, REG_SERIALIZER,   0x00);
 711         reg_write(priv, REG_BUFFER_OUT,   0x00);
 712         reg_write(priv, REG_PLL_SCG1,     0x00);
 713         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 714         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 715         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 716         reg_write(priv, REG_PLL_SCGN2,    0x00);
 717         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 718         reg_write(priv, REG_PLL_SCGR2,    0x00);
 719         reg_write(priv, REG_PLL_SCG2,     0x10);
 720
 721         /* Write the default value MUX register */
 722         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 723 }
 724
 725 /*
 726  * The TDA998x has a problem when trying to read the EDID close to a
 727  * HPD assertion: it needs a delay of 100ms to avoid timing out while
 728  * trying to read EDID data.
 729  *
 730  * However, tda998x_connector_get_modes() may be called at any moment
 731  * after tda998x_connector_detect() indicates that we are connected, so
 732  * we need to delay probing modes in tda998x_connector_get_modes() after
 733  * we have seen a HPD inactive->active transition.  This code implements
 734  * that delay.
 735  */
 736 static void tda998x_edid_delay_done(struct timer_list *t)
 737 {
 738         struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
 739
 740         priv->edid_delay_active = false;
 741         wake_up(&priv->edid_delay_waitq);
 742         schedule_work(&priv->detect_work);
 743 }
 744
 745 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 746 {
 747         priv->edid_delay_active = true;
 748         mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 749 }
 750
 751 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 752 {
 753         return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 754 }
 755
 756 /*
 757  * We need to run the KMS hotplug event helper outside of our threaded
 758  * interrupt routine as this can call back into our get_modes method,
 759  * which will want to make use of interrupts.
 760  */
 761 static void tda998x_detect_work(struct work_struct *work)
 762 {
 763         struct tda998x_priv *priv =
 764                 container_of(work, struct tda998x_priv, detect_work);
 765         struct drm_device *dev = priv->encoder.dev;
 766
 767         if (dev)
 768                 drm_kms_helper_hotplug_event(dev);
 769 }
 770
 771 /*
 772  * only 2 interrupts may occur: screen plug/unplug and EDID read
 773  */
 774 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 775 {
 776         struct tda998x_priv *priv = data;
 777         u8 sta, cec, lvl, flag0, flag1, flag2;
 778         bool handled = false;
 779
 780         sta = cec_read(priv, REG_CEC_INTSTATUS);
 781         if (sta & CEC_INTSTATUS_HDMI) {
 782                 cec = cec_read(priv, REG_CEC_RXSHPDINT);
 783                 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 784                 flag0 = reg_read(priv, REG_INT_FLAGS_0);
 785                 flag1 = reg_read(priv, REG_INT_FLAGS_1);
 786                 flag2 = reg_read(priv, REG_INT_FLAGS_2);
 787                 DRM_DEBUG_DRIVER(
 788                         "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 789                         sta, cec, lvl, flag0, flag1, flag2);
 790
 791                 if (cec & CEC_RXSHPDINT_HPD) {
 792                         if (lvl & CEC_RXSHPDLEV_HPD) {
 793                                 tda998x_edid_delay_start(priv);
 794                         } else {
 795                                 schedule_work(&priv->detect_work);
 796                                 cec_notifier_set_phys_addr(priv->cec_notify,
 797                                                    CEC_PHYS_ADDR_INVALID);
 798                         }
 799
 800                         handled = true;
 801                 }
 802
 803                 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 804                         priv->wq_edid_wait = 0;
 805                         wake_up(&priv->wq_edid);
 806                         handled = true;
 807                 }
 808         }
 809
 810         return IRQ_RETVAL(handled);
 811 }
 812
 813 static void
 814 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 815                  union hdmi_infoframe *frame)
 816 {
 817         u8 buf[MAX_WRITE_RANGE_BUF];
 818         ssize_t len;
 819
 820         len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
 821         if (len < 0) {
 822                 dev_err(&priv->hdmi->dev,
 823                         "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
 824                         frame->any.type, len);
 825                 return;
 826         }
 827
 828         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 829         reg_write_range(priv, addr, buf, len);
 830         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 831 }
 832
 833 static int tda998x_write_aif(struct tda998x_priv *priv,
 834                              struct hdmi_audio_infoframe *cea)
 835 {
 836         union hdmi_infoframe frame;
 837
 838         frame.audio = *cea;
 839
 840         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
 841
 842         return 0;
 843 }
 844
 845 static void
 846 tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
 847 {
 848         union hdmi_infoframe frame;
 849
 850         drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
 851         frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 852
 853         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
 854 }
 855
 856 /* Audio support */
 857
 858 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 859 {
 860         if (on) {
 861                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 862                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 863                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 864         } else {
 865                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 866         }
 867 }
 868
 869 static int
 870 tda998x_configure_audio(struct tda998x_priv *priv,
 871                         struct tda998x_audio_params *params)
 872 {
 873         u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
 874         u32 n;
 875
 876         /* Enable audio ports */
 877         reg_write(priv, REG_ENA_AP, params->config);
 878
 879         /* Set audio input source */
 880         switch (params->format) {
 881         case AFMT_SPDIF:
 882                 reg_write(priv, REG_ENA_ACLK, 0);
 883                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
 884                 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
 885                 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
 886                 cts_n = CTS_N_M(3) | CTS_N_K(3);
 887                 break;
 888
 889         case AFMT_I2S:
 890                 reg_write(priv, REG_ENA_ACLK, 1);
 891                 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
 892                 clksel_aip = AIP_CLKSEL_AIP_I2S;
 893                 clksel_fs = AIP_CLKSEL_FS_ACLK;
 894                 switch (params->sample_width) {
 895                 case 16:
 896                         cts_n = CTS_N_M(3) | CTS_N_K(1);
 897                         break;
 898                 case 18:
 899                 case 20:
 900                 case 24:
 901                         cts_n = CTS_N_M(3) | CTS_N_K(2);
 902                         break;
 903                 default:
 904                 case 32:
 905                         cts_n = CTS_N_M(3) | CTS_N_K(3);
 906                         break;
 907                 }
 908                 break;
 909
 910         default:
 911                 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n");
 912                 return -EINVAL;
 913         }
 914
 915         reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
 916         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
 917                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
 918         reg_write(priv, REG_CTS_N, cts_n);
 919
 920         /*
 921          * Audio input somehow depends on HDMI line rate which is
 922          * related to pixclk. Testing showed that modes with pixclk
 923          * >100MHz need a larger divider while <40MHz need the default.
 924          * There is no detailed info in the datasheet, so we just
 925          * assume 100MHz requires larger divider.
 926          */
 927         adiv = AUDIO_DIV_SERCLK_8;
 928         if (priv->tmds_clock > 100000)
 929                 adiv++;                 /* AUDIO_DIV_SERCLK_16 */
 930
 931         /* S/PDIF asks for a larger divider */
 932         if (params->format == AFMT_SPDIF)
 933                 adiv++;                 /* AUDIO_DIV_SERCLK_16 or _32 */
 934
 935         reg_write(priv, REG_AUDIO_DIV, adiv);
 936
 937         /*
 938          * This is the approximate value of N, which happens to be
 939          * the recommended values for non-coherent clocks.
 940          */
 941         n = 128 * params->sample_rate / 1000;
 942
 943         /* Write the CTS and N values */
 944         buf[0] = 0x44;
 945         buf[1] = 0x42;
 946         buf[2] = 0x01;
 947         buf[3] = n;
 948         buf[4] = n >> 8;
 949         buf[5] = n >> 16;
 950         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
 951
 952         /* Set CTS clock reference */
 953         reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
 954
 955         /* Reset CTS generator */
 956         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 957         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
 958
 959         /* Write the channel status
 960          * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
 961          * there is a separate register for each I2S wire.
 962          */
 963         buf[0] = params->status[0];
 964         buf[1] = params->status[1];
 965         buf[2] = params->status[3];
 966         buf[3] = params->status[4];
 967         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
 968
 969         tda998x_audio_mute(priv, true);
 970         msleep(20);
 971         tda998x_audio_mute(priv, false);
 972
 973         return tda998x_write_aif(priv, &params->cea);
 974 }
 975
 976 static int tda998x_audio_hw_params(struct device *dev, void *data,
 977                                    struct hdmi_codec_daifmt *daifmt,
 978                                    struct hdmi_codec_params *params)
 979 {
 980         struct tda998x_priv *priv = dev_get_drvdata(dev);
 981         int i, ret;
 982         struct tda998x_audio_params audio = {
 983                 .sample_width = params->sample_width,
 984                 .sample_rate = params->sample_rate,
 985                 .cea = params->cea,
 986         };
 987
 988         memcpy(audio.status, params->iec.status,
 989                min(sizeof(audio.status), sizeof(params->iec.status)));
 990
 991         switch (daifmt->fmt) {
 992         case HDMI_I2S:
 993                 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
 994                     daifmt->bit_clk_master || daifmt->frame_clk_master) {
 995                         dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
 996                                 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
 997                                 daifmt->bit_clk_master,
 998                                 daifmt->frame_clk_master);
 999                         return -EINVAL;
1000                 }
1001                 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
1002                         if (priv->audio_port[i].format == AFMT_I2S)
1003                                 audio.config = priv->audio_port[i].config;
1004                 audio.format = AFMT_I2S;
1005                 break;
1006         case HDMI_SPDIF:
1007                 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
1008                         if (priv->audio_port[i].format == AFMT_SPDIF)
1009                                 audio.config = priv->audio_port[i].config;
1010                 audio.format = AFMT_SPDIF;
1011                 break;
1012         default:
1013                 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1014                 return -EINVAL;
1015         }
1016
1017         if (audio.config == 0) {
1018                 dev_err(dev, "%s: No audio configuration found\n", __func__);
1019                 return -EINVAL;
1020         }
1021
1022         mutex_lock(&priv->audio_mutex);
1023         if (priv->supports_infoframes && priv->sink_has_audio)
1024                 ret = tda998x_configure_audio(priv, &audio);
1025         else
1026                 ret = 0;
1027
1028         if (ret == 0)
1029                 priv->audio_params = audio;
1030         mutex_unlock(&priv->audio_mutex);
1031
1032         return ret;
1033 }
1034
1035 static void tda998x_audio_shutdown(struct device *dev, void *data)
1036 {
1037         struct tda998x_priv *priv = dev_get_drvdata(dev);
1038
1039         mutex_lock(&priv->audio_mutex);
1040
1041         reg_write(priv, REG_ENA_AP, 0);
1042
1043         priv->audio_params.format = AFMT_UNUSED;
1044
1045         mutex_unlock(&priv->audio_mutex);
1046 }
1047
1048 int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
1049 {
1050         struct tda998x_priv *priv = dev_get_drvdata(dev);
1051
1052         mutex_lock(&priv->audio_mutex);
1053
1054         tda998x_audio_mute(priv, enable);
1055
1056         mutex_unlock(&priv->audio_mutex);
1057         return 0;
1058 }
1059
1060 static int tda998x_audio_get_eld(struct device *dev, void *data,
1061                                  uint8_t *buf, size_t len)
1062 {
1063         struct tda998x_priv *priv = dev_get_drvdata(dev);
1064
1065         mutex_lock(&priv->audio_mutex);
1066         memcpy(buf, priv->connector.eld,
1067                min(sizeof(priv->connector.eld), len));
1068         mutex_unlock(&priv->audio_mutex);
1069
1070         return 0;
1071 }
1072
1073 static const struct hdmi_codec_ops audio_codec_ops = {
1074         .hw_params = tda998x_audio_hw_params,
1075         .audio_shutdown = tda998x_audio_shutdown,
1076         .digital_mute = tda998x_audio_digital_mute,
1077         .get_eld = tda998x_audio_get_eld,
1078 };
1079
1080 static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1081                                     struct device *dev)
1082 {
1083         struct hdmi_codec_pdata codec_data = {
1084                 .ops = &audio_codec_ops,
1085                 .max_i2s_channels = 2,
1086         };
1087         int i;
1088
1089         for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) {
1090                 if (priv->audio_port[i].format == AFMT_I2S &&
1091                     priv->audio_port[i].config != 0)
1092                         codec_data.i2s = 1;
1093                 if (priv->audio_port[i].format == AFMT_SPDIF &&
1094                     priv->audio_port[i].config != 0)
1095                         codec_data.spdif = 1;
1096         }
1097
1098         priv->audio_pdev = platform_device_register_data(
1099                 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1100                 &codec_data, sizeof(codec_data));
1101
1102         return PTR_ERR_OR_ZERO(priv->audio_pdev);
1103 }
1104
1105 /* DRM connector functions */
1106
1107 static int tda998x_connector_fill_modes(struct drm_connector *connector,
1108                                         uint32_t maxX, uint32_t maxY)
1109 {
1110         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1111         int ret;
1112
1113         mutex_lock(&priv->audio_mutex);
1114         ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
1115
1116         if (connector->edid_blob_ptr) {
1117                 struct edid *edid = (void *)connector->edid_blob_ptr->data;
1118
1119                 cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1120
1121                 priv->sink_has_audio = drm_detect_monitor_audio(edid);
1122         } else {
1123                 priv->sink_has_audio = false;
1124         }
1125         mutex_unlock(&priv->audio_mutex);
1126
1127         return ret;
1128 }
1129
1130 static enum drm_connector_status
1131 tda998x_connector_detect(struct drm_connector *connector, bool force)
1132 {
1133         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1134         u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1135
1136         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1137                         connector_status_disconnected;
1138 }
1139
1140 static void tda998x_connector_destroy(struct drm_connector *connector)
1141 {
1142         drm_connector_cleanup(connector);
1143 }
1144
1145 static const struct drm_connector_funcs tda998x_connector_funcs = {
1146         .dpms = drm_helper_connector_dpms,
1147         .reset = drm_atomic_helper_connector_reset,
1148         .fill_modes = tda998x_connector_fill_modes,
1149         .detect = tda998x_connector_detect,
1150         .destroy = tda998x_connector_destroy,
1151         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1152         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1153 };
1154
1155 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1156 {
1157         struct tda998x_priv *priv = data;
1158         u8 offset, segptr;
1159         int ret, i;
1160
1161         offset = (blk & 1) ? 128 : 0;
1162         segptr = blk / 2;
1163
1164         mutex_lock(&priv->edid_mutex);
1165
1166         reg_write(priv, REG_DDC_ADDR, 0xa0);
1167         reg_write(priv, REG_DDC_OFFS, offset);
1168         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1169         reg_write(priv, REG_DDC_SEGM, segptr);
1170
1171         /* enable reading EDID: */
1172         priv->wq_edid_wait = 1;
1173         reg_write(priv, REG_EDID_CTRL, 0x1);
1174
1175         /* flag must be cleared by sw: */
1176         reg_write(priv, REG_EDID_CTRL, 0x0);
1177
1178         /* wait for block read to complete: */
1179         if (priv->hdmi->irq) {
1180                 i = wait_event_timeout(priv->wq_edid,
1181                                         !priv->wq_edid_wait,
1182                                         msecs_to_jiffies(100));
1183                 if (i < 0) {
1184                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1185                         ret = i;
1186                         goto failed;
1187                 }
1188         } else {
1189                 for (i = 100; i > 0; i--) {
1190                         msleep(1);
1191                         ret = reg_read(priv, REG_INT_FLAGS_2);
1192                         if (ret < 0)
1193                                 goto failed;
1194                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1195                                 break;
1196                 }
1197         }
1198
1199         if (i == 0) {
1200                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1201                 ret = -ETIMEDOUT;
1202                 goto failed;
1203         }
1204
1205         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1206         if (ret != length) {
1207                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1208                         blk, ret);
1209                 goto failed;
1210         }
1211
1212         ret = 0;
1213
1214  failed:
1215         mutex_unlock(&priv->edid_mutex);
1216         return ret;
1217 }
1218
1219 static int tda998x_connector_get_modes(struct drm_connector *connector)
1220 {
1221         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1222         struct edid *edid;
1223         int n;
1224
1225         /*
1226          * If we get killed while waiting for the HPD timeout, return
1227          * no modes found: we are not in a restartable path, so we
1228          * can't handle signals gracefully.
1229          */
1230         if (tda998x_edid_delay_wait(priv))
1231                 return 0;
1232
1233         if (priv->rev == TDA19988)
1234                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1235
1236         edid = drm_do_get_edid(connector, read_edid_block, priv);
1237
1238         if (priv->rev == TDA19988)
1239                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1240
1241         if (!edid) {
1242                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1243                 return 0;
1244         }
1245
1246         drm_mode_connector_update_edid_property(connector, edid);
1247         n = drm_add_edid_modes(connector, edid);
1248
1249         kfree(edid);
1250
1251         return n;
1252 }
1253
1254 static enum drm_mode_status tda998x_connector_mode_valid(struct drm_connector *connector,
1255                                         struct drm_display_mode *mode)
1256 {
1257         /* TDA19988 dotclock can go up to 165MHz */
1258         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1259
1260         if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1261                 return MODE_CLOCK_HIGH;
1262         if (mode->htotal >= BIT(13))
1263                 return MODE_BAD_HVALUE;
1264         if (mode->vtotal >= BIT(11))
1265                 return MODE_BAD_VVALUE;
1266         return MODE_OK;
1267 }
1268
1269 static struct drm_encoder *
1270 tda998x_connector_best_encoder(struct drm_connector *connector)
1271 {
1272         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1273
1274         return &priv->encoder;
1275 }
1276
1277 static
1278 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1279         .get_modes = tda998x_connector_get_modes,
1280         .mode_valid = tda998x_connector_mode_valid,
1281         .best_encoder = tda998x_connector_best_encoder,
1282 };
1283
1284 static int tda998x_connector_init(struct tda998x_priv *priv,
1285                                   struct drm_device *drm)
1286 {
1287         struct drm_connector *connector = &priv->connector;
1288         int ret;
1289
1290         connector->interlace_allowed = 1;
1291
1292         if (priv->hdmi->irq)
1293                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1294         else
1295                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1296                         DRM_CONNECTOR_POLL_DISCONNECT;
1297
1298         drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1299         ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1300                                  DRM_MODE_CONNECTOR_HDMIA);
1301         if (ret)
1302                 return ret;
1303
1304         drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1305
1306         return 0;
1307 }
1308
1309 /* DRM encoder functions */
1310
1311 static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
1312 {
1313         struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1314         bool on;
1315
1316         /* we only care about on or off: */
1317         on = mode == DRM_MODE_DPMS_ON;
1318
1319         if (on == priv->is_on)
1320                 return;
1321
1322         if (on) {
1323                 /* enable video ports, audio will be enabled later */
1324                 reg_write(priv, REG_ENA_VP_0, 0xff);
1325                 reg_write(priv, REG_ENA_VP_1, 0xff);
1326                 reg_write(priv, REG_ENA_VP_2, 0xff);
1327                 /* set muxing after enabling ports: */
1328                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1329                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1330                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1331
1332                 priv->is_on = true;
1333         } else {
1334                 /* disable video ports */
1335                 reg_write(priv, REG_ENA_VP_0, 0x00);
1336                 reg_write(priv, REG_ENA_VP_1, 0x00);
1337                 reg_write(priv, REG_ENA_VP_2, 0x00);
1338
1339                 priv->is_on = false;
1340         }
1341 }
1342
1343 static void
1344 tda998x_encoder_mode_set(struct drm_encoder *encoder,
1345                          struct drm_display_mode *mode,
1346                          struct drm_display_mode *adjusted_mode)
1347 {
1348         struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1349         u16 ref_pix, ref_line, n_pix, n_line;
1350         u16 hs_pix_s, hs_pix_e;
1351         u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1352         u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1353         u16 vwin1_line_s, vwin1_line_e;
1354         u16 vwin2_line_s, vwin2_line_e;
1355         u16 de_pix_s, de_pix_e;
1356         u8 reg, div, rep;
1357
1358         /*
1359          * Internally TDA998x is using ITU-R BT.656 style sync but
1360          * we get VESA style sync. TDA998x is using a reference pixel
1361          * relative to ITU to sync to the input frame and for output
1362          * sync generation. Currently, we are using reference detection
1363          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1364          * which is position of rising VS with coincident rising HS.
1365          *
1366          * Now there is some issues to take care of:
1367          * - HDMI data islands require sync-before-active
1368          * - TDA998x register values must be > 0 to be enabled
1369          * - REFLINE needs an additional offset of +1
1370          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1371          *
1372          * So we add +1 to all horizontal and vertical register values,
1373          * plus an additional +3 for REFPIX as we are using RGB input only.
1374          */
1375         n_pix        = mode->htotal;
1376         n_line       = mode->vtotal;
1377
1378         hs_pix_e     = mode->hsync_end - mode->hdisplay;
1379         hs_pix_s     = mode->hsync_start - mode->hdisplay;
1380         de_pix_e     = mode->htotal;
1381         de_pix_s     = mode->htotal - mode->hdisplay;
1382         ref_pix      = 3 + hs_pix_s;
1383
1384         /*
1385          * Attached LCD controllers may generate broken sync. Allow
1386          * those to adjust the position of the rising VS edge by adding
1387          * HSKEW to ref_pix.
1388          */
1389         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1390                 ref_pix += adjusted_mode->hskew;
1391
1392         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1393                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
1394                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1395                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1396                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1397                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
1398                 vs1_line_e   = vs1_line_s +
1399                                mode->vsync_end - mode->vsync_start;
1400                 vwin2_line_s = vwin2_line_e = 0;
1401                 vs2_pix_s    = vs2_pix_e  = 0;
1402                 vs2_line_s   = vs2_line_e = 0;
1403         } else {
1404                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
1405                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1406                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1407                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1408                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
1409                 vs1_line_e   = vs1_line_s +
1410                                (mode->vsync_end - mode->vsync_start)/2;
1411                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1412                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1413                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
1414                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
1415                 vs2_line_e   = vs2_line_s +
1416                                (mode->vsync_end - mode->vsync_start)/2;
1417         }
1418
1419         div = 148500 / mode->clock;
1420         if (div != 0) {
1421                 div--;
1422                 if (div > 3)
1423                         div = 3;
1424         }
1425
1426         mutex_lock(&priv->audio_mutex);
1427
1428         /* mute the audio FIFO: */
1429         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1430
1431         /* set HDMI HDCP mode off: */
1432         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1433         reg_clear(priv, REG_TX33, TX33_HDMI);
1434         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1435
1436         /* no pre-filter or interpolator: */
1437         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1438                         HVF_CNTRL_0_INTPOL(0));
1439         reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1440         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1441         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1442                         VIP_CNTRL_4_BLC(0));
1443
1444         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1445         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1446                                           PLL_SERIAL_3_SRL_DE);
1447         reg_write(priv, REG_SERIALIZER, 0);
1448         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1449
1450         /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
1451         rep = 0;
1452         reg_write(priv, REG_RPT_CNTRL, 0);
1453         reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
1454                         SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1455
1456         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1457                         PLL_SERIAL_2_SRL_PR(rep));
1458
1459         /* set color matrix bypass flag: */
1460         reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1461                                 MAT_CONTRL_MAT_SC(1));
1462         reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1463
1464         /* set BIAS tmds value: */
1465         reg_write(priv, REG_ANA_GENERAL, 0x09);
1466
1467         /*
1468          * Sync on rising HSYNC/VSYNC
1469          */
1470         reg = VIP_CNTRL_3_SYNC_HS;
1471
1472         /*
1473          * TDA19988 requires high-active sync at input stage,
1474          * so invert low-active sync provided by master encoder here
1475          */
1476         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1477                 reg |= VIP_CNTRL_3_H_TGL;
1478         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1479                 reg |= VIP_CNTRL_3_V_TGL;
1480         reg_write(priv, REG_VIP_CNTRL_3, reg);
1481
1482         reg_write(priv, REG_VIDFORMAT, 0x00);
1483         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1484         reg_write16(priv, REG_REFLINE_MSB, ref_line);
1485         reg_write16(priv, REG_NPIX_MSB, n_pix);
1486         reg_write16(priv, REG_NLINE_MSB, n_line);
1487         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1488         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1489         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1490         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1491         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1492         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1493         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1494         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1495         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1496         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1497         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1498         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1499         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1500         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1501         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1502         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1503
1504         if (priv->rev == TDA19988) {
1505                 /* let incoming pixels fill the active space (if any) */
1506                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1507         }
1508
1509         /*
1510          * Always generate sync polarity relative to input sync and
1511          * revert input stage toggled sync at output stage
1512          */
1513         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1514         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1515                 reg |= TBG_CNTRL_1_H_TGL;
1516         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1517                 reg |= TBG_CNTRL_1_V_TGL;
1518         reg_write(priv, REG_TBG_CNTRL_1, reg);
1519
1520         /* must be last register set: */
1521         reg_write(priv, REG_TBG_CNTRL_0, 0);
1522
1523         priv->tmds_clock = adjusted_mode->clock;
1524
1525         /* CEA-861B section 6 says that:
1526          * CEA version 1 (CEA-861) has no support for infoframes.
1527          * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1528          * and optional basic audio.
1529          * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1530          * and optional digital audio, with audio infoframes.
1531          *
1532          * Since we only support generation of version 2 AVI infoframes,
1533          * ignore CEA version 2 and below (iow, behave as if we're a
1534          * CEA-861 source.)
1535          */
1536         priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1537
1538         if (priv->supports_infoframes) {
1539                 /* We need to turn HDMI HDCP stuff on to get audio through */
1540                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1541                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1542                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1543                 reg_set(priv, REG_TX33, TX33_HDMI);
1544
1545                 tda998x_write_avi(priv, adjusted_mode);
1546
1547                 if (priv->audio_params.format != AFMT_UNUSED &&
1548                     priv->sink_has_audio)
1549                         tda998x_configure_audio(priv, &priv->audio_params);
1550         }
1551
1552         mutex_unlock(&priv->audio_mutex);
1553 }
1554
1555 static void tda998x_destroy(struct tda998x_priv *priv)
1556 {
1557         /* disable all IRQs and free the IRQ handler */
1558         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1559         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1560
1561         if (priv->audio_pdev)
1562                 platform_device_unregister(priv->audio_pdev);
1563
1564         if (priv->hdmi->irq)
1565                 free_irq(priv->hdmi->irq, priv);
1566
1567         del_timer_sync(&priv->edid_delay_timer);
1568         cancel_work_sync(&priv->detect_work);
1569
1570         i2c_unregister_device(priv->cec);
1571
1572         if (priv->cec_notify)
1573                 cec_notifier_put(priv->cec_notify);
1574 }
1575
1576 /* I2C driver functions */
1577
1578 static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1579                                    struct device_node *np)
1580 {
1581         const u32 *port_data;
1582         u32 size;
1583         int i;
1584
1585         port_data = of_get_property(np, "audio-ports", &size);
1586         if (!port_data)
1587                 return 0;
1588
1589         size /= sizeof(u32);
1590         if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) {
1591                 dev_err(&priv->hdmi->dev,
1592                         "Bad number of elements in audio-ports dt-property\n");
1593                 return -EINVAL;
1594         }
1595
1596         size /= 2;
1597
1598         for (i = 0; i < size; i++) {
1599                 u8 afmt = be32_to_cpup(&port_data[2*i]);
1600                 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1601
1602                 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) {
1603                         dev_err(&priv->hdmi->dev,
1604                                 "Bad audio format %u\n", afmt);
1605                         return -EINVAL;
1606                 }
1607
1608                 priv->audio_port[i].format = afmt;
1609                 priv->audio_port[i].config = ena_ap;
1610         }
1611
1612         if (priv->audio_port[0].format == priv->audio_port[1].format) {
1613                 dev_err(&priv->hdmi->dev,
1614                         "There can only be on I2S port and one SPDIF port\n");
1615                 return -EINVAL;
1616         }
1617         return 0;
1618 }
1619
1620 static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1621 {
1622         struct device_node *np = client->dev.of_node;
1623         struct i2c_board_info cec_info;
1624         u32 video;
1625         int rev_lo, rev_hi, ret;
1626
1627         mutex_init(&priv->mutex);       /* protect the page access */
1628         mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1629         mutex_init(&priv->edid_mutex);
1630         init_waitqueue_head(&priv->edid_delay_waitq);
1631         timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1632         INIT_WORK(&priv->detect_work, tda998x_detect_work);
1633
1634         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1635         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1636         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1637
1638         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1639         priv->cec_addr = 0x34 + (client->addr & 0x03);
1640         priv->current_page = 0xff;
1641         priv->hdmi = client;
1642
1643         /* wake up the device: */
1644         cec_write(priv, REG_CEC_ENAMODS,
1645                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1646
1647         tda998x_reset(priv);
1648
1649         /* read version: */
1650         rev_lo = reg_read(priv, REG_VERSION_LSB);
1651         if (rev_lo < 0) {
1652                 dev_err(&client->dev, "failed to read version: %d\n", rev_lo);
1653                 return rev_lo;
1654         }
1655
1656         rev_hi = reg_read(priv, REG_VERSION_MSB);
1657         if (rev_hi < 0) {
1658                 dev_err(&client->dev, "failed to read version: %d\n", rev_hi);
1659                 return rev_hi;
1660         }
1661
1662         priv->rev = rev_lo | rev_hi << 8;
1663
1664         /* mask off feature bits: */
1665         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1666
1667         switch (priv->rev) {
1668         case TDA9989N2:
1669                 dev_info(&client->dev, "found TDA9989 n2");
1670                 break;
1671         case TDA19989:
1672                 dev_info(&client->dev, "found TDA19989");
1673                 break;
1674         case TDA19989N2:
1675                 dev_info(&client->dev, "found TDA19989 n2");
1676                 break;
1677         case TDA19988:
1678                 dev_info(&client->dev, "found TDA19988");
1679                 break;
1680         default:
1681                 dev_err(&client->dev, "found unsupported device: %04x\n",
1682                         priv->rev);
1683                 return -ENXIO;
1684         }
1685
1686         /* after reset, enable DDC: */
1687         reg_write(priv, REG_DDC_DISABLE, 0x00);
1688
1689         /* set clock on DDC channel: */
1690         reg_write(priv, REG_TX3, 39);
1691
1692         /* if necessary, disable multi-master: */
1693         if (priv->rev == TDA19989)
1694                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1695
1696         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1697                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1698
1699         /* ensure interrupts are disabled */
1700         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1701
1702         /* clear pending interrupts */
1703         cec_read(priv, REG_CEC_RXSHPDINT);
1704         reg_read(priv, REG_INT_FLAGS_0);
1705         reg_read(priv, REG_INT_FLAGS_1);
1706         reg_read(priv, REG_INT_FLAGS_2);
1707
1708         /* initialize the optional IRQ */
1709         if (client->irq) {
1710                 unsigned long irq_flags;
1711
1712                 /* init read EDID waitqueue and HDP work */
1713                 init_waitqueue_head(&priv->wq_edid);
1714
1715                 irq_flags =
1716                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1717
1718                 priv->cec_glue.irq_flags = irq_flags;
1719
1720                 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1721                 ret = request_threaded_irq(client->irq, NULL,
1722                                            tda998x_irq_thread, irq_flags,
1723                                            "tda998x", priv);
1724                 if (ret) {
1725                         dev_err(&client->dev,
1726                                 "failed to request IRQ#%u: %d\n",
1727                                 client->irq, ret);
1728                         goto err_irq;
1729                 }
1730
1731                 /* enable HPD irq */
1732                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1733         }
1734
1735         priv->cec_notify = cec_notifier_get(&client->dev);
1736         if (!priv->cec_notify) {
1737                 ret = -ENOMEM;
1738                 goto fail;
1739         }
1740
1741         priv->cec_glue.parent = &client->dev;
1742         priv->cec_glue.data = priv;
1743         priv->cec_glue.init = tda998x_cec_hook_init;
1744         priv->cec_glue.exit = tda998x_cec_hook_exit;
1745         priv->cec_glue.open = tda998x_cec_hook_open;
1746         priv->cec_glue.release = tda998x_cec_hook_release;
1747
1748         /*
1749          * Some TDA998x are actually two I2C devices merged onto one piece
1750          * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1751          * with a slightly modified TDA9950 CEC device.  The CEC device
1752          * is at the TDA9950 address, with the address pins strapped across
1753          * to the TDA998x address pins.  Hence, it always has the same
1754          * offset.
1755          */
1756         memset(&cec_info, 0, sizeof(cec_info));
1757         strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1758         cec_info.addr = priv->cec_addr;
1759         cec_info.platform_data = &priv->cec_glue;
1760         cec_info.irq = client->irq;
1761
1762         priv->cec = i2c_new_device(client->adapter, &cec_info);
1763         if (!priv->cec) {
1764                 ret = -ENODEV;
1765                 goto fail;
1766         }
1767
1768         /* enable EDID read irq: */
1769         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1770
1771         if (!np)
1772                 return 0;               /* non-DT */
1773
1774         /* get the device tree parameters */
1775         ret = of_property_read_u32(np, "video-ports", &video);
1776         if (ret == 0) {
1777                 priv->vip_cntrl_0 = video >> 16;
1778                 priv->vip_cntrl_1 = video >> 8;
1779                 priv->vip_cntrl_2 = video;
1780         }
1781
1782         ret = tda998x_get_audio_ports(priv, np);
1783         if (ret)
1784                 goto fail;
1785
1786         if (priv->audio_port[0].format != AFMT_UNUSED)
1787                 tda998x_audio_codec_init(priv, &client->dev);
1788
1789         return 0;
1790
1791 fail:
1792         /* if encoder_init fails, the encoder slave is never registered,
1793          * so cleanup here:
1794          */
1795         i2c_unregister_device(priv->cec);
1796         if (priv->cec_notify)
1797                 cec_notifier_put(priv->cec_notify);
1798         if (client->irq)
1799                 free_irq(client->irq, priv);
1800 err_irq:
1801         return ret;
1802 }
1803
1804 static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1805 {
1806         tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1807 }
1808
1809 static void tda998x_encoder_commit(struct drm_encoder *encoder)
1810 {
1811         tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1812 }
1813
1814 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1815         .dpms = tda998x_encoder_dpms,
1816         .prepare = tda998x_encoder_prepare,
1817         .commit = tda998x_encoder_commit,
1818         .mode_set = tda998x_encoder_mode_set,
1819 };
1820
1821 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1822 {
1823         struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1824
1825         tda998x_destroy(priv);
1826         drm_encoder_cleanup(encoder);
1827 }
1828
1829 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1830         .destroy = tda998x_encoder_destroy,
1831 };
1832
1833 static void tda998x_set_config(struct tda998x_priv *priv,
1834                                const struct tda998x_encoder_params *p)
1835 {
1836         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1837                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1838                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
1839                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1840         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1841                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1842                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
1843                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1844         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1845                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1846                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
1847                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1848
1849         priv->audio_params = p->audio_params;
1850 }
1851
1852 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1853 {
1854         struct tda998x_encoder_params *params = dev->platform_data;
1855         struct i2c_client *client = to_i2c_client(dev);
1856         struct drm_device *drm = data;
1857         struct tda998x_priv *priv;
1858         u32 crtcs = 0;
1859         int ret;
1860
1861         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1862         if (!priv)
1863                 return -ENOMEM;
1864
1865         dev_set_drvdata(dev, priv);
1866
1867         if (dev->of_node)
1868                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1869
1870         /* If no CRTCs were found, fall back to our old behaviour */
1871         if (crtcs == 0) {
1872                 dev_warn(dev, "Falling back to first CRTC\n");
1873                 crtcs = 1 << 0;
1874         }
1875
1876         priv->encoder.possible_crtcs = crtcs;
1877
1878         ret = tda998x_create(client, priv);
1879         if (ret)
1880                 return ret;
1881
1882         if (!dev->of_node && params)
1883                 tda998x_set_config(priv, params);
1884
1885         drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1886         ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1887                                DRM_MODE_ENCODER_TMDS, NULL);
1888         if (ret)
1889                 goto err_encoder;
1890
1891         ret = tda998x_connector_init(priv, drm);
1892         if (ret)
1893                 goto err_connector;
1894
1895         return 0;
1896
1897 err_connector:
1898         drm_encoder_cleanup(&priv->encoder);
1899 err_encoder:
1900         tda998x_destroy(priv);
1901         return ret;
1902 }
1903
1904 static void tda998x_unbind(struct device *dev, struct device *master,
1905                            void *data)
1906 {
1907         struct tda998x_priv *priv = dev_get_drvdata(dev);
1908
1909         drm_connector_cleanup(&priv->connector);
1910         drm_encoder_cleanup(&priv->encoder);
1911         tda998x_destroy(priv);
1912 }
1913
1914 static const struct component_ops tda998x_ops = {
1915         .bind = tda998x_bind,
1916         .unbind = tda998x_unbind,
1917 };
1918
1919 static int
1920 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1921 {
1922         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1923                 dev_warn(&client->dev, "adapter does not support I2C\n");
1924                 return -EIO;
1925         }
1926         return component_add(&client->dev, &tda998x_ops);
1927 }
1928
1929 static int tda998x_remove(struct i2c_client *client)
1930 {
1931         component_del(&client->dev, &tda998x_ops);
1932         return 0;
1933 }
1934
1935 #ifdef CONFIG_OF
1936 static const struct of_device_id tda998x_dt_ids[] = {
1937         { .compatible = "nxp,tda998x", },
1938         { }
1939 };
1940 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1941 #endif
1942
1943 static const struct i2c_device_id tda998x_ids[] = {
1944         { "tda998x", 0 },
1945         { }
1946 };
1947 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1948
1949 static struct i2c_driver tda998x_driver = {
1950         .probe = tda998x_probe,
1951         .remove = tda998x_remove,
1952         .driver = {
1953                 .name = "tda998x",
1954                 .of_match_table = of_match_ptr(tda998x_dt_ids),
1955         },
1956         .id_table = tda998x_ids,
1957 };
1958
1959 module_i2c_driver(tda998x_driver);
1960
1961 MODULE_AUTHOR("Rob Clark <[email protected]");
1962 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1963 MODULE_LICENSE("GPL");