drivers/usb/phy/phy-tegra-usb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2010 Google, Inc.
   4  * Copyright (C) 2013 NVIDIA Corporation
   5  *
   6  * Author:
   7  *      Erik Gilling <[email protected]>
   8  *      Benoit Goby <[email protected]>
   9  *      Venu Byravarasu <[email protected]>
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/err.h>
  14 #include <linux/export.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/resource.h>
  22 #include <linux/slab.h>
  23 #include <linux/spinlock.h>
  24
  25 #include <linux/regulator/consumer.h>
  26
  27 #include <linux/usb/ehci_def.h>
  28 #include <linux/usb/of.h>
  29 #include <linux/usb/tegra_usb_phy.h>
  30 #include <linux/usb/ulpi.h>
  31
  32 #define ULPI_VIEWPORT                           0x170
  33
  34 /* PORTSC PTS/PHCD bits, Tegra20 only */
  35 #define TEGRA_USB_PORTSC1                       0x184
  36 #define TEGRA_USB_PORTSC1_PTS(x)                (((x) & 0x3) << 30)
  37 #define TEGRA_USB_PORTSC1_PHCD                  BIT(23)
  38
  39 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
  40 #define TEGRA_USB_HOSTPC1_DEVLC                 0x1b4
  41 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
  42 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD            BIT(22)
  43
  44 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
  45 #define TEGRA_PORTSC1_RWC_BITS  (PORT_CSC | PORT_PEC | PORT_OCC)
  46
  47 #define USB_SUSP_CTRL                           0x400
  48 #define   USB_WAKE_ON_RESUME_EN                 BIT(2)
  49 #define   USB_WAKE_ON_CNNT_EN_DEV               BIT(3)
  50 #define   USB_WAKE_ON_DISCON_EN_DEV             BIT(4)
  51 #define   USB_SUSP_CLR                          BIT(5)
  52 #define   USB_PHY_CLK_VALID                     BIT(7)
  53 #define   UTMIP_RESET                           BIT(11)
  54 #define   UHSIC_RESET                           BIT(11)
  55 #define   UTMIP_PHY_ENABLE                      BIT(12)
  56 #define   ULPI_PHY_ENABLE                       BIT(13)
  57 #define   USB_SUSP_SET                          BIT(14)
  58 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)          (((x) & 0x7) << 16)
  59
  60 #define USB_PHY_VBUS_SENSORS                    0x404
  61 #define   B_SESS_VLD_WAKEUP_EN                  BIT(14)
  62 #define   A_SESS_VLD_WAKEUP_EN                  BIT(22)
  63 #define   A_VBUS_VLD_WAKEUP_EN                  BIT(30)
  64
  65 #define USB_PHY_VBUS_WAKEUP_ID                  0x408
  66 #define   VBUS_WAKEUP_STS                       BIT(10)
  67 #define   VBUS_WAKEUP_WAKEUP_EN                 BIT(30)
  68
  69 #define USB1_LEGACY_CTRL                        0x410
  70 #define   USB1_NO_LEGACY_MODE                   BIT(0)
  71 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  72 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  73 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  74                                                 (1 << 1)
  75 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  76 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  77
  78 #define ULPI_TIMING_CTRL_0                      0x424
  79 #define   ULPI_OUTPUT_PINMUX_BYP                BIT(10)
  80 #define   ULPI_CLKOUT_PINMUX_BYP                BIT(11)
  81
  82 #define ULPI_TIMING_CTRL_1                      0x428
  83 #define   ULPI_DATA_TRIMMER_LOAD                BIT(0)
  84 #define   ULPI_DATA_TRIMMER_SEL(x)              (((x) & 0x7) << 1)
  85 #define   ULPI_STPDIRNXT_TRIMMER_LOAD           BIT(16)
  86 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x)         (((x) & 0x7) << 17)
  87 #define   ULPI_DIR_TRIMMER_LOAD                 BIT(24)
  88 #define   ULPI_DIR_TRIMMER_SEL(x)               (((x) & 0x7) << 25)
  89
  90 #define UTMIP_PLL_CFG1                          0x804
  91 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  92 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  93
  94 #define UTMIP_XCVR_CFG0                         0x808
  95 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  96 #define   UTMIP_XCVR_SETUP_MSB(x)               ((((x) & 0x70) >> 4) << 22)
  97 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  98 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  99 #define   UTMIP_FORCE_PD_POWERDOWN              BIT(14)
 100 #define   UTMIP_FORCE_PD2_POWERDOWN             BIT(16)
 101 #define   UTMIP_FORCE_PDZI_POWERDOWN            BIT(18)
 102 #define   UTMIP_XCVR_LSBIAS_SEL                 BIT(21)
 103 #define   UTMIP_XCVR_HSSLEW(x)                  (((x) & 0x3) << 4)
 104 #define   UTMIP_XCVR_HSSLEW_MSB(x)              ((((x) & 0x1fc) >> 2) << 25)
 105
 106 #define UTMIP_BIAS_CFG0                         0x80c
 107 #define   UTMIP_OTGPD                           BIT(11)
 108 #define   UTMIP_BIASPD                          BIT(10)
 109 #define   UTMIP_HSSQUELCH_LEVEL(x)              (((x) & 0x3) << 0)
 110 #define   UTMIP_HSDISCON_LEVEL(x)               (((x) & 0x3) << 2)
 111 #define   UTMIP_HSDISCON_LEVEL_MSB(x)           ((((x) & 0x4) >> 2) << 24)
 112
 113 #define UTMIP_HSRX_CFG0                         0x810
 114 #define   UTMIP_ELASTIC_LIMIT(x)                (((x) & 0x1f) << 10)
 115 #define   UTMIP_IDLE_WAIT(x)                    (((x) & 0x1f) << 15)
 116
 117 #define UTMIP_HSRX_CFG1                         0x814
 118 #define   UTMIP_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
 119
 120 #define UTMIP_TX_CFG0                           0x820
 121 #define   UTMIP_FS_PREABMLE_J                   BIT(19)
 122 #define   UTMIP_HS_DISCON_DISABLE               BIT(8)
 123
 124 #define UTMIP_MISC_CFG0                         0x824
 125 #define   UTMIP_DPDM_OBSERVE                    BIT(26)
 126 #define   UTMIP_DPDM_OBSERVE_SEL(x)             (((x) & 0xf) << 27)
 127 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J           UTMIP_DPDM_OBSERVE_SEL(0xf)
 128 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K           UTMIP_DPDM_OBSERVE_SEL(0xe)
 129 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1         UTMIP_DPDM_OBSERVE_SEL(0xd)
 130 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0         UTMIP_DPDM_OBSERVE_SEL(0xc)
 131 #define   UTMIP_SUSPEND_EXIT_ON_EDGE            BIT(22)
 132
 133 #define UTMIP_MISC_CFG1                         0x828
 134 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x)         (((x) & 0x1f) << 18)
 135 #define   UTMIP_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 6)
 136
 137 #define UTMIP_DEBOUNCE_CFG0                     0x82c
 138 #define   UTMIP_BIAS_DEBOUNCE_A(x)              (((x) & 0xffff) << 0)
 139
 140 #define UTMIP_BAT_CHRG_CFG0                     0x830
 141 #define   UTMIP_PD_CHRG                         BIT(0)
 142
 143 #define UTMIP_SPARE_CFG0                        0x834
 144 #define   FUSE_SETUP_SEL                        BIT(3)
 145
 146 #define UTMIP_XCVR_CFG1                         0x838
 147 #define   UTMIP_FORCE_PDDISC_POWERDOWN          BIT(0)
 148 #define   UTMIP_FORCE_PDCHRP_POWERDOWN          BIT(2)
 149 #define   UTMIP_FORCE_PDDR_POWERDOWN            BIT(4)
 150 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)          (((x) & 0xf) << 18)
 151
 152 #define UTMIP_BIAS_CFG1                         0x83c
 153 #define   UTMIP_BIAS_PDTRK_COUNT(x)             (((x) & 0x1f) << 3)
 154
 155 /* For Tegra30 and above only, the address is different in Tegra20 */
 156 #define USB_USBMODE                             0x1f8
 157 #define   USB_USBMODE_MASK                      (3 << 0)
 158 #define   USB_USBMODE_HOST                      (3 << 0)
 159 #define   USB_USBMODE_DEVICE                    (2 << 0)
 160
 161 static DEFINE_SPINLOCK(utmip_pad_lock);
 162 static unsigned int utmip_pad_count;
 163
 164 struct tegra_xtal_freq {
 165         unsigned int freq;
 166         u8 enable_delay;
 167         u8 stable_count;
 168         u8 active_delay;
 169         u8 xtal_freq_count;
 170         u16 debounce;
 171 };
 172
 173 static const struct tegra_xtal_freq tegra_freq_table[] = {
 174         {
 175                 .freq = 12000000,
 176                 .enable_delay = 0x02,
 177                 .stable_count = 0x2F,
 178                 .active_delay = 0x04,
 179                 .xtal_freq_count = 0x76,
 180                 .debounce = 0x7530,
 181         },
 182         {
 183                 .freq = 13000000,
 184                 .enable_delay = 0x02,
 185                 .stable_count = 0x33,
 186                 .active_delay = 0x05,
 187                 .xtal_freq_count = 0x7F,
 188                 .debounce = 0x7EF4,
 189         },
 190         {
 191                 .freq = 19200000,
 192                 .enable_delay = 0x03,
 193                 .stable_count = 0x4B,
 194                 .active_delay = 0x06,
 195                 .xtal_freq_count = 0xBB,
 196                 .debounce = 0xBB80,
 197         },
 198         {
 199                 .freq = 26000000,
 200                 .enable_delay = 0x04,
 201                 .stable_count = 0x66,
 202                 .active_delay = 0x09,
 203                 .xtal_freq_count = 0xFE,
 204                 .debounce = 0xFDE8,
 205         },
 206 };
 207
 208 static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)
 209 {
 210         return container_of(u_phy, struct tegra_usb_phy, u_phy);
 211 }
 212
 213 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
 214 {
 215         void __iomem *base = phy->regs;
 216         u32 val;
 217
 218         if (phy->soc_config->has_hostpc) {
 219                 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
 220                 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
 221                 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
 222                 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 223         } else {
 224                 val = readl_relaxed(base + TEGRA_USB_PORTSC1);
 225                 val &= ~TEGRA_PORTSC1_RWC_BITS;
 226                 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
 227                 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
 228                 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
 229         }
 230 }
 231
 232 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
 233 {
 234         void __iomem *base = phy->regs;
 235         u32 val;
 236
 237         if (phy->soc_config->has_hostpc) {
 238                 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
 239                 if (enable)
 240                         val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 241                 else
 242                         val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 243                 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 244         } else {
 245                 val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
 246                 if (enable)
 247                         val |= TEGRA_USB_PORTSC1_PHCD;
 248                 else
 249                         val &= ~TEGRA_USB_PORTSC1_PHCD;
 250                 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
 251         }
 252 }
 253
 254 static int utmip_pad_open(struct tegra_usb_phy *phy)
 255 {
 256         int ret;
 257
 258         ret = clk_prepare_enable(phy->pad_clk);
 259         if (ret) {
 260                 dev_err(phy->u_phy.dev,
 261                         "Failed to enable UTMI-pads clock: %d\n", ret);
 262                 return ret;
 263         }
 264
 265         spin_lock(&utmip_pad_lock);
 266
 267         ret = reset_control_deassert(phy->pad_rst);
 268         if (ret) {
 269                 dev_err(phy->u_phy.dev,
 270                         "Failed to initialize UTMI-pads reset: %d\n", ret);
 271                 goto unlock;
 272         }
 273
 274         ret = reset_control_assert(phy->pad_rst);
 275         if (ret) {
 276                 dev_err(phy->u_phy.dev,
 277                         "Failed to assert UTMI-pads reset: %d\n", ret);
 278                 goto unlock;
 279         }
 280
 281         udelay(1);
 282
 283         ret = reset_control_deassert(phy->pad_rst);
 284         if (ret)
 285                 dev_err(phy->u_phy.dev,
 286                         "Failed to deassert UTMI-pads reset: %d\n", ret);
 287 unlock:
 288         spin_unlock(&utmip_pad_lock);
 289
 290         clk_disable_unprepare(phy->pad_clk);
 291
 292         return ret;
 293 }
 294
 295 static int utmip_pad_close(struct tegra_usb_phy *phy)
 296 {
 297         int ret;
 298
 299         ret = clk_prepare_enable(phy->pad_clk);
 300         if (ret) {
 301                 dev_err(phy->u_phy.dev,
 302                         "Failed to enable UTMI-pads clock: %d\n", ret);
 303                 return ret;
 304         }
 305
 306         ret = reset_control_assert(phy->pad_rst);
 307         if (ret)
 308                 dev_err(phy->u_phy.dev,
 309                         "Failed to assert UTMI-pads reset: %d\n", ret);
 310
 311         udelay(1);
 312
 313         clk_disable_unprepare(phy->pad_clk);
 314
 315         return ret;
 316 }
 317
 318 static int utmip_pad_power_on(struct tegra_usb_phy *phy)
 319 {
 320         struct tegra_utmip_config *config = phy->config;
 321         void __iomem *base = phy->pad_regs;
 322         u32 val;
 323         int err;
 324
 325         err = clk_prepare_enable(phy->pad_clk);
 326         if (err)
 327                 return err;
 328
 329         spin_lock(&utmip_pad_lock);
 330
 331         if (utmip_pad_count++ == 0) {
 332                 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
 333                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 334
 335                 if (phy->soc_config->requires_extra_tuning_parameters) {
 336                         val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
 337                                 UTMIP_HSDISCON_LEVEL(~0) |
 338                                 UTMIP_HSDISCON_LEVEL_MSB(~0));
 339
 340                         val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
 341                         val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
 342                         val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
 343                 }
 344                 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
 345         }
 346
 347         if (phy->pad_wakeup) {
 348                 phy->pad_wakeup = false;
 349                 utmip_pad_count--;
 350         }
 351
 352         spin_unlock(&utmip_pad_lock);
 353
 354         clk_disable_unprepare(phy->pad_clk);
 355
 356         return 0;
 357 }
 358
 359 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 360 {
 361         void __iomem *base = phy->pad_regs;
 362         u32 val;
 363         int ret;
 364
 365         ret = clk_prepare_enable(phy->pad_clk);
 366         if (ret)
 367                 return ret;
 368
 369         spin_lock(&utmip_pad_lock);
 370
 371         if (!utmip_pad_count) {
 372                 dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
 373                 ret = -EINVAL;
 374                 goto ulock;
 375         }
 376
 377         /*
 378          * In accordance to TRM, OTG and Bias pad circuits could be turned off
 379          * to save power if wake is enabled, but the VBUS-change detection
 380          * method is board-specific and these circuits may need to be enabled
 381          * to generate wakeup event, hence we will just keep them both enabled.
 382          */
 383         if (phy->wakeup_enabled) {
 384                 phy->pad_wakeup = true;
 385                 utmip_pad_count++;
 386         }
 387
 388         if (--utmip_pad_count == 0) {
 389                 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
 390                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 391                 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
 392         }
 393 ulock:
 394         spin_unlock(&utmip_pad_lock);
 395
 396         clk_disable_unprepare(phy->pad_clk);
 397
 398         return ret;
 399 }
 400
 401 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 402 {
 403         u32 tmp;
 404
 405         return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
 406                                           2000, 6000);
 407 }
 408
 409 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 410 {
 411         void __iomem *base = phy->regs;
 412         u32 val;
 413
 414         /*
 415          * The USB driver may have already initiated the phy clock
 416          * disable so wait to see if the clock turns off and if not
 417          * then proceed with gating the clock.
 418          */
 419         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
 420                 return;
 421
 422         if (phy->is_legacy_phy) {
 423                 val = readl_relaxed(base + USB_SUSP_CTRL);
 424                 val |= USB_SUSP_SET;
 425                 writel_relaxed(val, base + USB_SUSP_CTRL);
 426
 427                 usleep_range(10, 100);
 428
 429                 val = readl_relaxed(base + USB_SUSP_CTRL);
 430                 val &= ~USB_SUSP_SET;
 431                 writel_relaxed(val, base + USB_SUSP_CTRL);
 432         } else {
 433                 set_phcd(phy, true);
 434         }
 435
 436         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
 437                 dev_err(phy->u_phy.dev,
 438                         "Timeout waiting for PHY to stabilize on disable\n");
 439 }
 440
 441 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 442 {
 443         void __iomem *base = phy->regs;
 444         u32 val;
 445
 446         /*
 447          * The USB driver may have already initiated the phy clock
 448          * enable so wait to see if the clock turns on and if not
 449          * then proceed with ungating the clock.
 450          */
 451         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 452                                USB_PHY_CLK_VALID) == 0)
 453                 return;
 454
 455         if (phy->is_legacy_phy) {
 456                 val = readl_relaxed(base + USB_SUSP_CTRL);
 457                 val |= USB_SUSP_CLR;
 458                 writel_relaxed(val, base + USB_SUSP_CTRL);
 459
 460                 usleep_range(10, 100);
 461
 462                 val = readl_relaxed(base + USB_SUSP_CTRL);
 463                 val &= ~USB_SUSP_CLR;
 464                 writel_relaxed(val, base + USB_SUSP_CTRL);
 465         } else {
 466                 set_phcd(phy, false);
 467         }
 468
 469         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 470                                USB_PHY_CLK_VALID))
 471                 dev_err(phy->u_phy.dev,
 472                         "Timeout waiting for PHY to stabilize on enable\n");
 473 }
 474
 475 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 476 {
 477         struct tegra_utmip_config *config = phy->config;
 478         void __iomem *base = phy->regs;
 479         u32 val;
 480         int err;
 481
 482         val = readl_relaxed(base + USB_SUSP_CTRL);
 483         val |= UTMIP_RESET;
 484         writel_relaxed(val, base + USB_SUSP_CTRL);
 485
 486         if (phy->is_legacy_phy) {
 487                 val = readl_relaxed(base + USB1_LEGACY_CTRL);
 488                 val |= USB1_NO_LEGACY_MODE;
 489                 writel_relaxed(val, base + USB1_LEGACY_CTRL);
 490         }
 491
 492         val = readl_relaxed(base + UTMIP_TX_CFG0);
 493         val |= UTMIP_FS_PREABMLE_J;
 494         writel_relaxed(val, base + UTMIP_TX_CFG0);
 495
 496         val = readl_relaxed(base + UTMIP_HSRX_CFG0);
 497         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 498         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 499         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 500         writel_relaxed(val, base + UTMIP_HSRX_CFG0);
 501
 502         val = readl_relaxed(base + UTMIP_HSRX_CFG1);
 503         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 504         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 505         writel_relaxed(val, base + UTMIP_HSRX_CFG1);
 506
 507         val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
 508         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 509         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 510         writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
 511
 512         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 513         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 514         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 515
 516         if (!phy->soc_config->utmi_pll_config_in_car_module) {
 517                 val = readl_relaxed(base + UTMIP_MISC_CFG1);
 518                 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
 519                         UTMIP_PLLU_STABLE_COUNT(~0));
 520                 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 521                         UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 522                 writel_relaxed(val, base + UTMIP_MISC_CFG1);
 523
 524                 val = readl_relaxed(base + UTMIP_PLL_CFG1);
 525                 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
 526                         UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 527                 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 528                         UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 529                 writel_relaxed(val, base + UTMIP_PLL_CFG1);
 530         }
 531
 532         val = readl_relaxed(base + USB_SUSP_CTRL);
 533         val &= ~USB_WAKE_ON_RESUME_EN;
 534         writel_relaxed(val, base + USB_SUSP_CTRL);
 535
 536         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 537                 val = readl_relaxed(base + USB_SUSP_CTRL);
 538                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 539                 writel_relaxed(val, base + USB_SUSP_CTRL);
 540
 541                 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
 542                 val &= ~VBUS_WAKEUP_WAKEUP_EN;
 543                 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
 544
 545                 val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
 546                 val &= ~(A_VBUS_VLD_WAKEUP_EN | A_SESS_VLD_WAKEUP_EN);
 547                 val &= ~(B_SESS_VLD_WAKEUP_EN);
 548                 writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
 549
 550                 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
 551                 val &= ~UTMIP_PD_CHRG;
 552                 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
 553         } else {
 554                 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
 555                 val |= UTMIP_PD_CHRG;
 556                 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
 557         }
 558
 559         err = utmip_pad_power_on(phy);
 560         if (err)
 561                 return err;
 562
 563         val = readl_relaxed(base + UTMIP_XCVR_CFG0);
 564         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 565                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
 566                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
 567                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
 568
 569         if (!config->xcvr_setup_use_fuses) {
 570                 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 571                 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
 572         }
 573         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 574         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 575
 576         if (phy->soc_config->requires_extra_tuning_parameters) {
 577                 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
 578                 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
 579                 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
 580         }
 581         writel_relaxed(val, base + UTMIP_XCVR_CFG0);
 582
 583         val = readl_relaxed(base + UTMIP_XCVR_CFG1);
 584         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 585                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 586         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 587         writel_relaxed(val, base + UTMIP_XCVR_CFG1);
 588
 589         val = readl_relaxed(base + UTMIP_BIAS_CFG1);
 590         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 591         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 592         writel_relaxed(val, base + UTMIP_BIAS_CFG1);
 593
 594         val = readl_relaxed(base + UTMIP_SPARE_CFG0);
 595         if (config->xcvr_setup_use_fuses)
 596                 val |= FUSE_SETUP_SEL;
 597         else
 598                 val &= ~FUSE_SETUP_SEL;
 599         writel_relaxed(val, base + UTMIP_SPARE_CFG0);
 600
 601         if (!phy->is_legacy_phy) {
 602                 val = readl_relaxed(base + USB_SUSP_CTRL);
 603                 val |= UTMIP_PHY_ENABLE;
 604                 writel_relaxed(val, base + USB_SUSP_CTRL);
 605         }
 606
 607         val = readl_relaxed(base + USB_SUSP_CTRL);
 608         val &= ~UTMIP_RESET;
 609         writel_relaxed(val, base + USB_SUSP_CTRL);
 610
 611         if (phy->is_legacy_phy) {
 612                 val = readl_relaxed(base + USB1_LEGACY_CTRL);
 613                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 614                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 615                 writel_relaxed(val, base + USB1_LEGACY_CTRL);
 616
 617                 val = readl_relaxed(base + USB_SUSP_CTRL);
 618                 val &= ~USB_SUSP_SET;
 619                 writel_relaxed(val, base + USB_SUSP_CTRL);
 620         }
 621
 622         utmi_phy_clk_enable(phy);
 623
 624         if (phy->soc_config->requires_usbmode_setup) {
 625                 val = readl_relaxed(base + USB_USBMODE);
 626                 val &= ~USB_USBMODE_MASK;
 627                 if (phy->mode == USB_DR_MODE_HOST)
 628                         val |= USB_USBMODE_HOST;
 629                 else
 630                         val |= USB_USBMODE_DEVICE;
 631                 writel_relaxed(val, base + USB_USBMODE);
 632         }
 633
 634         if (!phy->is_legacy_phy)
 635                 set_pts(phy, 0);
 636
 637         return 0;
 638 }
 639
 640 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 641 {
 642         void __iomem *base = phy->regs;
 643         u32 val;
 644
 645         /*
 646          * Give hardware time to settle down after VBUS disconnection,
 647          * otherwise PHY will immediately wake up from suspend.
 648          */
 649         if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST)
 650                 readl_relaxed_poll_timeout(base + USB_PHY_VBUS_WAKEUP_ID,
 651                                            val, !(val & VBUS_WAKEUP_STS),
 652                                            5000, 100000);
 653
 654         utmi_phy_clk_disable(phy);
 655
 656         /* PHY won't resume if reset is asserted */
 657         if (!phy->wakeup_enabled) {
 658                 val = readl_relaxed(base + USB_SUSP_CTRL);
 659                 val |= UTMIP_RESET;
 660                 writel_relaxed(val, base + USB_SUSP_CTRL);
 661         }
 662
 663         val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
 664         val |= UTMIP_PD_CHRG;
 665         writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
 666
 667         if (!phy->wakeup_enabled) {
 668                 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
 669                 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 670                        UTMIP_FORCE_PDZI_POWERDOWN;
 671                 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
 672         }
 673
 674         val = readl_relaxed(base + UTMIP_XCVR_CFG1);
 675         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 676                UTMIP_FORCE_PDDR_POWERDOWN;
 677         writel_relaxed(val, base + UTMIP_XCVR_CFG1);
 678
 679         if (phy->wakeup_enabled) {
 680                 val = readl_relaxed(base + USB_SUSP_CTRL);
 681                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 682                 val |= USB_WAKEUP_DEBOUNCE_COUNT(5);
 683                 val |= USB_WAKE_ON_RESUME_EN;
 684                 writel_relaxed(val, base + USB_SUSP_CTRL);
 685
 686                 /*
 687                  * Ask VBUS sensor to generate wake event once cable is
 688                  * connected.
 689                  */
 690                 if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 691                         val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
 692                         val |= VBUS_WAKEUP_WAKEUP_EN;
 693                         writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
 694
 695                         val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
 696                         val |= A_VBUS_VLD_WAKEUP_EN;
 697                         writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
 698                 }
 699         }
 700
 701         return utmip_pad_power_off(phy);
 702 }
 703
 704 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 705 {
 706         void __iomem *base = phy->regs;
 707         u32 val;
 708
 709         val = readl_relaxed(base + UTMIP_TX_CFG0);
 710         val |= UTMIP_HS_DISCON_DISABLE;
 711         writel_relaxed(val, base + UTMIP_TX_CFG0);
 712 }
 713
 714 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 715 {
 716         void __iomem *base = phy->regs;
 717         u32 val;
 718
 719         val = readl_relaxed(base + UTMIP_TX_CFG0);
 720         val &= ~UTMIP_HS_DISCON_DISABLE;
 721         writel_relaxed(val, base + UTMIP_TX_CFG0);
 722 }
 723
 724 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 725                                    enum tegra_usb_phy_port_speed port_speed)
 726 {
 727         void __iomem *base = phy->regs;
 728         u32 val;
 729
 730         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 731         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 732         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 733                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 734         else
 735                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 736         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 737         usleep_range(1, 10);
 738
 739         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 740         val |= UTMIP_DPDM_OBSERVE;
 741         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 742         usleep_range(10, 100);
 743 }
 744
 745 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 746 {
 747         void __iomem *base = phy->regs;
 748         u32 val;
 749
 750         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 751         val &= ~UTMIP_DPDM_OBSERVE;
 752         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 753         usleep_range(10, 100);
 754 }
 755
 756 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 757 {
 758         void __iomem *base = phy->regs;
 759         u32 val;
 760         int err;
 761
 762         gpiod_set_value_cansleep(phy->reset_gpio, 1);
 763
 764         err = clk_prepare_enable(phy->clk);
 765         if (err)
 766                 return err;
 767
 768         usleep_range(5000, 6000);
 769
 770         gpiod_set_value_cansleep(phy->reset_gpio, 0);
 771
 772         usleep_range(1000, 2000);
 773
 774         val = readl_relaxed(base + USB_SUSP_CTRL);
 775         val |= UHSIC_RESET;
 776         writel_relaxed(val, base + USB_SUSP_CTRL);
 777
 778         val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
 779         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 780         writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
 781
 782         val = readl_relaxed(base + USB_SUSP_CTRL);
 783         val |= ULPI_PHY_ENABLE;
 784         writel_relaxed(val, base + USB_SUSP_CTRL);
 785
 786         val = 0;
 787         writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
 788
 789         val |= ULPI_DATA_TRIMMER_SEL(4);
 790         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 791         val |= ULPI_DIR_TRIMMER_SEL(4);
 792         writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
 793         usleep_range(10, 100);
 794
 795         val |= ULPI_DATA_TRIMMER_LOAD;
 796         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 797         val |= ULPI_DIR_TRIMMER_LOAD;
 798         writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
 799
 800         /* Fix VbusInvalid due to floating VBUS */
 801         err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 802         if (err) {
 803                 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
 804                 goto disable_clk;
 805         }
 806
 807         err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 808         if (err) {
 809                 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
 810                 goto disable_clk;
 811         }
 812
 813         val = readl_relaxed(base + USB_SUSP_CTRL);
 814         val |= USB_SUSP_CLR;
 815         writel_relaxed(val, base + USB_SUSP_CTRL);
 816         usleep_range(100, 1000);
 817
 818         val = readl_relaxed(base + USB_SUSP_CTRL);
 819         val &= ~USB_SUSP_CLR;
 820         writel_relaxed(val, base + USB_SUSP_CTRL);
 821
 822         return 0;
 823
 824 disable_clk:
 825         clk_disable_unprepare(phy->clk);
 826
 827         return err;
 828 }
 829
 830 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 831 {
 832         gpiod_set_value_cansleep(phy->reset_gpio, 1);
 833         usleep_range(5000, 6000);
 834         clk_disable_unprepare(phy->clk);
 835
 836         /*
 837          * Wakeup currently unimplemented for ULPI, thus PHY needs to be
 838          * force-resumed.
 839          */
 840         if (WARN_ON_ONCE(phy->wakeup_enabled)) {
 841                 ulpi_phy_power_on(phy);
 842                 return -EOPNOTSUPP;
 843         }
 844
 845         return 0;
 846 }
 847
 848 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 849 {
 850         int err;
 851
 852         if (phy->powered_on)
 853                 return 0;
 854
 855         if (phy->is_ulpi_phy)
 856                 err = ulpi_phy_power_on(phy);
 857         else
 858                 err = utmi_phy_power_on(phy);
 859         if (err)
 860                 return err;
 861
 862         phy->powered_on = true;
 863
 864         /* Let PHY settle down */
 865         usleep_range(2000, 2500);
 866
 867         return 0;
 868 }
 869
 870 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 871 {
 872         int err;
 873
 874         if (!phy->powered_on)
 875                 return 0;
 876
 877         if (phy->is_ulpi_phy)
 878                 err = ulpi_phy_power_off(phy);
 879         else
 880                 err = utmi_phy_power_off(phy);
 881         if (err)
 882                 return err;
 883
 884         phy->powered_on = false;
 885
 886         return 0;
 887 }
 888
 889 static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
 890 {
 891         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 892
 893         if (WARN_ON(!phy->freq))
 894                 return;
 895
 896         tegra_usb_phy_power_off(phy);
 897
 898         if (!phy->is_ulpi_phy)
 899                 utmip_pad_close(phy);
 900
 901         regulator_disable(phy->vbus);
 902         clk_disable_unprepare(phy->pll_u);
 903
 904         phy->freq = NULL;
 905 }
 906
 907 static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable)
 908 {
 909         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 910
 911         phy->wakeup_enabled = enable;
 912
 913         return 0;
 914 }
 915
 916 static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
 917 {
 918         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 919
 920         if (WARN_ON(!phy->freq))
 921                 return -EINVAL;
 922
 923         if (suspend)
 924                 return tegra_usb_phy_power_off(phy);
 925         else
 926                 return tegra_usb_phy_power_on(phy);
 927 }
 928
 929 static int tegra_usb_phy_init(struct usb_phy *u_phy)
 930 {
 931         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 932         unsigned long parent_rate;
 933         unsigned int i;
 934         int err;
 935
 936         if (WARN_ON(phy->freq))
 937                 return 0;
 938
 939         err = clk_prepare_enable(phy->pll_u);
 940         if (err)
 941                 return err;
 942
 943         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 944         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 945                 if (tegra_freq_table[i].freq == parent_rate) {
 946                         phy->freq = &tegra_freq_table[i];
 947                         break;
 948                 }
 949         }
 950         if (!phy->freq) {
 951                 dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
 952                         parent_rate);
 953                 err = -EINVAL;
 954                 goto disable_clk;
 955         }
 956
 957         err = regulator_enable(phy->vbus);
 958         if (err) {
 959                 dev_err(phy->u_phy.dev,
 960                         "Failed to enable USB VBUS regulator: %d\n", err);
 961                 goto disable_clk;
 962         }
 963
 964         if (!phy->is_ulpi_phy) {
 965                 err = utmip_pad_open(phy);
 966                 if (err)
 967                         goto disable_vbus;
 968         }
 969
 970         err = tegra_usb_phy_power_on(phy);
 971         if (err)
 972                 goto close_phy;
 973
 974         return 0;
 975
 976 close_phy:
 977         if (!phy->is_ulpi_phy)
 978                 utmip_pad_close(phy);
 979
 980 disable_vbus:
 981         regulator_disable(phy->vbus);
 982
 983 disable_clk:
 984         clk_disable_unprepare(phy->pll_u);
 985
 986         phy->freq = NULL;
 987
 988         return err;
 989 }
 990
 991 void tegra_usb_phy_preresume(struct usb_phy *u_phy)
 992 {
 993         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 994
 995         if (!phy->is_ulpi_phy)
 996                 utmi_phy_preresume(phy);
 997 }
 998 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 999
1000 void tegra_usb_phy_postresume(struct usb_phy *u_phy)
1001 {
1002         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1003
1004         if (!phy->is_ulpi_phy)
1005                 utmi_phy_postresume(phy);
1006 }
1007 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
1008
1009 void tegra_ehci_phy_restore_start(struct usb_phy *u_phy,
1010                                   enum tegra_usb_phy_port_speed port_speed)
1011 {
1012         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1013
1014         if (!phy->is_ulpi_phy)
1015                 utmi_phy_restore_start(phy, port_speed);
1016 }
1017 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
1018
1019 void tegra_ehci_phy_restore_end(struct usb_phy *u_phy)
1020 {
1021         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1022
1023         if (!phy->is_ulpi_phy)
1024                 utmi_phy_restore_end(phy);
1025 }
1026 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
1027
1028 static int read_utmi_param(struct platform_device *pdev, const char *param,
1029                            u8 *dest)
1030 {
1031         u32 value;
1032         int err;
1033
1034         err = of_property_read_u32(pdev->dev.of_node, param, &value);
1035         if (err)
1036                 dev_err(&pdev->dev,
1037                         "Failed to read USB UTMI parameter %s: %d\n",
1038                         param, err);
1039         else
1040                 *dest = value;
1041
1042         return err;
1043 }
1044
1045 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
1046                           struct platform_device *pdev)
1047 {
1048         struct tegra_utmip_config *config;
1049         struct resource *res;
1050         int err;
1051
1052         tegra_phy->is_ulpi_phy = false;
1053
1054         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1055         if (!res) {
1056                 dev_err(&pdev->dev, "Failed to get UTMI pad regs\n");
1057                 return  -ENXIO;
1058         }
1059
1060         /*
1061          * Note that UTMI pad registers are shared by all PHYs, therefore
1062          * devm_platform_ioremap_resource() can't be used here.
1063          */
1064         tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
1065                                            resource_size(res));
1066         if (!tegra_phy->pad_regs) {
1067                 dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
1068                 return -ENOMEM;
1069         }
1070
1071         tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
1072                                          GFP_KERNEL);
1073         if (!tegra_phy->config)
1074                 return -ENOMEM;
1075
1076         config = tegra_phy->config;
1077
1078         err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
1079                               &config->hssync_start_delay);
1080         if (err)
1081                 return err;
1082
1083         err = read_utmi_param(pdev, "nvidia,elastic-limit",
1084                               &config->elastic_limit);
1085         if (err)
1086                 return err;
1087
1088         err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
1089                               &config->idle_wait_delay);
1090         if (err)
1091                 return err;
1092
1093         err = read_utmi_param(pdev, "nvidia,term-range-adj",
1094                               &config->term_range_adj);
1095         if (err)
1096                 return err;
1097
1098         err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
1099                               &config->xcvr_lsfslew);
1100         if (err)
1101                 return err;
1102
1103         err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
1104                               &config->xcvr_lsrslew);
1105         if (err)
1106                 return err;
1107
1108         if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
1109                 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1110                                       &config->xcvr_hsslew);
1111                 if (err)
1112                         return err;
1113
1114                 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1115                                       &config->hssquelch_level);
1116                 if (err)
1117                         return err;
1118
1119                 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1120                                       &config->hsdiscon_level);
1121                 if (err)
1122                         return err;
1123         }
1124
1125         config->xcvr_setup_use_fuses = of_property_read_bool(
1126                 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
1127
1128         if (!config->xcvr_setup_use_fuses) {
1129                 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1130                                       &config->xcvr_setup);
1131                 if (err)
1132                         return err;
1133         }
1134
1135         return 0;
1136 }
1137
1138 static const struct tegra_phy_soc_config tegra20_soc_config = {
1139         .utmi_pll_config_in_car_module = false,
1140         .has_hostpc = false,
1141         .requires_usbmode_setup = false,
1142         .requires_extra_tuning_parameters = false,
1143 };
1144
1145 static const struct tegra_phy_soc_config tegra30_soc_config = {
1146         .utmi_pll_config_in_car_module = true,
1147         .has_hostpc = true,
1148         .requires_usbmode_setup = true,
1149         .requires_extra_tuning_parameters = true,
1150 };
1151
1152 static const struct of_device_id tegra_usb_phy_id_table[] = {
1153         { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
1154         { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
1155         { },
1156 };
1157 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
1158
1159 static int tegra_usb_phy_probe(struct platform_device *pdev)
1160 {
1161         struct device_node *np = pdev->dev.of_node;
1162         struct tegra_usb_phy *tegra_phy;
1163         enum usb_phy_interface phy_type;
1164         struct reset_control *reset;
1165         struct gpio_desc *gpiod;
1166         struct resource *res;
1167         struct usb_phy *phy;
1168         int err;
1169
1170         tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
1171         if (!tegra_phy)
1172                 return -ENOMEM;
1173
1174         tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
1175
1176         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1177         if (!res) {
1178                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1179                 return  -ENXIO;
1180         }
1181
1182         /*
1183          * Note that PHY and USB controller are using shared registers,
1184          * therefore devm_platform_ioremap_resource() can't be used here.
1185          */
1186         tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1187                                        resource_size(res));
1188         if (!tegra_phy->regs) {
1189                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1190                 return -ENOMEM;
1191         }
1192
1193         tegra_phy->is_legacy_phy =
1194                 of_property_read_bool(np, "nvidia,has-legacy-mode");
1195
1196         if (of_find_property(np, "dr_mode", NULL))
1197                 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1198         else
1199                 tegra_phy->mode = USB_DR_MODE_HOST;
1200
1201         if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1202                 dev_err(&pdev->dev, "dr_mode is invalid\n");
1203                 return -EINVAL;
1204         }
1205
1206         /* On some boards, the VBUS regulator doesn't need to be controlled */
1207         tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1208         if (IS_ERR(tegra_phy->vbus))
1209                 return PTR_ERR(tegra_phy->vbus);
1210
1211         tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
1212         err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
1213         if (err) {
1214                 dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
1215                 return err;
1216         }
1217
1218         phy_type = of_usb_get_phy_mode(np);
1219         switch (phy_type) {
1220         case USBPHY_INTERFACE_MODE_UTMI:
1221                 err = utmi_phy_probe(tegra_phy, pdev);
1222                 if (err)
1223                         return err;
1224
1225                 tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
1226                 err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
1227                 if (err) {
1228                         dev_err(&pdev->dev,
1229                                 "Failed to get UTMIP pad clock: %d\n", err);
1230                         return err;
1231                 }
1232
1233                 reset = devm_reset_control_get_optional_shared(&pdev->dev,
1234                                                                "utmi-pads");
1235                 err = PTR_ERR_OR_ZERO(reset);
1236                 if (err) {
1237                         dev_err(&pdev->dev,
1238                                 "Failed to get UTMI-pads reset: %d\n", err);
1239                         return err;
1240                 }
1241                 tegra_phy->pad_rst = reset;
1242                 break;
1243
1244         case USBPHY_INTERFACE_MODE_ULPI:
1245                 tegra_phy->is_ulpi_phy = true;
1246
1247                 tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
1248                 err = PTR_ERR_OR_ZERO(tegra_phy->clk);
1249                 if (err) {
1250                         dev_err(&pdev->dev,
1251                                 "Failed to get ULPI clock: %d\n", err);
1252                         return err;
1253                 }
1254
1255                 gpiod = devm_gpiod_get_from_of_node(&pdev->dev, np,
1256                                                     "nvidia,phy-reset-gpio",
1257                                                     0, GPIOD_OUT_HIGH,
1258                                                     "ulpi_phy_reset_b");
1259                 err = PTR_ERR_OR_ZERO(gpiod);
1260                 if (err) {
1261                         dev_err(&pdev->dev,
1262                                 "Request failed for reset GPIO: %d\n", err);
1263                         return err;
1264                 }
1265                 tegra_phy->reset_gpio = gpiod;
1266
1267                 phy = devm_otg_ulpi_create(&pdev->dev,
1268                                            &ulpi_viewport_access_ops, 0);
1269                 if (!phy) {
1270                         dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
1271                         return -ENOMEM;
1272                 }
1273
1274                 tegra_phy->ulpi = phy;
1275                 tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
1276                 break;
1277
1278         default:
1279                 dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1280                         phy_type);
1281                 return -EINVAL;
1282         }
1283
1284         tegra_phy->u_phy.dev = &pdev->dev;
1285         tegra_phy->u_phy.init = tegra_usb_phy_init;
1286         tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
1287         tegra_phy->u_phy.set_wakeup = tegra_usb_phy_set_wakeup;
1288         tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
1289
1290         platform_set_drvdata(pdev, tegra_phy);
1291
1292         return usb_add_phy_dev(&tegra_phy->u_phy);
1293 }
1294
1295 static int tegra_usb_phy_remove(struct platform_device *pdev)
1296 {
1297         struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1298
1299         usb_remove_phy(&tegra_phy->u_phy);
1300
1301         return 0;
1302 }
1303
1304 static struct platform_driver tegra_usb_phy_driver = {
1305         .probe          = tegra_usb_phy_probe,
1306         .remove         = tegra_usb_phy_remove,
1307         .driver         = {
1308                 .name   = "tegra-phy",
1309                 .of_match_table = tegra_usb_phy_id_table,
1310         },
1311 };
1312 module_platform_driver(tegra_usb_phy_driver);
1313
1314 MODULE_DESCRIPTION("Tegra USB PHY driver");
1315 MODULE_LICENSE("GPL v2");