drivers/gpu/drm/omapdrm/omap_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   4  * Author: Rob Clark <[email protected]>
   5  */
   6
   7 #include <drm/drm_atomic.h>
   8 #include <drm/drm_atomic_helper.h>
   9 #include <drm/drm_crtc.h>
  10 #include <drm/drm_mode.h>
  11 #include <drm/drm_plane_helper.h>
  12 #include <linux/math64.h>
  13
  14 #include "omap_drv.h"
  15
  16 #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
  17
  18 struct omap_crtc_state {
  19         /* Must be first. */
  20         struct drm_crtc_state base;
  21         /* Shadow values for legacy userspace support. */
  22         unsigned int rotation;
  23         unsigned int zpos;
  24         bool manually_updated;
  25 };
  26
  27 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  28
  29 struct omap_crtc {
  30         struct drm_crtc base;
  31
  32         const char *name;
  33         struct omap_drm_pipeline *pipe;
  34         enum omap_channel channel;
  35
  36         struct videomode vm;
  37
  38         bool ignore_digit_sync_lost;
  39
  40         bool enabled;
  41         bool pending;
  42         wait_queue_head_t pending_wait;
  43         struct drm_pending_vblank_event *event;
  44         struct delayed_work update_work;
  45
  46         void (*framedone_handler)(void *);
  47         void *framedone_handler_data;
  48 };
  49
  50 /* -----------------------------------------------------------------------------
  51  * Helper Functions
  52  */
  53
  54 struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
  55 {
  56         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  57         return &omap_crtc->vm;
  58 }
  59
  60 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  61 {
  62         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  63         return omap_crtc->channel;
  64 }
  65
  66 static bool omap_crtc_is_pending(struct drm_crtc *crtc)
  67 {
  68         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  69         unsigned long flags;
  70         bool pending;
  71
  72         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  73         pending = omap_crtc->pending;
  74         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  75
  76         return pending;
  77 }
  78
  79 int omap_crtc_wait_pending(struct drm_crtc *crtc)
  80 {
  81         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  82
  83         /*
  84          * Timeout is set to a "sufficiently" high value, which should cover
  85          * a single frame refresh even on slower displays.
  86          */
  87         return wait_event_timeout(omap_crtc->pending_wait,
  88                                   !omap_crtc_is_pending(crtc),
  89                                   msecs_to_jiffies(250));
  90 }
  91
  92 /* -----------------------------------------------------------------------------
  93  * DSS Manager Functions
  94  */
  95
  96 /*
  97  * Manager-ops, callbacks from output when they need to configure
  98  * the upstream part of the video pipe.
  99  */
 100
 101 static void omap_crtc_dss_start_update(struct omap_drm_private *priv,
 102                                        enum omap_channel channel)
 103 {
 104         priv->dispc_ops->mgr_enable(priv->dispc, channel, true);
 105 }
 106
 107 /* Called only from the encoder enable/disable and suspend/resume handlers. */
 108 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
 109 {
 110         struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
 111         struct drm_device *dev = crtc->dev;
 112         struct omap_drm_private *priv = dev->dev_private;
 113         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 114         enum omap_channel channel = omap_crtc->channel;
 115         struct omap_irq_wait *wait;
 116         u32 framedone_irq, vsync_irq;
 117         int ret;
 118
 119         if (WARN_ON(omap_crtc->enabled == enable))
 120                 return;
 121
 122         if (omap_state->manually_updated) {
 123                 omap_irq_enable_framedone(crtc, enable);
 124                 omap_crtc->enabled = enable;
 125                 return;
 126         }
 127
 128         if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) {
 129                 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
 130                 omap_crtc->enabled = enable;
 131                 return;
 132         }
 133
 134         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 135                 /*
 136                  * Digit output produces some sync lost interrupts during the
 137                  * first frame when enabling, so we need to ignore those.
 138                  */
 139                 omap_crtc->ignore_digit_sync_lost = true;
 140         }
 141
 142         framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc,
 143                                                                channel);
 144         vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel);
 145
 146         if (enable) {
 147                 wait = omap_irq_wait_init(dev, vsync_irq, 1);
 148         } else {
 149                 /*
 150                  * When we disable the digit output, we need to wait for
 151                  * FRAMEDONE to know that DISPC has finished with the output.
 152                  *
 153                  * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
 154                  * that case we need to use vsync interrupt, and wait for both
 155                  * even and odd frames.
 156                  */
 157
 158                 if (framedone_irq)
 159                         wait = omap_irq_wait_init(dev, framedone_irq, 1);
 160                 else
 161                         wait = omap_irq_wait_init(dev, vsync_irq, 2);
 162         }
 163
 164         priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
 165         omap_crtc->enabled = enable;
 166
 167         ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
 168         if (ret) {
 169                 dev_err(dev->dev, "%s: timeout waiting for %s\n",
 170                                 omap_crtc->name, enable ? "enable" : "disable");
 171         }
 172
 173         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 174                 omap_crtc->ignore_digit_sync_lost = false;
 175                 /* make sure the irq handler sees the value above */
 176                 mb();
 177         }
 178 }
 179
 180
 181 static int omap_crtc_dss_enable(struct omap_drm_private *priv,
 182                                 enum omap_channel channel)
 183 {
 184         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 185         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 186
 187         priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel,
 188                                          &omap_crtc->vm);
 189         omap_crtc_set_enabled(&omap_crtc->base, true);
 190
 191         return 0;
 192 }
 193
 194 static void omap_crtc_dss_disable(struct omap_drm_private *priv,
 195                                   enum omap_channel channel)
 196 {
 197         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 198         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 199
 200         omap_crtc_set_enabled(&omap_crtc->base, false);
 201 }
 202
 203 static void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
 204                 enum omap_channel channel,
 205                 const struct videomode *vm)
 206 {
 207         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 208         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 209
 210         DBG("%s", omap_crtc->name);
 211         omap_crtc->vm = *vm;
 212 }
 213
 214 static void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
 215                 enum omap_channel channel,
 216                 const struct dss_lcd_mgr_config *config)
 217 {
 218         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 219         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 220
 221         DBG("%s", omap_crtc->name);
 222         priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel,
 223                                             config);
 224 }
 225
 226 static int omap_crtc_dss_register_framedone(
 227                 struct omap_drm_private *priv, enum omap_channel channel,
 228                 void (*handler)(void *), void *data)
 229 {
 230         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 231         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 232         struct drm_device *dev = omap_crtc->base.dev;
 233
 234         if (omap_crtc->framedone_handler)
 235                 return -EBUSY;
 236
 237         dev_dbg(dev->dev, "register framedone %s", omap_crtc->name);
 238
 239         omap_crtc->framedone_handler = handler;
 240         omap_crtc->framedone_handler_data = data;
 241
 242         return 0;
 243 }
 244
 245 static void omap_crtc_dss_unregister_framedone(
 246                 struct omap_drm_private *priv, enum omap_channel channel,
 247                 void (*handler)(void *), void *data)
 248 {
 249         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 250         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 251         struct drm_device *dev = omap_crtc->base.dev;
 252
 253         dev_dbg(dev->dev, "unregister framedone %s", omap_crtc->name);
 254
 255         WARN_ON(omap_crtc->framedone_handler != handler);
 256         WARN_ON(omap_crtc->framedone_handler_data != data);
 257
 258         omap_crtc->framedone_handler = NULL;
 259         omap_crtc->framedone_handler_data = NULL;
 260 }
 261
 262 static const struct dss_mgr_ops mgr_ops = {
 263         .start_update = omap_crtc_dss_start_update,
 264         .enable = omap_crtc_dss_enable,
 265         .disable = omap_crtc_dss_disable,
 266         .set_timings = omap_crtc_dss_set_timings,
 267         .set_lcd_config = omap_crtc_dss_set_lcd_config,
 268         .register_framedone_handler = omap_crtc_dss_register_framedone,
 269         .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
 270 };
 271
 272 /* -----------------------------------------------------------------------------
 273  * Setup, Flush and Page Flip
 274  */
 275
 276 void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)
 277 {
 278         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 279
 280         if (omap_crtc->ignore_digit_sync_lost) {
 281                 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
 282                 if (!irqstatus)
 283                         return;
 284         }
 285
 286         DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
 287 }
 288
 289 void omap_crtc_vblank_irq(struct drm_crtc *crtc)
 290 {
 291         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 292         struct drm_device *dev = omap_crtc->base.dev;
 293         struct omap_drm_private *priv = dev->dev_private;
 294         bool pending;
 295
 296         spin_lock(&crtc->dev->event_lock);
 297         /*
 298          * If the dispc is busy we're racing the flush operation. Try again on
 299          * the next vblank interrupt.
 300          */
 301         if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) {
 302                 spin_unlock(&crtc->dev->event_lock);
 303                 return;
 304         }
 305
 306         /* Send the vblank event if one has been requested. */
 307         if (omap_crtc->event) {
 308                 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
 309                 omap_crtc->event = NULL;
 310         }
 311
 312         pending = omap_crtc->pending;
 313         omap_crtc->pending = false;
 314         spin_unlock(&crtc->dev->event_lock);
 315
 316         if (pending)
 317                 drm_crtc_vblank_put(crtc);
 318
 319         /* Wake up omap_atomic_complete. */
 320         wake_up(&omap_crtc->pending_wait);
 321
 322         DBG("%s: apply done", omap_crtc->name);
 323 }
 324
 325 void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus)
 326 {
 327         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 328
 329         if (!omap_crtc->framedone_handler)
 330                 return;
 331
 332         omap_crtc->framedone_handler(omap_crtc->framedone_handler_data);
 333
 334         spin_lock(&crtc->dev->event_lock);
 335         /* Send the vblank event if one has been requested. */
 336         if (omap_crtc->event) {
 337                 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
 338                 omap_crtc->event = NULL;
 339         }
 340         omap_crtc->pending = false;
 341         spin_unlock(&crtc->dev->event_lock);
 342
 343         /* Wake up omap_atomic_complete. */
 344         wake_up(&omap_crtc->pending_wait);
 345 }
 346
 347 void omap_crtc_flush(struct drm_crtc *crtc)
 348 {
 349         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 350         struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
 351
 352         if (!omap_state->manually_updated)
 353                 return;
 354
 355         if (!delayed_work_pending(&omap_crtc->update_work))
 356                 schedule_delayed_work(&omap_crtc->update_work, 0);
 357 }
 358
 359 static void omap_crtc_manual_display_update(struct work_struct *data)
 360 {
 361         struct omap_crtc *omap_crtc =
 362                         container_of(data, struct omap_crtc, update_work.work);
 363         struct drm_display_mode *mode = &omap_crtc->pipe->crtc->mode;
 364         struct omap_dss_device *dssdev = omap_crtc->pipe->output->next;
 365         struct drm_device *dev = omap_crtc->base.dev;
 366         const struct omap_dss_driver *dssdrv;
 367         int ret;
 368
 369         if (!dssdev) {
 370                 dev_err_once(dev->dev, "missing display dssdev!");
 371                 return;
 372         }
 373
 374         dssdrv = dssdev->driver;
 375         if (!dssdrv || !dssdrv->update) {
 376                 dev_err_once(dev->dev, "missing or incorrect dssdrv!");
 377                 return;
 378         }
 379
 380         if (dssdrv->sync)
 381                 dssdrv->sync(dssdev);
 382
 383         ret = dssdrv->update(dssdev, 0, 0, mode->hdisplay, mode->vdisplay);
 384         if (ret < 0) {
 385                 spin_lock_irq(&dev->event_lock);
 386                 omap_crtc->pending = false;
 387                 spin_unlock_irq(&dev->event_lock);
 388                 wake_up(&omap_crtc->pending_wait);
 389         }
 390 }
 391
 392 static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
 393 {
 394         struct omap_drm_private *priv = crtc->dev->dev_private;
 395         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 396         struct omap_overlay_manager_info info;
 397
 398         memset(&info, 0, sizeof(info));
 399
 400         info.default_color = 0x000000;
 401         info.trans_enabled = false;
 402         info.partial_alpha_enabled = false;
 403         info.cpr_enable = false;
 404
 405         priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info);
 406 }
 407
 408 /* -----------------------------------------------------------------------------
 409  * CRTC Functions
 410  */
 411
 412 static void omap_crtc_destroy(struct drm_crtc *crtc)
 413 {
 414         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 415
 416         DBG("%s", omap_crtc->name);
 417
 418         drm_crtc_cleanup(crtc);
 419
 420         kfree(omap_crtc);
 421 }
 422
 423 static void omap_crtc_arm_event(struct drm_crtc *crtc)
 424 {
 425         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 426
 427         WARN_ON(omap_crtc->pending);
 428         omap_crtc->pending = true;
 429
 430         if (crtc->state->event) {
 431                 omap_crtc->event = crtc->state->event;
 432                 crtc->state->event = NULL;
 433         }
 434 }
 435
 436 static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
 437                                     struct drm_crtc_state *old_state)
 438 {
 439         struct omap_drm_private *priv = crtc->dev->dev_private;
 440         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 441         struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
 442         int ret;
 443
 444         DBG("%s", omap_crtc->name);
 445
 446         priv->dispc_ops->runtime_get(priv->dispc);
 447
 448         /* manual updated display will not trigger vsync irq */
 449         if (omap_state->manually_updated)
 450                 return;
 451
 452         spin_lock_irq(&crtc->dev->event_lock);
 453         drm_crtc_vblank_on(crtc);
 454         ret = drm_crtc_vblank_get(crtc);
 455         WARN_ON(ret != 0);
 456
 457         omap_crtc_arm_event(crtc);
 458         spin_unlock_irq(&crtc->dev->event_lock);
 459 }
 460
 461 static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
 462                                      struct drm_crtc_state *old_state)
 463 {
 464         struct omap_drm_private *priv = crtc->dev->dev_private;
 465         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 466         struct drm_device *dev = crtc->dev;
 467
 468         DBG("%s", omap_crtc->name);
 469
 470         spin_lock_irq(&crtc->dev->event_lock);
 471         if (crtc->state->event) {
 472                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 473                 crtc->state->event = NULL;
 474         }
 475         spin_unlock_irq(&crtc->dev->event_lock);
 476
 477         cancel_delayed_work(&omap_crtc->update_work);
 478
 479         if (!omap_crtc_wait_pending(crtc))
 480                 dev_warn(dev->dev, "manual display update did not finish!");
 481
 482         drm_crtc_vblank_off(crtc);
 483
 484         priv->dispc_ops->runtime_put(priv->dispc);
 485 }
 486
 487 static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
 488                                         const struct drm_display_mode *mode)
 489 {
 490         struct omap_drm_private *priv = crtc->dev->dev_private;
 491         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 492         struct videomode vm = {0};
 493         int r;
 494
 495         drm_display_mode_to_videomode(mode, &vm);
 496
 497         /*
 498          * DSI might not call this, since the supplied mode is not a
 499          * valid DISPC mode. DSI will calculate and configure the
 500          * proper DISPC mode later.
 501          */
 502         if (omap_crtc->pipe->output->next == NULL ||
 503             omap_crtc->pipe->output->next->type != OMAP_DISPLAY_TYPE_DSI) {
 504                 r = priv->dispc_ops->mgr_check_timings(priv->dispc,
 505                                                        omap_crtc->channel,
 506                                                        &vm);
 507                 if (r)
 508                         return r;
 509         }
 510
 511         /* Check for bandwidth limit */
 512         if (priv->max_bandwidth) {
 513                 /*
 514                  * Estimation for the bandwidth need of a given mode with one
 515                  * full screen plane:
 516                  * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal))
 517                  *                                      ^^ Refresh rate ^^
 518                  *
 519                  * The interlaced mode is taken into account by using the
 520                  * pixelclock in the calculation.
 521                  *
 522                  * The equation is rearranged for 64bit arithmetic.
 523                  */
 524                 uint64_t bandwidth = mode->clock * 1000;
 525                 unsigned int bpp = 4;
 526
 527                 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
 528                 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
 529
 530                 /*
 531                  * Reject modes which would need more bandwidth if used with one
 532                  * full resolution plane (most common use case).
 533                  */
 534                 if (priv->max_bandwidth < bandwidth)
 535                         return MODE_BAD;
 536         }
 537
 538         return MODE_OK;
 539 }
 540
 541 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
 542 {
 543         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 544         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 545
 546         DBG("%s: set mode: " DRM_MODE_FMT,
 547             omap_crtc->name, DRM_MODE_ARG(mode));
 548
 549         drm_display_mode_to_videomode(mode, &omap_crtc->vm);
 550 }
 551
 552 static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc)
 553 {
 554         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 555         struct omap_dss_device *display = omap_crtc->pipe->output->next;
 556
 557         if (!display)
 558                 return false;
 559
 560         if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
 561                 DBG("detected manually updated display!");
 562                 return true;
 563         }
 564
 565         return false;
 566 }
 567
 568 static int omap_crtc_atomic_check(struct drm_crtc *crtc,
 569                                 struct drm_crtc_state *state)
 570 {
 571         struct drm_plane_state *pri_state;
 572
 573         if (state->color_mgmt_changed && state->gamma_lut) {
 574                 unsigned int length = state->gamma_lut->length /
 575                         sizeof(struct drm_color_lut);
 576
 577                 if (length < 2)
 578                         return -EINVAL;
 579         }
 580
 581         pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary);
 582         if (pri_state) {
 583                 struct omap_crtc_state *omap_crtc_state =
 584                         to_omap_crtc_state(state);
 585
 586                 /* Mirror new values for zpos and rotation in omap_crtc_state */
 587                 omap_crtc_state->zpos = pri_state->zpos;
 588                 omap_crtc_state->rotation = pri_state->rotation;
 589
 590                 /* Check if this CRTC is for a manually updated display */
 591                 omap_crtc_state->manually_updated = omap_crtc_is_manually_updated(crtc);
 592         }
 593
 594         return 0;
 595 }
 596
 597 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
 598                                    struct drm_crtc_state *old_crtc_state)
 599 {
 600 }
 601
 602 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
 603                                    struct drm_crtc_state *old_crtc_state)
 604 {
 605         struct omap_drm_private *priv = crtc->dev->dev_private;
 606         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 607         struct omap_crtc_state *omap_crtc_state = to_omap_crtc_state(crtc->state);
 608         int ret;
 609
 610         if (crtc->state->color_mgmt_changed) {
 611                 struct drm_color_lut *lut = NULL;
 612                 unsigned int length = 0;
 613
 614                 if (crtc->state->gamma_lut) {
 615                         lut = (struct drm_color_lut *)
 616                                 crtc->state->gamma_lut->data;
 617                         length = crtc->state->gamma_lut->length /
 618                                 sizeof(*lut);
 619                 }
 620                 priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel,
 621                                                lut, length);
 622         }
 623
 624         omap_crtc_write_crtc_properties(crtc);
 625
 626         /* Only flush the CRTC if it is currently enabled. */
 627         if (!omap_crtc->enabled)
 628                 return;
 629
 630         DBG("%s: GO", omap_crtc->name);
 631
 632         if (omap_crtc_state->manually_updated) {
 633                 /* send new image for page flips and modeset changes */
 634                 spin_lock_irq(&crtc->dev->event_lock);
 635                 omap_crtc_flush(crtc);
 636                 omap_crtc_arm_event(crtc);
 637                 spin_unlock_irq(&crtc->dev->event_lock);
 638                 return;
 639         }
 640
 641         ret = drm_crtc_vblank_get(crtc);
 642         WARN_ON(ret != 0);
 643
 644         spin_lock_irq(&crtc->dev->event_lock);
 645         priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel);
 646         omap_crtc_arm_event(crtc);
 647         spin_unlock_irq(&crtc->dev->event_lock);
 648 }
 649
 650 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
 651                                          struct drm_crtc_state *state,
 652                                          struct drm_property *property,
 653                                          u64 val)
 654 {
 655         struct omap_drm_private *priv = crtc->dev->dev_private;
 656         struct drm_plane_state *plane_state;
 657
 658         /*
 659          * Delegate property set to the primary plane. Get the plane state and
 660          * set the property directly, the shadow copy will be assigned in the
 661          * omap_crtc_atomic_check callback. This way updates to plane state will
 662          * always be mirrored in the crtc state correctly.
 663          */
 664         plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
 665         if (IS_ERR(plane_state))
 666                 return PTR_ERR(plane_state);
 667
 668         if (property == crtc->primary->rotation_property)
 669                 plane_state->rotation = val;
 670         else if (property == priv->zorder_prop)
 671                 plane_state->zpos = val;
 672         else
 673                 return -EINVAL;
 674
 675         return 0;
 676 }
 677
 678 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
 679                                          const struct drm_crtc_state *state,
 680                                          struct drm_property *property,
 681                                          u64 *val)
 682 {
 683         struct omap_drm_private *priv = crtc->dev->dev_private;
 684         struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
 685
 686         if (property == crtc->primary->rotation_property)
 687                 *val = omap_state->rotation;
 688         else if (property == priv->zorder_prop)
 689                 *val = omap_state->zpos;
 690         else
 691                 return -EINVAL;
 692
 693         return 0;
 694 }
 695
 696 static void omap_crtc_reset(struct drm_crtc *crtc)
 697 {
 698         if (crtc->state)
 699                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 700
 701         kfree(crtc->state);
 702         crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL);
 703
 704         if (crtc->state)
 705                 crtc->state->crtc = crtc;
 706 }
 707
 708 static struct drm_crtc_state *
 709 omap_crtc_duplicate_state(struct drm_crtc *crtc)
 710 {
 711         struct omap_crtc_state *state, *current_state;
 712
 713         if (WARN_ON(!crtc->state))
 714                 return NULL;
 715
 716         current_state = to_omap_crtc_state(crtc->state);
 717
 718         state = kmalloc(sizeof(*state), GFP_KERNEL);
 719         if (!state)
 720                 return NULL;
 721
 722         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 723
 724         state->zpos = current_state->zpos;
 725         state->rotation = current_state->rotation;
 726         state->manually_updated = current_state->manually_updated;
 727
 728         return &state->base;
 729 }
 730
 731 static const struct drm_crtc_funcs omap_crtc_funcs = {
 732         .reset = omap_crtc_reset,
 733         .set_config = drm_atomic_helper_set_config,
 734         .destroy = omap_crtc_destroy,
 735         .page_flip = drm_atomic_helper_page_flip,
 736         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 737         .atomic_duplicate_state = omap_crtc_duplicate_state,
 738         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 739         .atomic_set_property = omap_crtc_atomic_set_property,
 740         .atomic_get_property = omap_crtc_atomic_get_property,
 741         .enable_vblank = omap_irq_enable_vblank,
 742         .disable_vblank = omap_irq_disable_vblank,
 743 };
 744
 745 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
 746         .mode_set_nofb = omap_crtc_mode_set_nofb,
 747         .atomic_check = omap_crtc_atomic_check,
 748         .atomic_begin = omap_crtc_atomic_begin,
 749         .atomic_flush = omap_crtc_atomic_flush,
 750         .atomic_enable = omap_crtc_atomic_enable,
 751         .atomic_disable = omap_crtc_atomic_disable,
 752         .mode_valid = omap_crtc_mode_valid,
 753 };
 754
 755 /* -----------------------------------------------------------------------------
 756  * Init and Cleanup
 757  */
 758
 759 static const char *channel_names[] = {
 760         [OMAP_DSS_CHANNEL_LCD] = "lcd",
 761         [OMAP_DSS_CHANNEL_DIGIT] = "tv",
 762         [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
 763         [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
 764 };
 765
 766 void omap_crtc_pre_init(struct omap_drm_private *priv)
 767 {
 768         dss_install_mgr_ops(priv->dss, &mgr_ops, priv);
 769 }
 770
 771 void omap_crtc_pre_uninit(struct omap_drm_private *priv)
 772 {
 773         dss_uninstall_mgr_ops(priv->dss);
 774 }
 775
 776 /* initialize crtc */
 777 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
 778                                 struct omap_drm_pipeline *pipe,
 779                                 struct drm_plane *plane)
 780 {
 781         struct omap_drm_private *priv = dev->dev_private;
 782         struct drm_crtc *crtc = NULL;
 783         struct omap_crtc *omap_crtc;
 784         enum omap_channel channel;
 785         int ret;
 786
 787         channel = pipe->output->dispc_channel;
 788
 789         DBG("%s", channel_names[channel]);
 790
 791         omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
 792         if (!omap_crtc)
 793                 return ERR_PTR(-ENOMEM);
 794
 795         crtc = &omap_crtc->base;
 796
 797         init_waitqueue_head(&omap_crtc->pending_wait);
 798
 799         omap_crtc->pipe = pipe;
 800         omap_crtc->channel = channel;
 801         omap_crtc->name = channel_names[channel];
 802
 803         /*
 804          * We want to refresh manually updated displays from dirty callback,
 805          * which is called quite often (e.g. for each drawn line). This will
 806          * be used to do the display update asynchronously to avoid blocking
 807          * the rendering process and merges multiple dirty calls into one
 808          * update if they arrive very fast. We also call this function for
 809          * atomic display updates (e.g. for page flips), which means we do
 810          * not need extra locking. Atomic updates should be synchronous, but
 811          * need to wait for the framedone interrupt anyways.
 812          */
 813         INIT_DELAYED_WORK(&omap_crtc->update_work,
 814                           omap_crtc_manual_display_update);
 815
 816         ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
 817                                         &omap_crtc_funcs, NULL);
 818         if (ret < 0) {
 819                 dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
 820                         __func__, pipe->output->name);
 821                 kfree(omap_crtc);
 822                 return ERR_PTR(ret);
 823         }
 824
 825         drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
 826
 827         /* The dispc API adapts to what ever size, but the HW supports
 828          * 256 element gamma table for LCDs and 1024 element table for
 829          * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
 830          * tables so lets use that. Size of HW gamma table can be
 831          * extracted with dispc_mgr_gamma_size(). If it returns 0
 832          * gamma table is not supprted.
 833          */
 834         if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) {
 835                 unsigned int gamma_lut_size = 256;
 836
 837                 drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
 838                 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
 839         }
 840
 841         omap_plane_install_properties(crtc->primary, &crtc->base);
 842
 843         return crtc;
 844 }