drivers/gpu/drm/meson/meson_drv.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2016 BayLibre, SAS
   4  * Author: Neil Armstrong <[email protected]>
   5  */
   6
   7 #ifndef __MESON_DRV_H
   8 #define __MESON_DRV_H
   9
  10 #include <linux/platform_device.h>
  11 #include <linux/regmap.h>
  12 #include <linux/of.h>
  13 #include <linux/soc/amlogic/meson-canvas.h>
  14 #include <drm/drmP.h>
  15
  16 struct meson_drm {
  17         struct device *dev;
  18         void __iomem *io_base;
  19         struct regmap *hhi;
  20         int vsync_irq;
  21
  22         struct meson_canvas *canvas;
  23         u8 canvas_id_osd1;
  24         u8 canvas_id_vd1_0;
  25         u8 canvas_id_vd1_1;
  26         u8 canvas_id_vd1_2;
  27
  28         struct drm_device *drm;
  29         struct drm_crtc *crtc;
  30         struct drm_plane *primary_plane;
  31         struct drm_plane *overlay_plane;
  32
  33         /* Components Data */
  34         struct {
  35                 bool osd1_enabled;
  36                 bool osd1_interlace;
  37                 bool osd1_commit;
  38                 uint32_t osd1_ctrl_stat;
  39                 uint32_t osd1_blk0_cfg[5];
  40                 uint32_t osd1_addr;
  41                 uint32_t osd1_stride;
  42                 uint32_t osd1_height;
  43                 uint32_t osd_sc_ctrl0;
  44                 uint32_t osd_sc_i_wh_m1;
  45                 uint32_t osd_sc_o_h_start_end;
  46                 uint32_t osd_sc_o_v_start_end;
  47                 uint32_t osd_sc_v_ini_phase;
  48                 uint32_t osd_sc_v_phase_step;
  49                 uint32_t osd_sc_h_ini_phase;
  50                 uint32_t osd_sc_h_phase_step;
  51                 uint32_t osd_sc_h_ctrl0;
  52                 uint32_t osd_sc_v_ctrl0;
  53                 uint32_t osd_blend_din0_scope_h;
  54                 uint32_t osd_blend_din0_scope_v;
  55                 uint32_t osb_blend0_size;
  56                 uint32_t osb_blend1_size;
  57
  58                 bool vd1_enabled;
  59                 bool vd1_commit;
  60                 unsigned int vd1_planes;
  61                 uint32_t vd1_if0_gen_reg;
  62                 uint32_t vd1_if0_luma_x0;
  63                 uint32_t vd1_if0_luma_y0;
  64                 uint32_t vd1_if0_chroma_x0;
  65                 uint32_t vd1_if0_chroma_y0;
  66                 uint32_t vd1_if0_repeat_loop;
  67                 uint32_t vd1_if0_luma0_rpt_pat;
  68                 uint32_t vd1_if0_chroma0_rpt_pat;
  69                 uint32_t vd1_range_map_y;
  70                 uint32_t vd1_range_map_cb;
  71                 uint32_t vd1_range_map_cr;
  72                 uint32_t viu_vd1_fmt_w;
  73                 uint32_t vd1_if0_canvas0;
  74                 uint32_t vd1_if0_gen_reg2;
  75                 uint32_t viu_vd1_fmt_ctrl;
  76                 uint32_t vd1_addr0;
  77                 uint32_t vd1_addr1;
  78                 uint32_t vd1_addr2;
  79                 uint32_t vd1_stride0;
  80                 uint32_t vd1_stride1;
  81                 uint32_t vd1_stride2;
  82                 uint32_t vd1_height0;
  83                 uint32_t vd1_height1;
  84                 uint32_t vd1_height2;
  85                 uint32_t vpp_pic_in_height;
  86                 uint32_t vpp_postblend_vd1_h_start_end;
  87                 uint32_t vpp_postblend_vd1_v_start_end;
  88                 uint32_t vpp_hsc_region12_startp;
  89                 uint32_t vpp_hsc_region34_startp;
  90                 uint32_t vpp_hsc_region4_endp;
  91                 uint32_t vpp_hsc_start_phase_step;
  92                 uint32_t vpp_hsc_region1_phase_slope;
  93                 uint32_t vpp_hsc_region3_phase_slope;
  94                 uint32_t vpp_line_in_length;
  95                 uint32_t vpp_preblend_h_size;
  96                 uint32_t vpp_vsc_region12_startp;
  97                 uint32_t vpp_vsc_region34_startp;
  98                 uint32_t vpp_vsc_region4_endp;
  99                 uint32_t vpp_vsc_start_phase_step;
 100                 uint32_t vpp_vsc_ini_phase;
 101                 uint32_t vpp_vsc_phase_ctrl;
 102                 uint32_t vpp_hsc_phase_ctrl;
 103                 uint32_t vpp_blend_vd2_h_start_end;
 104                 uint32_t vpp_blend_vd2_v_start_end;
 105         } viu;
 106
 107         struct {
 108                 unsigned int current_mode;
 109                 bool hdmi_repeat;
 110                 bool venc_repeat;
 111                 bool hdmi_use_enci;
 112         } venc;
 113 };
 114
 115 static inline int meson_vpu_is_compatible(struct meson_drm *priv,
 116                                           const char *compat)
 117 {
 118         return of_device_is_compatible(priv->dev->of_node, compat);
 119 }
 120
 121 #endif /* __MESON_DRV_H */