drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "hdp/hdp_5_0_0_offset.h"
  36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "navi10_sdma_pkt_open.h"
  42 #include "nbio_v2_3.h"
  43 #include "sdma_v5_0.h"
  44
  45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  47
  48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  53
  54 #define SDMA1_REG_OFFSET 0x600
  55 #define SDMA0_HYP_DEC_REG_START 0x5880
  56 #define SDMA0_HYP_DEC_REG_END 0x5893
  57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  58
  59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  63
  64 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  65         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  89 };
  90
  91 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112 };
 113
 114 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 117 };
 118
 119 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 122 };
 123
 124 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 127 };
 128
 129 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 130 {
 131         u32 base;
 132
 133         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 134             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 135                 base = adev->reg_offset[GC_HWIP][0][1];
 136                 if (instance == 1)
 137                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 138         } else {
 139                 base = adev->reg_offset[GC_HWIP][0][0];
 140                 if (instance == 1)
 141                         internal_offset += SDMA1_REG_OFFSET;
 142         }
 143
 144         return base + internal_offset;
 145 }
 146
 147 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 148 {
 149         switch (adev->asic_type) {
 150         case CHIP_NAVI10:
 151                 soc15_program_register_sequence(adev,
 152                                                 golden_settings_sdma_5,
 153                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 154                 soc15_program_register_sequence(adev,
 155                                                 golden_settings_sdma_nv10,
 156                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 157                 break;
 158         case CHIP_NAVI14:
 159                 soc15_program_register_sequence(adev,
 160                                                 golden_settings_sdma_5,
 161                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 162                 soc15_program_register_sequence(adev,
 163                                                 golden_settings_sdma_nv14,
 164                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 165                 break;
 166         case CHIP_NAVI12:
 167                 if (amdgpu_sriov_vf(adev))
 168                         soc15_program_register_sequence(adev,
 169                                                         golden_settings_sdma_5_sriov,
 170                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 171                 else
 172                         soc15_program_register_sequence(adev,
 173                                                         golden_settings_sdma_5,
 174                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 175                 soc15_program_register_sequence(adev,
 176                                                 golden_settings_sdma_nv12,
 177                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 178                 break;
 179         default:
 180                 break;
 181         }
 182 }
 183
 184 /**
 185  * sdma_v5_0_init_microcode - load ucode images from disk
 186  *
 187  * @adev: amdgpu_device pointer
 188  *
 189  * Use the firmware interface to load the ucode images into
 190  * the driver (not loaded into hw).
 191  * Returns 0 on success, error on failure.
 192  */
 193
 194 // emulation only, won't work on real chip
 195 // navi10 real chip need to use PSP to load firmware
 196 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 197 {
 198         const char *chip_name;
 199         char fw_name[30];
 200         int err = 0, i;
 201         struct amdgpu_firmware_info *info = NULL;
 202         const struct common_firmware_header *header = NULL;
 203         const struct sdma_firmware_header_v1_0 *hdr;
 204
 205         DRM_DEBUG("\n");
 206
 207         switch (adev->asic_type) {
 208         case CHIP_NAVI10:
 209                 chip_name = "navi10";
 210                 break;
 211         case CHIP_NAVI14:
 212                 chip_name = "navi14";
 213                 break;
 214         case CHIP_NAVI12:
 215                 chip_name = "navi12";
 216                 break;
 217         default:
 218                 BUG();
 219         }
 220
 221         for (i = 0; i < adev->sdma.num_instances; i++) {
 222                 if (i == 0)
 223                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 224                 else
 225                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 226                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 227                 if (err)
 228                         goto out;
 229                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 230                 if (err)
 231                         goto out;
 232                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 233                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 234                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 235                 if (adev->sdma.instance[i].feature_version >= 20)
 236                         adev->sdma.instance[i].burst_nop = true;
 237                 DRM_DEBUG("psp_load == '%s'\n",
 238                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 239
 240                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 241                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 242                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 243                         info->fw = adev->sdma.instance[i].fw;
 244                         header = (const struct common_firmware_header *)info->fw->data;
 245                         adev->firmware.fw_size +=
 246                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 247                 }
 248         }
 249 out:
 250         if (err) {
 251                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 252                 for (i = 0; i < adev->sdma.num_instances; i++) {
 253                         release_firmware(adev->sdma.instance[i].fw);
 254                         adev->sdma.instance[i].fw = NULL;
 255                 }
 256         }
 257         return err;
 258 }
 259
 260 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 261 {
 262         unsigned ret;
 263
 264         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 265         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 266         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 267         amdgpu_ring_write(ring, 1);
 268         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 269         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 270
 271         return ret;
 272 }
 273
 274 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 275                                            unsigned offset)
 276 {
 277         unsigned cur;
 278
 279         BUG_ON(offset > ring->buf_mask);
 280         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 281
 282         cur = (ring->wptr - 1) & ring->buf_mask;
 283         if (cur > offset)
 284                 ring->ring[offset] = cur - offset;
 285         else
 286                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 287 }
 288
 289 /**
 290  * sdma_v5_0_ring_get_rptr - get the current read pointer
 291  *
 292  * @ring: amdgpu ring pointer
 293  *
 294  * Get the current rptr from the hardware (NAVI10+).
 295  */
 296 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 297 {
 298         u64 *rptr;
 299
 300         /* XXX check if swapping is necessary on BE */
 301         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 302
 303         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 304         return ((*rptr) >> 2);
 305 }
 306
 307 /**
 308  * sdma_v5_0_ring_get_wptr - get the current write pointer
 309  *
 310  * @ring: amdgpu ring pointer
 311  *
 312  * Get the current wptr from the hardware (NAVI10+).
 313  */
 314 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 315 {
 316         struct amdgpu_device *adev = ring->adev;
 317         u64 wptr;
 318
 319         if (ring->use_doorbell) {
 320                 /* XXX check if swapping is necessary on BE */
 321                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 322                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 323         } else {
 324                 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 325                 wptr = wptr << 32;
 326                 wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 327                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 328         }
 329
 330         return wptr >> 2;
 331 }
 332
 333 /**
 334  * sdma_v5_0_ring_set_wptr - commit the write pointer
 335  *
 336  * @ring: amdgpu ring pointer
 337  *
 338  * Write the wptr back to the hardware (NAVI10+).
 339  */
 340 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 341 {
 342         struct amdgpu_device *adev = ring->adev;
 343
 344         DRM_DEBUG("Setting write pointer\n");
 345         if (ring->use_doorbell) {
 346                 DRM_DEBUG("Using doorbell -- "
 347                                 "wptr_offs == 0x%08x "
 348                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 349                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 350                                 ring->wptr_offs,
 351                                 lower_32_bits(ring->wptr << 2),
 352                                 upper_32_bits(ring->wptr << 2));
 353                 /* XXX check if swapping is necessary on BE */
 354                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 355                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 356                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 357                                 ring->doorbell_index, ring->wptr << 2);
 358                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 359         } else {
 360                 DRM_DEBUG("Not using doorbell -- "
 361                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 362                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 363                                 ring->me,
 364                                 lower_32_bits(ring->wptr << 2),
 365                                 ring->me,
 366                                 upper_32_bits(ring->wptr << 2));
 367                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 368                         lower_32_bits(ring->wptr << 2));
 369                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 370                         upper_32_bits(ring->wptr << 2));
 371         }
 372 }
 373
 374 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 375 {
 376         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 377         int i;
 378
 379         for (i = 0; i < count; i++)
 380                 if (sdma && sdma->burst_nop && (i == 0))
 381                         amdgpu_ring_write(ring, ring->funcs->nop |
 382                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 383                 else
 384                         amdgpu_ring_write(ring, ring->funcs->nop);
 385 }
 386
 387 /**
 388  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 389  *
 390  * @ring: amdgpu ring pointer
 391  * @ib: IB object to schedule
 392  *
 393  * Schedule an IB in the DMA ring (NAVI10).
 394  */
 395 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 396                                    struct amdgpu_job *job,
 397                                    struct amdgpu_ib *ib,
 398                                    uint32_t flags)
 399 {
 400         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 401         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 402
 403         /* Invalidate L2, because if we don't do it, we might get stale cache
 404          * lines from previous IBs.
 405          */
 406         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 407         amdgpu_ring_write(ring, 0);
 408         amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
 409                                  SDMA_GCR_GL2_WB |
 410                                  SDMA_GCR_GLM_INV |
 411                                  SDMA_GCR_GLM_WB) << 16);
 412         amdgpu_ring_write(ring, 0xffffff80);
 413         amdgpu_ring_write(ring, 0xffff);
 414
 415         /* An IB packet must end on a 8 DW boundary--the next dword
 416          * must be on a 8-dword boundary. Our IB packet below is 6
 417          * dwords long, thus add x number of NOPs, such that, in
 418          * modular arithmetic,
 419          * wptr + 6 + x = 8k, k >= 0, which in C is,
 420          * (wptr + 6 + x) % 8 = 0.
 421          * The expression below, is a solution of x.
 422          */
 423         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 424
 425         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 426                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 427         /* base must be 32 byte aligned */
 428         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 429         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 430         amdgpu_ring_write(ring, ib->length_dw);
 431         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 432         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 433 }
 434
 435 /**
 436  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 437  *
 438  * @ring: amdgpu ring pointer
 439  *
 440  * Emit an hdp flush packet on the requested DMA ring.
 441  */
 442 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 443 {
 444         struct amdgpu_device *adev = ring->adev;
 445         u32 ref_and_mask = 0;
 446         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 447
 448         if (ring->me == 0)
 449                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 450         else
 451                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 452
 453         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 454                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 455                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 456         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 457         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 458         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 459         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 460         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 461                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 462 }
 463
 464 /**
 465  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 466  *
 467  * @ring: amdgpu ring pointer
 468  * @fence: amdgpu fence object
 469  *
 470  * Add a DMA fence packet to the ring to write
 471  * the fence seq number and DMA trap packet to generate
 472  * an interrupt if needed (NAVI10).
 473  */
 474 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 475                                       unsigned flags)
 476 {
 477         struct amdgpu_device *adev = ring->adev;
 478         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 479         /* write the fence */
 480         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 481                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 482         /* zero in first two bits */
 483         BUG_ON(addr & 0x3);
 484         amdgpu_ring_write(ring, lower_32_bits(addr));
 485         amdgpu_ring_write(ring, upper_32_bits(addr));
 486         amdgpu_ring_write(ring, lower_32_bits(seq));
 487
 488         /* optionally write high bits as well */
 489         if (write64bit) {
 490                 addr += 4;
 491                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 492                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 493                 /* zero in first two bits */
 494                 BUG_ON(addr & 0x3);
 495                 amdgpu_ring_write(ring, lower_32_bits(addr));
 496                 amdgpu_ring_write(ring, upper_32_bits(addr));
 497                 amdgpu_ring_write(ring, upper_32_bits(seq));
 498         }
 499
 500         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
 501         if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
 502                 /* generate an interrupt */
 503                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 504                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 505         }
 506 }
 507
 508
 509 /**
 510  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 511  *
 512  * @adev: amdgpu_device pointer
 513  *
 514  * Stop the gfx async dma ring buffers (NAVI10).
 515  */
 516 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 517 {
 518         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 519         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 520         u32 rb_cntl, ib_cntl;
 521         int i;
 522
 523         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 524             (adev->mman.buffer_funcs_ring == sdma1))
 525                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 526
 527         for (i = 0; i < adev->sdma.num_instances; i++) {
 528                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 529                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 530                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 531                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 532                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 533                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 534         }
 535 }
 536
 537 /**
 538  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 539  *
 540  * @adev: amdgpu_device pointer
 541  *
 542  * Stop the compute async dma queues (NAVI10).
 543  */
 544 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 545 {
 546         /* XXX todo */
 547 }
 548
 549 /**
 550  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 551  *
 552  * @adev: amdgpu_device pointer
 553  * @enable: enable/disable the DMA MEs context switch.
 554  *
 555  * Halt or unhalt the async dma engines context switch (NAVI10).
 556  */
 557 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 558 {
 559         u32 f32_cntl = 0, phase_quantum = 0;
 560         int i;
 561
 562         if (amdgpu_sdma_phase_quantum) {
 563                 unsigned value = amdgpu_sdma_phase_quantum;
 564                 unsigned unit = 0;
 565
 566                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 567                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 568                         value = (value + 1) >> 1;
 569                         unit++;
 570                 }
 571                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 572                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 573                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 574                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 575                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 576                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 577                         WARN_ONCE(1,
 578                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 579                                   value << unit);
 580                 }
 581                 phase_quantum =
 582                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 583                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 584         }
 585
 586         for (i = 0; i < adev->sdma.num_instances; i++) {
 587                 if (!amdgpu_sriov_vf(adev)) {
 588                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 589                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 590                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 591                 }
 592
 593                 if (enable && amdgpu_sdma_phase_quantum) {
 594                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 595                                phase_quantum);
 596                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 597                                phase_quantum);
 598                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 599                                phase_quantum);
 600                 }
 601                 if (!amdgpu_sriov_vf(adev))
 602                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 603         }
 604
 605 }
 606
 607 /**
 608  * sdma_v5_0_enable - stop the async dma engines
 609  *
 610  * @adev: amdgpu_device pointer
 611  * @enable: enable/disable the DMA MEs.
 612  *
 613  * Halt or unhalt the async dma engines (NAVI10).
 614  */
 615 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 616 {
 617         u32 f32_cntl;
 618         int i;
 619
 620         if (enable == false) {
 621                 sdma_v5_0_gfx_stop(adev);
 622                 sdma_v5_0_rlc_stop(adev);
 623         }
 624
 625         if (amdgpu_sriov_vf(adev))
 626                 return;
 627
 628         for (i = 0; i < adev->sdma.num_instances; i++) {
 629                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 630                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 631                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 632         }
 633 }
 634
 635 /**
 636  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 637  *
 638  * @adev: amdgpu_device pointer
 639  *
 640  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 641  * Returns 0 for success, error for failure.
 642  */
 643 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 644 {
 645         struct amdgpu_ring *ring;
 646         u32 rb_cntl, ib_cntl;
 647         u32 rb_bufsz;
 648         u32 wb_offset;
 649         u32 doorbell;
 650         u32 doorbell_offset;
 651         u32 temp;
 652         u32 wptr_poll_cntl;
 653         u64 wptr_gpu_addr;
 654         int i, r;
 655
 656         for (i = 0; i < adev->sdma.num_instances; i++) {
 657                 ring = &adev->sdma.instance[i].ring;
 658                 wb_offset = (ring->rptr_offs * 4);
 659
 660                 if (!amdgpu_sriov_vf(adev))
 661                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 662
 663                 /* Set ring buffer size in dwords */
 664                 rb_bufsz = order_base_2(ring->ring_size / 4);
 665                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 666                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 667 #ifdef __BIG_ENDIAN
 668                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 669                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 670                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 671 #endif
 672                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 673
 674                 /* Initialize the ring buffer's read and write pointers */
 675                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 676                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 677                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 678                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 679
 680                 /* setup the wptr shadow polling */
 681                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 682                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 683                        lower_32_bits(wptr_gpu_addr));
 684                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 685                        upper_32_bits(wptr_gpu_addr));
 686                 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
 687                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 688                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 689                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 690                                                F32_POLL_ENABLE, 1);
 691                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 692                        wptr_poll_cntl);
 693
 694                 /* set the wb address whether it's enabled or not */
 695                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 696                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 697                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 698                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 699
 700                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 701
 702                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 703                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 704
 705                 ring->wptr = 0;
 706
 707                 /* before programing wptr to a less value, need set minor_ptr_update first */
 708                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 709
 710                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 711                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 712                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 713                 }
 714
 715                 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 716                 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 717
 718                 if (ring->use_doorbell) {
 719                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 720                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 721                                         OFFSET, ring->doorbell_index);
 722                 } else {
 723                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 724                 }
 725                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 726                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 727
 728                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 729                                                       ring->doorbell_index, 20);
 730
 731                 if (amdgpu_sriov_vf(adev))
 732                         sdma_v5_0_ring_set_wptr(ring);
 733
 734                 /* set minor_ptr_update to 0 after wptr programed */
 735                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 736
 737                 if (!amdgpu_sriov_vf(adev)) {
 738                         /* set utc l1 enable flag always to 1 */
 739                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 740                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 741
 742                         /* enable MCBP */
 743                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 744                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 745
 746                         /* Set up RESP_MODE to non-copy addresses */
 747                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 748                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 749                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 750                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 751
 752                         /* program default cache read and write policy */
 753                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 754                         /* clean read policy and write policy bits */
 755                         temp &= 0xFF0FFF;
 756                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 757                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 758                 }
 759
 760                 if (!amdgpu_sriov_vf(adev)) {
 761                         /* unhalt engine */
 762                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 763                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 764                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 765                 }
 766
 767                 /* enable DMA RB */
 768                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 769                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 770
 771                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 772                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 773 #ifdef __BIG_ENDIAN
 774                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 775 #endif
 776                 /* enable DMA IBs */
 777                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 778
 779                 ring->sched.ready = true;
 780
 781                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 782                         sdma_v5_0_ctx_switch_enable(adev, true);
 783                         sdma_v5_0_enable(adev, true);
 784                 }
 785
 786                 r = amdgpu_ring_test_helper(ring);
 787                 if (r)
 788                         return r;
 789
 790                 if (adev->mman.buffer_funcs_ring == ring)
 791                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 792         }
 793
 794         return 0;
 795 }
 796
 797 /**
 798  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 799  *
 800  * @adev: amdgpu_device pointer
 801  *
 802  * Set up the compute DMA queues and enable them (NAVI10).
 803  * Returns 0 for success, error for failure.
 804  */
 805 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 806 {
 807         return 0;
 808 }
 809
 810 /**
 811  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 812  *
 813  * @adev: amdgpu_device pointer
 814  *
 815  * Loads the sDMA0/1 ucode.
 816  * Returns 0 for success, -EINVAL if the ucode is not available.
 817  */
 818 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 819 {
 820         const struct sdma_firmware_header_v1_0 *hdr;
 821         const __le32 *fw_data;
 822         u32 fw_size;
 823         int i, j;
 824
 825         /* halt the MEs */
 826         sdma_v5_0_enable(adev, false);
 827
 828         for (i = 0; i < adev->sdma.num_instances; i++) {
 829                 if (!adev->sdma.instance[i].fw)
 830                         return -EINVAL;
 831
 832                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 833                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 834                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 835
 836                 fw_data = (const __le32 *)
 837                         (adev->sdma.instance[i].fw->data +
 838                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 839
 840                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 841
 842                 for (j = 0; j < fw_size; j++) {
 843                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 844                                 msleep(1);
 845                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 846                 }
 847
 848                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 849         }
 850
 851         return 0;
 852 }
 853
 854 /**
 855  * sdma_v5_0_start - setup and start the async dma engines
 856  *
 857  * @adev: amdgpu_device pointer
 858  *
 859  * Set up the DMA engines and enable them (NAVI10).
 860  * Returns 0 for success, error for failure.
 861  */
 862 static int sdma_v5_0_start(struct amdgpu_device *adev)
 863 {
 864         int r = 0;
 865
 866         if (amdgpu_sriov_vf(adev)) {
 867                 sdma_v5_0_ctx_switch_enable(adev, false);
 868                 sdma_v5_0_enable(adev, false);
 869
 870                 /* set RB registers */
 871                 r = sdma_v5_0_gfx_resume(adev);
 872                 return r;
 873         }
 874
 875         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 876                 r = sdma_v5_0_load_microcode(adev);
 877                 if (r)
 878                         return r;
 879
 880                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 881                 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d)
 882                         msleep(1000);
 883         }
 884
 885         /* unhalt the MEs */
 886         sdma_v5_0_enable(adev, true);
 887         /* enable sdma ring preemption */
 888         sdma_v5_0_ctx_switch_enable(adev, true);
 889
 890         /* start the gfx rings and rlc compute queues */
 891         r = sdma_v5_0_gfx_resume(adev);
 892         if (r)
 893                 return r;
 894         r = sdma_v5_0_rlc_resume(adev);
 895
 896         return r;
 897 }
 898
 899 /**
 900  * sdma_v5_0_ring_test_ring - simple async dma engine test
 901  *
 902  * @ring: amdgpu_ring structure holding ring information
 903  *
 904  * Test the DMA engine by writing using it to write an
 905  * value to memory. (NAVI10).
 906  * Returns 0 for success, error for failure.
 907  */
 908 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 909 {
 910         struct amdgpu_device *adev = ring->adev;
 911         unsigned i;
 912         unsigned index;
 913         int r;
 914         u32 tmp;
 915         u64 gpu_addr;
 916
 917         r = amdgpu_device_wb_get(adev, &index);
 918         if (r) {
 919                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 920                 return r;
 921         }
 922
 923         gpu_addr = adev->wb.gpu_addr + (index * 4);
 924         tmp = 0xCAFEDEAD;
 925         adev->wb.wb[index] = cpu_to_le32(tmp);
 926
 927         r = amdgpu_ring_alloc(ring, 5);
 928         if (r) {
 929                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 930                 amdgpu_device_wb_free(adev, index);
 931                 return r;
 932         }
 933
 934         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 935                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 936         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 937         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 938         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 939         amdgpu_ring_write(ring, 0xDEADBEEF);
 940         amdgpu_ring_commit(ring);
 941
 942         for (i = 0; i < adev->usec_timeout; i++) {
 943                 tmp = le32_to_cpu(adev->wb.wb[index]);
 944                 if (tmp == 0xDEADBEEF)
 945                         break;
 946                 if (amdgpu_emu_mode == 1)
 947                         msleep(1);
 948                 else
 949                         udelay(1);
 950         }
 951
 952         if (i >= adev->usec_timeout)
 953                 r = -ETIMEDOUT;
 954
 955         amdgpu_device_wb_free(adev, index);
 956
 957         return r;
 958 }
 959
 960 /**
 961  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
 962  *
 963  * @ring: amdgpu_ring structure holding ring information
 964  *
 965  * Test a simple IB in the DMA ring (NAVI10).
 966  * Returns 0 on success, error on failure.
 967  */
 968 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 969 {
 970         struct amdgpu_device *adev = ring->adev;
 971         struct amdgpu_ib ib;
 972         struct dma_fence *f = NULL;
 973         unsigned index;
 974         long r;
 975         u32 tmp = 0;
 976         u64 gpu_addr;
 977
 978         r = amdgpu_device_wb_get(adev, &index);
 979         if (r) {
 980                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 981                 return r;
 982         }
 983
 984         gpu_addr = adev->wb.gpu_addr + (index * 4);
 985         tmp = 0xCAFEDEAD;
 986         adev->wb.wb[index] = cpu_to_le32(tmp);
 987         memset(&ib, 0, sizeof(ib));
 988         r = amdgpu_ib_get(adev, NULL, 256,
 989                                         AMDGPU_IB_POOL_DIRECT, &ib);
 990         if (r) {
 991                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 992                 goto err0;
 993         }
 994
 995         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 996                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 997         ib.ptr[1] = lower_32_bits(gpu_addr);
 998         ib.ptr[2] = upper_32_bits(gpu_addr);
 999         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1000         ib.ptr[4] = 0xDEADBEEF;
1001         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1002         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1003         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1004         ib.length_dw = 8;
1005
1006         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1007         if (r)
1008                 goto err1;
1009
1010         r = dma_fence_wait_timeout(f, false, timeout);
1011         if (r == 0) {
1012                 DRM_ERROR("amdgpu: IB test timed out\n");
1013                 r = -ETIMEDOUT;
1014                 goto err1;
1015         } else if (r < 0) {
1016                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1017                 goto err1;
1018         }
1019         tmp = le32_to_cpu(adev->wb.wb[index]);
1020         if (tmp == 0xDEADBEEF)
1021                 r = 0;
1022         else
1023                 r = -EINVAL;
1024
1025 err1:
1026         amdgpu_ib_free(adev, &ib, NULL);
1027         dma_fence_put(f);
1028 err0:
1029         amdgpu_device_wb_free(adev, index);
1030         return r;
1031 }
1032
1033
1034 /**
1035  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1036  *
1037  * @ib: indirect buffer to fill with commands
1038  * @pe: addr of the page entry
1039  * @src: src addr to copy from
1040  * @count: number of page entries to update
1041  *
1042  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1043  */
1044 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1045                                   uint64_t pe, uint64_t src,
1046                                   unsigned count)
1047 {
1048         unsigned bytes = count * 8;
1049
1050         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1051                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1052         ib->ptr[ib->length_dw++] = bytes - 1;
1053         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1054         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1055         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1056         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1057         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1058
1059 }
1060
1061 /**
1062  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1063  *
1064  * @ib: indirect buffer to fill with commands
1065  * @pe: addr of the page entry
1066  * @addr: dst addr to write into pe
1067  * @count: number of page entries to update
1068  * @incr: increase next addr by incr bytes
1069  * @flags: access flags
1070  *
1071  * Update PTEs by writing them manually using sDMA (NAVI10).
1072  */
1073 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1074                                    uint64_t value, unsigned count,
1075                                    uint32_t incr)
1076 {
1077         unsigned ndw = count * 2;
1078
1079         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1080                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1081         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1082         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1083         ib->ptr[ib->length_dw++] = ndw - 1;
1084         for (; ndw > 0; ndw -= 2) {
1085                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1086                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1087                 value += incr;
1088         }
1089 }
1090
1091 /**
1092  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1093  *
1094  * @ib: indirect buffer to fill with commands
1095  * @pe: addr of the page entry
1096  * @addr: dst addr to write into pe
1097  * @count: number of page entries to update
1098  * @incr: increase next addr by incr bytes
1099  * @flags: access flags
1100  *
1101  * Update the page tables using sDMA (NAVI10).
1102  */
1103 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1104                                      uint64_t pe,
1105                                      uint64_t addr, unsigned count,
1106                                      uint32_t incr, uint64_t flags)
1107 {
1108         /* for physically contiguous pages (vram) */
1109         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1110         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1111         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1112         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1113         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1114         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1115         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1116         ib->ptr[ib->length_dw++] = incr; /* increment size */
1117         ib->ptr[ib->length_dw++] = 0;
1118         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1119 }
1120
1121 /**
1122  * sdma_v5_0_ring_pad_ib - pad the IB
1123  * @ib: indirect buffer to fill with padding
1124  *
1125  * Pad the IB with NOPs to a boundary multiple of 8.
1126  */
1127 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1128 {
1129         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1130         u32 pad_count;
1131         int i;
1132
1133         pad_count = (-ib->length_dw) & 0x7;
1134         for (i = 0; i < pad_count; i++)
1135                 if (sdma && sdma->burst_nop && (i == 0))
1136                         ib->ptr[ib->length_dw++] =
1137                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1138                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1139                 else
1140                         ib->ptr[ib->length_dw++] =
1141                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1142 }
1143
1144
1145 /**
1146  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1147  *
1148  * @ring: amdgpu_ring pointer
1149  *
1150  * Make sure all previous operations are completed (CIK).
1151  */
1152 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1153 {
1154         uint32_t seq = ring->fence_drv.sync_seq;
1155         uint64_t addr = ring->fence_drv.gpu_addr;
1156
1157         /* wait for idle */
1158         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1159                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1160                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1161                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1162         amdgpu_ring_write(ring, addr & 0xfffffffc);
1163         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1164         amdgpu_ring_write(ring, seq); /* reference */
1165         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1166         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1167                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1168 }
1169
1170
1171 /**
1172  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1173  *
1174  * @ring: amdgpu_ring pointer
1175  * @vm: amdgpu_vm pointer
1176  *
1177  * Update the page table base and flush the VM TLB
1178  * using sDMA (NAVI10).
1179  */
1180 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1181                                          unsigned vmid, uint64_t pd_addr)
1182 {
1183         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1184 }
1185
1186 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1187                                      uint32_t reg, uint32_t val)
1188 {
1189         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1190                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1191         amdgpu_ring_write(ring, reg);
1192         amdgpu_ring_write(ring, val);
1193 }
1194
1195 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1196                                          uint32_t val, uint32_t mask)
1197 {
1198         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1199                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1200                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1201         amdgpu_ring_write(ring, reg << 2);
1202         amdgpu_ring_write(ring, 0);
1203         amdgpu_ring_write(ring, val); /* reference */
1204         amdgpu_ring_write(ring, mask); /* mask */
1205         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1206                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1207 }
1208
1209 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1210                                                    uint32_t reg0, uint32_t reg1,
1211                                                    uint32_t ref, uint32_t mask)
1212 {
1213         amdgpu_ring_emit_wreg(ring, reg0, ref);
1214         /* wait for a cycle to reset vm_inv_eng*_ack */
1215         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1216         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1217 }
1218
1219 static int sdma_v5_0_early_init(void *handle)
1220 {
1221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222
1223         adev->sdma.num_instances = 2;
1224
1225         sdma_v5_0_set_ring_funcs(adev);
1226         sdma_v5_0_set_buffer_funcs(adev);
1227         sdma_v5_0_set_vm_pte_funcs(adev);
1228         sdma_v5_0_set_irq_funcs(adev);
1229
1230         return 0;
1231 }
1232
1233
1234 static int sdma_v5_0_sw_init(void *handle)
1235 {
1236         struct amdgpu_ring *ring;
1237         int r, i;
1238         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1239
1240         /* SDMA trap event */
1241         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1242                               SDMA0_5_0__SRCID__SDMA_TRAP,
1243                               &adev->sdma.trap_irq);
1244         if (r)
1245                 return r;
1246
1247         /* SDMA trap event */
1248         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1249                               SDMA1_5_0__SRCID__SDMA_TRAP,
1250                               &adev->sdma.trap_irq);
1251         if (r)
1252                 return r;
1253
1254         r = sdma_v5_0_init_microcode(adev);
1255         if (r) {
1256                 DRM_ERROR("Failed to load sdma firmware!\n");
1257                 return r;
1258         }
1259
1260         for (i = 0; i < adev->sdma.num_instances; i++) {
1261                 ring = &adev->sdma.instance[i].ring;
1262                 ring->ring_obj = NULL;
1263                 ring->use_doorbell = true;
1264
1265                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1266                                 ring->use_doorbell?"true":"false");
1267
1268                 ring->doorbell_index = (i == 0) ?
1269                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1270                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1271
1272                 sprintf(ring->name, "sdma%d", i);
1273                 r = amdgpu_ring_init(adev, ring, 1024,
1274                                      &adev->sdma.trap_irq,
1275                                      (i == 0) ?
1276                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1277                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1278                                      AMDGPU_RING_PRIO_DEFAULT);
1279                 if (r)
1280                         return r;
1281         }
1282
1283         return r;
1284 }
1285
1286 static int sdma_v5_0_sw_fini(void *handle)
1287 {
1288         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1289         int i;
1290
1291         for (i = 0; i < adev->sdma.num_instances; i++) {
1292                 if (adev->sdma.instance[i].fw != NULL)
1293                         release_firmware(adev->sdma.instance[i].fw);
1294
1295                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1296         }
1297
1298         return 0;
1299 }
1300
1301 static int sdma_v5_0_hw_init(void *handle)
1302 {
1303         int r;
1304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1305
1306         sdma_v5_0_init_golden_registers(adev);
1307
1308         r = sdma_v5_0_start(adev);
1309
1310         return r;
1311 }
1312
1313 static int sdma_v5_0_hw_fini(void *handle)
1314 {
1315         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317         if (amdgpu_sriov_vf(adev))
1318                 return 0;
1319
1320         sdma_v5_0_ctx_switch_enable(adev, false);
1321         sdma_v5_0_enable(adev, false);
1322
1323         return 0;
1324 }
1325
1326 static int sdma_v5_0_suspend(void *handle)
1327 {
1328         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1329
1330         return sdma_v5_0_hw_fini(adev);
1331 }
1332
1333 static int sdma_v5_0_resume(void *handle)
1334 {
1335         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1336
1337         return sdma_v5_0_hw_init(adev);
1338 }
1339
1340 static bool sdma_v5_0_is_idle(void *handle)
1341 {
1342         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1343         u32 i;
1344
1345         for (i = 0; i < adev->sdma.num_instances; i++) {
1346                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1347
1348                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1349                         return false;
1350         }
1351
1352         return true;
1353 }
1354
1355 static int sdma_v5_0_wait_for_idle(void *handle)
1356 {
1357         unsigned i;
1358         u32 sdma0, sdma1;
1359         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1360
1361         for (i = 0; i < adev->usec_timeout; i++) {
1362                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1363                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1364
1365                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1366                         return 0;
1367                 udelay(1);
1368         }
1369         return -ETIMEDOUT;
1370 }
1371
1372 static int sdma_v5_0_soft_reset(void *handle)
1373 {
1374         /* todo */
1375
1376         return 0;
1377 }
1378
1379 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1380 {
1381         int i, r = 0;
1382         struct amdgpu_device *adev = ring->adev;
1383         u32 index = 0;
1384         u64 sdma_gfx_preempt;
1385
1386         amdgpu_sdma_get_index_from_ring(ring, &index);
1387         if (index == 0)
1388                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1389         else
1390                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1391
1392         /* assert preemption condition */
1393         amdgpu_ring_set_preempt_cond_exec(ring, false);
1394
1395         /* emit the trailing fence */
1396         ring->trail_seq += 1;
1397         amdgpu_ring_alloc(ring, 10);
1398         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1399                                   ring->trail_seq, 0);
1400         amdgpu_ring_commit(ring);
1401
1402         /* assert IB preemption */
1403         WREG32(sdma_gfx_preempt, 1);
1404
1405         /* poll the trailing fence */
1406         for (i = 0; i < adev->usec_timeout; i++) {
1407                 if (ring->trail_seq ==
1408                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1409                         break;
1410                 udelay(1);
1411         }
1412
1413         if (i >= adev->usec_timeout) {
1414                 r = -EINVAL;
1415                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1416         }
1417
1418         /* deassert IB preemption */
1419         WREG32(sdma_gfx_preempt, 0);
1420
1421         /* deassert the preemption condition */
1422         amdgpu_ring_set_preempt_cond_exec(ring, true);
1423         return r;
1424 }
1425
1426 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1427                                         struct amdgpu_irq_src *source,
1428                                         unsigned type,
1429                                         enum amdgpu_interrupt_state state)
1430 {
1431         u32 sdma_cntl;
1432
1433         if (!amdgpu_sriov_vf(adev)) {
1434                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1435                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1436                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1437
1438                 sdma_cntl = RREG32(reg_offset);
1439                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1440                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1441                 WREG32(reg_offset, sdma_cntl);
1442         }
1443
1444         return 0;
1445 }
1446
1447 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1448                                       struct amdgpu_irq_src *source,
1449                                       struct amdgpu_iv_entry *entry)
1450 {
1451         DRM_DEBUG("IH: SDMA trap\n");
1452         switch (entry->client_id) {
1453         case SOC15_IH_CLIENTID_SDMA0:
1454                 switch (entry->ring_id) {
1455                 case 0:
1456                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1457                         break;
1458                 case 1:
1459                         /* XXX compute */
1460                         break;
1461                 case 2:
1462                         /* XXX compute */
1463                         break;
1464                 case 3:
1465                         /* XXX page queue*/
1466                         break;
1467                 }
1468                 break;
1469         case SOC15_IH_CLIENTID_SDMA1:
1470                 switch (entry->ring_id) {
1471                 case 0:
1472                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1473                         break;
1474                 case 1:
1475                         /* XXX compute */
1476                         break;
1477                 case 2:
1478                         /* XXX compute */
1479                         break;
1480                 case 3:
1481                         /* XXX page queue*/
1482                         break;
1483                 }
1484                 break;
1485         }
1486         return 0;
1487 }
1488
1489 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1490                                               struct amdgpu_irq_src *source,
1491                                               struct amdgpu_iv_entry *entry)
1492 {
1493         return 0;
1494 }
1495
1496 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1497                                                        bool enable)
1498 {
1499         uint32_t data, def;
1500         int i;
1501
1502         for (i = 0; i < adev->sdma.num_instances; i++) {
1503                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1504                         /* Enable sdma clock gating */
1505                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1506                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1507                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1508                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1509                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1510                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1511                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1512                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1513                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1514                         if (def != data)
1515                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1516                 } else {
1517                         /* Disable sdma clock gating */
1518                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1519                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1520                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1521                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1522                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1523                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1524                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1525                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1526                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1527                         if (def != data)
1528                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1529                 }
1530         }
1531 }
1532
1533 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1534                                                       bool enable)
1535 {
1536         uint32_t data, def;
1537         int i;
1538
1539         for (i = 0; i < adev->sdma.num_instances; i++) {
1540                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1541                         /* Enable sdma mem light sleep */
1542                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1543                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1544                         if (def != data)
1545                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1546
1547                 } else {
1548                         /* Disable sdma mem light sleep */
1549                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1550                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1551                         if (def != data)
1552                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1553
1554                 }
1555         }
1556 }
1557
1558 static int sdma_v5_0_set_clockgating_state(void *handle,
1559                                            enum amd_clockgating_state state)
1560 {
1561         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1562
1563         if (amdgpu_sriov_vf(adev))
1564                 return 0;
1565
1566         switch (adev->asic_type) {
1567         case CHIP_NAVI10:
1568         case CHIP_NAVI14:
1569         case CHIP_NAVI12:
1570                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1571                                 state == AMD_CG_STATE_GATE);
1572                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1573                                 state == AMD_CG_STATE_GATE);
1574                 break;
1575         default:
1576                 break;
1577         }
1578
1579         return 0;
1580 }
1581
1582 static int sdma_v5_0_set_powergating_state(void *handle,
1583                                           enum amd_powergating_state state)
1584 {
1585         return 0;
1586 }
1587
1588 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1589 {
1590         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1591         int data;
1592
1593         if (amdgpu_sriov_vf(adev))
1594                 *flags = 0;
1595
1596         /* AMD_CG_SUPPORT_SDMA_MGCG */
1597         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1598         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1599                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1600
1601         /* AMD_CG_SUPPORT_SDMA_LS */
1602         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1603         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1604                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1605 }
1606
1607 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1608         .name = "sdma_v5_0",
1609         .early_init = sdma_v5_0_early_init,
1610         .late_init = NULL,
1611         .sw_init = sdma_v5_0_sw_init,
1612         .sw_fini = sdma_v5_0_sw_fini,
1613         .hw_init = sdma_v5_0_hw_init,
1614         .hw_fini = sdma_v5_0_hw_fini,
1615         .suspend = sdma_v5_0_suspend,
1616         .resume = sdma_v5_0_resume,
1617         .is_idle = sdma_v5_0_is_idle,
1618         .wait_for_idle = sdma_v5_0_wait_for_idle,
1619         .soft_reset = sdma_v5_0_soft_reset,
1620         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1621         .set_powergating_state = sdma_v5_0_set_powergating_state,
1622         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1623 };
1624
1625 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1626         .type = AMDGPU_RING_TYPE_SDMA,
1627         .align_mask = 0xf,
1628         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1629         .support_64bit_ptrs = true,
1630         .vmhub = AMDGPU_GFXHUB_0,
1631         .get_rptr = sdma_v5_0_ring_get_rptr,
1632         .get_wptr = sdma_v5_0_ring_get_wptr,
1633         .set_wptr = sdma_v5_0_ring_set_wptr,
1634         .emit_frame_size =
1635                 5 + /* sdma_v5_0_ring_init_cond_exec */
1636                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1637                 3 + /* hdp_invalidate */
1638                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1639                 /* sdma_v5_0_ring_emit_vm_flush */
1640                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1641                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1642                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1643         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1644         .emit_ib = sdma_v5_0_ring_emit_ib,
1645         .emit_fence = sdma_v5_0_ring_emit_fence,
1646         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1647         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1648         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1649         .test_ring = sdma_v5_0_ring_test_ring,
1650         .test_ib = sdma_v5_0_ring_test_ib,
1651         .insert_nop = sdma_v5_0_ring_insert_nop,
1652         .pad_ib = sdma_v5_0_ring_pad_ib,
1653         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1654         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1655         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1656         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1657         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1658         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1659 };
1660
1661 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1662 {
1663         int i;
1664
1665         for (i = 0; i < adev->sdma.num_instances; i++) {
1666                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1667                 adev->sdma.instance[i].ring.me = i;
1668         }
1669 }
1670
1671 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1672         .set = sdma_v5_0_set_trap_irq_state,
1673         .process = sdma_v5_0_process_trap_irq,
1674 };
1675
1676 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1677         .process = sdma_v5_0_process_illegal_inst_irq,
1678 };
1679
1680 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1681 {
1682         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1683                                         adev->sdma.num_instances;
1684         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1685         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1686 }
1687
1688 /**
1689  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1690  *
1691  * @ring: amdgpu_ring structure holding ring information
1692  * @src_offset: src GPU address
1693  * @dst_offset: dst GPU address
1694  * @byte_count: number of bytes to xfer
1695  *
1696  * Copy GPU buffers using the DMA engine (NAVI10).
1697  * Used by the amdgpu ttm implementation to move pages if
1698  * registered as the asic copy callback.
1699  */
1700 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1701                                        uint64_t src_offset,
1702                                        uint64_t dst_offset,
1703                                        uint32_t byte_count,
1704                                        bool tmz)
1705 {
1706         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1707                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1708                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1709         ib->ptr[ib->length_dw++] = byte_count - 1;
1710         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1711         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1712         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1713         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1714         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1715 }
1716
1717 /**
1718  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1719  *
1720  * @ring: amdgpu_ring structure holding ring information
1721  * @src_data: value to write to buffer
1722  * @dst_offset: dst GPU address
1723  * @byte_count: number of bytes to xfer
1724  *
1725  * Fill GPU buffers using the DMA engine (NAVI10).
1726  */
1727 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1728                                        uint32_t src_data,
1729                                        uint64_t dst_offset,
1730                                        uint32_t byte_count)
1731 {
1732         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1733         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1734         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1735         ib->ptr[ib->length_dw++] = src_data;
1736         ib->ptr[ib->length_dw++] = byte_count - 1;
1737 }
1738
1739 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1740         .copy_max_bytes = 0x400000,
1741         .copy_num_dw = 7,
1742         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1743
1744         .fill_max_bytes = 0x400000,
1745         .fill_num_dw = 5,
1746         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1747 };
1748
1749 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1750 {
1751         if (adev->mman.buffer_funcs == NULL) {
1752                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1753                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1754         }
1755 }
1756
1757 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1758         .copy_pte_num_dw = 7,
1759         .copy_pte = sdma_v5_0_vm_copy_pte,
1760         .write_pte = sdma_v5_0_vm_write_pte,
1761         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1762 };
1763
1764 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1765 {
1766         unsigned i;
1767
1768         if (adev->vm_manager.vm_pte_funcs == NULL) {
1769                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1770                 for (i = 0; i < adev->sdma.num_instances; i++) {
1771                         adev->vm_manager.vm_pte_scheds[i] =
1772                                 &adev->sdma.instance[i].ring.sched;
1773                 }
1774                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1775         }
1776 }
1777
1778 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1779         .type = AMD_IP_BLOCK_TYPE_SDMA,
1780         .major = 5,
1781         .minor = 0,
1782         .rev = 0,
1783         .funcs = &sdma_v5_0_ip_funcs,
1784 };