drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include <linux/pm_runtime.h>
  41 #include "hwmgr.h"
  42 #define WIDTH_4K 3840
  43
  44 static const struct cg_flag_name clocks[] = {
  45         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  50         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  55         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  58         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  61         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  64         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  67         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  68         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  69
  70         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  71         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  72         {0, NULL},
  73 };
  74
  75 static const struct hwmon_temp_label {
  76         enum PP_HWMON_TEMP channel;
  77         const char *label;
  78 } temp_label[] = {
  79         {PP_TEMP_EDGE, "edge"},
  80         {PP_TEMP_JUNCTION, "junction"},
  81         {PP_TEMP_MEM, "mem"},
  82 };
  83
  84 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  85 {
  86         if (adev->pm.dpm_enabled) {
  87                 mutex_lock(&adev->pm.mutex);
  88                 if (power_supply_is_system_supplied() > 0)
  89                         adev->pm.ac_power = true;
  90                 else
  91                         adev->pm.ac_power = false;
  92                 if (adev->powerplay.pp_funcs &&
  93                     adev->powerplay.pp_funcs->enable_bapm)
  94                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  95                 mutex_unlock(&adev->pm.mutex);
  96
  97                 if (is_support_sw_smu(adev))
  98                         smu_set_ac_dc(&adev->smu);
  99         }
 100 }
 101
 102 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
 103                            void *data, uint32_t *size)
 104 {
 105         int ret = 0;
 106
 107         if (!data || !size)
 108                 return -EINVAL;
 109
 110         if (is_support_sw_smu(adev))
 111                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 112         else {
 113                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 114                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 115                                                                     sensor, data, size);
 116                 else
 117                         ret = -EINVAL;
 118         }
 119
 120         return ret;
 121 }
 122
 123 /**
 124  * DOC: power_dpm_state
 125  *
 126  * The power_dpm_state file is a legacy interface and is only provided for
 127  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 128  * certain power related parameters.  The file power_dpm_state is used for this.
 129  * It accepts the following arguments:
 130  *
 131  * - battery
 132  *
 133  * - balanced
 134  *
 135  * - performance
 136  *
 137  * battery
 138  *
 139  * On older GPUs, the vbios provided a special power state for battery
 140  * operation.  Selecting battery switched to this state.  This is no
 141  * longer provided on newer GPUs so the option does nothing in that case.
 142  *
 143  * balanced
 144  *
 145  * On older GPUs, the vbios provided a special power state for balanced
 146  * operation.  Selecting balanced switched to this state.  This is no
 147  * longer provided on newer GPUs so the option does nothing in that case.
 148  *
 149  * performance
 150  *
 151  * On older GPUs, the vbios provided a special power state for performance
 152  * operation.  Selecting performance switched to this state.  This is no
 153  * longer provided on newer GPUs so the option does nothing in that case.
 154  *
 155  */
 156
 157 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 158                                           struct device_attribute *attr,
 159                                           char *buf)
 160 {
 161         struct drm_device *ddev = dev_get_drvdata(dev);
 162         struct amdgpu_device *adev = ddev->dev_private;
 163         enum amd_pm_state_type pm;
 164         int ret;
 165
 166         if (adev->in_gpu_reset)
 167                 return -EPERM;
 168
 169         ret = pm_runtime_get_sync(ddev->dev);
 170         if (ret < 0)
 171                 return ret;
 172
 173         if (is_support_sw_smu(adev)) {
 174                 if (adev->smu.ppt_funcs->get_current_power_state)
 175                         pm = smu_get_current_power_state(&adev->smu);
 176                 else
 177                         pm = adev->pm.dpm.user_state;
 178         } else if (adev->powerplay.pp_funcs->get_current_power_state) {
 179                 pm = amdgpu_dpm_get_current_power_state(adev);
 180         } else {
 181                 pm = adev->pm.dpm.user_state;
 182         }
 183
 184         pm_runtime_mark_last_busy(ddev->dev);
 185         pm_runtime_put_autosuspend(ddev->dev);
 186
 187         return snprintf(buf, PAGE_SIZE, "%s\n",
 188                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 189                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 190 }
 191
 192 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 193                                           struct device_attribute *attr,
 194                                           const char *buf,
 195                                           size_t count)
 196 {
 197         struct drm_device *ddev = dev_get_drvdata(dev);
 198         struct amdgpu_device *adev = ddev->dev_private;
 199         enum amd_pm_state_type  state;
 200         int ret;
 201
 202         if (adev->in_gpu_reset)
 203                 return -EPERM;
 204
 205         if (strncmp("battery", buf, strlen("battery")) == 0)
 206                 state = POWER_STATE_TYPE_BATTERY;
 207         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 208                 state = POWER_STATE_TYPE_BALANCED;
 209         else if (strncmp("performance", buf, strlen("performance")) == 0)
 210                 state = POWER_STATE_TYPE_PERFORMANCE;
 211         else
 212                 return -EINVAL;
 213
 214         ret = pm_runtime_get_sync(ddev->dev);
 215         if (ret < 0)
 216                 return ret;
 217
 218         if (is_support_sw_smu(adev)) {
 219                 mutex_lock(&adev->pm.mutex);
 220                 adev->pm.dpm.user_state = state;
 221                 mutex_unlock(&adev->pm.mutex);
 222         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 223                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 224         } else {
 225                 mutex_lock(&adev->pm.mutex);
 226                 adev->pm.dpm.user_state = state;
 227                 mutex_unlock(&adev->pm.mutex);
 228
 229                 amdgpu_pm_compute_clocks(adev);
 230         }
 231         pm_runtime_mark_last_busy(ddev->dev);
 232         pm_runtime_put_autosuspend(ddev->dev);
 233
 234         return count;
 235 }
 236
 237
 238 /**
 239  * DOC: power_dpm_force_performance_level
 240  *
 241  * The amdgpu driver provides a sysfs API for adjusting certain power
 242  * related parameters.  The file power_dpm_force_performance_level is
 243  * used for this.  It accepts the following arguments:
 244  *
 245  * - auto
 246  *
 247  * - low
 248  *
 249  * - high
 250  *
 251  * - manual
 252  *
 253  * - profile_standard
 254  *
 255  * - profile_min_sclk
 256  *
 257  * - profile_min_mclk
 258  *
 259  * - profile_peak
 260  *
 261  * auto
 262  *
 263  * When auto is selected, the driver will attempt to dynamically select
 264  * the optimal power profile for current conditions in the driver.
 265  *
 266  * low
 267  *
 268  * When low is selected, the clocks are forced to the lowest power state.
 269  *
 270  * high
 271  *
 272  * When high is selected, the clocks are forced to the highest power state.
 273  *
 274  * manual
 275  *
 276  * When manual is selected, the user can manually adjust which power states
 277  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 278  * and pp_dpm_pcie files and adjust the power state transition heuristics
 279  * via the pp_power_profile_mode sysfs file.
 280  *
 281  * profile_standard
 282  * profile_min_sclk
 283  * profile_min_mclk
 284  * profile_peak
 285  *
 286  * When the profiling modes are selected, clock and power gating are
 287  * disabled and the clocks are set for different profiling cases. This
 288  * mode is recommended for profiling specific work loads where you do
 289  * not want clock or power gating for clock fluctuation to interfere
 290  * with your results. profile_standard sets the clocks to a fixed clock
 291  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 292  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 293  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 294  *
 295  */
 296
 297 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 298                                                             struct device_attribute *attr,
 299                                                             char *buf)
 300 {
 301         struct drm_device *ddev = dev_get_drvdata(dev);
 302         struct amdgpu_device *adev = ddev->dev_private;
 303         enum amd_dpm_forced_level level = 0xff;
 304         int ret;
 305
 306         if (adev->in_gpu_reset)
 307                 return -EPERM;
 308
 309         ret = pm_runtime_get_sync(ddev->dev);
 310         if (ret < 0)
 311                 return ret;
 312
 313         if (is_support_sw_smu(adev))
 314                 level = smu_get_performance_level(&adev->smu);
 315         else if (adev->powerplay.pp_funcs->get_performance_level)
 316                 level = amdgpu_dpm_get_performance_level(adev);
 317         else
 318                 level = adev->pm.dpm.forced_level;
 319
 320         pm_runtime_mark_last_busy(ddev->dev);
 321         pm_runtime_put_autosuspend(ddev->dev);
 322
 323         return snprintf(buf, PAGE_SIZE, "%s\n",
 324                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 325                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 326                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 327                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 328                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 329                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 330                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 331                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 332                         "unknown");
 333 }
 334
 335 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 336                                                             struct device_attribute *attr,
 337                                                             const char *buf,
 338                                                             size_t count)
 339 {
 340         struct drm_device *ddev = dev_get_drvdata(dev);
 341         struct amdgpu_device *adev = ddev->dev_private;
 342         enum amd_dpm_forced_level level;
 343         enum amd_dpm_forced_level current_level = 0xff;
 344         int ret = 0;
 345
 346         if (adev->in_gpu_reset)
 347                 return -EPERM;
 348
 349         if (strncmp("low", buf, strlen("low")) == 0) {
 350                 level = AMD_DPM_FORCED_LEVEL_LOW;
 351         } else if (strncmp("high", buf, strlen("high")) == 0) {
 352                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 353         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 354                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 355         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 356                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 357         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 358                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 359         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 360                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 361         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 362                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 363         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 364                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 365         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 366                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 367         }  else {
 368                 return -EINVAL;
 369         }
 370
 371         ret = pm_runtime_get_sync(ddev->dev);
 372         if (ret < 0)
 373                 return ret;
 374
 375         if (is_support_sw_smu(adev))
 376                 current_level = smu_get_performance_level(&adev->smu);
 377         else if (adev->powerplay.pp_funcs->get_performance_level)
 378                 current_level = amdgpu_dpm_get_performance_level(adev);
 379
 380         if (current_level == level) {
 381                 pm_runtime_mark_last_busy(ddev->dev);
 382                 pm_runtime_put_autosuspend(ddev->dev);
 383                 return count;
 384         }
 385
 386         if (adev->asic_type == CHIP_RAVEN) {
 387                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 388                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
 389                                 amdgpu_gfx_off_ctrl(adev, false);
 390                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 391                                 amdgpu_gfx_off_ctrl(adev, true);
 392                 }
 393         }
 394
 395         /* profile_exit setting is valid only when current mode is in profile mode */
 396         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 397             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 398             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 399             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 400             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 401                 pr_err("Currently not in any profile mode!\n");
 402                 pm_runtime_mark_last_busy(ddev->dev);
 403                 pm_runtime_put_autosuspend(ddev->dev);
 404                 return -EINVAL;
 405         }
 406
 407         if (is_support_sw_smu(adev)) {
 408                 ret = smu_force_performance_level(&adev->smu, level);
 409                 if (ret) {
 410                         pm_runtime_mark_last_busy(ddev->dev);
 411                         pm_runtime_put_autosuspend(ddev->dev);
 412                         return -EINVAL;
 413                 }
 414         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 415                 mutex_lock(&adev->pm.mutex);
 416                 if (adev->pm.dpm.thermal_active) {
 417                         mutex_unlock(&adev->pm.mutex);
 418                         pm_runtime_mark_last_busy(ddev->dev);
 419                         pm_runtime_put_autosuspend(ddev->dev);
 420                         return -EINVAL;
 421                 }
 422                 ret = amdgpu_dpm_force_performance_level(adev, level);
 423                 if (ret) {
 424                         mutex_unlock(&adev->pm.mutex);
 425                         pm_runtime_mark_last_busy(ddev->dev);
 426                         pm_runtime_put_autosuspend(ddev->dev);
 427                         return -EINVAL;
 428                 } else {
 429                         adev->pm.dpm.forced_level = level;
 430                 }
 431                 mutex_unlock(&adev->pm.mutex);
 432         }
 433         pm_runtime_mark_last_busy(ddev->dev);
 434         pm_runtime_put_autosuspend(ddev->dev);
 435
 436         return count;
 437 }
 438
 439 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 440                 struct device_attribute *attr,
 441                 char *buf)
 442 {
 443         struct drm_device *ddev = dev_get_drvdata(dev);
 444         struct amdgpu_device *adev = ddev->dev_private;
 445         struct pp_states_info data;
 446         int i, buf_len, ret;
 447
 448         if (adev->in_gpu_reset)
 449                 return -EPERM;
 450
 451         ret = pm_runtime_get_sync(ddev->dev);
 452         if (ret < 0)
 453                 return ret;
 454
 455         if (is_support_sw_smu(adev)) {
 456                 ret = smu_get_power_num_states(&adev->smu, &data);
 457                 if (ret)
 458                         return ret;
 459         } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
 460                 amdgpu_dpm_get_pp_num_states(adev, &data);
 461         } else {
 462                 memset(&data, 0, sizeof(data));
 463         }
 464
 465         pm_runtime_mark_last_busy(ddev->dev);
 466         pm_runtime_put_autosuspend(ddev->dev);
 467
 468         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 469         for (i = 0; i < data.nums; i++)
 470                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 471                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 472                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 473                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 474                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 475
 476         return buf_len;
 477 }
 478
 479 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 480                 struct device_attribute *attr,
 481                 char *buf)
 482 {
 483         struct drm_device *ddev = dev_get_drvdata(dev);
 484         struct amdgpu_device *adev = ddev->dev_private;
 485         struct pp_states_info data;
 486         struct smu_context *smu = &adev->smu;
 487         enum amd_pm_state_type pm = 0;
 488         int i = 0, ret = 0;
 489
 490         if (adev->in_gpu_reset)
 491                 return -EPERM;
 492
 493         ret = pm_runtime_get_sync(ddev->dev);
 494         if (ret < 0)
 495                 return ret;
 496
 497         if (is_support_sw_smu(adev)) {
 498                 pm = smu_get_current_power_state(smu);
 499                 ret = smu_get_power_num_states(smu, &data);
 500                 if (ret)
 501                         return ret;
 502         } else if (adev->powerplay.pp_funcs->get_current_power_state
 503                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 504                 pm = amdgpu_dpm_get_current_power_state(adev);
 505                 amdgpu_dpm_get_pp_num_states(adev, &data);
 506         }
 507
 508         pm_runtime_mark_last_busy(ddev->dev);
 509         pm_runtime_put_autosuspend(ddev->dev);
 510
 511         for (i = 0; i < data.nums; i++) {
 512                 if (pm == data.states[i])
 513                         break;
 514         }
 515
 516         if (i == data.nums)
 517                 i = -EINVAL;
 518
 519         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 520 }
 521
 522 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 523                 struct device_attribute *attr,
 524                 char *buf)
 525 {
 526         struct drm_device *ddev = dev_get_drvdata(dev);
 527         struct amdgpu_device *adev = ddev->dev_private;
 528
 529         if (adev->in_gpu_reset)
 530                 return -EPERM;
 531
 532         if (adev->pp_force_state_enabled)
 533                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 534         else
 535                 return snprintf(buf, PAGE_SIZE, "\n");
 536 }
 537
 538 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 539                 struct device_attribute *attr,
 540                 const char *buf,
 541                 size_t count)
 542 {
 543         struct drm_device *ddev = dev_get_drvdata(dev);
 544         struct amdgpu_device *adev = ddev->dev_private;
 545         enum amd_pm_state_type state = 0;
 546         unsigned long idx;
 547         int ret;
 548
 549         if (adev->in_gpu_reset)
 550                 return -EPERM;
 551
 552         if (strlen(buf) == 1)
 553                 adev->pp_force_state_enabled = false;
 554         else if (is_support_sw_smu(adev))
 555                 adev->pp_force_state_enabled = false;
 556         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 557                         adev->powerplay.pp_funcs->get_pp_num_states) {
 558                 struct pp_states_info data;
 559
 560                 ret = kstrtoul(buf, 0, &idx);
 561                 if (ret || idx >= ARRAY_SIZE(data.states))
 562                         return -EINVAL;
 563
 564                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 565
 566                 amdgpu_dpm_get_pp_num_states(adev, &data);
 567                 state = data.states[idx];
 568
 569                 ret = pm_runtime_get_sync(ddev->dev);
 570                 if (ret < 0)
 571                         return ret;
 572
 573                 /* only set user selected power states */
 574                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 575                     state != POWER_STATE_TYPE_DEFAULT) {
 576                         amdgpu_dpm_dispatch_task(adev,
 577                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 578                         adev->pp_force_state_enabled = true;
 579                 }
 580                 pm_runtime_mark_last_busy(ddev->dev);
 581                 pm_runtime_put_autosuspend(ddev->dev);
 582         }
 583
 584         return count;
 585 }
 586
 587 /**
 588  * DOC: pp_table
 589  *
 590  * The amdgpu driver provides a sysfs API for uploading new powerplay
 591  * tables.  The file pp_table is used for this.  Reading the file
 592  * will dump the current power play table.  Writing to the file
 593  * will attempt to upload a new powerplay table and re-initialize
 594  * powerplay using that new table.
 595  *
 596  */
 597
 598 static ssize_t amdgpu_get_pp_table(struct device *dev,
 599                 struct device_attribute *attr,
 600                 char *buf)
 601 {
 602         struct drm_device *ddev = dev_get_drvdata(dev);
 603         struct amdgpu_device *adev = ddev->dev_private;
 604         char *table = NULL;
 605         int size, ret;
 606
 607         if (adev->in_gpu_reset)
 608                 return -EPERM;
 609
 610         ret = pm_runtime_get_sync(ddev->dev);
 611         if (ret < 0)
 612                 return ret;
 613
 614         if (is_support_sw_smu(adev)) {
 615                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 616                 pm_runtime_mark_last_busy(ddev->dev);
 617                 pm_runtime_put_autosuspend(ddev->dev);
 618                 if (size < 0)
 619                         return size;
 620         } else if (adev->powerplay.pp_funcs->get_pp_table) {
 621                 size = amdgpu_dpm_get_pp_table(adev, &table);
 622                 pm_runtime_mark_last_busy(ddev->dev);
 623                 pm_runtime_put_autosuspend(ddev->dev);
 624                 if (size < 0)
 625                         return size;
 626         } else {
 627                 pm_runtime_mark_last_busy(ddev->dev);
 628                 pm_runtime_put_autosuspend(ddev->dev);
 629                 return 0;
 630         }
 631
 632         if (size >= PAGE_SIZE)
 633                 size = PAGE_SIZE - 1;
 634
 635         memcpy(buf, table, size);
 636
 637         return size;
 638 }
 639
 640 static ssize_t amdgpu_set_pp_table(struct device *dev,
 641                 struct device_attribute *attr,
 642                 const char *buf,
 643                 size_t count)
 644 {
 645         struct drm_device *ddev = dev_get_drvdata(dev);
 646         struct amdgpu_device *adev = ddev->dev_private;
 647         int ret = 0;
 648
 649         if (adev->in_gpu_reset)
 650                 return -EPERM;
 651
 652         ret = pm_runtime_get_sync(ddev->dev);
 653         if (ret < 0)
 654                 return ret;
 655
 656         if (is_support_sw_smu(adev)) {
 657                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 658                 if (ret) {
 659                         pm_runtime_mark_last_busy(ddev->dev);
 660                         pm_runtime_put_autosuspend(ddev->dev);
 661                         return ret;
 662                 }
 663         } else if (adev->powerplay.pp_funcs->set_pp_table)
 664                 amdgpu_dpm_set_pp_table(adev, buf, count);
 665
 666         pm_runtime_mark_last_busy(ddev->dev);
 667         pm_runtime_put_autosuspend(ddev->dev);
 668
 669         return count;
 670 }
 671
 672 /**
 673  * DOC: pp_od_clk_voltage
 674  *
 675  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 676  * in each power level within a power state.  The pp_od_clk_voltage is used for
 677  * this.
 678  *
 679  * < For Vega10 and previous ASICs >
 680  *
 681  * Reading the file will display:
 682  *
 683  * - a list of engine clock levels and voltages labeled OD_SCLK
 684  *
 685  * - a list of memory clock levels and voltages labeled OD_MCLK
 686  *
 687  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 688  *
 689  * To manually adjust these settings, first select manual using
 690  * power_dpm_force_performance_level. Enter a new value for each
 691  * level by writing a string that contains "s/m level clock voltage" to
 692  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 693  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 694  * 810 mV.  When you have edited all of the states as needed, write
 695  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 696  * default power levels, write "r" (reset) to the file to reset them.
 697  *
 698  *
 699  * < For Vega20 and newer ASICs >
 700  *
 701  * Reading the file will display:
 702  *
 703  * - minimum and maximum engine clock labeled OD_SCLK
 704  *
 705  * - maximum memory clock labeled OD_MCLK
 706  *
 707  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 708  *   They can be used to calibrate the sclk voltage curve.
 709  *
 710  * - a list of valid ranges for sclk, mclk, and voltage curve points
 711  *   labeled OD_RANGE
 712  *
 713  * To manually adjust these settings:
 714  *
 715  * - First select manual using power_dpm_force_performance_level
 716  *
 717  * - For clock frequency setting, enter a new value by writing a
 718  *   string that contains "s/m index clock" to the file. The index
 719  *   should be 0 if to set minimum clock. And 1 if to set maximum
 720  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 721  *   "m 1 800" will update maximum mclk to be 800Mhz.
 722  *
 723  *   For sclk voltage curve, enter the new values by writing a
 724  *   string that contains "vc point clock voltage" to the file. The
 725  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 726  *   update point1 with clock set as 300Mhz and voltage as
 727  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 728  *   as 1000Mhz and voltage 1000mV.
 729  *
 730  * - When you have edited all of the states as needed, write "c" (commit)
 731  *   to the file to commit your changes
 732  *
 733  * - If you want to reset to the default power levels, write "r" (reset)
 734  *   to the file to reset them
 735  *
 736  */
 737
 738 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 739                 struct device_attribute *attr,
 740                 const char *buf,
 741                 size_t count)
 742 {
 743         struct drm_device *ddev = dev_get_drvdata(dev);
 744         struct amdgpu_device *adev = ddev->dev_private;
 745         int ret;
 746         uint32_t parameter_size = 0;
 747         long parameter[64];
 748         char buf_cpy[128];
 749         char *tmp_str;
 750         char *sub_str;
 751         const char delimiter[3] = {' ', '\n', '\0'};
 752         uint32_t type;
 753
 754         if (adev->in_gpu_reset)
 755                 return -EPERM;
 756
 757         if (count > 127)
 758                 return -EINVAL;
 759
 760         if (*buf == 's')
 761                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 762         else if (*buf == 'm')
 763                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 764         else if(*buf == 'r')
 765                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 766         else if (*buf == 'c')
 767                 type = PP_OD_COMMIT_DPM_TABLE;
 768         else if (!strncmp(buf, "vc", 2))
 769                 type = PP_OD_EDIT_VDDC_CURVE;
 770         else
 771                 return -EINVAL;
 772
 773         memcpy(buf_cpy, buf, count+1);
 774
 775         tmp_str = buf_cpy;
 776
 777         if (type == PP_OD_EDIT_VDDC_CURVE)
 778                 tmp_str++;
 779         while (isspace(*++tmp_str));
 780
 781         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 782                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 783                 if (ret)
 784                         return -EINVAL;
 785                 parameter_size++;
 786
 787                 while (isspace(*tmp_str))
 788                         tmp_str++;
 789         }
 790
 791         ret = pm_runtime_get_sync(ddev->dev);
 792         if (ret < 0)
 793                 return ret;
 794
 795         if (is_support_sw_smu(adev)) {
 796                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 797                                             parameter, parameter_size);
 798
 799                 if (ret) {
 800                         pm_runtime_mark_last_busy(ddev->dev);
 801                         pm_runtime_put_autosuspend(ddev->dev);
 802                         return -EINVAL;
 803                 }
 804         } else {
 805                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 806                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 807                                                 parameter, parameter_size);
 808                         if (ret) {
 809                                 pm_runtime_mark_last_busy(ddev->dev);
 810                                 pm_runtime_put_autosuspend(ddev->dev);
 811                                 return -EINVAL;
 812                         }
 813                 }
 814
 815                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 816                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 817                                 amdgpu_dpm_dispatch_task(adev,
 818                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 819                                                 NULL);
 820                                 pm_runtime_mark_last_busy(ddev->dev);
 821                                 pm_runtime_put_autosuspend(ddev->dev);
 822                                 return count;
 823                         } else {
 824                                 pm_runtime_mark_last_busy(ddev->dev);
 825                                 pm_runtime_put_autosuspend(ddev->dev);
 826                                 return -EINVAL;
 827                         }
 828                 }
 829         }
 830         pm_runtime_mark_last_busy(ddev->dev);
 831         pm_runtime_put_autosuspend(ddev->dev);
 832
 833         return count;
 834 }
 835
 836 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 837                 struct device_attribute *attr,
 838                 char *buf)
 839 {
 840         struct drm_device *ddev = dev_get_drvdata(dev);
 841         struct amdgpu_device *adev = ddev->dev_private;
 842         ssize_t size;
 843         int ret;
 844
 845         if (adev->in_gpu_reset)
 846                 return -EPERM;
 847
 848         ret = pm_runtime_get_sync(ddev->dev);
 849         if (ret < 0)
 850                 return ret;
 851
 852         if (is_support_sw_smu(adev)) {
 853                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 854                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 855                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 856                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 857         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 858                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 859                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 860                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 861                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 862         } else {
 863                 size = snprintf(buf, PAGE_SIZE, "\n");
 864         }
 865         pm_runtime_mark_last_busy(ddev->dev);
 866         pm_runtime_put_autosuspend(ddev->dev);
 867
 868         return size;
 869 }
 870
 871 /**
 872  * DOC: pp_features
 873  *
 874  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 875  * features to be enabled. The file pp_features is used for this. And
 876  * this is only available for Vega10 and later dGPUs.
 877  *
 878  * Reading back the file will show you the followings:
 879  * - Current ppfeature masks
 880  * - List of the all supported powerplay features with their naming,
 881  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 882  *
 883  * To manually enable or disable a specific feature, just set or clear
 884  * the corresponding bit from original ppfeature masks and input the
 885  * new ppfeature masks.
 886  */
 887 static ssize_t amdgpu_set_pp_features(struct device *dev,
 888                                       struct device_attribute *attr,
 889                                       const char *buf,
 890                                       size_t count)
 891 {
 892         struct drm_device *ddev = dev_get_drvdata(dev);
 893         struct amdgpu_device *adev = ddev->dev_private;
 894         uint64_t featuremask;
 895         int ret;
 896
 897         if (adev->in_gpu_reset)
 898                 return -EPERM;
 899
 900         ret = kstrtou64(buf, 0, &featuremask);
 901         if (ret)
 902                 return -EINVAL;
 903
 904         pr_debug("featuremask = 0x%llx\n", featuremask);
 905
 906         ret = pm_runtime_get_sync(ddev->dev);
 907         if (ret < 0)
 908                 return ret;
 909
 910         if (is_support_sw_smu(adev)) {
 911                 ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 912                 if (ret) {
 913                         pm_runtime_mark_last_busy(ddev->dev);
 914                         pm_runtime_put_autosuspend(ddev->dev);
 915                         return -EINVAL;
 916                 }
 917         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 918                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 919                 if (ret) {
 920                         pm_runtime_mark_last_busy(ddev->dev);
 921                         pm_runtime_put_autosuspend(ddev->dev);
 922                         return -EINVAL;
 923                 }
 924         }
 925         pm_runtime_mark_last_busy(ddev->dev);
 926         pm_runtime_put_autosuspend(ddev->dev);
 927
 928         return count;
 929 }
 930
 931 static ssize_t amdgpu_get_pp_features(struct device *dev,
 932                                       struct device_attribute *attr,
 933                                       char *buf)
 934 {
 935         struct drm_device *ddev = dev_get_drvdata(dev);
 936         struct amdgpu_device *adev = ddev->dev_private;
 937         ssize_t size;
 938         int ret;
 939
 940         if (adev->in_gpu_reset)
 941                 return -EPERM;
 942
 943         ret = pm_runtime_get_sync(ddev->dev);
 944         if (ret < 0)
 945                 return ret;
 946
 947         if (is_support_sw_smu(adev))
 948                 size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
 949         else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 950                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 951         else
 952                 size = snprintf(buf, PAGE_SIZE, "\n");
 953
 954         pm_runtime_mark_last_busy(ddev->dev);
 955         pm_runtime_put_autosuspend(ddev->dev);
 956
 957         return size;
 958 }
 959
 960 /**
 961  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 962  *
 963  * The amdgpu driver provides a sysfs API for adjusting what power levels
 964  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 965  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 966  * this.
 967  *
 968  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 969  * Vega10 and later ASICs.
 970  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 971  *
 972  * Reading back the files will show you the available power levels within
 973  * the power state and the clock information for those levels.
 974  *
 975  * To manually adjust these states, first select manual using
 976  * power_dpm_force_performance_level.
 977  * Secondly, enter a new value for each level by inputing a string that
 978  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 979  * E.g.,
 980  *
 981  * .. code-block:: bash
 982  *
 983  *      echo "4 5 6" > pp_dpm_sclk
 984  *
 985  * will enable sclk levels 4, 5, and 6.
 986  *
 987  * NOTE: change to the dcefclk max dpm level is not supported now
 988  */
 989
 990 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 991                 struct device_attribute *attr,
 992                 char *buf)
 993 {
 994         struct drm_device *ddev = dev_get_drvdata(dev);
 995         struct amdgpu_device *adev = ddev->dev_private;
 996         ssize_t size;
 997         int ret;
 998
 999         if (adev->in_gpu_reset)
1000                 return -EPERM;
1001
1002         ret = pm_runtime_get_sync(ddev->dev);
1003         if (ret < 0)
1004                 return ret;
1005
1006         if (is_support_sw_smu(adev))
1007                 size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
1008         else if (adev->powerplay.pp_funcs->print_clock_levels)
1009                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
1010         else
1011                 size = snprintf(buf, PAGE_SIZE, "\n");
1012
1013         pm_runtime_mark_last_busy(ddev->dev);
1014         pm_runtime_put_autosuspend(ddev->dev);
1015
1016         return size;
1017 }
1018
1019 /*
1020  * Worst case: 32 bits individually specified, in octal at 12 characters
1021  * per line (+1 for \n).
1022  */
1023 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1024
1025 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1026 {
1027         int ret;
1028         long level;
1029         char *sub_str = NULL;
1030         char *tmp;
1031         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1032         const char delimiter[3] = {' ', '\n', '\0'};
1033         size_t bytes;
1034
1035         *mask = 0;
1036
1037         bytes = min(count, sizeof(buf_cpy) - 1);
1038         memcpy(buf_cpy, buf, bytes);
1039         buf_cpy[bytes] = '\0';
1040         tmp = buf_cpy;
1041         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1042                 if (strlen(sub_str)) {
1043                         ret = kstrtol(sub_str, 0, &level);
1044                         if (ret)
1045                                 return -EINVAL;
1046                         *mask |= 1 << level;
1047                 } else
1048                         break;
1049         }
1050
1051         return 0;
1052 }
1053
1054 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1055                 struct device_attribute *attr,
1056                 const char *buf,
1057                 size_t count)
1058 {
1059         struct drm_device *ddev = dev_get_drvdata(dev);
1060         struct amdgpu_device *adev = ddev->dev_private;
1061         int ret;
1062         uint32_t mask = 0;
1063
1064         if (adev->in_gpu_reset)
1065                 return -EPERM;
1066
1067         ret = amdgpu_read_mask(buf, count, &mask);
1068         if (ret)
1069                 return ret;
1070
1071         ret = pm_runtime_get_sync(ddev->dev);
1072         if (ret < 0)
1073                 return ret;
1074
1075         if (is_support_sw_smu(adev))
1076                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
1077         else if (adev->powerplay.pp_funcs->force_clock_level)
1078                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
1079
1080         pm_runtime_mark_last_busy(ddev->dev);
1081         pm_runtime_put_autosuspend(ddev->dev);
1082
1083         if (ret)
1084                 return -EINVAL;
1085
1086         return count;
1087 }
1088
1089 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1090                 struct device_attribute *attr,
1091                 char *buf)
1092 {
1093         struct drm_device *ddev = dev_get_drvdata(dev);
1094         struct amdgpu_device *adev = ddev->dev_private;
1095         ssize_t size;
1096         int ret;
1097
1098         if (adev->in_gpu_reset)
1099                 return -EPERM;
1100
1101         ret = pm_runtime_get_sync(ddev->dev);
1102         if (ret < 0)
1103                 return ret;
1104
1105         if (is_support_sw_smu(adev))
1106                 size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
1107         else if (adev->powerplay.pp_funcs->print_clock_levels)
1108                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
1109         else
1110                 size = snprintf(buf, PAGE_SIZE, "\n");
1111
1112         pm_runtime_mark_last_busy(ddev->dev);
1113         pm_runtime_put_autosuspend(ddev->dev);
1114
1115         return size;
1116 }
1117
1118 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1119                 struct device_attribute *attr,
1120                 const char *buf,
1121                 size_t count)
1122 {
1123         struct drm_device *ddev = dev_get_drvdata(dev);
1124         struct amdgpu_device *adev = ddev->dev_private;
1125         uint32_t mask = 0;
1126         int ret;
1127
1128         if (adev->in_gpu_reset)
1129                 return -EPERM;
1130
1131         ret = amdgpu_read_mask(buf, count, &mask);
1132         if (ret)
1133                 return ret;
1134
1135         ret = pm_runtime_get_sync(ddev->dev);
1136         if (ret < 0)
1137                 return ret;
1138
1139         if (is_support_sw_smu(adev))
1140                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
1141         else if (adev->powerplay.pp_funcs->force_clock_level)
1142                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
1143
1144         pm_runtime_mark_last_busy(ddev->dev);
1145         pm_runtime_put_autosuspend(ddev->dev);
1146
1147         if (ret)
1148                 return -EINVAL;
1149
1150         return count;
1151 }
1152
1153 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1154                 struct device_attribute *attr,
1155                 char *buf)
1156 {
1157         struct drm_device *ddev = dev_get_drvdata(dev);
1158         struct amdgpu_device *adev = ddev->dev_private;
1159         ssize_t size;
1160         int ret;
1161
1162         if (adev->in_gpu_reset)
1163                 return -EPERM;
1164
1165         ret = pm_runtime_get_sync(ddev->dev);
1166         if (ret < 0)
1167                 return ret;
1168
1169         if (is_support_sw_smu(adev))
1170                 size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
1171         else if (adev->powerplay.pp_funcs->print_clock_levels)
1172                 size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
1173         else
1174                 size = snprintf(buf, PAGE_SIZE, "\n");
1175
1176         pm_runtime_mark_last_busy(ddev->dev);
1177         pm_runtime_put_autosuspend(ddev->dev);
1178
1179         return size;
1180 }
1181
1182 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1183                 struct device_attribute *attr,
1184                 const char *buf,
1185                 size_t count)
1186 {
1187         struct drm_device *ddev = dev_get_drvdata(dev);
1188         struct amdgpu_device *adev = ddev->dev_private;
1189         int ret;
1190         uint32_t mask = 0;
1191
1192         if (adev->in_gpu_reset)
1193                 return -EPERM;
1194
1195         ret = amdgpu_read_mask(buf, count, &mask);
1196         if (ret)
1197                 return ret;
1198
1199         ret = pm_runtime_get_sync(ddev->dev);
1200         if (ret < 0)
1201                 return ret;
1202
1203         if (is_support_sw_smu(adev))
1204                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
1205         else if (adev->powerplay.pp_funcs->force_clock_level)
1206                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
1207         else
1208                 ret = 0;
1209
1210         pm_runtime_mark_last_busy(ddev->dev);
1211         pm_runtime_put_autosuspend(ddev->dev);
1212
1213         if (ret)
1214                 return -EINVAL;
1215
1216         return count;
1217 }
1218
1219 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1220                 struct device_attribute *attr,
1221                 char *buf)
1222 {
1223         struct drm_device *ddev = dev_get_drvdata(dev);
1224         struct amdgpu_device *adev = ddev->dev_private;
1225         ssize_t size;
1226         int ret;
1227
1228         if (adev->in_gpu_reset)
1229                 return -EPERM;
1230
1231         ret = pm_runtime_get_sync(ddev->dev);
1232         if (ret < 0)
1233                 return ret;
1234
1235         if (is_support_sw_smu(adev))
1236                 size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1237         else if (adev->powerplay.pp_funcs->print_clock_levels)
1238                 size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1239         else
1240                 size = snprintf(buf, PAGE_SIZE, "\n");
1241
1242         pm_runtime_mark_last_busy(ddev->dev);
1243         pm_runtime_put_autosuspend(ddev->dev);
1244
1245         return size;
1246 }
1247
1248 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1249                 struct device_attribute *attr,
1250                 const char *buf,
1251                 size_t count)
1252 {
1253         struct drm_device *ddev = dev_get_drvdata(dev);
1254         struct amdgpu_device *adev = ddev->dev_private;
1255         int ret;
1256         uint32_t mask = 0;
1257
1258         if (adev->in_gpu_reset)
1259                 return -EPERM;
1260
1261         ret = amdgpu_read_mask(buf, count, &mask);
1262         if (ret)
1263                 return ret;
1264
1265         ret = pm_runtime_get_sync(ddev->dev);
1266         if (ret < 0)
1267                 return ret;
1268
1269         if (is_support_sw_smu(adev))
1270                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
1271         else if (adev->powerplay.pp_funcs->force_clock_level)
1272                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1273         else
1274                 ret = 0;
1275
1276         pm_runtime_mark_last_busy(ddev->dev);
1277         pm_runtime_put_autosuspend(ddev->dev);
1278
1279         if (ret)
1280                 return -EINVAL;
1281
1282         return count;
1283 }
1284
1285 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1286                 struct device_attribute *attr,
1287                 char *buf)
1288 {
1289         struct drm_device *ddev = dev_get_drvdata(dev);
1290         struct amdgpu_device *adev = ddev->dev_private;
1291         ssize_t size;
1292         int ret;
1293
1294         if (adev->in_gpu_reset)
1295                 return -EPERM;
1296
1297         ret = pm_runtime_get_sync(ddev->dev);
1298         if (ret < 0)
1299                 return ret;
1300
1301         if (is_support_sw_smu(adev))
1302                 size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1303         else if (adev->powerplay.pp_funcs->print_clock_levels)
1304                 size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1305         else
1306                 size = snprintf(buf, PAGE_SIZE, "\n");
1307
1308         pm_runtime_mark_last_busy(ddev->dev);
1309         pm_runtime_put_autosuspend(ddev->dev);
1310
1311         return size;
1312 }
1313
1314 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1315                 struct device_attribute *attr,
1316                 const char *buf,
1317                 size_t count)
1318 {
1319         struct drm_device *ddev = dev_get_drvdata(dev);
1320         struct amdgpu_device *adev = ddev->dev_private;
1321         int ret;
1322         uint32_t mask = 0;
1323
1324         if (adev->in_gpu_reset)
1325                 return -EPERM;
1326
1327         ret = amdgpu_read_mask(buf, count, &mask);
1328         if (ret)
1329                 return ret;
1330
1331         ret = pm_runtime_get_sync(ddev->dev);
1332         if (ret < 0)
1333                 return ret;
1334
1335         if (is_support_sw_smu(adev))
1336                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
1337         else if (adev->powerplay.pp_funcs->force_clock_level)
1338                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1339         else
1340                 ret = 0;
1341
1342         pm_runtime_mark_last_busy(ddev->dev);
1343         pm_runtime_put_autosuspend(ddev->dev);
1344
1345         if (ret)
1346                 return -EINVAL;
1347
1348         return count;
1349 }
1350
1351 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1352                 struct device_attribute *attr,
1353                 char *buf)
1354 {
1355         struct drm_device *ddev = dev_get_drvdata(dev);
1356         struct amdgpu_device *adev = ddev->dev_private;
1357         ssize_t size;
1358         int ret;
1359
1360         if (adev->in_gpu_reset)
1361                 return -EPERM;
1362
1363         ret = pm_runtime_get_sync(ddev->dev);
1364         if (ret < 0)
1365                 return ret;
1366
1367         if (is_support_sw_smu(adev))
1368                 size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1369         else if (adev->powerplay.pp_funcs->print_clock_levels)
1370                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1371         else
1372                 size = snprintf(buf, PAGE_SIZE, "\n");
1373
1374         pm_runtime_mark_last_busy(ddev->dev);
1375         pm_runtime_put_autosuspend(ddev->dev);
1376
1377         return size;
1378 }
1379
1380 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1381                 struct device_attribute *attr,
1382                 const char *buf,
1383                 size_t count)
1384 {
1385         struct drm_device *ddev = dev_get_drvdata(dev);
1386         struct amdgpu_device *adev = ddev->dev_private;
1387         int ret;
1388         uint32_t mask = 0;
1389
1390         if (adev->in_gpu_reset)
1391                 return -EPERM;
1392
1393         ret = amdgpu_read_mask(buf, count, &mask);
1394         if (ret)
1395                 return ret;
1396
1397         ret = pm_runtime_get_sync(ddev->dev);
1398         if (ret < 0)
1399                 return ret;
1400
1401         if (is_support_sw_smu(adev))
1402                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
1403         else if (adev->powerplay.pp_funcs->force_clock_level)
1404                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1405         else
1406                 ret = 0;
1407
1408         pm_runtime_mark_last_busy(ddev->dev);
1409         pm_runtime_put_autosuspend(ddev->dev);
1410
1411         if (ret)
1412                 return -EINVAL;
1413
1414         return count;
1415 }
1416
1417 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1418                 struct device_attribute *attr,
1419                 char *buf)
1420 {
1421         struct drm_device *ddev = dev_get_drvdata(dev);
1422         struct amdgpu_device *adev = ddev->dev_private;
1423         uint32_t value = 0;
1424         int ret;
1425
1426         if (adev->in_gpu_reset)
1427                 return -EPERM;
1428
1429         ret = pm_runtime_get_sync(ddev->dev);
1430         if (ret < 0)
1431                 return ret;
1432
1433         if (is_support_sw_smu(adev))
1434                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
1435         else if (adev->powerplay.pp_funcs->get_sclk_od)
1436                 value = amdgpu_dpm_get_sclk_od(adev);
1437
1438         pm_runtime_mark_last_busy(ddev->dev);
1439         pm_runtime_put_autosuspend(ddev->dev);
1440
1441         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1442 }
1443
1444 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1445                 struct device_attribute *attr,
1446                 const char *buf,
1447                 size_t count)
1448 {
1449         struct drm_device *ddev = dev_get_drvdata(dev);
1450         struct amdgpu_device *adev = ddev->dev_private;
1451         int ret;
1452         long int value;
1453
1454         if (adev->in_gpu_reset)
1455                 return -EPERM;
1456
1457         ret = kstrtol(buf, 0, &value);
1458
1459         if (ret)
1460                 return -EINVAL;
1461
1462         ret = pm_runtime_get_sync(ddev->dev);
1463         if (ret < 0)
1464                 return ret;
1465
1466         if (is_support_sw_smu(adev)) {
1467                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
1468         } else {
1469                 if (adev->powerplay.pp_funcs->set_sclk_od)
1470                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1471
1472                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1473                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1474                 } else {
1475                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1476                         amdgpu_pm_compute_clocks(adev);
1477                 }
1478         }
1479
1480         pm_runtime_mark_last_busy(ddev->dev);
1481         pm_runtime_put_autosuspend(ddev->dev);
1482
1483         return count;
1484 }
1485
1486 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1487                 struct device_attribute *attr,
1488                 char *buf)
1489 {
1490         struct drm_device *ddev = dev_get_drvdata(dev);
1491         struct amdgpu_device *adev = ddev->dev_private;
1492         uint32_t value = 0;
1493         int ret;
1494
1495         if (adev->in_gpu_reset)
1496                 return -EPERM;
1497
1498         ret = pm_runtime_get_sync(ddev->dev);
1499         if (ret < 0)
1500                 return ret;
1501
1502         if (is_support_sw_smu(adev))
1503                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
1504         else if (adev->powerplay.pp_funcs->get_mclk_od)
1505                 value = amdgpu_dpm_get_mclk_od(adev);
1506
1507         pm_runtime_mark_last_busy(ddev->dev);
1508         pm_runtime_put_autosuspend(ddev->dev);
1509
1510         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1511 }
1512
1513 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1514                 struct device_attribute *attr,
1515                 const char *buf,
1516                 size_t count)
1517 {
1518         struct drm_device *ddev = dev_get_drvdata(dev);
1519         struct amdgpu_device *adev = ddev->dev_private;
1520         int ret;
1521         long int value;
1522
1523         if (adev->in_gpu_reset)
1524                 return -EPERM;
1525
1526         ret = kstrtol(buf, 0, &value);
1527
1528         if (ret)
1529                 return -EINVAL;
1530
1531         ret = pm_runtime_get_sync(ddev->dev);
1532         if (ret < 0)
1533                 return ret;
1534
1535         if (is_support_sw_smu(adev)) {
1536                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
1537         } else {
1538                 if (adev->powerplay.pp_funcs->set_mclk_od)
1539                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1540
1541                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1542                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1543                 } else {
1544                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1545                         amdgpu_pm_compute_clocks(adev);
1546                 }
1547         }
1548
1549         pm_runtime_mark_last_busy(ddev->dev);
1550         pm_runtime_put_autosuspend(ddev->dev);
1551
1552         return count;
1553 }
1554
1555 /**
1556  * DOC: pp_power_profile_mode
1557  *
1558  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1559  * related to switching between power levels in a power state.  The file
1560  * pp_power_profile_mode is used for this.
1561  *
1562  * Reading this file outputs a list of all of the predefined power profiles
1563  * and the relevant heuristics settings for that profile.
1564  *
1565  * To select a profile or create a custom profile, first select manual using
1566  * power_dpm_force_performance_level.  Writing the number of a predefined
1567  * profile to pp_power_profile_mode will enable those heuristics.  To
1568  * create a custom set of heuristics, write a string of numbers to the file
1569  * starting with the number of the custom profile along with a setting
1570  * for each heuristic parameter.  Due to differences across asic families
1571  * the heuristic parameters vary from family to family.
1572  *
1573  */
1574
1575 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1576                 struct device_attribute *attr,
1577                 char *buf)
1578 {
1579         struct drm_device *ddev = dev_get_drvdata(dev);
1580         struct amdgpu_device *adev = ddev->dev_private;
1581         ssize_t size;
1582         int ret;
1583
1584         if (adev->in_gpu_reset)
1585                 return -EPERM;
1586
1587         ret = pm_runtime_get_sync(ddev->dev);
1588         if (ret < 0)
1589                 return ret;
1590
1591         if (is_support_sw_smu(adev))
1592                 size = smu_get_power_profile_mode(&adev->smu, buf);
1593         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1594                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1595         else
1596                 size = snprintf(buf, PAGE_SIZE, "\n");
1597
1598         pm_runtime_mark_last_busy(ddev->dev);
1599         pm_runtime_put_autosuspend(ddev->dev);
1600
1601         return size;
1602 }
1603
1604
1605 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1606                 struct device_attribute *attr,
1607                 const char *buf,
1608                 size_t count)
1609 {
1610         int ret = 0xff;
1611         struct drm_device *ddev = dev_get_drvdata(dev);
1612         struct amdgpu_device *adev = ddev->dev_private;
1613         uint32_t parameter_size = 0;
1614         long parameter[64];
1615         char *sub_str, buf_cpy[128];
1616         char *tmp_str;
1617         uint32_t i = 0;
1618         char tmp[2];
1619         long int profile_mode = 0;
1620         const char delimiter[3] = {' ', '\n', '\0'};
1621
1622         if (adev->in_gpu_reset)
1623                 return -EPERM;
1624
1625         tmp[0] = *(buf);
1626         tmp[1] = '\0';
1627         ret = kstrtol(tmp, 0, &profile_mode);
1628         if (ret)
1629                 return -EINVAL;
1630
1631         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1632                 if (count < 2 || count > 127)
1633                         return -EINVAL;
1634                 while (isspace(*++buf))
1635                         i++;
1636                 memcpy(buf_cpy, buf, count-i);
1637                 tmp_str = buf_cpy;
1638                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1639                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1640                         if (ret)
1641                                 return -EINVAL;
1642                         parameter_size++;
1643                         while (isspace(*tmp_str))
1644                                 tmp_str++;
1645                 }
1646         }
1647         parameter[parameter_size] = profile_mode;
1648
1649         ret = pm_runtime_get_sync(ddev->dev);
1650         if (ret < 0)
1651                 return ret;
1652
1653         if (is_support_sw_smu(adev))
1654                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
1655         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1656                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1657
1658         pm_runtime_mark_last_busy(ddev->dev);
1659         pm_runtime_put_autosuspend(ddev->dev);
1660
1661         if (!ret)
1662                 return count;
1663
1664         return -EINVAL;
1665 }
1666
1667 /**
1668  * DOC: gpu_busy_percent
1669  *
1670  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1671  * is as a percentage.  The file gpu_busy_percent is used for this.
1672  * The SMU firmware computes a percentage of load based on the
1673  * aggregate activity level in the IP cores.
1674  */
1675 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1676                                            struct device_attribute *attr,
1677                                            char *buf)
1678 {
1679         struct drm_device *ddev = dev_get_drvdata(dev);
1680         struct amdgpu_device *adev = ddev->dev_private;
1681         int r, value, size = sizeof(value);
1682
1683         if (adev->in_gpu_reset)
1684                 return -EPERM;
1685
1686         r = pm_runtime_get_sync(ddev->dev);
1687         if (r < 0)
1688                 return r;
1689
1690         /* read the IP busy sensor */
1691         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1692                                    (void *)&value, &size);
1693
1694         pm_runtime_mark_last_busy(ddev->dev);
1695         pm_runtime_put_autosuspend(ddev->dev);
1696
1697         if (r)
1698                 return r;
1699
1700         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1701 }
1702
1703 /**
1704  * DOC: mem_busy_percent
1705  *
1706  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1707  * is as a percentage.  The file mem_busy_percent is used for this.
1708  * The SMU firmware computes a percentage of load based on the
1709  * aggregate activity level in the IP cores.
1710  */
1711 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1712                                            struct device_attribute *attr,
1713                                            char *buf)
1714 {
1715         struct drm_device *ddev = dev_get_drvdata(dev);
1716         struct amdgpu_device *adev = ddev->dev_private;
1717         int r, value, size = sizeof(value);
1718
1719         if (adev->in_gpu_reset)
1720                 return -EPERM;
1721
1722         r = pm_runtime_get_sync(ddev->dev);
1723         if (r < 0)
1724                 return r;
1725
1726         /* read the IP busy sensor */
1727         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1728                                    (void *)&value, &size);
1729
1730         pm_runtime_mark_last_busy(ddev->dev);
1731         pm_runtime_put_autosuspend(ddev->dev);
1732
1733         if (r)
1734                 return r;
1735
1736         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1737 }
1738
1739 /**
1740  * DOC: pcie_bw
1741  *
1742  * The amdgpu driver provides a sysfs API for estimating how much data
1743  * has been received and sent by the GPU in the last second through PCIe.
1744  * The file pcie_bw is used for this.
1745  * The Perf counters count the number of received and sent messages and return
1746  * those values, as well as the maximum payload size of a PCIe packet (mps).
1747  * Note that it is not possible to easily and quickly obtain the size of each
1748  * packet transmitted, so we output the max payload size (mps) to allow for
1749  * quick estimation of the PCIe bandwidth usage
1750  */
1751 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1752                 struct device_attribute *attr,
1753                 char *buf)
1754 {
1755         struct drm_device *ddev = dev_get_drvdata(dev);
1756         struct amdgpu_device *adev = ddev->dev_private;
1757         uint64_t count0 = 0, count1 = 0;
1758         int ret;
1759
1760         if (adev->in_gpu_reset)
1761                 return -EPERM;
1762
1763         if (adev->flags & AMD_IS_APU)
1764                 return -ENODATA;
1765
1766         if (!adev->asic_funcs->get_pcie_usage)
1767                 return -ENODATA;
1768
1769         ret = pm_runtime_get_sync(ddev->dev);
1770         if (ret < 0)
1771                 return ret;
1772
1773         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1774
1775         pm_runtime_mark_last_busy(ddev->dev);
1776         pm_runtime_put_autosuspend(ddev->dev);
1777
1778         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1779                         count0, count1, pcie_get_mps(adev->pdev));
1780 }
1781
1782 /**
1783  * DOC: unique_id
1784  *
1785  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1786  * The file unique_id is used for this.
1787  * This will provide a Unique ID that will persist from machine to machine
1788  *
1789  * NOTE: This will only work for GFX9 and newer. This file will be absent
1790  * on unsupported ASICs (GFX8 and older)
1791  */
1792 static ssize_t amdgpu_get_unique_id(struct device *dev,
1793                 struct device_attribute *attr,
1794                 char *buf)
1795 {
1796         struct drm_device *ddev = dev_get_drvdata(dev);
1797         struct amdgpu_device *adev = ddev->dev_private;
1798
1799         if (adev->in_gpu_reset)
1800                 return -EPERM;
1801
1802         if (adev->unique_id)
1803                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1804
1805         return 0;
1806 }
1807
1808 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1809         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1810         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1811         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC),
1812         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC),
1813         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC),
1814         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC),
1815         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1816         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1817         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1818         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1819         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC),
1820         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC),
1821         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
1822         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
1823         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC),
1824         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
1825         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC),
1826         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC),
1827         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
1828         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC),
1829         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC),
1830 };
1831
1832 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1833                                uint32_t mask, enum amdgpu_device_attr_states *states)
1834 {
1835         struct device_attribute *dev_attr = &attr->dev_attr;
1836         const char *attr_name = dev_attr->attr.name;
1837         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
1838         enum amd_asic_type asic_type = adev->asic_type;
1839
1840         if (!(attr->flags & mask)) {
1841                 *states = ATTR_STATE_UNSUPPORTED;
1842                 return 0;
1843         }
1844
1845 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
1846
1847         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
1848                 if (asic_type < CHIP_VEGA10)
1849                         *states = ATTR_STATE_UNSUPPORTED;
1850         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
1851                 if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
1852                         *states = ATTR_STATE_UNSUPPORTED;
1853         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
1854                 if (asic_type < CHIP_VEGA20)
1855                         *states = ATTR_STATE_UNSUPPORTED;
1856         } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
1857                 if (asic_type == CHIP_ARCTURUS)
1858                         *states = ATTR_STATE_UNSUPPORTED;
1859         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
1860                 *states = ATTR_STATE_UNSUPPORTED;
1861                 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
1862                     (!is_support_sw_smu(adev) && hwmgr->od_enabled))
1863                         *states = ATTR_STATE_SUPPORTED;
1864         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
1865                 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
1866                         *states = ATTR_STATE_UNSUPPORTED;
1867         } else if (DEVICE_ATTR_IS(pcie_bw)) {
1868                 /* PCIe Perf counters won't work on APU nodes */
1869                 if (adev->flags & AMD_IS_APU)
1870                         *states = ATTR_STATE_UNSUPPORTED;
1871         } else if (DEVICE_ATTR_IS(unique_id)) {
1872                 if (!adev->unique_id)
1873                         *states = ATTR_STATE_UNSUPPORTED;
1874         } else if (DEVICE_ATTR_IS(pp_features)) {
1875                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
1876                         *states = ATTR_STATE_UNSUPPORTED;
1877         }
1878
1879         if (asic_type == CHIP_ARCTURUS) {
1880                 /* Arcturus does not support standalone mclk/socclk/fclk level setting */
1881                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
1882                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
1883                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
1884                         dev_attr->attr.mode &= ~S_IWUGO;
1885                         dev_attr->store = NULL;
1886                 }
1887         }
1888
1889 #undef DEVICE_ATTR_IS
1890
1891         return 0;
1892 }
1893
1894
1895 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
1896                                      struct amdgpu_device_attr *attr,
1897                                      uint32_t mask, struct list_head *attr_list)
1898 {
1899         int ret = 0;
1900         struct device_attribute *dev_attr = &attr->dev_attr;
1901         const char *name = dev_attr->attr.name;
1902         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
1903         struct amdgpu_device_attr_entry *attr_entry;
1904
1905         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1906                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
1907
1908         BUG_ON(!attr);
1909
1910         attr_update = attr->attr_update ? attr_update : default_attr_update;
1911
1912         ret = attr_update(adev, attr, mask, &attr_states);
1913         if (ret) {
1914                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
1915                         name, ret);
1916                 return ret;
1917         }
1918
1919         if (attr_states == ATTR_STATE_UNSUPPORTED)
1920                 return 0;
1921
1922         ret = device_create_file(adev->dev, dev_attr);
1923         if (ret) {
1924                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
1925                         name, ret);
1926         }
1927
1928         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
1929         if (!attr_entry)
1930                 return -ENOMEM;
1931
1932         attr_entry->attr = attr;
1933         INIT_LIST_HEAD(&attr_entry->entry);
1934
1935         list_add_tail(&attr_entry->entry, attr_list);
1936
1937         return ret;
1938 }
1939
1940 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
1941 {
1942         struct device_attribute *dev_attr = &attr->dev_attr;
1943
1944         device_remove_file(adev->dev, dev_attr);
1945 }
1946
1947 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
1948                                              struct list_head *attr_list);
1949
1950 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
1951                                             struct amdgpu_device_attr *attrs,
1952                                             uint32_t counts,
1953                                             uint32_t mask,
1954                                             struct list_head *attr_list)
1955 {
1956         int ret = 0;
1957         uint32_t i = 0;
1958
1959         for (i = 0; i < counts; i++) {
1960                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
1961                 if (ret)
1962                         goto failed;
1963         }
1964
1965         return 0;
1966
1967 failed:
1968         amdgpu_device_attr_remove_groups(adev, attr_list);
1969
1970         return ret;
1971 }
1972
1973 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
1974                                              struct list_head *attr_list)
1975 {
1976         struct amdgpu_device_attr_entry *entry, *entry_tmp;
1977
1978         if (list_empty(attr_list))
1979                 return ;
1980
1981         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
1982                 amdgpu_device_attr_remove(adev, entry->attr);
1983                 list_del(&entry->entry);
1984                 kfree(entry);
1985         }
1986 }
1987
1988 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1989                                       struct device_attribute *attr,
1990                                       char *buf)
1991 {
1992         struct amdgpu_device *adev = dev_get_drvdata(dev);
1993         int channel = to_sensor_dev_attr(attr)->index;
1994         int r, temp = 0, size = sizeof(temp);
1995
1996         if (adev->in_gpu_reset)
1997                 return -EPERM;
1998
1999         if (channel >= PP_TEMP_MAX)
2000                 return -EINVAL;
2001
2002         r = pm_runtime_get_sync(adev->ddev->dev);
2003         if (r < 0)
2004                 return r;
2005
2006         switch (channel) {
2007         case PP_TEMP_JUNCTION:
2008                 /* get current junction temperature */
2009                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2010                                            (void *)&temp, &size);
2011                 break;
2012         case PP_TEMP_EDGE:
2013                 /* get current edge temperature */
2014                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2015                                            (void *)&temp, &size);
2016                 break;
2017         case PP_TEMP_MEM:
2018                 /* get current memory temperature */
2019                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2020                                            (void *)&temp, &size);
2021                 break;
2022         default:
2023                 r = -EINVAL;
2024                 break;
2025         }
2026
2027         pm_runtime_mark_last_busy(adev->ddev->dev);
2028         pm_runtime_put_autosuspend(adev->ddev->dev);
2029
2030         if (r)
2031                 return r;
2032
2033         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2034 }
2035
2036 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2037                                              struct device_attribute *attr,
2038                                              char *buf)
2039 {
2040         struct amdgpu_device *adev = dev_get_drvdata(dev);
2041         int hyst = to_sensor_dev_attr(attr)->index;
2042         int temp;
2043
2044         if (hyst)
2045                 temp = adev->pm.dpm.thermal.min_temp;
2046         else
2047                 temp = adev->pm.dpm.thermal.max_temp;
2048
2049         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2050 }
2051
2052 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2053                                              struct device_attribute *attr,
2054                                              char *buf)
2055 {
2056         struct amdgpu_device *adev = dev_get_drvdata(dev);
2057         int hyst = to_sensor_dev_attr(attr)->index;
2058         int temp;
2059
2060         if (hyst)
2061                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2062         else
2063                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2064
2065         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2066 }
2067
2068 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2069                                              struct device_attribute *attr,
2070                                              char *buf)
2071 {
2072         struct amdgpu_device *adev = dev_get_drvdata(dev);
2073         int hyst = to_sensor_dev_attr(attr)->index;
2074         int temp;
2075
2076         if (hyst)
2077                 temp = adev->pm.dpm.thermal.min_mem_temp;
2078         else
2079                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2080
2081         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2082 }
2083
2084 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2085                                              struct device_attribute *attr,
2086                                              char *buf)
2087 {
2088         int channel = to_sensor_dev_attr(attr)->index;
2089
2090         if (channel >= PP_TEMP_MAX)
2091                 return -EINVAL;
2092
2093         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
2094 }
2095
2096 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2097                                              struct device_attribute *attr,
2098                                              char *buf)
2099 {
2100         struct amdgpu_device *adev = dev_get_drvdata(dev);
2101         int channel = to_sensor_dev_attr(attr)->index;
2102         int temp = 0;
2103
2104         if (channel >= PP_TEMP_MAX)
2105                 return -EINVAL;
2106
2107         switch (channel) {
2108         case PP_TEMP_JUNCTION:
2109                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2110                 break;
2111         case PP_TEMP_EDGE:
2112                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2113                 break;
2114         case PP_TEMP_MEM:
2115                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2116                 break;
2117         }
2118
2119         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2120 }
2121
2122 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2123                                             struct device_attribute *attr,
2124                                             char *buf)
2125 {
2126         struct amdgpu_device *adev = dev_get_drvdata(dev);
2127         u32 pwm_mode = 0;
2128         int ret;
2129
2130         if (adev->in_gpu_reset)
2131                 return -EPERM;
2132
2133         ret = pm_runtime_get_sync(adev->ddev->dev);
2134         if (ret < 0)
2135                 return ret;
2136
2137         if (is_support_sw_smu(adev)) {
2138                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2139         } else {
2140                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2141                         pm_runtime_mark_last_busy(adev->ddev->dev);
2142                         pm_runtime_put_autosuspend(adev->ddev->dev);
2143                         return -EINVAL;
2144                 }
2145
2146                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2147         }
2148
2149         pm_runtime_mark_last_busy(adev->ddev->dev);
2150         pm_runtime_put_autosuspend(adev->ddev->dev);
2151
2152         return sprintf(buf, "%i\n", pwm_mode);
2153 }
2154
2155 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2156                                             struct device_attribute *attr,
2157                                             const char *buf,
2158                                             size_t count)
2159 {
2160         struct amdgpu_device *adev = dev_get_drvdata(dev);
2161         int err, ret;
2162         int value;
2163
2164         if (adev->in_gpu_reset)
2165                 return -EPERM;
2166
2167         err = kstrtoint(buf, 10, &value);
2168         if (err)
2169                 return err;
2170
2171         ret = pm_runtime_get_sync(adev->ddev->dev);
2172         if (ret < 0)
2173                 return ret;
2174
2175         if (is_support_sw_smu(adev)) {
2176                 smu_set_fan_control_mode(&adev->smu, value);
2177         } else {
2178                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2179                         pm_runtime_mark_last_busy(adev->ddev->dev);
2180                         pm_runtime_put_autosuspend(adev->ddev->dev);
2181                         return -EINVAL;
2182                 }
2183
2184                 amdgpu_dpm_set_fan_control_mode(adev, value);
2185         }
2186
2187         pm_runtime_mark_last_busy(adev->ddev->dev);
2188         pm_runtime_put_autosuspend(adev->ddev->dev);
2189
2190         return count;
2191 }
2192
2193 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2194                                          struct device_attribute *attr,
2195                                          char *buf)
2196 {
2197         return sprintf(buf, "%i\n", 0);
2198 }
2199
2200 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2201                                          struct device_attribute *attr,
2202                                          char *buf)
2203 {
2204         return sprintf(buf, "%i\n", 255);
2205 }
2206
2207 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2208                                      struct device_attribute *attr,
2209                                      const char *buf, size_t count)
2210 {
2211         struct amdgpu_device *adev = dev_get_drvdata(dev);
2212         int err;
2213         u32 value;
2214         u32 pwm_mode;
2215
2216         if (adev->in_gpu_reset)
2217                 return -EPERM;
2218
2219         err = pm_runtime_get_sync(adev->ddev->dev);
2220         if (err < 0)
2221                 return err;
2222
2223         if (is_support_sw_smu(adev))
2224                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2225         else
2226                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2227
2228         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2229                 pr_info("manual fan speed control should be enabled first\n");
2230                 pm_runtime_mark_last_busy(adev->ddev->dev);
2231                 pm_runtime_put_autosuspend(adev->ddev->dev);
2232                 return -EINVAL;
2233         }
2234
2235         err = kstrtou32(buf, 10, &value);
2236         if (err) {
2237                 pm_runtime_mark_last_busy(adev->ddev->dev);
2238                 pm_runtime_put_autosuspend(adev->ddev->dev);
2239                 return err;
2240         }
2241
2242         value = (value * 100) / 255;
2243
2244         if (is_support_sw_smu(adev))
2245                 err = smu_set_fan_speed_percent(&adev->smu, value);
2246         else if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2247                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2248         else
2249                 err = -EINVAL;
2250
2251         pm_runtime_mark_last_busy(adev->ddev->dev);
2252         pm_runtime_put_autosuspend(adev->ddev->dev);
2253
2254         if (err)
2255                 return err;
2256
2257         return count;
2258 }
2259
2260 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2261                                      struct device_attribute *attr,
2262                                      char *buf)
2263 {
2264         struct amdgpu_device *adev = dev_get_drvdata(dev);
2265         int err;
2266         u32 speed = 0;
2267
2268         if (adev->in_gpu_reset)
2269                 return -EPERM;
2270
2271         err = pm_runtime_get_sync(adev->ddev->dev);
2272         if (err < 0)
2273                 return err;
2274
2275         if (is_support_sw_smu(adev))
2276                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
2277         else if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2278                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2279         else
2280                 err = -EINVAL;
2281
2282         pm_runtime_mark_last_busy(adev->ddev->dev);
2283         pm_runtime_put_autosuspend(adev->ddev->dev);
2284
2285         if (err)
2286                 return err;
2287
2288         speed = (speed * 255) / 100;
2289
2290         return sprintf(buf, "%i\n", speed);
2291 }
2292
2293 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2294                                            struct device_attribute *attr,
2295                                            char *buf)
2296 {
2297         struct amdgpu_device *adev = dev_get_drvdata(dev);
2298         int err;
2299         u32 speed = 0;
2300
2301         if (adev->in_gpu_reset)
2302                 return -EPERM;
2303
2304         err = pm_runtime_get_sync(adev->ddev->dev);
2305         if (err < 0)
2306                 return err;
2307
2308         if (is_support_sw_smu(adev))
2309                 err = smu_get_fan_speed_rpm(&adev->smu, &speed);
2310         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2311                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2312         else
2313                 err = -EINVAL;
2314
2315         pm_runtime_mark_last_busy(adev->ddev->dev);
2316         pm_runtime_put_autosuspend(adev->ddev->dev);
2317
2318         if (err)
2319                 return err;
2320
2321         return sprintf(buf, "%i\n", speed);
2322 }
2323
2324 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2325                                          struct device_attribute *attr,
2326                                          char *buf)
2327 {
2328         struct amdgpu_device *adev = dev_get_drvdata(dev);
2329         u32 min_rpm = 0;
2330         u32 size = sizeof(min_rpm);
2331         int r;
2332
2333         if (adev->in_gpu_reset)
2334                 return -EPERM;
2335
2336         r = pm_runtime_get_sync(adev->ddev->dev);
2337         if (r < 0)
2338                 return r;
2339
2340         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2341                                    (void *)&min_rpm, &size);
2342
2343         pm_runtime_mark_last_busy(adev->ddev->dev);
2344         pm_runtime_put_autosuspend(adev->ddev->dev);
2345
2346         if (r)
2347                 return r;
2348
2349         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
2350 }
2351
2352 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2353                                          struct device_attribute *attr,
2354                                          char *buf)
2355 {
2356         struct amdgpu_device *adev = dev_get_drvdata(dev);
2357         u32 max_rpm = 0;
2358         u32 size = sizeof(max_rpm);
2359         int r;
2360
2361         if (adev->in_gpu_reset)
2362                 return -EPERM;
2363
2364         r = pm_runtime_get_sync(adev->ddev->dev);
2365         if (r < 0)
2366                 return r;
2367
2368         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2369                                    (void *)&max_rpm, &size);
2370
2371         pm_runtime_mark_last_busy(adev->ddev->dev);
2372         pm_runtime_put_autosuspend(adev->ddev->dev);
2373
2374         if (r)
2375                 return r;
2376
2377         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
2378 }
2379
2380 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2381                                            struct device_attribute *attr,
2382                                            char *buf)
2383 {
2384         struct amdgpu_device *adev = dev_get_drvdata(dev);
2385         int err;
2386         u32 rpm = 0;
2387
2388         if (adev->in_gpu_reset)
2389                 return -EPERM;
2390
2391         err = pm_runtime_get_sync(adev->ddev->dev);
2392         if (err < 0)
2393                 return err;
2394
2395         if (is_support_sw_smu(adev))
2396                 err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
2397         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2398                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2399         else
2400                 err = -EINVAL;
2401
2402         pm_runtime_mark_last_busy(adev->ddev->dev);
2403         pm_runtime_put_autosuspend(adev->ddev->dev);
2404
2405         if (err)
2406                 return err;
2407
2408         return sprintf(buf, "%i\n", rpm);
2409 }
2410
2411 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2412                                      struct device_attribute *attr,
2413                                      const char *buf, size_t count)
2414 {
2415         struct amdgpu_device *adev = dev_get_drvdata(dev);
2416         int err;
2417         u32 value;
2418         u32 pwm_mode;
2419
2420         if (adev->in_gpu_reset)
2421                 return -EPERM;
2422
2423         err = pm_runtime_get_sync(adev->ddev->dev);
2424         if (err < 0)
2425                 return err;
2426
2427         if (is_support_sw_smu(adev))
2428                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2429         else
2430                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2431
2432         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2433                 pm_runtime_mark_last_busy(adev->ddev->dev);
2434                 pm_runtime_put_autosuspend(adev->ddev->dev);
2435                 return -ENODATA;
2436         }
2437
2438         err = kstrtou32(buf, 10, &value);
2439         if (err) {
2440                 pm_runtime_mark_last_busy(adev->ddev->dev);
2441                 pm_runtime_put_autosuspend(adev->ddev->dev);
2442                 return err;
2443         }
2444
2445         if (is_support_sw_smu(adev))
2446                 err = smu_set_fan_speed_rpm(&adev->smu, value);
2447         else if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2448                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2449         else
2450                 err = -EINVAL;
2451
2452         pm_runtime_mark_last_busy(adev->ddev->dev);
2453         pm_runtime_put_autosuspend(adev->ddev->dev);
2454
2455         if (err)
2456                 return err;
2457
2458         return count;
2459 }
2460
2461 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2462                                             struct device_attribute *attr,
2463                                             char *buf)
2464 {
2465         struct amdgpu_device *adev = dev_get_drvdata(dev);
2466         u32 pwm_mode = 0;
2467         int ret;
2468
2469         if (adev->in_gpu_reset)
2470                 return -EPERM;
2471
2472         ret = pm_runtime_get_sync(adev->ddev->dev);
2473         if (ret < 0)
2474                 return ret;
2475
2476         if (is_support_sw_smu(adev)) {
2477                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2478         } else {
2479                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2480                         pm_runtime_mark_last_busy(adev->ddev->dev);
2481                         pm_runtime_put_autosuspend(adev->ddev->dev);
2482                         return -EINVAL;
2483                 }
2484
2485                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2486         }
2487
2488         pm_runtime_mark_last_busy(adev->ddev->dev);
2489         pm_runtime_put_autosuspend(adev->ddev->dev);
2490
2491         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2492 }
2493
2494 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2495                                             struct device_attribute *attr,
2496                                             const char *buf,
2497                                             size_t count)
2498 {
2499         struct amdgpu_device *adev = dev_get_drvdata(dev);
2500         int err;
2501         int value;
2502         u32 pwm_mode;
2503
2504         if (adev->in_gpu_reset)
2505                 return -EPERM;
2506
2507         err = kstrtoint(buf, 10, &value);
2508         if (err)
2509                 return err;
2510
2511         if (value == 0)
2512                 pwm_mode = AMD_FAN_CTRL_AUTO;
2513         else if (value == 1)
2514                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2515         else
2516                 return -EINVAL;
2517
2518         err = pm_runtime_get_sync(adev->ddev->dev);
2519         if (err < 0)
2520                 return err;
2521
2522         if (is_support_sw_smu(adev)) {
2523                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
2524         } else {
2525                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2526                         pm_runtime_mark_last_busy(adev->ddev->dev);
2527                         pm_runtime_put_autosuspend(adev->ddev->dev);
2528                         return -EINVAL;
2529                 }
2530                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2531         }
2532
2533         pm_runtime_mark_last_busy(adev->ddev->dev);
2534         pm_runtime_put_autosuspend(adev->ddev->dev);
2535
2536         return count;
2537 }
2538
2539 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2540                                         struct device_attribute *attr,
2541                                         char *buf)
2542 {
2543         struct amdgpu_device *adev = dev_get_drvdata(dev);
2544         u32 vddgfx;
2545         int r, size = sizeof(vddgfx);
2546
2547         if (adev->in_gpu_reset)
2548                 return -EPERM;
2549
2550         r = pm_runtime_get_sync(adev->ddev->dev);
2551         if (r < 0)
2552                 return r;
2553
2554         /* get the voltage */
2555         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2556                                    (void *)&vddgfx, &size);
2557
2558         pm_runtime_mark_last_busy(adev->ddev->dev);
2559         pm_runtime_put_autosuspend(adev->ddev->dev);
2560
2561         if (r)
2562                 return r;
2563
2564         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
2565 }
2566
2567 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2568                                               struct device_attribute *attr,
2569                                               char *buf)
2570 {
2571         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
2572 }
2573
2574 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2575                                        struct device_attribute *attr,
2576                                        char *buf)
2577 {
2578         struct amdgpu_device *adev = dev_get_drvdata(dev);
2579         u32 vddnb;
2580         int r, size = sizeof(vddnb);
2581
2582         if (adev->in_gpu_reset)
2583                 return -EPERM;
2584
2585         /* only APUs have vddnb */
2586         if  (!(adev->flags & AMD_IS_APU))
2587                 return -EINVAL;
2588
2589         r = pm_runtime_get_sync(adev->ddev->dev);
2590         if (r < 0)
2591                 return r;
2592
2593         /* get the voltage */
2594         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2595                                    (void *)&vddnb, &size);
2596
2597         pm_runtime_mark_last_busy(adev->ddev->dev);
2598         pm_runtime_put_autosuspend(adev->ddev->dev);
2599
2600         if (r)
2601                 return r;
2602
2603         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
2604 }
2605
2606 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2607                                               struct device_attribute *attr,
2608                                               char *buf)
2609 {
2610         return snprintf(buf, PAGE_SIZE, "vddnb\n");
2611 }
2612
2613 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2614                                            struct device_attribute *attr,
2615                                            char *buf)
2616 {
2617         struct amdgpu_device *adev = dev_get_drvdata(dev);
2618         u32 query = 0;
2619         int r, size = sizeof(u32);
2620         unsigned uw;
2621
2622         if (adev->in_gpu_reset)
2623                 return -EPERM;
2624
2625         r = pm_runtime_get_sync(adev->ddev->dev);
2626         if (r < 0)
2627                 return r;
2628
2629         /* get the voltage */
2630         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2631                                    (void *)&query, &size);
2632
2633         pm_runtime_mark_last_busy(adev->ddev->dev);
2634         pm_runtime_put_autosuspend(adev->ddev->dev);
2635
2636         if (r)
2637                 return r;
2638
2639         /* convert to microwatts */
2640         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2641
2642         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
2643 }
2644
2645 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2646                                          struct device_attribute *attr,
2647                                          char *buf)
2648 {
2649         return sprintf(buf, "%i\n", 0);
2650 }
2651
2652 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2653                                          struct device_attribute *attr,
2654                                          char *buf)
2655 {
2656         struct amdgpu_device *adev = dev_get_drvdata(dev);
2657         uint32_t limit = 0;
2658         ssize_t size;
2659         int r;
2660
2661         if (adev->in_gpu_reset)
2662                 return -EPERM;
2663
2664         r = pm_runtime_get_sync(adev->ddev->dev);
2665         if (r < 0)
2666                 return r;
2667
2668         if (is_support_sw_smu(adev)) {
2669                 smu_get_power_limit(&adev->smu, &limit, true, true);
2670                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2671         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2672                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2673                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2674         } else {
2675                 size = snprintf(buf, PAGE_SIZE, "\n");
2676         }
2677
2678         pm_runtime_mark_last_busy(adev->ddev->dev);
2679         pm_runtime_put_autosuspend(adev->ddev->dev);
2680
2681         return size;
2682 }
2683
2684 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2685                                          struct device_attribute *attr,
2686                                          char *buf)
2687 {
2688         struct amdgpu_device *adev = dev_get_drvdata(dev);
2689         uint32_t limit = 0;
2690         ssize_t size;
2691         int r;
2692
2693         if (adev->in_gpu_reset)
2694                 return -EPERM;
2695
2696         r = pm_runtime_get_sync(adev->ddev->dev);
2697         if (r < 0)
2698                 return r;
2699
2700         if (is_support_sw_smu(adev)) {
2701                 smu_get_power_limit(&adev->smu, &limit, false,  true);
2702                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2703         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2704                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2705                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2706         } else {
2707                 size = snprintf(buf, PAGE_SIZE, "\n");
2708         }
2709
2710         pm_runtime_mark_last_busy(adev->ddev->dev);
2711         pm_runtime_put_autosuspend(adev->ddev->dev);
2712
2713         return size;
2714 }
2715
2716
2717 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2718                 struct device_attribute *attr,
2719                 const char *buf,
2720                 size_t count)
2721 {
2722         struct amdgpu_device *adev = dev_get_drvdata(dev);
2723         int err;
2724         u32 value;
2725
2726         if (adev->in_gpu_reset)
2727                 return -EPERM;
2728
2729         if (amdgpu_sriov_vf(adev))
2730                 return -EINVAL;
2731
2732         err = kstrtou32(buf, 10, &value);
2733         if (err)
2734                 return err;
2735
2736         value = value / 1000000; /* convert to Watt */
2737
2738
2739         err = pm_runtime_get_sync(adev->ddev->dev);
2740         if (err < 0)
2741                 return err;
2742
2743         if (is_support_sw_smu(adev))
2744                 err = smu_set_power_limit(&adev->smu, value);
2745         else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
2746                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2747         else
2748                 err = -EINVAL;
2749
2750         pm_runtime_mark_last_busy(adev->ddev->dev);
2751         pm_runtime_put_autosuspend(adev->ddev->dev);
2752
2753         if (err)
2754                 return err;
2755
2756         return count;
2757 }
2758
2759 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2760                                       struct device_attribute *attr,
2761                                       char *buf)
2762 {
2763         struct amdgpu_device *adev = dev_get_drvdata(dev);
2764         uint32_t sclk;
2765         int r, size = sizeof(sclk);
2766
2767         if (adev->in_gpu_reset)
2768                 return -EPERM;
2769
2770         r = pm_runtime_get_sync(adev->ddev->dev);
2771         if (r < 0)
2772                 return r;
2773
2774         /* get the sclk */
2775         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2776                                    (void *)&sclk, &size);
2777
2778         pm_runtime_mark_last_busy(adev->ddev->dev);
2779         pm_runtime_put_autosuspend(adev->ddev->dev);
2780
2781         if (r)
2782                 return r;
2783
2784         return snprintf(buf, PAGE_SIZE, "%u\n", sclk * 10 * 1000);
2785 }
2786
2787 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2788                                             struct device_attribute *attr,
2789                                             char *buf)
2790 {
2791         return snprintf(buf, PAGE_SIZE, "sclk\n");
2792 }
2793
2794 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2795                                       struct device_attribute *attr,
2796                                       char *buf)
2797 {
2798         struct amdgpu_device *adev = dev_get_drvdata(dev);
2799         uint32_t mclk;
2800         int r, size = sizeof(mclk);
2801
2802         if (adev->in_gpu_reset)
2803                 return -EPERM;
2804
2805         r = pm_runtime_get_sync(adev->ddev->dev);
2806         if (r < 0)
2807                 return r;
2808
2809         /* get the sclk */
2810         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2811                                    (void *)&mclk, &size);
2812
2813         pm_runtime_mark_last_busy(adev->ddev->dev);
2814         pm_runtime_put_autosuspend(adev->ddev->dev);
2815
2816         if (r)
2817                 return r;
2818
2819         return snprintf(buf, PAGE_SIZE, "%u\n", mclk * 10 * 1000);
2820 }
2821
2822 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2823                                             struct device_attribute *attr,
2824                                             char *buf)
2825 {
2826         return snprintf(buf, PAGE_SIZE, "mclk\n");
2827 }
2828
2829 /**
2830  * DOC: hwmon
2831  *
2832  * The amdgpu driver exposes the following sensor interfaces:
2833  *
2834  * - GPU temperature (via the on-die sensor)
2835  *
2836  * - GPU voltage
2837  *
2838  * - Northbridge voltage (APUs only)
2839  *
2840  * - GPU power
2841  *
2842  * - GPU fan
2843  *
2844  * - GPU gfx/compute engine clock
2845  *
2846  * - GPU memory clock (dGPU only)
2847  *
2848  * hwmon interfaces for GPU temperature:
2849  *
2850  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2851  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2852  *
2853  * - temp[1-3]_label: temperature channel label
2854  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2855  *
2856  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2857  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2858  *
2859  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2860  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2861  *
2862  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2863  *   - these are supported on SOC15 dGPUs only
2864  *
2865  * hwmon interfaces for GPU voltage:
2866  *
2867  * - in0_input: the voltage on the GPU in millivolts
2868  *
2869  * - in1_input: the voltage on the Northbridge in millivolts
2870  *
2871  * hwmon interfaces for GPU power:
2872  *
2873  * - power1_average: average power used by the GPU in microWatts
2874  *
2875  * - power1_cap_min: minimum cap supported in microWatts
2876  *
2877  * - power1_cap_max: maximum cap supported in microWatts
2878  *
2879  * - power1_cap: selected power cap in microWatts
2880  *
2881  * hwmon interfaces for GPU fan:
2882  *
2883  * - pwm1: pulse width modulation fan level (0-255)
2884  *
2885  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2886  *
2887  * - pwm1_min: pulse width modulation fan control minimum level (0)
2888  *
2889  * - pwm1_max: pulse width modulation fan control maximum level (255)
2890  *
2891  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2892  *
2893  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2894  *
2895  * - fan1_input: fan speed in RPM
2896  *
2897  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
2898  *
2899  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2900  *
2901  * hwmon interfaces for GPU clocks:
2902  *
2903  * - freq1_input: the gfx/compute clock in hertz
2904  *
2905  * - freq2_input: the memory clock in hertz
2906  *
2907  * You can use hwmon tools like sensors to view this information on your system.
2908  *
2909  */
2910
2911 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2912 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2913 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2914 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2915 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2916 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2917 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2918 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2919 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2920 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2921 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2922 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2923 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2924 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2925 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2926 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2927 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2928 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2929 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2930 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2931 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2932 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2933 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2934 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2935 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2936 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2937 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2938 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2939 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2940 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2941 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2942 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2943 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2944 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2945 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2946 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2947
2948 static struct attribute *hwmon_attributes[] = {
2949         &sensor_dev_attr_temp1_input.dev_attr.attr,
2950         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2951         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2952         &sensor_dev_attr_temp2_input.dev_attr.attr,
2953         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2954         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2955         &sensor_dev_attr_temp3_input.dev_attr.attr,
2956         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2957         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2958         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2959         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2960         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2961         &sensor_dev_attr_temp1_label.dev_attr.attr,
2962         &sensor_dev_attr_temp2_label.dev_attr.attr,
2963         &sensor_dev_attr_temp3_label.dev_attr.attr,
2964         &sensor_dev_attr_pwm1.dev_attr.attr,
2965         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2966         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2967         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2968         &sensor_dev_attr_fan1_input.dev_attr.attr,
2969         &sensor_dev_attr_fan1_min.dev_attr.attr,
2970         &sensor_dev_attr_fan1_max.dev_attr.attr,
2971         &sensor_dev_attr_fan1_target.dev_attr.attr,
2972         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2973         &sensor_dev_attr_in0_input.dev_attr.attr,
2974         &sensor_dev_attr_in0_label.dev_attr.attr,
2975         &sensor_dev_attr_in1_input.dev_attr.attr,
2976         &sensor_dev_attr_in1_label.dev_attr.attr,
2977         &sensor_dev_attr_power1_average.dev_attr.attr,
2978         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2979         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2980         &sensor_dev_attr_power1_cap.dev_attr.attr,
2981         &sensor_dev_attr_freq1_input.dev_attr.attr,
2982         &sensor_dev_attr_freq1_label.dev_attr.attr,
2983         &sensor_dev_attr_freq2_input.dev_attr.attr,
2984         &sensor_dev_attr_freq2_label.dev_attr.attr,
2985         NULL
2986 };
2987
2988 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2989                                         struct attribute *attr, int index)
2990 {
2991         struct device *dev = kobj_to_dev(kobj);
2992         struct amdgpu_device *adev = dev_get_drvdata(dev);
2993         umode_t effective_mode = attr->mode;
2994
2995         /* under multi-vf mode, the hwmon attributes are all not supported */
2996         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
2997                 return 0;
2998
2999         /* there is no fan under pp one vf mode */
3000         if (amdgpu_sriov_is_pp_one_vf(adev) &&
3001             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3002              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3003              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3004              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3005              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3006              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3007              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3008              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3009              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3010                 return 0;
3011
3012         /* Skip fan attributes if fan is not present */
3013         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3014             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3015             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3016             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3017             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3018             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3019             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3020             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3021             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3022                 return 0;
3023
3024         /* Skip fan attributes on APU */
3025         if ((adev->flags & AMD_IS_APU) &&
3026             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3027              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3028              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3029              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3030              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3031              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3032              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3033              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3034              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3035                 return 0;
3036
3037         /* Skip limit attributes if DPM is not enabled */
3038         if (!adev->pm.dpm_enabled &&
3039             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3040              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3041              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3042              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3043              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3044              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3045              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3046              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3047              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3048              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3049              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3050                 return 0;
3051
3052         if (!is_support_sw_smu(adev)) {
3053                 /* mask fan attributes if we have no bindings for this asic to expose */
3054                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
3055                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3056                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
3057                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3058                         effective_mode &= ~S_IRUGO;
3059
3060                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3061                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3062                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
3063                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3064                         effective_mode &= ~S_IWUSR;
3065         }
3066
3067         if (((adev->flags & AMD_IS_APU) ||
3068              adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3069              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3070             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
3071              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3072              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3073              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
3074                 return 0;
3075
3076         if (!is_support_sw_smu(adev)) {
3077                 /* hide max/min values if we can't both query and manage the fan */
3078                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3079                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
3080                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3081                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3082                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3083                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3084                         return 0;
3085
3086                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3087                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3088                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3089                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3090                         return 0;
3091         }
3092
3093         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3094              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3095             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3096              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3097                 return 0;
3098
3099         /* only APUs have vddnb */
3100         if (!(adev->flags & AMD_IS_APU) &&
3101             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3102              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3103                 return 0;
3104
3105         /* no mclk on APUs */
3106         if ((adev->flags & AMD_IS_APU) &&
3107             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3108              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3109                 return 0;
3110
3111         /* only SOC15 dGPUs support hotspot and mem temperatures */
3112         if (((adev->flags & AMD_IS_APU) ||
3113              adev->asic_type < CHIP_VEGA10) &&
3114             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3115              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3116              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3117              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3118              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3119              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3120              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3121              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3122              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3123              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3124              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3125                 return 0;
3126
3127         return effective_mode;
3128 }
3129
3130 static const struct attribute_group hwmon_attrgroup = {
3131         .attrs = hwmon_attributes,
3132         .is_visible = hwmon_attributes_visible,
3133 };
3134
3135 static const struct attribute_group *hwmon_groups[] = {
3136         &hwmon_attrgroup,
3137         NULL
3138 };
3139
3140 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
3141 {
3142         struct amdgpu_device *adev =
3143                 container_of(work, struct amdgpu_device,
3144                              pm.dpm.thermal.work);
3145         /* switch to the thermal state */
3146         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
3147         int temp, size = sizeof(temp);
3148
3149         if (!adev->pm.dpm_enabled)
3150                 return;
3151
3152         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
3153                                     (void *)&temp, &size)) {
3154                 if (temp < adev->pm.dpm.thermal.min_temp)
3155                         /* switch back the user state */
3156                         dpm_state = adev->pm.dpm.user_state;
3157         } else {
3158                 if (adev->pm.dpm.thermal.high_to_low)
3159                         /* switch back the user state */
3160                         dpm_state = adev->pm.dpm.user_state;
3161         }
3162         mutex_lock(&adev->pm.mutex);
3163         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
3164                 adev->pm.dpm.thermal_active = true;
3165         else
3166                 adev->pm.dpm.thermal_active = false;
3167         adev->pm.dpm.state = dpm_state;
3168         mutex_unlock(&adev->pm.mutex);
3169
3170         amdgpu_pm_compute_clocks(adev);
3171 }
3172
3173 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
3174                                                      enum amd_pm_state_type dpm_state)
3175 {
3176         int i;
3177         struct amdgpu_ps *ps;
3178         u32 ui_class;
3179         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
3180                 true : false;
3181
3182         /* check if the vblank period is too short to adjust the mclk */
3183         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
3184                 if (amdgpu_dpm_vblank_too_short(adev))
3185                         single_display = false;
3186         }
3187
3188         /* certain older asics have a separare 3D performance state,
3189          * so try that first if the user selected performance
3190          */
3191         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
3192                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
3193         /* balanced states don't exist at the moment */
3194         if (dpm_state == POWER_STATE_TYPE_BALANCED)
3195                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3196
3197 restart_search:
3198         /* Pick the best power state based on current conditions */
3199         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
3200                 ps = &adev->pm.dpm.ps[i];
3201                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
3202                 switch (dpm_state) {
3203                 /* user states */
3204                 case POWER_STATE_TYPE_BATTERY:
3205                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
3206                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3207                                         if (single_display)
3208                                                 return ps;
3209                                 } else
3210                                         return ps;
3211                         }
3212                         break;
3213                 case POWER_STATE_TYPE_BALANCED:
3214                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
3215                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3216                                         if (single_display)
3217                                                 return ps;
3218                                 } else
3219                                         return ps;
3220                         }
3221                         break;
3222                 case POWER_STATE_TYPE_PERFORMANCE:
3223                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
3224                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3225                                         if (single_display)
3226                                                 return ps;
3227                                 } else
3228                                         return ps;
3229                         }
3230                         break;
3231                 /* internal states */
3232                 case POWER_STATE_TYPE_INTERNAL_UVD:
3233                         if (adev->pm.dpm.uvd_ps)
3234                                 return adev->pm.dpm.uvd_ps;
3235                         else
3236                                 break;
3237                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3238                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3239                                 return ps;
3240                         break;
3241                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3242                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3243                                 return ps;
3244                         break;
3245                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3246                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3247                                 return ps;
3248                         break;
3249                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3250                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3251                                 return ps;
3252                         break;
3253                 case POWER_STATE_TYPE_INTERNAL_BOOT:
3254                         return adev->pm.dpm.boot_ps;
3255                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
3256                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
3257                                 return ps;
3258                         break;
3259                 case POWER_STATE_TYPE_INTERNAL_ACPI:
3260                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
3261                                 return ps;
3262                         break;
3263                 case POWER_STATE_TYPE_INTERNAL_ULV:
3264                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
3265                                 return ps;
3266                         break;
3267                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
3268                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
3269                                 return ps;
3270                         break;
3271                 default:
3272                         break;
3273                 }
3274         }
3275         /* use a fallback state if we didn't match */
3276         switch (dpm_state) {
3277         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3278                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
3279                 goto restart_search;
3280         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3281         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3282         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3283                 if (adev->pm.dpm.uvd_ps) {
3284                         return adev->pm.dpm.uvd_ps;
3285                 } else {
3286                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3287                         goto restart_search;
3288                 }
3289         case POWER_STATE_TYPE_INTERNAL_THERMAL:
3290                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
3291                 goto restart_search;
3292         case POWER_STATE_TYPE_INTERNAL_ACPI:
3293                 dpm_state = POWER_STATE_TYPE_BATTERY;
3294                 goto restart_search;
3295         case POWER_STATE_TYPE_BATTERY:
3296         case POWER_STATE_TYPE_BALANCED:
3297         case POWER_STATE_TYPE_INTERNAL_3DPERF:
3298                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3299                 goto restart_search;
3300         default:
3301                 break;
3302         }
3303
3304         return NULL;
3305 }
3306
3307 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
3308 {
3309         struct amdgpu_ps *ps;
3310         enum amd_pm_state_type dpm_state;
3311         int ret;
3312         bool equal = false;
3313
3314         /* if dpm init failed */
3315         if (!adev->pm.dpm_enabled)
3316                 return;
3317
3318         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
3319                 /* add other state override checks here */
3320                 if ((!adev->pm.dpm.thermal_active) &&
3321                     (!adev->pm.dpm.uvd_active))
3322                         adev->pm.dpm.state = adev->pm.dpm.user_state;
3323         }
3324         dpm_state = adev->pm.dpm.state;
3325
3326         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
3327         if (ps)
3328                 adev->pm.dpm.requested_ps = ps;
3329         else
3330                 return;
3331
3332         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
3333                 printk("switching from power state:\n");
3334                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
3335                 printk("switching to power state:\n");
3336                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
3337         }
3338
3339         /* update whether vce is active */
3340         ps->vce_active = adev->pm.dpm.vce_active;
3341         if (adev->powerplay.pp_funcs->display_configuration_changed)
3342                 amdgpu_dpm_display_configuration_changed(adev);
3343
3344         ret = amdgpu_dpm_pre_set_power_state(adev);
3345         if (ret)
3346                 return;
3347
3348         if (adev->powerplay.pp_funcs->check_state_equal) {
3349                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
3350                         equal = false;
3351         }
3352
3353         if (equal)
3354                 return;
3355
3356         amdgpu_dpm_set_power_state(adev);
3357         amdgpu_dpm_post_set_power_state(adev);
3358
3359         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
3360         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
3361
3362         if (adev->powerplay.pp_funcs->force_performance_level) {
3363                 if (adev->pm.dpm.thermal_active) {
3364                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
3365                         /* force low perf level for thermal */
3366                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
3367                         /* save the user's level */
3368                         adev->pm.dpm.forced_level = level;
3369                 } else {
3370                         /* otherwise, user selected level */
3371                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
3372                 }
3373         }
3374 }
3375
3376 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
3377 {
3378         int ret = 0;
3379
3380         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
3381         if (ret)
3382                 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
3383                           enable ? "enable" : "disable", ret);
3384
3385         /* enable/disable Low Memory PState for UVD (4k videos) */
3386         if (adev->asic_type == CHIP_STONEY &&
3387                 adev->uvd.decode_image_width >= WIDTH_4K) {
3388                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3389
3390                 if (hwmgr && hwmgr->hwmgr_func &&
3391                     hwmgr->hwmgr_func->update_nbdpm_pstate)
3392                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
3393                                                                !enable,
3394                                                                true);
3395         }
3396 }
3397
3398 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
3399 {
3400         int ret = 0;
3401
3402         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
3403         if (ret)
3404                 DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
3405                           enable ? "enable" : "disable", ret);
3406 }
3407
3408 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
3409 {
3410         int i;
3411
3412         if (adev->powerplay.pp_funcs->print_power_state == NULL)
3413                 return;
3414
3415         for (i = 0; i < adev->pm.dpm.num_ps; i++)
3416                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
3417
3418 }
3419
3420 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
3421 {
3422         int ret = 0;
3423
3424         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
3425         if (ret)
3426                 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
3427                           enable ? "enable" : "disable", ret);
3428 }
3429
3430 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
3431 {
3432         int r;
3433
3434         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
3435                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
3436                 if (r) {
3437                         pr_err("smu firmware loading failed\n");
3438                         return r;
3439                 }
3440                 *smu_version = adev->pm.fw_version;
3441         }
3442         return 0;
3443 }
3444
3445 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3446 {
3447         int ret;
3448         uint32_t mask = 0;
3449
3450         if (adev->pm.sysfs_initialized)
3451                 return 0;
3452
3453         if (adev->pm.dpm_enabled == 0)
3454                 return 0;
3455
3456         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3457
3458         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3459                                                                    DRIVER_NAME, adev,
3460                                                                    hwmon_groups);
3461         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3462                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3463                 dev_err(adev->dev,
3464                         "Unable to register hwmon device: %d\n", ret);
3465                 return ret;
3466         }
3467
3468         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3469         case SRIOV_VF_MODE_ONE_VF:
3470                 mask = ATTR_FLAG_ONEVF;
3471                 break;
3472         case SRIOV_VF_MODE_MULTI_VF:
3473                 mask = 0;
3474                 break;
3475         case SRIOV_VF_MODE_BARE_METAL:
3476         default:
3477                 mask = ATTR_FLAG_MASK_ALL;
3478                 break;
3479         }
3480
3481         ret = amdgpu_device_attr_create_groups(adev,
3482                                                amdgpu_device_attrs,
3483                                                ARRAY_SIZE(amdgpu_device_attrs),
3484                                                mask,
3485                                                &adev->pm.pm_attr_list);
3486         if (ret)
3487                 return ret;
3488
3489         adev->pm.sysfs_initialized = true;
3490
3491         return 0;
3492 }
3493
3494 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3495 {
3496         if (adev->pm.dpm_enabled == 0)
3497                 return;
3498
3499         if (adev->pm.int_hwmon_dev)
3500                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3501
3502         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3503 }
3504
3505 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
3506 {
3507         int i = 0;
3508
3509         if (!adev->pm.dpm_enabled)
3510                 return;
3511
3512         if (adev->mode_info.num_crtc)
3513                 amdgpu_display_bandwidth_update(adev);
3514
3515         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3516                 struct amdgpu_ring *ring = adev->rings[i];
3517                 if (ring && ring->sched.ready)
3518                         amdgpu_fence_wait_empty(ring);
3519         }
3520
3521         if (is_support_sw_smu(adev)) {
3522                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
3523                 smu_handle_task(&adev->smu,
3524                                 smu_dpm->dpm_level,
3525                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
3526                                 true);
3527         } else {
3528                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
3529                         if (!amdgpu_device_has_dc_support(adev)) {
3530                                 mutex_lock(&adev->pm.mutex);
3531                                 amdgpu_dpm_get_active_displays(adev);
3532                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
3533                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3534                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3535                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3536                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3537                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3538                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3539                                         adev->powerplay.pp_funcs->display_configuration_change(
3540                                                                         adev->powerplay.pp_handle,
3541                                                                         &adev->pm.pm_display_cfg);
3542                                 mutex_unlock(&adev->pm.mutex);
3543                         }
3544                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3545                 } else {
3546                         mutex_lock(&adev->pm.mutex);
3547                         amdgpu_dpm_get_active_displays(adev);
3548                         amdgpu_dpm_change_power_state_locked(adev);
3549                         mutex_unlock(&adev->pm.mutex);
3550                 }
3551         }
3552 }
3553
3554 /*
3555  * Debugfs info
3556  */
3557 #if defined(CONFIG_DEBUG_FS)
3558
3559 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3560 {
3561         uint32_t value;
3562         uint64_t value64;
3563         uint32_t query = 0;
3564         int size;
3565
3566         /* GPU Clocks */
3567         size = sizeof(value);
3568         seq_printf(m, "GFX Clocks and Power:\n");
3569         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3570                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3571         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3572                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3573         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3574                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3575         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3576                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3577         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3578                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3579         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3580                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3581         size = sizeof(uint32_t);
3582         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3583                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3584         size = sizeof(value);
3585         seq_printf(m, "\n");
3586
3587         /* GPU Temp */
3588         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3589                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3590
3591         /* GPU Load */
3592         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3593                 seq_printf(m, "GPU Load: %u %%\n", value);
3594         /* MEM Load */
3595         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3596                 seq_printf(m, "MEM Load: %u %%\n", value);
3597
3598         seq_printf(m, "\n");
3599
3600         /* SMC feature mask */
3601         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3602                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3603
3604         if (adev->asic_type > CHIP_VEGA20) {
3605                 /* VCN clocks */
3606                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3607                         if (!value) {
3608                                 seq_printf(m, "VCN: Disabled\n");
3609                         } else {
3610                                 seq_printf(m, "VCN: Enabled\n");
3611                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3612                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3613                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3614                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3615                         }
3616                 }
3617                 seq_printf(m, "\n");
3618         } else {
3619                 /* UVD clocks */
3620                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3621                         if (!value) {
3622                                 seq_printf(m, "UVD: Disabled\n");
3623                         } else {
3624                                 seq_printf(m, "UVD: Enabled\n");
3625                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3626                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3627                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3628                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3629                         }
3630                 }
3631                 seq_printf(m, "\n");
3632
3633                 /* VCE clocks */
3634                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3635                         if (!value) {
3636                                 seq_printf(m, "VCE: Disabled\n");
3637                         } else {
3638                                 seq_printf(m, "VCE: Enabled\n");
3639                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3640                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3641                         }
3642                 }
3643         }
3644
3645         return 0;
3646 }
3647
3648 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3649 {
3650         int i;
3651
3652         for (i = 0; clocks[i].flag; i++)
3653                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3654                            (flags & clocks[i].flag) ? "On" : "Off");
3655 }
3656
3657 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3658 {
3659         struct drm_info_node *node = (struct drm_info_node *) m->private;
3660         struct drm_device *dev = node->minor->dev;
3661         struct amdgpu_device *adev = dev->dev_private;
3662         u32 flags = 0;
3663         int r;
3664
3665         if (adev->in_gpu_reset)
3666                 return -EPERM;
3667
3668         r = pm_runtime_get_sync(dev->dev);
3669         if (r < 0)
3670                 return r;
3671
3672         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3673         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3674         amdgpu_parse_cg_state(m, flags);
3675         seq_printf(m, "\n");
3676
3677         if (!adev->pm.dpm_enabled) {
3678                 seq_printf(m, "dpm not enabled\n");
3679                 pm_runtime_mark_last_busy(dev->dev);
3680                 pm_runtime_put_autosuspend(dev->dev);
3681                 return 0;
3682         }
3683
3684         if (!is_support_sw_smu(adev) &&
3685             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3686                 mutex_lock(&adev->pm.mutex);
3687                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3688                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3689                 else
3690                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3691                 mutex_unlock(&adev->pm.mutex);
3692                 r = 0;
3693         } else {
3694                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3695         }
3696
3697         pm_runtime_mark_last_busy(dev->dev);
3698         pm_runtime_put_autosuspend(dev->dev);
3699
3700         return r;
3701 }
3702
3703 static const struct drm_info_list amdgpu_pm_info_list[] = {
3704         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3705 };
3706 #endif
3707
3708 int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3709 {
3710 #if defined(CONFIG_DEBUG_FS)
3711         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3712 #else
3713         return 0;
3714 #endif
3715 }