drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <drm/drmP.h>
  27
  28 #include "dm_services_types.h"
  29 #include "dc.h"
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_dm.h"
  33 #include "amdgpu_dm_irq.h"
  34
  35 /******************************************************************************
  36  * Private declarations.
  37  *****************************************************************************/
  38
  39 struct handler_common_data {
  40         struct list_head list;
  41         interrupt_handler handler;
  42         void *handler_arg;
  43
  44         /* DM which this handler belongs to */
  45         struct amdgpu_display_manager *dm;
  46 };
  47
  48 struct amdgpu_dm_irq_handler_data {
  49         struct handler_common_data hcd;
  50         /* DAL irq source which registered for this interrupt. */
  51         enum dc_irq_source irq_source;
  52 };
  53
  54 struct amdgpu_dm_timer_handler_data {
  55         struct handler_common_data hcd;
  56         struct delayed_work d_work;
  57 };
  58
  59 #define DM_IRQ_TABLE_LOCK(adev, flags) \
  60         spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
  61
  62 #define DM_IRQ_TABLE_UNLOCK(adev, flags) \
  63         spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
  64
  65 /******************************************************************************
  66  * Private functions.
  67  *****************************************************************************/
  68
  69 static void init_handler_common_data(
  70         struct handler_common_data *hcd,
  71         void (*ih)(void *),
  72         void *args,
  73         struct amdgpu_display_manager *dm)
  74 {
  75         hcd->handler = ih;
  76         hcd->handler_arg = args;
  77         hcd->dm = dm;
  78 }
  79
  80 /**
  81  * dm_irq_work_func - Handle an IRQ outside of the interrupt handler proper.
  82  *
  83  * @work: work struct
  84  */
  85 static void dm_irq_work_func(struct work_struct *work)
  86 {
  87         struct list_head *entry;
  88         struct irq_list_head *irq_list_head =
  89                 container_of(work, struct irq_list_head, work);
  90         struct list_head *handler_list = &irq_list_head->head;
  91         struct amdgpu_dm_irq_handler_data *handler_data;
  92
  93         list_for_each(entry, handler_list) {
  94                 handler_data =
  95                         list_entry(
  96                                 entry,
  97                                 struct amdgpu_dm_irq_handler_data,
  98                                 hcd.list);
  99
 100                 DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
 101                                 handler_data->irq_source);
 102
 103                 DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
 104                         handler_data->irq_source);
 105
 106                 handler_data->hcd.handler(handler_data->hcd.handler_arg);
 107         }
 108
 109         /* Call a DAL subcomponent which registered for interrupt notification
 110          * at INTERRUPT_LOW_IRQ_CONTEXT.
 111          * (The most common use is HPD interrupt) */
 112 }
 113
 114 /**
 115  * Remove a handler and return a pointer to hander list from which the
 116  * handler was removed.
 117  */
 118 static struct list_head *remove_irq_handler(
 119         struct amdgpu_device *adev,
 120         void *ih,
 121         const struct dc_interrupt_params *int_params)
 122 {
 123         struct list_head *hnd_list;
 124         struct list_head *entry, *tmp;
 125         struct amdgpu_dm_irq_handler_data *handler;
 126         unsigned long irq_table_flags;
 127         bool handler_removed = false;
 128         enum dc_irq_source irq_source;
 129
 130         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 131
 132         irq_source = int_params->irq_source;
 133
 134         switch (int_params->int_context) {
 135         case INTERRUPT_HIGH_IRQ_CONTEXT:
 136                 hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
 137                 break;
 138         case INTERRUPT_LOW_IRQ_CONTEXT:
 139         default:
 140                 hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
 141                 break;
 142         }
 143
 144         list_for_each_safe(entry, tmp, hnd_list) {
 145
 146                 handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
 147                                 hcd.list);
 148
 149                 if (ih == handler) {
 150                         /* Found our handler. Remove it from the list. */
 151                         list_del(&handler->hcd.list);
 152                         handler_removed = true;
 153                         break;
 154                 }
 155         }
 156
 157         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 158
 159         if (handler_removed == false) {
 160                 /* Not necessarily an error - caller may not
 161                  * know the context. */
 162                 return NULL;
 163         }
 164
 165         kfree(handler);
 166
 167         DRM_DEBUG_KMS(
 168         "DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
 169                 ih, int_params->irq_source, int_params->int_context);
 170
 171         return hnd_list;
 172 }
 173
 174 /* If 'handler_in == NULL' then remove ALL handlers. */
 175 static void remove_timer_handler(
 176         struct amdgpu_device *adev,
 177         struct amdgpu_dm_timer_handler_data *handler_in)
 178 {
 179         struct amdgpu_dm_timer_handler_data *handler_temp;
 180         struct list_head *handler_list;
 181         struct list_head *entry, *tmp;
 182         unsigned long irq_table_flags;
 183         bool handler_removed = false;
 184
 185         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 186
 187         handler_list = &adev->dm.timer_handler_list;
 188
 189         list_for_each_safe(entry, tmp, handler_list) {
 190                 /* Note that list_for_each_safe() guarantees that
 191                  * handler_temp is NOT null. */
 192                 handler_temp = list_entry(entry,
 193                                 struct amdgpu_dm_timer_handler_data, hcd.list);
 194
 195                 if (handler_in == NULL || handler_in == handler_temp) {
 196                         list_del(&handler_temp->hcd.list);
 197                         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 198
 199                         DRM_DEBUG_KMS("DM_IRQ: removing timer handler: %p\n",
 200                                         handler_temp);
 201
 202                         if (handler_in == NULL) {
 203                                 /* Since it is still in the queue, it must
 204                                  * be cancelled. */
 205                                 cancel_delayed_work_sync(&handler_temp->d_work);
 206                         }
 207
 208                         kfree(handler_temp);
 209                         handler_removed = true;
 210
 211                         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 212                 }
 213
 214                 if (handler_in == NULL) {
 215                         /* Remove ALL handlers. */
 216                         continue;
 217                 }
 218
 219                 if (handler_in == handler_temp) {
 220                         /* Remove a SPECIFIC handler.
 221                          * Found our handler - we can stop here. */
 222                         break;
 223                 }
 224         }
 225
 226         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 227
 228         if (handler_in != NULL && handler_removed == false) {
 229                 DRM_ERROR("DM_IRQ: handler: %p is not in the list!\n",
 230                                 handler_in);
 231         }
 232 }
 233
 234 /**
 235  * dm_timer_work_func - Handle a timer.
 236  *
 237  * @work: work struct
 238  */
 239 static void dm_timer_work_func(
 240         struct work_struct *work)
 241 {
 242         struct amdgpu_dm_timer_handler_data *handler_data =
 243                 container_of(work, struct amdgpu_dm_timer_handler_data,
 244                                 d_work.work);
 245
 246         DRM_DEBUG_KMS("DM_IRQ: work_func: handler_data=%p\n", handler_data);
 247
 248         /* Call a DAL subcomponent which registered for timer notification. */
 249         handler_data->hcd.handler(handler_data->hcd.handler_arg);
 250
 251         /* We support only "single shot" timers. That means we must delete
 252          * the handler after it was called. */
 253         remove_timer_handler(handler_data->hcd.dm->adev, handler_data);
 254 }
 255
 256 static bool validate_irq_registration_params(
 257         struct dc_interrupt_params *int_params,
 258         void (*ih)(void *))
 259 {
 260         if (NULL == int_params || NULL == ih) {
 261                 DRM_ERROR("DM_IRQ: invalid input!\n");
 262                 return false;
 263         }
 264
 265         if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
 266                 DRM_ERROR("DM_IRQ: invalid context: %d!\n",
 267                                 int_params->int_context);
 268                 return false;
 269         }
 270
 271         if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
 272                 DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
 273                                 int_params->irq_source);
 274                 return false;
 275         }
 276
 277         return true;
 278 }
 279
 280 static bool validate_irq_unregistration_params(
 281         enum dc_irq_source irq_source,
 282         irq_handler_idx handler_idx)
 283 {
 284         if (DAL_INVALID_IRQ_HANDLER_IDX == handler_idx) {
 285                 DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
 286                 return false;
 287         }
 288
 289         if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
 290                 DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
 291                 return false;
 292         }
 293
 294         return true;
 295 }
 296 /******************************************************************************
 297  * Public functions.
 298  *
 299  * Note: caller is responsible for input validation.
 300  *****************************************************************************/
 301
 302 void *amdgpu_dm_irq_register_interrupt(
 303         struct amdgpu_device *adev,
 304         struct dc_interrupt_params *int_params,
 305         void (*ih)(void *),
 306         void *handler_args)
 307 {
 308         struct list_head *hnd_list;
 309         struct amdgpu_dm_irq_handler_data *handler_data;
 310         unsigned long irq_table_flags;
 311         enum dc_irq_source irq_source;
 312
 313         if (false == validate_irq_registration_params(int_params, ih))
 314                 return DAL_INVALID_IRQ_HANDLER_IDX;
 315
 316         handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
 317         if (!handler_data) {
 318                 DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
 319                 return DAL_INVALID_IRQ_HANDLER_IDX;
 320         }
 321
 322         memset(handler_data, 0, sizeof(*handler_data));
 323
 324         init_handler_common_data(&handler_data->hcd, ih, handler_args,
 325                         &adev->dm);
 326
 327         irq_source = int_params->irq_source;
 328
 329         handler_data->irq_source = irq_source;
 330
 331         /* Lock the list, add the handler. */
 332         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 333
 334         switch (int_params->int_context) {
 335         case INTERRUPT_HIGH_IRQ_CONTEXT:
 336                 hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
 337                 break;
 338         case INTERRUPT_LOW_IRQ_CONTEXT:
 339         default:
 340                 hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
 341                 break;
 342         }
 343
 344         list_add_tail(&handler_data->hcd.list, hnd_list);
 345
 346         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 347
 348         /* This pointer will be stored by code which requested interrupt
 349          * registration.
 350          * The same pointer will be needed in order to unregister the
 351          * interrupt. */
 352
 353         DRM_DEBUG_KMS(
 354                 "DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
 355                 handler_data,
 356                 irq_source,
 357                 int_params->int_context);
 358
 359         return handler_data;
 360 }
 361
 362 void amdgpu_dm_irq_unregister_interrupt(
 363         struct amdgpu_device *adev,
 364         enum dc_irq_source irq_source,
 365         void *ih)
 366 {
 367         struct list_head *handler_list;
 368         struct dc_interrupt_params int_params;
 369         int i;
 370
 371         if (false == validate_irq_unregistration_params(irq_source, ih))
 372                 return;
 373
 374         memset(&int_params, 0, sizeof(int_params));
 375
 376         int_params.irq_source = irq_source;
 377
 378         for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
 379
 380                 int_params.int_context = i;
 381
 382                 handler_list = remove_irq_handler(adev, ih, &int_params);
 383
 384                 if (handler_list != NULL)
 385                         break;
 386         }
 387
 388         if (handler_list == NULL) {
 389                 /* If we got here, it means we searched all irq contexts
 390                  * for this irq source, but the handler was not found. */
 391                 DRM_ERROR(
 392                 "DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
 393                         ih, irq_source);
 394         }
 395 }
 396
 397 int amdgpu_dm_irq_init(
 398         struct amdgpu_device *adev)
 399 {
 400         int src;
 401         struct irq_list_head *lh;
 402
 403         DRM_DEBUG_KMS("DM_IRQ\n");
 404
 405         spin_lock_init(&adev->dm.irq_handler_list_table_lock);
 406
 407         for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
 408                 /* low context handler list init */
 409                 lh = &adev->dm.irq_handler_list_low_tab[src];
 410                 INIT_LIST_HEAD(&lh->head);
 411                 INIT_WORK(&lh->work, dm_irq_work_func);
 412
 413                 /* high context handler init */
 414                 INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
 415         }
 416
 417         INIT_LIST_HEAD(&adev->dm.timer_handler_list);
 418
 419         /* allocate and initialize the workqueue for DM timer */
 420         adev->dm.timer_workqueue = create_singlethread_workqueue(
 421                         "dm_timer_queue");
 422         if (adev->dm.timer_workqueue == NULL) {
 423                 DRM_ERROR("DM_IRQ: unable to create timer queue!\n");
 424                 return -1;
 425         }
 426
 427         return 0;
 428 }
 429
 430 void amdgpu_dm_irq_register_timer(
 431         struct amdgpu_device *adev,
 432         struct dc_timer_interrupt_params *int_params,
 433         interrupt_handler ih,
 434         void *args)
 435 {
 436         unsigned long jf_delay;
 437         struct list_head *handler_list;
 438         struct amdgpu_dm_timer_handler_data *handler_data;
 439         unsigned long irq_table_flags;
 440
 441         handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
 442         if (!handler_data) {
 443                 DRM_ERROR("DM_IRQ: failed to allocate timer handler!\n");
 444                 return;
 445         }
 446
 447         memset(handler_data, 0, sizeof(*handler_data));
 448
 449         init_handler_common_data(&handler_data->hcd, ih, args, &adev->dm);
 450
 451         INIT_DELAYED_WORK(&handler_data->d_work, dm_timer_work_func);
 452
 453         /* Lock the list, add the handler. */
 454         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 455
 456         handler_list = &adev->dm.timer_handler_list;
 457
 458         list_add_tail(&handler_data->hcd.list, handler_list);
 459
 460         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 461
 462         jf_delay = usecs_to_jiffies(int_params->micro_sec_interval);
 463
 464         queue_delayed_work(adev->dm.timer_workqueue, &handler_data->d_work,
 465                         jf_delay);
 466
 467         DRM_DEBUG_KMS("DM_IRQ: added handler:%p with micro_sec_interval=%u\n",
 468                         handler_data, int_params->micro_sec_interval);
 469         return;
 470 }
 471
 472 /* DM IRQ and timer resource release */
 473 void amdgpu_dm_irq_fini(
 474         struct amdgpu_device *adev)
 475 {
 476         int src;
 477         struct irq_list_head *lh;
 478         DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
 479
 480         for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
 481
 482                 /* The handler was removed from the table,
 483                  * it means it is safe to flush all the 'work'
 484                  * (because no code can schedule a new one). */
 485                 lh = &adev->dm.irq_handler_list_low_tab[src];
 486                 flush_work(&lh->work);
 487         }
 488
 489         /* Cancel ALL timers and release handlers (if any). */
 490         remove_timer_handler(adev, NULL);
 491         /* Release the queue itself. */
 492         destroy_workqueue(adev->dm.timer_workqueue);
 493 }
 494
 495 int amdgpu_dm_irq_suspend(
 496         struct amdgpu_device *adev)
 497 {
 498         int src;
 499         struct list_head *hnd_list_h;
 500         struct list_head *hnd_list_l;
 501         unsigned long irq_table_flags;
 502
 503         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 504
 505         DRM_DEBUG_KMS("DM_IRQ: suspend\n");
 506
 507         /**
 508          * Disable HW interrupt  for HPD and HPDRX only since FLIP and VBLANK
 509          * will be disabled from manage_dm_interrupts on disable CRTC.
 510          */
 511         for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6RX; src++) {
 512                 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
 513                 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 514                 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
 515                         dc_interrupt_set(adev->dm.dc, src, false);
 516
 517                 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 518                 flush_work(&adev->dm.irq_handler_list_low_tab[src].work);
 519
 520                 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 521         }
 522
 523         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 524         return 0;
 525 }
 526
 527 int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
 528 {
 529         int src;
 530         struct list_head *hnd_list_h, *hnd_list_l;
 531         unsigned long irq_table_flags;
 532
 533         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 534
 535         DRM_DEBUG_KMS("DM_IRQ: early resume\n");
 536
 537         /* re-enable short pulse interrupts HW interrupt */
 538         for (src = DC_IRQ_SOURCE_HPD1RX; src < DC_IRQ_SOURCE_HPD6RX + 1; src++) {
 539                 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
 540                 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 541                 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
 542                         dc_interrupt_set(adev->dm.dc, src, true);
 543         }
 544
 545         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 546
 547         return 0;
 548 }
 549
 550 int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
 551 {
 552         int src;
 553         struct list_head *hnd_list_h, *hnd_list_l;
 554         unsigned long irq_table_flags;
 555
 556         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 557
 558         DRM_DEBUG_KMS("DM_IRQ: resume\n");
 559
 560         /**
 561          * Renable HW interrupt  for HPD and only since FLIP and VBLANK
 562          * will be enabled from manage_dm_interrupts on enable CRTC.
 563          */
 564         for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6; src++) {
 565                 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
 566                 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 567                 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
 568                         dc_interrupt_set(adev->dm.dc, src, true);
 569         }
 570
 571         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 572         return 0;
 573 }
 574
 575 /**
 576  * amdgpu_dm_irq_schedule_work - schedule all work items registered for the
 577  * "irq_source".
 578  */
 579 static void amdgpu_dm_irq_schedule_work(
 580         struct amdgpu_device *adev,
 581         enum dc_irq_source irq_source)
 582 {
 583         unsigned long irq_table_flags;
 584         struct work_struct *work = NULL;
 585
 586         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 587
 588         if (!list_empty(&adev->dm.irq_handler_list_low_tab[irq_source].head))
 589                 work = &adev->dm.irq_handler_list_low_tab[irq_source].work;
 590
 591         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 592
 593         if (work) {
 594                 if (!schedule_work(work))
 595                         DRM_INFO("amdgpu_dm_irq_schedule_work FAILED src %d\n",
 596                                                 irq_source);
 597         }
 598
 599 }
 600
 601 /** amdgpu_dm_irq_immediate_work
 602  *  Callback high irq work immediately, don't send to work queue
 603  */
 604 static void amdgpu_dm_irq_immediate_work(
 605         struct amdgpu_device *adev,
 606         enum dc_irq_source irq_source)
 607 {
 608         struct amdgpu_dm_irq_handler_data *handler_data;
 609         struct list_head *entry;
 610         unsigned long irq_table_flags;
 611
 612         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 613
 614         list_for_each(
 615                 entry,
 616                 &adev->dm.irq_handler_list_high_tab[irq_source]) {
 617
 618                 handler_data =
 619                         list_entry(
 620                                 entry,
 621                                 struct amdgpu_dm_irq_handler_data,
 622                                 hcd.list);
 623
 624                 /* Call a subcomponent which registered for immediate
 625                  * interrupt notification */
 626                 handler_data->hcd.handler(handler_data->hcd.handler_arg);
 627         }
 628
 629         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 630 }
 631
 632 /*
 633  * amdgpu_dm_irq_handler
 634  *
 635  * Generic IRQ handler, calls all registered high irq work immediately, and
 636  * schedules work for low irq
 637  */
 638 int amdgpu_dm_irq_handler(
 639                 struct amdgpu_device *adev,
 640                 struct amdgpu_irq_src *source,
 641                 struct amdgpu_iv_entry *entry)
 642 {
 643
 644         enum dc_irq_source src =
 645                 dc_interrupt_to_irq_source(
 646                         adev->dm.dc,
 647                         entry->src_id,
 648                         entry->src_data[0]);
 649
 650         dc_interrupt_ack(adev->dm.dc, src);
 651
 652         /* Call high irq work immediately */
 653         amdgpu_dm_irq_immediate_work(adev, src);
 654         /*Schedule low_irq work */
 655         amdgpu_dm_irq_schedule_work(adev, src);
 656
 657         return 0;
 658 }
 659
 660 static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned type)
 661 {
 662         switch (type) {
 663         case AMDGPU_HPD_1:
 664                 return DC_IRQ_SOURCE_HPD1;
 665         case AMDGPU_HPD_2:
 666                 return DC_IRQ_SOURCE_HPD2;
 667         case AMDGPU_HPD_3:
 668                 return DC_IRQ_SOURCE_HPD3;
 669         case AMDGPU_HPD_4:
 670                 return DC_IRQ_SOURCE_HPD4;
 671         case AMDGPU_HPD_5:
 672                 return DC_IRQ_SOURCE_HPD5;
 673         case AMDGPU_HPD_6:
 674                 return DC_IRQ_SOURCE_HPD6;
 675         default:
 676                 return DC_IRQ_SOURCE_INVALID;
 677         }
 678 }
 679
 680 static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
 681                                         struct amdgpu_irq_src *source,
 682                                         unsigned type,
 683                                         enum amdgpu_interrupt_state state)
 684 {
 685         enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
 686         bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
 687
 688         dc_interrupt_set(adev->dm.dc, src, st);
 689         return 0;
 690 }
 691
 692 static inline int dm_irq_state(
 693         struct amdgpu_device *adev,
 694         struct amdgpu_irq_src *source,
 695         unsigned crtc_id,
 696         enum amdgpu_interrupt_state state,
 697         const enum irq_type dal_irq_type,
 698         const char *func)
 699 {
 700         bool st;
 701         enum dc_irq_source irq_source;
 702
 703         struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
 704
 705         if (!acrtc) {
 706                 DRM_ERROR(
 707                         "%s: crtc is NULL at id :%d\n",
 708                         func,
 709                         crtc_id);
 710                 return 0;
 711         }
 712
 713         irq_source = dal_irq_type + acrtc->otg_inst;
 714
 715         st = (state == AMDGPU_IRQ_STATE_ENABLE);
 716
 717         dc_interrupt_set(adev->dm.dc, irq_source, st);
 718         return 0;
 719 }
 720
 721 static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
 722                                         struct amdgpu_irq_src *source,
 723                                         unsigned crtc_id,
 724                                         enum amdgpu_interrupt_state state)
 725 {
 726         return dm_irq_state(
 727                 adev,
 728                 source,
 729                 crtc_id,
 730                 state,
 731                 IRQ_TYPE_PFLIP,
 732                 __func__);
 733 }
 734
 735 static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
 736                                         struct amdgpu_irq_src *source,
 737                                         unsigned crtc_id,
 738                                         enum amdgpu_interrupt_state state)
 739 {
 740         return dm_irq_state(
 741                 adev,
 742                 source,
 743                 crtc_id,
 744                 state,
 745                 IRQ_TYPE_VBLANK,
 746                 __func__);
 747 }
 748
 749 static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
 750         .set = amdgpu_dm_set_crtc_irq_state,
 751         .process = amdgpu_dm_irq_handler,
 752 };
 753
 754 static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
 755         .set = amdgpu_dm_set_pflip_irq_state,
 756         .process = amdgpu_dm_irq_handler,
 757 };
 758
 759 static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
 760         .set = amdgpu_dm_set_hpd_irq_state,
 761         .process = amdgpu_dm_irq_handler,
 762 };
 763
 764 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
 765 {
 766         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
 767         adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
 768
 769         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
 770         adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
 771
 772         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
 773         adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
 774 }
 775
 776 /*
 777  * amdgpu_dm_hpd_init - hpd setup callback.
 778  *
 779  * @adev: amdgpu_device pointer
 780  *
 781  * Setup the hpd pins used by the card (evergreen+).
 782  * Enable the pin, set the polarity, and enable the hpd interrupts.
 783  */
 784 void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
 785 {
 786         struct drm_device *dev = adev->ddev;
 787         struct drm_connector *connector;
 788
 789         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 790                 struct amdgpu_dm_connector *amdgpu_dm_connector =
 791                                 to_amdgpu_dm_connector(connector);
 792
 793                 const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
 794
 795                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
 796                         dc_interrupt_set(adev->dm.dc,
 797                                         dc_link->irq_source_hpd,
 798                                         true);
 799                 }
 800
 801                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
 802                         dc_interrupt_set(adev->dm.dc,
 803                                         dc_link->irq_source_hpd_rx,
 804                                         true);
 805                 }
 806         }
 807 }
 808
 809 /**
 810  * amdgpu_dm_hpd_fini - hpd tear down callback.
 811  *
 812  * @adev: amdgpu_device pointer
 813  *
 814  * Tear down the hpd pins used by the card (evergreen+).
 815  * Disable the hpd interrupts.
 816  */
 817 void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
 818 {
 819         struct drm_device *dev = adev->ddev;
 820         struct drm_connector *connector;
 821
 822         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 823                 struct amdgpu_dm_connector *amdgpu_dm_connector =
 824                                 to_amdgpu_dm_connector(connector);
 825                 const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
 826
 827                 dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
 828
 829                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
 830                         dc_interrupt_set(adev->dm.dc,
 831                                         dc_link->irq_source_hpd_rx,
 832                                         false);
 833                 }
 834         }
 835 }