drivers/gpu/drm/amd/include/kgd_pp_interface.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __KGD_PP_INTERFACE_H__
  25 #define __KGD_PP_INTERFACE_H__
  26
  27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
  28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
  29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
  30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
  31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
  32
  33 enum smu_event_type {
  34         SMU_EVENT_RESET_COMPLETE = 0,
  35 };
  36
  37 struct amd_vce_state {
  38         /* vce clocks */
  39         u32 evclk;
  40         u32 ecclk;
  41         /* gpu clocks */
  42         u32 sclk;
  43         u32 mclk;
  44         u8 clk_idx;
  45         u8 pstate;
  46 };
  47
  48
  49 enum amd_dpm_forced_level {
  50         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  51         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  52         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  53         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  54         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  55         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  56         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  57         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  58         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  59         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
  60 };
  61
  62 enum amd_pm_state_type {
  63         /* not used for dpm */
  64         POWER_STATE_TYPE_DEFAULT,
  65         POWER_STATE_TYPE_POWERSAVE,
  66         /* user selectable states */
  67         POWER_STATE_TYPE_BATTERY,
  68         POWER_STATE_TYPE_BALANCED,
  69         POWER_STATE_TYPE_PERFORMANCE,
  70         /* internal states */
  71         POWER_STATE_TYPE_INTERNAL_UVD,
  72         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  73         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  74         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  75         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  76         POWER_STATE_TYPE_INTERNAL_BOOT,
  77         POWER_STATE_TYPE_INTERNAL_THERMAL,
  78         POWER_STATE_TYPE_INTERNAL_ACPI,
  79         POWER_STATE_TYPE_INTERNAL_ULV,
  80         POWER_STATE_TYPE_INTERNAL_3DPERF,
  81 };
  82
  83 #define AMD_MAX_VCE_LEVELS 6
  84
  85 enum amd_vce_level {
  86         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  87         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  88         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  89         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  90         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  91         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  92 };
  93
  94 enum amd_fan_ctrl_mode {
  95         AMD_FAN_CTRL_NONE = 0,
  96         AMD_FAN_CTRL_MANUAL = 1,
  97         AMD_FAN_CTRL_AUTO = 2,
  98 };
  99
 100 enum pp_clock_type {
 101         PP_SCLK,
 102         PP_MCLK,
 103         PP_PCIE,
 104         PP_SOCCLK,
 105         PP_FCLK,
 106         PP_DCEFCLK,
 107         PP_VCLK,
 108         PP_VCLK1,
 109         PP_DCLK,
 110         PP_DCLK1,
 111         OD_SCLK,
 112         OD_MCLK,
 113         OD_VDDC_CURVE,
 114         OD_RANGE,
 115         OD_VDDGFX_OFFSET,
 116         OD_CCLK,
 117         OD_FAN_CURVE,
 118         OD_ACOUSTIC_LIMIT,
 119         OD_ACOUSTIC_TARGET,
 120         OD_FAN_TARGET_TEMPERATURE,
 121         OD_FAN_MINIMUM_PWM,
 122         OD_FAN_ZERO_RPM_ENABLE,
 123         OD_FAN_ZERO_RPM_STOP_TEMP,
 124 };
 125
 126 enum amd_pp_sensors {
 127         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
 128         AMDGPU_PP_SENSOR_CPU_CLK,
 129         AMDGPU_PP_SENSOR_VDDNB,
 130         AMDGPU_PP_SENSOR_VDDGFX,
 131         AMDGPU_PP_SENSOR_UVD_VCLK,
 132         AMDGPU_PP_SENSOR_UVD_DCLK,
 133         AMDGPU_PP_SENSOR_VCE_ECCLK,
 134         AMDGPU_PP_SENSOR_GPU_LOAD,
 135         AMDGPU_PP_SENSOR_MEM_LOAD,
 136         AMDGPU_PP_SENSOR_GFX_MCLK,
 137         AMDGPU_PP_SENSOR_GPU_TEMP,
 138         AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
 139         AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 140         AMDGPU_PP_SENSOR_MEM_TEMP,
 141         AMDGPU_PP_SENSOR_VCE_POWER,
 142         AMDGPU_PP_SENSOR_UVD_POWER,
 143         AMDGPU_PP_SENSOR_GPU_AVG_POWER,
 144         AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
 145         AMDGPU_PP_SENSOR_SS_APU_SHARE,
 146         AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 147         AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 148         AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 149         AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 150         AMDGPU_PP_SENSOR_MIN_FAN_RPM,
 151         AMDGPU_PP_SENSOR_MAX_FAN_RPM,
 152         AMDGPU_PP_SENSOR_VCN_POWER_STATE,
 153         AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
 154         AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
 155         AMDGPU_PP_SENSOR_VCN_LOAD,
 156 };
 157
 158 enum amd_pp_task {
 159         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
 160         AMD_PP_TASK_ENABLE_USER_STATE,
 161         AMD_PP_TASK_READJUST_POWER_STATE,
 162         AMD_PP_TASK_COMPLETE_INIT,
 163         AMD_PP_TASK_MAX
 164 };
 165
 166 enum PP_SMC_POWER_PROFILE {
 167         PP_SMC_POWER_PROFILE_UNKNOWN = -1,
 168         PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
 169         PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
 170         PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
 171         PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
 172         PP_SMC_POWER_PROFILE_VR           = 0x4,
 173         PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
 174         PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 175         PP_SMC_POWER_PROFILE_WINDOW3D     = 0x7,
 176         PP_SMC_POWER_PROFILE_CAPPED       = 0x8,
 177         PP_SMC_POWER_PROFILE_UNCAPPED     = 0x9,
 178         PP_SMC_POWER_PROFILE_COUNT,
 179 };
 180
 181 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
 182
 183
 184
 185 enum {
 186         PP_GROUP_UNKNOWN = 0,
 187         PP_GROUP_GFX = 1,
 188         PP_GROUP_SYS,
 189         PP_GROUP_MAX
 190 };
 191
 192 enum PP_OD_DPM_TABLE_COMMAND {
 193         PP_OD_EDIT_SCLK_VDDC_TABLE,
 194         PP_OD_EDIT_MCLK_VDDC_TABLE,
 195         PP_OD_EDIT_CCLK_VDDC_TABLE,
 196         PP_OD_EDIT_VDDC_CURVE,
 197         PP_OD_RESTORE_DEFAULT_TABLE,
 198         PP_OD_COMMIT_DPM_TABLE,
 199         PP_OD_EDIT_VDDGFX_OFFSET,
 200         PP_OD_EDIT_FAN_CURVE,
 201         PP_OD_EDIT_ACOUSTIC_LIMIT,
 202         PP_OD_EDIT_ACOUSTIC_TARGET,
 203         PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
 204         PP_OD_EDIT_FAN_MINIMUM_PWM,
 205         PP_OD_EDIT_FAN_ZERO_RPM_ENABLE,
 206         PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP,
 207 };
 208
 209 struct pp_states_info {
 210         uint32_t nums;
 211         uint32_t states[16];
 212 };
 213
 214 enum PP_HWMON_TEMP {
 215         PP_TEMP_EDGE = 0,
 216         PP_TEMP_JUNCTION,
 217         PP_TEMP_MEM,
 218         PP_TEMP_MAX
 219 };
 220
 221 enum pp_mp1_state {
 222         PP_MP1_STATE_NONE,
 223         PP_MP1_STATE_SHUTDOWN,
 224         PP_MP1_STATE_UNLOAD,
 225         PP_MP1_STATE_RESET,
 226         PP_MP1_STATE_FLR,
 227 };
 228
 229 enum pp_df_cstate {
 230         DF_CSTATE_DISALLOW = 0,
 231         DF_CSTATE_ALLOW,
 232 };
 233
 234 /**
 235  * DOC: amdgpu_pp_power
 236  *
 237  * APU power is managed to system-level requirements through the PPT
 238  * (package power tracking) feature. PPT is intended to limit power to the
 239  * requirements of the power source and could be dynamically updated to
 240  * maximize APU performance within the system power budget.
 241  *
 242  * Two types of power measurement can be requested, where supported, with
 243  * :c:type:`enum pp_power_type <pp_power_type>`.
 244  */
 245
 246 /**
 247  * enum pp_power_limit_level - Used to query the power limits
 248  *
 249  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
 250  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
 251  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
 252  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
 253  */
 254 enum pp_power_limit_level {
 255         PP_PWR_LIMIT_MIN = -1,
 256         PP_PWR_LIMIT_CURRENT,
 257         PP_PWR_LIMIT_DEFAULT,
 258         PP_PWR_LIMIT_MAX,
 259 };
 260
 261 /**
 262  * enum pp_power_type - Used to specify the type of the requested power
 263  *
 264  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
 265  * moving average of APU power (default ~5000 ms).
 266  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
 267  * where supported.
 268  */
 269 enum pp_power_type {
 270         PP_PWR_TYPE_SUSTAINED,
 271         PP_PWR_TYPE_FAST,
 272 };
 273
 274 enum pp_xgmi_plpd_mode {
 275         XGMI_PLPD_NONE = -1,
 276         XGMI_PLPD_DISALLOW,
 277         XGMI_PLPD_DEFAULT,
 278         XGMI_PLPD_OPTIMIZED,
 279         XGMI_PLPD_COUNT,
 280 };
 281
 282 enum pp_pm_policy {
 283         PP_PM_POLICY_NONE = -1,
 284         PP_PM_POLICY_SOC_PSTATE = 0,
 285         PP_PM_POLICY_XGMI_PLPD,
 286         PP_PM_POLICY_NUM,
 287 };
 288
 289 enum pp_policy_soc_pstate {
 290         SOC_PSTATE_DEFAULT = 0,
 291         SOC_PSTATE_0,
 292         SOC_PSTATE_1,
 293         SOC_PSTATE_2,
 294         SOC_PSTAT_COUNT,
 295 };
 296
 297 #define PP_POLICY_MAX_LEVELS 5
 298
 299 #define PP_GROUP_MASK        0xF0000000
 300 #define PP_GROUP_SHIFT       28
 301
 302 #define PP_BLOCK_MASK        0x0FFFFF00
 303 #define PP_BLOCK_SHIFT       8
 304
 305 #define PP_BLOCK_GFX_CG         0x01
 306 #define PP_BLOCK_GFX_MG         0x02
 307 #define PP_BLOCK_GFX_3D         0x04
 308 #define PP_BLOCK_GFX_RLC        0x08
 309 #define PP_BLOCK_GFX_CP         0x10
 310 #define PP_BLOCK_SYS_BIF        0x01
 311 #define PP_BLOCK_SYS_MC         0x02
 312 #define PP_BLOCK_SYS_ROM        0x04
 313 #define PP_BLOCK_SYS_DRM        0x08
 314 #define PP_BLOCK_SYS_HDP        0x10
 315 #define PP_BLOCK_SYS_SDMA       0x20
 316
 317 #define PP_STATE_MASK           0x0000000F
 318 #define PP_STATE_SHIFT          0
 319 #define PP_STATE_SUPPORT_MASK   0x000000F0
 320 #define PP_STATE_SUPPORT_SHIFT  0
 321
 322 #define PP_STATE_CG             0x01
 323 #define PP_STATE_LS             0x02
 324 #define PP_STATE_DS             0x04
 325 #define PP_STATE_SD             0x08
 326 #define PP_STATE_SUPPORT_CG     0x10
 327 #define PP_STATE_SUPPORT_LS     0x20
 328 #define PP_STATE_SUPPORT_DS     0x40
 329 #define PP_STATE_SUPPORT_SD     0x80
 330
 331 #define PP_CG_MSG_ID(group, block, support, state) \
 332                 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
 333                 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
 334
 335 #define XGMI_MODE_PSTATE_D3 0
 336 #define XGMI_MODE_PSTATE_D0 1
 337
 338 #define NUM_HBM_INSTANCES 4
 339 #define NUM_XGMI_LINKS 8
 340 #define MAX_GFX_CLKS 8
 341 #define MAX_CLKS 4
 342 #define NUM_VCN 4
 343 #define NUM_JPEG_ENG 32
 344 #define MAX_XCC 8
 345 #define NUM_XCP 8
 346 struct seq_file;
 347 enum amd_pp_clock_type;
 348 struct amd_pp_simple_clock_info;
 349 struct amd_pp_display_configuration;
 350 struct amd_pp_clock_info;
 351 struct pp_display_clock_request;
 352 struct pp_clock_levels_with_voltage;
 353 struct pp_clock_levels_with_latency;
 354 struct amd_pp_clocks;
 355 struct pp_smu_wm_range_sets;
 356 struct pp_smu_nv_clock_table;
 357 struct dpm_clocks;
 358
 359 struct amdgpu_xcp_metrics {
 360         /* Utilization Instantaneous (%) */
 361         uint32_t gfx_busy_inst[MAX_XCC];
 362         uint16_t jpeg_busy[NUM_JPEG_ENG];
 363         uint16_t vcn_busy[NUM_VCN];
 364         /* Utilization Accumulated (%) */
 365         uint64_t gfx_busy_acc[MAX_XCC];
 366 };
 367
 368 struct amdgpu_xcp_metrics_v1_1 {
 369         /* Utilization Instantaneous (%) */
 370         uint32_t gfx_busy_inst[MAX_XCC];
 371         uint16_t jpeg_busy[NUM_JPEG_ENG];
 372         uint16_t vcn_busy[NUM_VCN];
 373         /* Utilization Accumulated (%) */
 374         uint64_t gfx_busy_acc[MAX_XCC];
 375         /* Total App Clock Counter Accumulated */
 376         uint64_t gfx_below_host_limit_acc[MAX_XCC];
 377 };
 378
 379 struct amd_pm_funcs {
 380 /* export for dpm on ci and si */
 381         int (*pre_set_power_state)(void *handle);
 382         int (*set_power_state)(void *handle);
 383         void (*post_set_power_state)(void *handle);
 384         void (*display_configuration_changed)(void *handle);
 385         void (*print_power_state)(void *handle, void *ps);
 386         bool (*vblank_too_short)(void *handle);
 387         void (*enable_bapm)(void *handle, bool enable);
 388         int (*check_state_equal)(void *handle,
 389                                 void  *cps,
 390                                 void  *rps,
 391                                 bool  *equal);
 392 /* export for sysfs */
 393         int (*set_fan_control_mode)(void *handle, u32 mode);
 394         int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
 395         int (*set_fan_speed_pwm)(void *handle, u32 speed);
 396         int (*get_fan_speed_pwm)(void *handle, u32 *speed);
 397         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 398         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 399         int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
 400         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 401         int (*get_sclk_od)(void *handle);
 402         int (*set_sclk_od)(void *handle, uint32_t value);
 403         int (*get_mclk_od)(void *handle);
 404         int (*set_mclk_od)(void *handle, uint32_t value);
 405         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 406         int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
 407         int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
 408         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 409         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 410         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 411         int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
 412         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 413         int (*get_pp_table)(void *handle, char **table);
 414         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 415         void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 416         int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 417 /* export to amdgpu */
 418         struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 419         int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 420                         enum amd_pm_state_type *user_state);
 421         int (*load_firmware)(void *handle);
 422         int (*wait_for_fw_loading_complete)(void *handle);
 423         int (*set_powergating_by_smu)(void *handle,
 424                                 uint32_t block_type,
 425                                 bool gate,
 426                                 int inst);
 427         int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 428         int (*set_power_limit)(void *handle, uint32_t n);
 429         int (*get_power_limit)(void *handle, uint32_t *limit,
 430                         enum pp_power_limit_level pp_limit_level,
 431                         enum pp_power_type power_type);
 432         int (*get_power_profile_mode)(void *handle, char *buf);
 433         int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 434         int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
 435         int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
 436                                   long *input, uint32_t size);
 437         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 438         int (*smu_i2c_bus_access)(void *handle, bool acquire);
 439         int (*gfx_state_change_set)(void *handle, uint32_t state);
 440 /* export to DC */
 441         u32 (*get_sclk)(void *handle, bool low);
 442         u32 (*get_mclk)(void *handle, bool low);
 443         int (*display_configuration_change)(void *handle,
 444                 const struct amd_pp_display_configuration *input);
 445         int (*get_display_power_level)(void *handle,
 446                 struct amd_pp_simple_clock_info *output);
 447         int (*get_current_clocks)(void *handle,
 448                 struct amd_pp_clock_info *clocks);
 449         int (*get_clock_by_type)(void *handle,
 450                 enum amd_pp_clock_type type,
 451                 struct amd_pp_clocks *clocks);
 452         int (*get_clock_by_type_with_latency)(void *handle,
 453                 enum amd_pp_clock_type type,
 454                 struct pp_clock_levels_with_latency *clocks);
 455         int (*get_clock_by_type_with_voltage)(void *handle,
 456                 enum amd_pp_clock_type type,
 457                 struct pp_clock_levels_with_voltage *clocks);
 458         int (*set_watermarks_for_clocks_ranges)(void *handle,
 459                                                 void *clock_ranges);
 460         int (*display_clock_voltage_request)(void *handle,
 461                                 struct pp_display_clock_request *clock);
 462         int (*get_display_mode_validation_clocks)(void *handle,
 463                 struct amd_pp_simple_clock_info *clocks);
 464         int (*notify_smu_enable_pwe)(void *handle);
 465         int (*enable_mgpu_fan_boost)(void *handle);
 466         int (*set_active_display_count)(void *handle, uint32_t count);
 467         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 468         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 469         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 470         int (*get_asic_baco_capability)(void *handle);
 471         int (*get_asic_baco_state)(void *handle, int *state);
 472         int (*set_asic_baco_state)(void *handle, int state);
 473         int (*get_ppfeature_status)(void *handle, char *buf);
 474         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 475         int (*asic_reset_mode_2)(void *handle);
 476         int (*asic_reset_enable_gfx_features)(void *handle);
 477         int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
 478         int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
 479         ssize_t (*get_gpu_metrics)(void *handle, void **table);
 480         ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
 481         int (*set_watermarks_for_clock_ranges)(void *handle,
 482                                                struct pp_smu_wm_range_sets *ranges);
 483         int (*display_disable_memory_clock_switch)(void *handle,
 484                                                    bool disable_memory_clock_switch);
 485         int (*get_max_sustainable_clocks_by_dc)(void *handle,
 486                                                 struct pp_smu_nv_clock_table *max_clocks);
 487         int (*get_uclk_dpm_states)(void *handle,
 488                                    unsigned int *clock_values_in_khz,
 489                                    unsigned int *num_states);
 490         int (*get_dpm_clock_table)(void *handle,
 491                                    struct dpm_clocks *clock_table);
 492         int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 493         void (*pm_compute_clocks)(void *handle);
 494         int (*notify_rlc_state)(void *handle, bool en);
 495 };
 496
 497 struct metrics_table_header {
 498         uint16_t                        structure_size;
 499         uint8_t                         format_revision;
 500         uint8_t                         content_revision;
 501 };
 502
 503 /*
 504  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
 505  * Use gpu_metrics_v1_1 or later instead.
 506  */
 507 struct gpu_metrics_v1_0 {
 508         struct metrics_table_header     common_header;
 509
 510         /* Driver attached timestamp (in ns) */
 511         uint64_t                        system_clock_counter;
 512
 513         /* Temperature */
 514         uint16_t                        temperature_edge;
 515         uint16_t                        temperature_hotspot;
 516         uint16_t                        temperature_mem;
 517         uint16_t                        temperature_vrgfx;
 518         uint16_t                        temperature_vrsoc;
 519         uint16_t                        temperature_vrmem;
 520
 521         /* Utilization */
 522         uint16_t                        average_gfx_activity;
 523         uint16_t                        average_umc_activity; // memory controller
 524         uint16_t                        average_mm_activity; // UVD or VCN
 525
 526         /* Power/Energy */
 527         uint16_t                        average_socket_power;
 528         uint32_t                        energy_accumulator;
 529
 530         /* Average clocks */
 531         uint16_t                        average_gfxclk_frequency;
 532         uint16_t                        average_socclk_frequency;
 533         uint16_t                        average_uclk_frequency;
 534         uint16_t                        average_vclk0_frequency;
 535         uint16_t                        average_dclk0_frequency;
 536         uint16_t                        average_vclk1_frequency;
 537         uint16_t                        average_dclk1_frequency;
 538
 539         /* Current clocks */
 540         uint16_t                        current_gfxclk;
 541         uint16_t                        current_socclk;
 542         uint16_t                        current_uclk;
 543         uint16_t                        current_vclk0;
 544         uint16_t                        current_dclk0;
 545         uint16_t                        current_vclk1;
 546         uint16_t                        current_dclk1;
 547
 548         /* Throttle status */
 549         uint32_t                        throttle_status;
 550
 551         /* Fans */
 552         uint16_t                        current_fan_speed;
 553
 554         /* Link width/speed */
 555         uint8_t                         pcie_link_width;
 556         uint8_t                         pcie_link_speed; // in 0.1 GT/s
 557 };
 558
 559 struct gpu_metrics_v1_1 {
 560         struct metrics_table_header     common_header;
 561
 562         /* Temperature */
 563         uint16_t                        temperature_edge;
 564         uint16_t                        temperature_hotspot;
 565         uint16_t                        temperature_mem;
 566         uint16_t                        temperature_vrgfx;
 567         uint16_t                        temperature_vrsoc;
 568         uint16_t                        temperature_vrmem;
 569
 570         /* Utilization */
 571         uint16_t                        average_gfx_activity;
 572         uint16_t                        average_umc_activity; // memory controller
 573         uint16_t                        average_mm_activity; // UVD or VCN
 574
 575         /* Power/Energy */
 576         uint16_t                        average_socket_power;
 577         uint64_t                        energy_accumulator;
 578
 579         /* Driver attached timestamp (in ns) */
 580         uint64_t                        system_clock_counter;
 581
 582         /* Average clocks */
 583         uint16_t                        average_gfxclk_frequency;
 584         uint16_t                        average_socclk_frequency;
 585         uint16_t                        average_uclk_frequency;
 586         uint16_t                        average_vclk0_frequency;
 587         uint16_t                        average_dclk0_frequency;
 588         uint16_t                        average_vclk1_frequency;
 589         uint16_t                        average_dclk1_frequency;
 590
 591         /* Current clocks */
 592         uint16_t                        current_gfxclk;
 593         uint16_t                        current_socclk;
 594         uint16_t                        current_uclk;
 595         uint16_t                        current_vclk0;
 596         uint16_t                        current_dclk0;
 597         uint16_t                        current_vclk1;
 598         uint16_t                        current_dclk1;
 599
 600         /* Throttle status */
 601         uint32_t                        throttle_status;
 602
 603         /* Fans */
 604         uint16_t                        current_fan_speed;
 605
 606         /* Link width/speed */
 607         uint16_t                        pcie_link_width;
 608         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 609
 610         uint16_t                        padding;
 611
 612         uint32_t                        gfx_activity_acc;
 613         uint32_t                        mem_activity_acc;
 614
 615         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 616 };
 617
 618 struct gpu_metrics_v1_2 {
 619         struct metrics_table_header     common_header;
 620
 621         /* Temperature */
 622         uint16_t                        temperature_edge;
 623         uint16_t                        temperature_hotspot;
 624         uint16_t                        temperature_mem;
 625         uint16_t                        temperature_vrgfx;
 626         uint16_t                        temperature_vrsoc;
 627         uint16_t                        temperature_vrmem;
 628
 629         /* Utilization */
 630         uint16_t                        average_gfx_activity;
 631         uint16_t                        average_umc_activity; // memory controller
 632         uint16_t                        average_mm_activity; // UVD or VCN
 633
 634         /* Power/Energy */
 635         uint16_t                        average_socket_power;
 636         uint64_t                        energy_accumulator;
 637
 638         /* Driver attached timestamp (in ns) */
 639         uint64_t                        system_clock_counter;
 640
 641         /* Average clocks */
 642         uint16_t                        average_gfxclk_frequency;
 643         uint16_t                        average_socclk_frequency;
 644         uint16_t                        average_uclk_frequency;
 645         uint16_t                        average_vclk0_frequency;
 646         uint16_t                        average_dclk0_frequency;
 647         uint16_t                        average_vclk1_frequency;
 648         uint16_t                        average_dclk1_frequency;
 649
 650         /* Current clocks */
 651         uint16_t                        current_gfxclk;
 652         uint16_t                        current_socclk;
 653         uint16_t                        current_uclk;
 654         uint16_t                        current_vclk0;
 655         uint16_t                        current_dclk0;
 656         uint16_t                        current_vclk1;
 657         uint16_t                        current_dclk1;
 658
 659         /* Throttle status (ASIC dependent) */
 660         uint32_t                        throttle_status;
 661
 662         /* Fans */
 663         uint16_t                        current_fan_speed;
 664
 665         /* Link width/speed */
 666         uint16_t                        pcie_link_width;
 667         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 668
 669         uint16_t                        padding;
 670
 671         uint32_t                        gfx_activity_acc;
 672         uint32_t                        mem_activity_acc;
 673
 674         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 675
 676         /* PMFW attached timestamp (10ns resolution) */
 677         uint64_t                        firmware_timestamp;
 678 };
 679
 680 struct gpu_metrics_v1_3 {
 681         struct metrics_table_header     common_header;
 682
 683         /* Temperature */
 684         uint16_t                        temperature_edge;
 685         uint16_t                        temperature_hotspot;
 686         uint16_t                        temperature_mem;
 687         uint16_t                        temperature_vrgfx;
 688         uint16_t                        temperature_vrsoc;
 689         uint16_t                        temperature_vrmem;
 690
 691         /* Utilization */
 692         uint16_t                        average_gfx_activity;
 693         uint16_t                        average_umc_activity; // memory controller
 694         uint16_t                        average_mm_activity; // UVD or VCN
 695
 696         /* Power/Energy */
 697         uint16_t                        average_socket_power;
 698         uint64_t                        energy_accumulator;
 699
 700         /* Driver attached timestamp (in ns) */
 701         uint64_t                        system_clock_counter;
 702
 703         /* Average clocks */
 704         uint16_t                        average_gfxclk_frequency;
 705         uint16_t                        average_socclk_frequency;
 706         uint16_t                        average_uclk_frequency;
 707         uint16_t                        average_vclk0_frequency;
 708         uint16_t                        average_dclk0_frequency;
 709         uint16_t                        average_vclk1_frequency;
 710         uint16_t                        average_dclk1_frequency;
 711
 712         /* Current clocks */
 713         uint16_t                        current_gfxclk;
 714         uint16_t                        current_socclk;
 715         uint16_t                        current_uclk;
 716         uint16_t                        current_vclk0;
 717         uint16_t                        current_dclk0;
 718         uint16_t                        current_vclk1;
 719         uint16_t                        current_dclk1;
 720
 721         /* Throttle status */
 722         uint32_t                        throttle_status;
 723
 724         /* Fans */
 725         uint16_t                        current_fan_speed;
 726
 727         /* Link width/speed */
 728         uint16_t                        pcie_link_width;
 729         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 730
 731         uint16_t                        padding;
 732
 733         uint32_t                        gfx_activity_acc;
 734         uint32_t                        mem_activity_acc;
 735
 736         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 737
 738         /* PMFW attached timestamp (10ns resolution) */
 739         uint64_t                        firmware_timestamp;
 740
 741         /* Voltage (mV) */
 742         uint16_t                        voltage_soc;
 743         uint16_t                        voltage_gfx;
 744         uint16_t                        voltage_mem;
 745
 746         uint16_t                        padding1;
 747
 748         /* Throttle status (ASIC independent) */
 749         uint64_t                        indep_throttle_status;
 750 };
 751
 752 struct gpu_metrics_v1_4 {
 753         struct metrics_table_header     common_header;
 754
 755         /* Temperature (Celsius) */
 756         uint16_t                        temperature_hotspot;
 757         uint16_t                        temperature_mem;
 758         uint16_t                        temperature_vrsoc;
 759
 760         /* Power (Watts) */
 761         uint16_t                        curr_socket_power;
 762
 763         /* Utilization (%) */
 764         uint16_t                        average_gfx_activity;
 765         uint16_t                        average_umc_activity; // memory controller
 766         uint16_t                        vcn_activity[NUM_VCN];
 767
 768         /* Energy (15.259uJ (2^-16) units) */
 769         uint64_t                        energy_accumulator;
 770
 771         /* Driver attached timestamp (in ns) */
 772         uint64_t                        system_clock_counter;
 773
 774         /* Throttle status */
 775         uint32_t                        throttle_status;
 776
 777         /* Clock Lock Status. Each bit corresponds to clock instance */
 778         uint32_t                        gfxclk_lock_status;
 779
 780         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 781         uint16_t                        pcie_link_width;
 782         uint16_t                        pcie_link_speed;
 783
 784         /* XGMI bus width and bitrate (in Gbps) */
 785         uint16_t                        xgmi_link_width;
 786         uint16_t                        xgmi_link_speed;
 787
 788         /* Utilization Accumulated (%) */
 789         uint32_t                        gfx_activity_acc;
 790         uint32_t                        mem_activity_acc;
 791
 792         /*PCIE accumulated bandwidth (GB/sec) */
 793         uint64_t                        pcie_bandwidth_acc;
 794
 795         /*PCIE instantaneous bandwidth (GB/sec) */
 796         uint64_t                        pcie_bandwidth_inst;
 797
 798         /* PCIE L0 to recovery state transition accumulated count */
 799         uint64_t                        pcie_l0_to_recov_count_acc;
 800
 801         /* PCIE replay accumulated count */
 802         uint64_t                        pcie_replay_count_acc;
 803
 804         /* PCIE replay rollover accumulated count */
 805         uint64_t                        pcie_replay_rover_count_acc;
 806
 807         /* XGMI accumulated data transfer size(KiloBytes) */
 808         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 809         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 810
 811         /* PMFW attached timestamp (10ns resolution) */
 812         uint64_t                        firmware_timestamp;
 813
 814         /* Current clocks (Mhz) */
 815         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 816         uint16_t                        current_socclk[MAX_CLKS];
 817         uint16_t                        current_vclk0[MAX_CLKS];
 818         uint16_t                        current_dclk0[MAX_CLKS];
 819         uint16_t                        current_uclk;
 820
 821         uint16_t                        padding;
 822 };
 823
 824 struct gpu_metrics_v1_5 {
 825         struct metrics_table_header     common_header;
 826
 827         /* Temperature (Celsius) */
 828         uint16_t                        temperature_hotspot;
 829         uint16_t                        temperature_mem;
 830         uint16_t                        temperature_vrsoc;
 831
 832         /* Power (Watts) */
 833         uint16_t                        curr_socket_power;
 834
 835         /* Utilization (%) */
 836         uint16_t                        average_gfx_activity;
 837         uint16_t                        average_umc_activity; // memory controller
 838         uint16_t                        vcn_activity[NUM_VCN];
 839         uint16_t                        jpeg_activity[NUM_JPEG_ENG];
 840
 841         /* Energy (15.259uJ (2^-16) units) */
 842         uint64_t                        energy_accumulator;
 843
 844         /* Driver attached timestamp (in ns) */
 845         uint64_t                        system_clock_counter;
 846
 847         /* Throttle status */
 848         uint32_t                        throttle_status;
 849
 850         /* Clock Lock Status. Each bit corresponds to clock instance */
 851         uint32_t                        gfxclk_lock_status;
 852
 853         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 854         uint16_t                        pcie_link_width;
 855         uint16_t                        pcie_link_speed;
 856
 857         /* XGMI bus width and bitrate (in Gbps) */
 858         uint16_t                        xgmi_link_width;
 859         uint16_t                        xgmi_link_speed;
 860
 861         /* Utilization Accumulated (%) */
 862         uint32_t                        gfx_activity_acc;
 863         uint32_t                        mem_activity_acc;
 864
 865         /*PCIE accumulated bandwidth (GB/sec) */
 866         uint64_t                        pcie_bandwidth_acc;
 867
 868         /*PCIE instantaneous bandwidth (GB/sec) */
 869         uint64_t                        pcie_bandwidth_inst;
 870
 871         /* PCIE L0 to recovery state transition accumulated count */
 872         uint64_t                        pcie_l0_to_recov_count_acc;
 873
 874         /* PCIE replay accumulated count */
 875         uint64_t                        pcie_replay_count_acc;
 876
 877         /* PCIE replay rollover accumulated count */
 878         uint64_t                        pcie_replay_rover_count_acc;
 879
 880         /* PCIE NAK sent  accumulated count */
 881         uint32_t                        pcie_nak_sent_count_acc;
 882
 883         /* PCIE NAK received accumulated count */
 884         uint32_t                        pcie_nak_rcvd_count_acc;
 885
 886         /* XGMI accumulated data transfer size(KiloBytes) */
 887         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 888         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 889
 890         /* PMFW attached timestamp (10ns resolution) */
 891         uint64_t                        firmware_timestamp;
 892
 893         /* Current clocks (Mhz) */
 894         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 895         uint16_t                        current_socclk[MAX_CLKS];
 896         uint16_t                        current_vclk0[MAX_CLKS];
 897         uint16_t                        current_dclk0[MAX_CLKS];
 898         uint16_t                        current_uclk;
 899
 900         uint16_t                        padding;
 901 };
 902
 903 struct gpu_metrics_v1_6 {
 904         struct metrics_table_header     common_header;
 905
 906         /* Temperature (Celsius) */
 907         uint16_t                        temperature_hotspot;
 908         uint16_t                        temperature_mem;
 909         uint16_t                        temperature_vrsoc;
 910
 911         /* Power (Watts) */
 912         uint16_t                        curr_socket_power;
 913
 914         /* Utilization (%) */
 915         uint16_t                        average_gfx_activity;
 916         uint16_t                        average_umc_activity; // memory controller
 917
 918         /* Energy (15.259uJ (2^-16) units) */
 919         uint64_t                        energy_accumulator;
 920
 921         /* Driver attached timestamp (in ns) */
 922         uint64_t                        system_clock_counter;
 923
 924         /* Accumulation cycle counter */
 925         uint32_t                        accumulation_counter;
 926
 927         /* Accumulated throttler residencies */
 928         uint32_t                        prochot_residency_acc;
 929         uint32_t                        ppt_residency_acc;
 930         uint32_t                        socket_thm_residency_acc;
 931         uint32_t                        vr_thm_residency_acc;
 932         uint32_t                        hbm_thm_residency_acc;
 933
 934         /* Clock Lock Status. Each bit corresponds to clock instance */
 935         uint32_t                        gfxclk_lock_status;
 936
 937         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 938         uint16_t                        pcie_link_width;
 939         uint16_t                        pcie_link_speed;
 940
 941         /* XGMI bus width and bitrate (in Gbps) */
 942         uint16_t                        xgmi_link_width;
 943         uint16_t                        xgmi_link_speed;
 944
 945         /* Utilization Accumulated (%) */
 946         uint32_t                        gfx_activity_acc;
 947         uint32_t                        mem_activity_acc;
 948
 949         /*PCIE accumulated bandwidth (GB/sec) */
 950         uint64_t                        pcie_bandwidth_acc;
 951
 952         /*PCIE instantaneous bandwidth (GB/sec) */
 953         uint64_t                        pcie_bandwidth_inst;
 954
 955         /* PCIE L0 to recovery state transition accumulated count */
 956         uint64_t                        pcie_l0_to_recov_count_acc;
 957
 958         /* PCIE replay accumulated count */
 959         uint64_t                        pcie_replay_count_acc;
 960
 961         /* PCIE replay rollover accumulated count */
 962         uint64_t                        pcie_replay_rover_count_acc;
 963
 964         /* PCIE NAK sent  accumulated count */
 965         uint32_t                        pcie_nak_sent_count_acc;
 966
 967         /* PCIE NAK received accumulated count */
 968         uint32_t                        pcie_nak_rcvd_count_acc;
 969
 970         /* XGMI accumulated data transfer size(KiloBytes) */
 971         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 972         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 973
 974         /* PMFW attached timestamp (10ns resolution) */
 975         uint64_t                        firmware_timestamp;
 976
 977         /* Current clocks (Mhz) */
 978         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 979         uint16_t                        current_socclk[MAX_CLKS];
 980         uint16_t                        current_vclk0[MAX_CLKS];
 981         uint16_t                        current_dclk0[MAX_CLKS];
 982         uint16_t                        current_uclk;
 983
 984         /* Number of current partition */
 985         uint16_t                        num_partition;
 986
 987         /* XCP metrics stats */
 988         struct amdgpu_xcp_metrics       xcp_stats[NUM_XCP];
 989
 990         /* PCIE other end recovery counter */
 991         uint32_t                        pcie_lc_perf_other_end_recovery;
 992 };
 993
 994 struct gpu_metrics_v1_7 {
 995         struct metrics_table_header     common_header;
 996
 997         /* Temperature (Celsius) */
 998         uint16_t                        temperature_hotspot;
 999         uint16_t                        temperature_mem;
1000         uint16_t                        temperature_vrsoc;
1001
1002         /* Power (Watts) */
1003         uint16_t                        curr_socket_power;
1004
1005         /* Utilization (%) */
1006         uint16_t                        average_gfx_activity;
1007         uint16_t                        average_umc_activity; // memory controller
1008
1009         /* VRAM max bandwidthi (in GB/sec) at max memory clock */
1010         uint64_t                        mem_max_bandwidth;
1011
1012         /* Energy (15.259uJ (2^-16) units) */
1013         uint64_t                        energy_accumulator;
1014
1015         /* Driver attached timestamp (in ns) */
1016         uint64_t                        system_clock_counter;
1017
1018         /* Accumulation cycle counter */
1019         uint32_t                        accumulation_counter;
1020
1021         /* Accumulated throttler residencies */
1022         uint32_t                        prochot_residency_acc;
1023         uint32_t                        ppt_residency_acc;
1024         uint32_t                        socket_thm_residency_acc;
1025         uint32_t                        vr_thm_residency_acc;
1026         uint32_t                        hbm_thm_residency_acc;
1027
1028         /* Clock Lock Status. Each bit corresponds to clock instance */
1029         uint32_t                        gfxclk_lock_status;
1030
1031         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
1032         uint16_t                        pcie_link_width;
1033         uint16_t                        pcie_link_speed;
1034
1035         /* XGMI bus width and bitrate (in Gbps) */
1036         uint16_t                        xgmi_link_width;
1037         uint16_t                        xgmi_link_speed;
1038
1039         /* Utilization Accumulated (%) */
1040         uint32_t                        gfx_activity_acc;
1041         uint32_t                        mem_activity_acc;
1042
1043         /*PCIE accumulated bandwidth (GB/sec) */
1044         uint64_t                        pcie_bandwidth_acc;
1045
1046         /*PCIE instantaneous bandwidth (GB/sec) */
1047         uint64_t                        pcie_bandwidth_inst;
1048
1049         /* PCIE L0 to recovery state transition accumulated count */
1050         uint64_t                        pcie_l0_to_recov_count_acc;
1051
1052         /* PCIE replay accumulated count */
1053         uint64_t                        pcie_replay_count_acc;
1054
1055         /* PCIE replay rollover accumulated count */
1056         uint64_t                        pcie_replay_rover_count_acc;
1057
1058         /* PCIE NAK sent  accumulated count */
1059         uint32_t                        pcie_nak_sent_count_acc;
1060
1061         /* PCIE NAK received accumulated count */
1062         uint32_t                        pcie_nak_rcvd_count_acc;
1063
1064         /* XGMI accumulated data transfer size(KiloBytes) */
1065         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
1066         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
1067
1068         /* XGMI link status(active/inactive) */
1069         uint16_t                        xgmi_link_status[NUM_XGMI_LINKS];
1070
1071         uint16_t                        padding;
1072
1073         /* PMFW attached timestamp (10ns resolution) */
1074         uint64_t                        firmware_timestamp;
1075
1076         /* Current clocks (Mhz) */
1077         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
1078         uint16_t                        current_socclk[MAX_CLKS];
1079         uint16_t                        current_vclk0[MAX_CLKS];
1080         uint16_t                        current_dclk0[MAX_CLKS];
1081         uint16_t                        current_uclk;
1082
1083         /* Number of current partition */
1084         uint16_t                        num_partition;
1085
1086         /* XCP metrics stats */
1087         struct amdgpu_xcp_metrics_v1_1  xcp_stats[NUM_XCP];
1088
1089         /* PCIE other end recovery counter */
1090         uint32_t                        pcie_lc_perf_other_end_recovery;
1091 };
1092
1093 /*
1094  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
1095  * Use gpu_metrics_v2_1 or later instead.
1096  */
1097 struct gpu_metrics_v2_0 {
1098         struct metrics_table_header     common_header;
1099
1100         /* Driver attached timestamp (in ns) */
1101         uint64_t                        system_clock_counter;
1102
1103         /* Temperature */
1104         uint16_t                        temperature_gfx; // gfx temperature on APUs
1105         uint16_t                        temperature_soc; // soc temperature on APUs
1106         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1107         uint16_t                        temperature_l3[2];
1108
1109         /* Utilization */
1110         uint16_t                        average_gfx_activity;
1111         uint16_t                        average_mm_activity; // UVD or VCN
1112
1113         /* Power/Energy */
1114         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1115         uint16_t                        average_cpu_power;
1116         uint16_t                        average_soc_power;
1117         uint16_t                        average_gfx_power;
1118         uint16_t                        average_core_power[8]; // CPU core power on APUs
1119
1120         /* Average clocks */
1121         uint16_t                        average_gfxclk_frequency;
1122         uint16_t                        average_socclk_frequency;
1123         uint16_t                        average_uclk_frequency;
1124         uint16_t                        average_fclk_frequency;
1125         uint16_t                        average_vclk_frequency;
1126         uint16_t                        average_dclk_frequency;
1127
1128         /* Current clocks */
1129         uint16_t                        current_gfxclk;
1130         uint16_t                        current_socclk;
1131         uint16_t                        current_uclk;
1132         uint16_t                        current_fclk;
1133         uint16_t                        current_vclk;
1134         uint16_t                        current_dclk;
1135         uint16_t                        current_coreclk[8]; // CPU core clocks
1136         uint16_t                        current_l3clk[2];
1137
1138         /* Throttle status */
1139         uint32_t                        throttle_status;
1140
1141         /* Fans */
1142         uint16_t                        fan_pwm;
1143
1144         uint16_t                        padding;
1145 };
1146
1147 struct gpu_metrics_v2_1 {
1148         struct metrics_table_header     common_header;
1149
1150         /* Temperature */
1151         uint16_t                        temperature_gfx; // gfx temperature on APUs
1152         uint16_t                        temperature_soc; // soc temperature on APUs
1153         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1154         uint16_t                        temperature_l3[2];
1155
1156         /* Utilization */
1157         uint16_t                        average_gfx_activity;
1158         uint16_t                        average_mm_activity; // UVD or VCN
1159
1160         /* Driver attached timestamp (in ns) */
1161         uint64_t                        system_clock_counter;
1162
1163         /* Power/Energy */
1164         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1165         uint16_t                        average_cpu_power;
1166         uint16_t                        average_soc_power;
1167         uint16_t                        average_gfx_power;
1168         uint16_t                        average_core_power[8]; // CPU core power on APUs
1169
1170         /* Average clocks */
1171         uint16_t                        average_gfxclk_frequency;
1172         uint16_t                        average_socclk_frequency;
1173         uint16_t                        average_uclk_frequency;
1174         uint16_t                        average_fclk_frequency;
1175         uint16_t                        average_vclk_frequency;
1176         uint16_t                        average_dclk_frequency;
1177
1178         /* Current clocks */
1179         uint16_t                        current_gfxclk;
1180         uint16_t                        current_socclk;
1181         uint16_t                        current_uclk;
1182         uint16_t                        current_fclk;
1183         uint16_t                        current_vclk;
1184         uint16_t                        current_dclk;
1185         uint16_t                        current_coreclk[8]; // CPU core clocks
1186         uint16_t                        current_l3clk[2];
1187
1188         /* Throttle status */
1189         uint32_t                        throttle_status;
1190
1191         /* Fans */
1192         uint16_t                        fan_pwm;
1193
1194         uint16_t                        padding[3];
1195 };
1196
1197 struct gpu_metrics_v2_2 {
1198         struct metrics_table_header     common_header;
1199
1200         /* Temperature */
1201         uint16_t                        temperature_gfx; // gfx temperature on APUs
1202         uint16_t                        temperature_soc; // soc temperature on APUs
1203         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1204         uint16_t                        temperature_l3[2];
1205
1206         /* Utilization */
1207         uint16_t                        average_gfx_activity;
1208         uint16_t                        average_mm_activity; // UVD or VCN
1209
1210         /* Driver attached timestamp (in ns) */
1211         uint64_t                        system_clock_counter;
1212
1213         /* Power/Energy */
1214         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1215         uint16_t                        average_cpu_power;
1216         uint16_t                        average_soc_power;
1217         uint16_t                        average_gfx_power;
1218         uint16_t                        average_core_power[8]; // CPU core power on APUs
1219
1220         /* Average clocks */
1221         uint16_t                        average_gfxclk_frequency;
1222         uint16_t                        average_socclk_frequency;
1223         uint16_t                        average_uclk_frequency;
1224         uint16_t                        average_fclk_frequency;
1225         uint16_t                        average_vclk_frequency;
1226         uint16_t                        average_dclk_frequency;
1227
1228         /* Current clocks */
1229         uint16_t                        current_gfxclk;
1230         uint16_t                        current_socclk;
1231         uint16_t                        current_uclk;
1232         uint16_t                        current_fclk;
1233         uint16_t                        current_vclk;
1234         uint16_t                        current_dclk;
1235         uint16_t                        current_coreclk[8]; // CPU core clocks
1236         uint16_t                        current_l3clk[2];
1237
1238         /* Throttle status (ASIC dependent) */
1239         uint32_t                        throttle_status;
1240
1241         /* Fans */
1242         uint16_t                        fan_pwm;
1243
1244         uint16_t                        padding[3];
1245
1246         /* Throttle status (ASIC independent) */
1247         uint64_t                        indep_throttle_status;
1248 };
1249
1250 struct gpu_metrics_v2_3 {
1251         struct metrics_table_header     common_header;
1252
1253         /* Temperature */
1254         uint16_t                        temperature_gfx; // gfx temperature on APUs
1255         uint16_t                        temperature_soc; // soc temperature on APUs
1256         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1257         uint16_t                        temperature_l3[2];
1258
1259         /* Utilization */
1260         uint16_t                        average_gfx_activity;
1261         uint16_t                        average_mm_activity; // UVD or VCN
1262
1263         /* Driver attached timestamp (in ns) */
1264         uint64_t                        system_clock_counter;
1265
1266         /* Power/Energy */
1267         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1268         uint16_t                        average_cpu_power;
1269         uint16_t                        average_soc_power;
1270         uint16_t                        average_gfx_power;
1271         uint16_t                        average_core_power[8]; // CPU core power on APUs
1272
1273         /* Average clocks */
1274         uint16_t                        average_gfxclk_frequency;
1275         uint16_t                        average_socclk_frequency;
1276         uint16_t                        average_uclk_frequency;
1277         uint16_t                        average_fclk_frequency;
1278         uint16_t                        average_vclk_frequency;
1279         uint16_t                        average_dclk_frequency;
1280
1281         /* Current clocks */
1282         uint16_t                        current_gfxclk;
1283         uint16_t                        current_socclk;
1284         uint16_t                        current_uclk;
1285         uint16_t                        current_fclk;
1286         uint16_t                        current_vclk;
1287         uint16_t                        current_dclk;
1288         uint16_t                        current_coreclk[8]; // CPU core clocks
1289         uint16_t                        current_l3clk[2];
1290
1291         /* Throttle status (ASIC dependent) */
1292         uint32_t                        throttle_status;
1293
1294         /* Fans */
1295         uint16_t                        fan_pwm;
1296
1297         uint16_t                        padding[3];
1298
1299         /* Throttle status (ASIC independent) */
1300         uint64_t                        indep_throttle_status;
1301
1302         /* Average Temperature */
1303         uint16_t                        average_temperature_gfx; // average gfx temperature on APUs
1304         uint16_t                        average_temperature_soc; // average soc temperature on APUs
1305         uint16_t                        average_temperature_core[8]; // average CPU core temperature on APUs
1306         uint16_t                        average_temperature_l3[2];
1307 };
1308
1309 struct gpu_metrics_v2_4 {
1310         struct metrics_table_header     common_header;
1311
1312         /* Temperature (unit: centi-Celsius) */
1313         uint16_t                        temperature_gfx;
1314         uint16_t                        temperature_soc;
1315         uint16_t                        temperature_core[8];
1316         uint16_t                        temperature_l3[2];
1317
1318         /* Utilization (unit: centi) */
1319         uint16_t                        average_gfx_activity;
1320         uint16_t                        average_mm_activity;
1321
1322         /* Driver attached timestamp (in ns) */
1323         uint64_t                        system_clock_counter;
1324
1325         /* Power/Energy (unit: mW) */
1326         uint16_t                        average_socket_power;
1327         uint16_t                        average_cpu_power;
1328         uint16_t                        average_soc_power;
1329         uint16_t                        average_gfx_power;
1330         uint16_t                        average_core_power[8];
1331
1332         /* Average clocks (unit: MHz) */
1333         uint16_t                        average_gfxclk_frequency;
1334         uint16_t                        average_socclk_frequency;
1335         uint16_t                        average_uclk_frequency;
1336         uint16_t                        average_fclk_frequency;
1337         uint16_t                        average_vclk_frequency;
1338         uint16_t                        average_dclk_frequency;
1339
1340         /* Current clocks (unit: MHz) */
1341         uint16_t                        current_gfxclk;
1342         uint16_t                        current_socclk;
1343         uint16_t                        current_uclk;
1344         uint16_t                        current_fclk;
1345         uint16_t                        current_vclk;
1346         uint16_t                        current_dclk;
1347         uint16_t                        current_coreclk[8];
1348         uint16_t                        current_l3clk[2];
1349
1350         /* Throttle status (ASIC dependent) */
1351         uint32_t                        throttle_status;
1352
1353         /* Fans */
1354         uint16_t                        fan_pwm;
1355
1356         uint16_t                        padding[3];
1357
1358         /* Throttle status (ASIC independent) */
1359         uint64_t                        indep_throttle_status;
1360
1361         /* Average Temperature (unit: centi-Celsius) */
1362         uint16_t                        average_temperature_gfx;
1363         uint16_t                        average_temperature_soc;
1364         uint16_t                        average_temperature_core[8];
1365         uint16_t                        average_temperature_l3[2];
1366
1367         /* Power/Voltage (unit: mV) */
1368         uint16_t                        average_cpu_voltage;
1369         uint16_t                        average_soc_voltage;
1370         uint16_t                        average_gfx_voltage;
1371
1372         /* Power/Current (unit: mA) */
1373         uint16_t                        average_cpu_current;
1374         uint16_t                        average_soc_current;
1375         uint16_t                        average_gfx_current;
1376 };
1377
1378 struct gpu_metrics_v3_0 {
1379         struct metrics_table_header     common_header;
1380
1381         /* Temperature */
1382         /* gfx temperature on APUs */
1383         uint16_t                        temperature_gfx;
1384         /* soc temperature on APUs */
1385         uint16_t                        temperature_soc;
1386         /* CPU core temperature on APUs */
1387         uint16_t                        temperature_core[16];
1388         /* skin temperature on APUs */
1389         uint16_t                        temperature_skin;
1390
1391         /* Utilization */
1392         /* time filtered GFX busy % [0-100] */
1393         uint16_t                        average_gfx_activity;
1394         /* time filtered VCN busy % [0-100] */
1395         uint16_t                        average_vcn_activity;
1396         /* time filtered IPU per-column busy % [0-100] */
1397         uint16_t                        average_ipu_activity[8];
1398         /* time filtered per-core C0 residency % [0-100]*/
1399         uint16_t                        average_core_c0_activity[16];
1400         /* time filtered DRAM read bandwidth [MB/sec] */
1401         uint16_t                        average_dram_reads;
1402         /* time filtered DRAM write bandwidth [MB/sec] */
1403         uint16_t                        average_dram_writes;
1404         /* time filtered IPU read bandwidth [MB/sec] */
1405         uint16_t                        average_ipu_reads;
1406         /* time filtered IPU write bandwidth [MB/sec] */
1407         uint16_t                        average_ipu_writes;
1408
1409         /* Driver attached timestamp (in ns) */
1410         uint64_t                        system_clock_counter;
1411
1412         /* Power/Energy */
1413         /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1414         uint32_t                        average_socket_power;
1415         /* time filtered IPU power [mW] */
1416         uint16_t                        average_ipu_power;
1417         /* time filtered APU power [mW] */
1418         uint32_t                        average_apu_power;
1419         /* time filtered GFX power [mW] */
1420         uint32_t                        average_gfx_power;
1421         /* time filtered dGPU power [mW] */
1422         uint32_t                        average_dgpu_power;
1423         /* time filtered sum of core power across all cores in the socket [mW] */
1424         uint32_t                        average_all_core_power;
1425         /* calculated core power [mW] */
1426         uint16_t                        average_core_power[16];
1427         /* time filtered total system power [mW] */
1428         uint16_t                        average_sys_power;
1429         /* maximum IRM defined STAPM power limit [mW] */
1430         uint16_t                        stapm_power_limit;
1431         /* time filtered STAPM power limit [mW] */
1432         uint16_t                        current_stapm_power_limit;
1433
1434         /* time filtered clocks [MHz] */
1435         uint16_t                        average_gfxclk_frequency;
1436         uint16_t                        average_socclk_frequency;
1437         uint16_t                        average_vpeclk_frequency;
1438         uint16_t                        average_ipuclk_frequency;
1439         uint16_t                        average_fclk_frequency;
1440         uint16_t                        average_vclk_frequency;
1441         uint16_t                        average_uclk_frequency;
1442         uint16_t                        average_mpipu_frequency;
1443
1444         /* Current clocks */
1445         /* target core frequency [MHz] */
1446         uint16_t                        current_coreclk[16];
1447         /* CCLK frequency limit enforced on classic cores [MHz] */
1448         uint16_t                        current_core_maxfreq;
1449         /* GFXCLK frequency limit enforced on GFX [MHz] */
1450         uint16_t                        current_gfx_maxfreq;
1451
1452         /* Throttle Residency (ASIC dependent) */
1453         uint32_t                        throttle_residency_prochot;
1454         uint32_t                        throttle_residency_spl;
1455         uint32_t                        throttle_residency_fppt;
1456         uint32_t                        throttle_residency_sppt;
1457         uint32_t                        throttle_residency_thm_core;
1458         uint32_t                        throttle_residency_thm_gfx;
1459         uint32_t                        throttle_residency_thm_soc;
1460
1461         /* Metrics table alpha filter time constant [us] */
1462         uint32_t                        time_filter_alphavalue;
1463 };
1464
1465 struct amdgpu_pmmetrics_header {
1466         uint16_t structure_size;
1467         uint16_t pad;
1468         uint32_t mp1_ip_discovery_version;
1469         uint32_t pmfw_version;
1470         uint32_t pmmetrics_version;
1471 };
1472
1473 struct amdgpu_pm_metrics {
1474         struct amdgpu_pmmetrics_header common_header;
1475
1476         uint8_t data[];
1477 };
1478
1479 #endif