drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39
  40
  41
  42 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
  43                                                 struct ttm_mem_reg *mem)
  44 {
  45         if (mem->start << PAGE_SHIFT >= adev->mc.visible_vram_size)
  46                 return 0;
  47
  48         return ((mem->start << PAGE_SHIFT) + mem->size) >
  49                 adev->mc.visible_vram_size ?
  50                 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
  51                 mem->size;
  52 }
  53
  54 static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
  55                        struct ttm_mem_reg *old_mem,
  56                        struct ttm_mem_reg *new_mem)
  57 {
  58         u64 vis_size;
  59         if (!adev)
  60                 return;
  61
  62         if (new_mem) {
  63                 switch (new_mem->mem_type) {
  64                 case TTM_PL_TT:
  65                         atomic64_add(new_mem->size, &adev->gtt_usage);
  66                         break;
  67                 case TTM_PL_VRAM:
  68                         atomic64_add(new_mem->size, &adev->vram_usage);
  69                         vis_size = amdgpu_get_vis_part_size(adev, new_mem);
  70                         atomic64_add(vis_size, &adev->vram_vis_usage);
  71                         break;
  72                 }
  73         }
  74
  75         if (old_mem) {
  76                 switch (old_mem->mem_type) {
  77                 case TTM_PL_TT:
  78                         atomic64_sub(old_mem->size, &adev->gtt_usage);
  79                         break;
  80                 case TTM_PL_VRAM:
  81                         atomic64_sub(old_mem->size, &adev->vram_usage);
  82                         vis_size = amdgpu_get_vis_part_size(adev, old_mem);
  83                         atomic64_sub(vis_size, &adev->vram_vis_usage);
  84                         break;
  85                 }
  86         }
  87 }
  88
  89 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  90 {
  91         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  92         struct amdgpu_bo *bo;
  93
  94         bo = container_of(tbo, struct amdgpu_bo, tbo);
  95
  96         amdgpu_update_memory_usage(adev, &bo->tbo.mem, NULL);
  97
  98         drm_gem_object_release(&bo->gem_base);
  99         amdgpu_bo_unref(&bo->parent);
 100         if (!list_empty(&bo->shadow_list)) {
 101                 mutex_lock(&adev->shadow_list_lock);
 102                 list_del_init(&bo->shadow_list);
 103                 mutex_unlock(&adev->shadow_list_lock);
 104         }
 105         kfree(bo->metadata);
 106         kfree(bo);
 107 }
 108
 109 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
 110 {
 111         if (bo->destroy == &amdgpu_ttm_bo_destroy)
 112                 return true;
 113         return false;
 114 }
 115
 116 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
 117                                       struct ttm_placement *placement,
 118                                       struct ttm_place *places,
 119                                       u32 domain, u64 flags)
 120 {
 121         u32 c = 0;
 122
 123         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 124                 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 125                 unsigned lpfn = 0;
 126
 127                 /* This forces a reallocation if the flag wasn't set before */
 128                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 129                         lpfn = adev->mc.real_vram_size >> PAGE_SHIFT;
 130
 131                 places[c].fpfn = 0;
 132                 places[c].lpfn = lpfn;
 133                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 134                         TTM_PL_FLAG_VRAM;
 135                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 136                         places[c].lpfn = visible_pfn;
 137                 else
 138                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 139                 c++;
 140         }
 141
 142         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 143                 places[c].fpfn = 0;
 144                 places[c].lpfn = 0;
 145                 places[c].flags = TTM_PL_FLAG_TT;
 146                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 147                         places[c].flags |= TTM_PL_FLAG_WC |
 148                                 TTM_PL_FLAG_UNCACHED;
 149                 else
 150                         places[c].flags |= TTM_PL_FLAG_CACHED;
 151                 c++;
 152         }
 153
 154         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 155                 places[c].fpfn = 0;
 156                 places[c].lpfn = 0;
 157                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 158                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 159                         places[c].flags |= TTM_PL_FLAG_WC |
 160                                 TTM_PL_FLAG_UNCACHED;
 161                 else
 162                         places[c].flags |= TTM_PL_FLAG_CACHED;
 163                 c++;
 164         }
 165
 166         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 167                 places[c].fpfn = 0;
 168                 places[c].lpfn = 0;
 169                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 170                 c++;
 171         }
 172
 173         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 174                 places[c].fpfn = 0;
 175                 places[c].lpfn = 0;
 176                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 177                 c++;
 178         }
 179
 180         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 181                 places[c].fpfn = 0;
 182                 places[c].lpfn = 0;
 183                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 184                 c++;
 185         }
 186
 187         if (!c) {
 188                 places[c].fpfn = 0;
 189                 places[c].lpfn = 0;
 190                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 191                 c++;
 192         }
 193
 194         placement->num_placement = c;
 195         placement->placement = places;
 196
 197         placement->num_busy_placement = c;
 198         placement->busy_placement = places;
 199 }
 200
 201 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
 202 {
 203         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 204
 205         amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements,
 206                                   domain, abo->flags);
 207 }
 208
 209 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
 210                                         struct ttm_placement *placement)
 211 {
 212         BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
 213
 214         memcpy(bo->placements, placement->placement,
 215                placement->num_placement * sizeof(struct ttm_place));
 216         bo->placement.num_placement = placement->num_placement;
 217         bo->placement.num_busy_placement = placement->num_busy_placement;
 218         bo->placement.placement = bo->placements;
 219         bo->placement.busy_placement = bo->placements;
 220 }
 221
 222 /**
 223  * amdgpu_bo_create_kernel - create BO for kernel use
 224  *
 225  * @adev: amdgpu device object
 226  * @size: size for the new BO
 227  * @align: alignment for the new BO
 228  * @domain: where to place it
 229  * @bo_ptr: resulting BO
 230  * @gpu_addr: GPU addr of the pinned BO
 231  * @cpu_addr: optional CPU address mapping
 232  *
 233  * Allocates and pins a BO for kernel internal use.
 234  *
 235  * Returns 0 on success, negative error code otherwise.
 236  */
 237 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 238                             unsigned long size, int align,
 239                             u32 domain, struct amdgpu_bo **bo_ptr,
 240                             u64 *gpu_addr, void **cpu_addr)
 241 {
 242         int r;
 243
 244         r = amdgpu_bo_create(adev, size, align, true, domain,
 245                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 246                              AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 247                              NULL, NULL, bo_ptr);
 248         if (r) {
 249                 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", r);
 250                 return r;
 251         }
 252
 253         r = amdgpu_bo_reserve(*bo_ptr, false);
 254         if (r) {
 255                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 256                 goto error_free;
 257         }
 258
 259         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 260         if (r) {
 261                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 262                 goto error_unreserve;
 263         }
 264
 265         if (cpu_addr) {
 266                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 267                 if (r) {
 268                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 269                         goto error_unreserve;
 270                 }
 271         }
 272
 273         amdgpu_bo_unreserve(*bo_ptr);
 274
 275         return 0;
 276
 277 error_unreserve:
 278         amdgpu_bo_unreserve(*bo_ptr);
 279
 280 error_free:
 281         amdgpu_bo_unref(bo_ptr);
 282
 283         return r;
 284 }
 285
 286 /**
 287  * amdgpu_bo_free_kernel - free BO for kernel use
 288  *
 289  * @bo: amdgpu BO to free
 290  *
 291  * unmaps and unpin a BO for kernel internal use.
 292  */
 293 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 294                            void **cpu_addr)
 295 {
 296         if (*bo == NULL)
 297                 return;
 298
 299         if (likely(amdgpu_bo_reserve(*bo, false) == 0)) {
 300                 if (cpu_addr)
 301                         amdgpu_bo_kunmap(*bo);
 302
 303                 amdgpu_bo_unpin(*bo);
 304                 amdgpu_bo_unreserve(*bo);
 305         }
 306         amdgpu_bo_unref(bo);
 307
 308         if (gpu_addr)
 309                 *gpu_addr = 0;
 310
 311         if (cpu_addr)
 312                 *cpu_addr = NULL;
 313 }
 314
 315 int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 316                                 unsigned long size, int byte_align,
 317                                 bool kernel, u32 domain, u64 flags,
 318                                 struct sg_table *sg,
 319                                 struct ttm_placement *placement,
 320                                 struct reservation_object *resv,
 321                                 struct amdgpu_bo **bo_ptr)
 322 {
 323         struct amdgpu_bo *bo;
 324         enum ttm_bo_type type;
 325         unsigned long page_align;
 326         u64 initial_bytes_moved;
 327         size_t acc_size;
 328         int r;
 329
 330         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 331         size = ALIGN(size, PAGE_SIZE);
 332
 333         if (kernel) {
 334                 type = ttm_bo_type_kernel;
 335         } else if (sg) {
 336                 type = ttm_bo_type_sg;
 337         } else {
 338                 type = ttm_bo_type_device;
 339         }
 340         *bo_ptr = NULL;
 341
 342         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 343                                        sizeof(struct amdgpu_bo));
 344
 345         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 346         if (bo == NULL)
 347                 return -ENOMEM;
 348         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 349         if (unlikely(r)) {
 350                 kfree(bo);
 351                 return r;
 352         }
 353         INIT_LIST_HEAD(&bo->shadow_list);
 354         INIT_LIST_HEAD(&bo->va);
 355         bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 356                                          AMDGPU_GEM_DOMAIN_GTT |
 357                                          AMDGPU_GEM_DOMAIN_CPU |
 358                                          AMDGPU_GEM_DOMAIN_GDS |
 359                                          AMDGPU_GEM_DOMAIN_GWS |
 360                                          AMDGPU_GEM_DOMAIN_OA);
 361         bo->allowed_domains = bo->prefered_domains;
 362         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 363                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 364
 365         bo->flags = flags;
 366
 367 #ifdef CONFIG_X86_32
 368         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 369          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 370          */
 371         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 372 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 373         /* Don't try to enable write-combining when it can't work, or things
 374          * may be slow
 375          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 376          */
 377
 378 #ifndef CONFIG_COMPILE_TEST
 379 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 380          thanks to write-combining
 381 #endif
 382
 383         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 384                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 385                               "better performance thanks to write-combining\n");
 386         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 387 #else
 388         /* For architectures that don't support WC memory,
 389          * mask out the WC flag from the BO
 390          */
 391         if (!drm_arch_can_wc_memory())
 392                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 393 #endif
 394
 395         amdgpu_fill_placement_to_bo(bo, placement);
 396         /* Kernel allocation are uninterruptible */
 397
 398         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 399         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 400                                  &bo->placement, page_align, !kernel, NULL,
 401                                  acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 402         amdgpu_cs_report_moved_bytes(adev,
 403                 atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved);
 404
 405         if (unlikely(r != 0))
 406                 return r;
 407
 408         if (kernel)
 409                 bo->tbo.priority = 1;
 410
 411         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 412             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 413                 struct dma_fence *fence;
 414
 415                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 416                 if (unlikely(r))
 417                         goto fail_unreserve;
 418
 419                 amdgpu_bo_fence(bo, fence, false);
 420                 dma_fence_put(bo->tbo.moving);
 421                 bo->tbo.moving = dma_fence_get(fence);
 422                 dma_fence_put(fence);
 423         }
 424         if (!resv)
 425                 amdgpu_bo_unreserve(bo);
 426         *bo_ptr = bo;
 427
 428         trace_amdgpu_bo_create(bo);
 429
 430         return 0;
 431
 432 fail_unreserve:
 433         if (!resv)
 434                 ww_mutex_unlock(&bo->tbo.resv->lock);
 435         amdgpu_bo_unref(&bo);
 436         return r;
 437 }
 438
 439 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 440                                    unsigned long size, int byte_align,
 441                                    struct amdgpu_bo *bo)
 442 {
 443         struct ttm_placement placement = {0};
 444         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 445         int r;
 446
 447         if (bo->shadow)
 448                 return 0;
 449
 450         bo->flags |= AMDGPU_GEM_CREATE_SHADOW;
 451         memset(&placements, 0,
 452                (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
 453
 454         amdgpu_ttm_placement_init(adev, &placement,
 455                                   placements, AMDGPU_GEM_DOMAIN_GTT,
 456                                   AMDGPU_GEM_CREATE_CPU_GTT_USWC);
 457
 458         r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
 459                                         AMDGPU_GEM_DOMAIN_GTT,
 460                                         AMDGPU_GEM_CREATE_CPU_GTT_USWC,
 461                                         NULL, &placement,
 462                                         bo->tbo.resv,
 463                                         &bo->shadow);
 464         if (!r) {
 465                 bo->shadow->parent = amdgpu_bo_ref(bo);
 466                 mutex_lock(&adev->shadow_list_lock);
 467                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 468                 mutex_unlock(&adev->shadow_list_lock);
 469         }
 470
 471         return r;
 472 }
 473
 474 int amdgpu_bo_create(struct amdgpu_device *adev,
 475                      unsigned long size, int byte_align,
 476                      bool kernel, u32 domain, u64 flags,
 477                      struct sg_table *sg,
 478                      struct reservation_object *resv,
 479                      struct amdgpu_bo **bo_ptr)
 480 {
 481         struct ttm_placement placement = {0};
 482         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 483         int r;
 484
 485         memset(&placements, 0,
 486                (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
 487
 488         amdgpu_ttm_placement_init(adev, &placement,
 489                                   placements, domain, flags);
 490
 491         r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
 492                                         domain, flags, sg, &placement,
 493                                         resv, bo_ptr);
 494         if (r)
 495                 return r;
 496
 497         if (amdgpu_need_backup(adev) && (flags & AMDGPU_GEM_CREATE_SHADOW)) {
 498                 if (!resv) {
 499                         r = ww_mutex_lock(&(*bo_ptr)->tbo.resv->lock, NULL);
 500                         WARN_ON(r != 0);
 501                 }
 502
 503                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 504
 505                 if (!resv)
 506                         ww_mutex_unlock(&(*bo_ptr)->tbo.resv->lock);
 507
 508                 if (r)
 509                         amdgpu_bo_unref(bo_ptr);
 510         }
 511
 512         return r;
 513 }
 514
 515 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 516                                struct amdgpu_ring *ring,
 517                                struct amdgpu_bo *bo,
 518                                struct reservation_object *resv,
 519                                struct dma_fence **fence,
 520                                bool direct)
 521
 522 {
 523         struct amdgpu_bo *shadow = bo->shadow;
 524         uint64_t bo_addr, shadow_addr;
 525         int r;
 526
 527         if (!shadow)
 528                 return -EINVAL;
 529
 530         bo_addr = amdgpu_bo_gpu_offset(bo);
 531         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 532
 533         r = reservation_object_reserve_shared(bo->tbo.resv);
 534         if (r)
 535                 goto err;
 536
 537         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 538                                amdgpu_bo_size(bo), resv, fence,
 539                                direct);
 540         if (!r)
 541                 amdgpu_bo_fence(bo, *fence, true);
 542
 543 err:
 544         return r;
 545 }
 546
 547 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 548                                   struct amdgpu_ring *ring,
 549                                   struct amdgpu_bo *bo,
 550                                   struct reservation_object *resv,
 551                                   struct dma_fence **fence,
 552                                   bool direct)
 553
 554 {
 555         struct amdgpu_bo *shadow = bo->shadow;
 556         uint64_t bo_addr, shadow_addr;
 557         int r;
 558
 559         if (!shadow)
 560                 return -EINVAL;
 561
 562         bo_addr = amdgpu_bo_gpu_offset(bo);
 563         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 564
 565         r = reservation_object_reserve_shared(bo->tbo.resv);
 566         if (r)
 567                 goto err;
 568
 569         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 570                                amdgpu_bo_size(bo), resv, fence,
 571                                direct);
 572         if (!r)
 573                 amdgpu_bo_fence(bo, *fence, true);
 574
 575 err:
 576         return r;
 577 }
 578
 579 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 580 {
 581         bool is_iomem;
 582         long r;
 583
 584         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 585                 return -EPERM;
 586
 587         if (bo->kptr) {
 588                 if (ptr) {
 589                         *ptr = bo->kptr;
 590                 }
 591                 return 0;
 592         }
 593
 594         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 595                                                 MAX_SCHEDULE_TIMEOUT);
 596         if (r < 0)
 597                 return r;
 598
 599         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 600         if (r)
 601                 return r;
 602
 603         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 604         if (ptr)
 605                 *ptr = bo->kptr;
 606
 607         return 0;
 608 }
 609
 610 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 611 {
 612         if (bo->kptr == NULL)
 613                 return;
 614         bo->kptr = NULL;
 615         ttm_bo_kunmap(&bo->kmap);
 616 }
 617
 618 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 619 {
 620         if (bo == NULL)
 621                 return NULL;
 622
 623         ttm_bo_reference(&bo->tbo);
 624         return bo;
 625 }
 626
 627 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 628 {
 629         struct ttm_buffer_object *tbo;
 630
 631         if ((*bo) == NULL)
 632                 return;
 633
 634         tbo = &((*bo)->tbo);
 635         ttm_bo_unref(&tbo);
 636         if (tbo == NULL)
 637                 *bo = NULL;
 638 }
 639
 640 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 641                              u64 min_offset, u64 max_offset,
 642                              u64 *gpu_addr)
 643 {
 644         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 645         int r, i;
 646         unsigned fpfn, lpfn;
 647
 648         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 649                 return -EPERM;
 650
 651         if (WARN_ON_ONCE(min_offset > max_offset))
 652                 return -EINVAL;
 653
 654         if (bo->pin_count) {
 655                 uint32_t mem_type = bo->tbo.mem.mem_type;
 656
 657                 if (domain != amdgpu_mem_type_to_domain(mem_type))
 658                         return -EINVAL;
 659
 660                 bo->pin_count++;
 661                 if (gpu_addr)
 662                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 663
 664                 if (max_offset != 0) {
 665                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 666                         WARN_ON_ONCE(max_offset <
 667                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 668                 }
 669
 670                 return 0;
 671         }
 672
 673         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 674         amdgpu_ttm_placement_from_domain(bo, domain);
 675         for (i = 0; i < bo->placement.num_placement; i++) {
 676                 /* force to pin into visible video ram */
 677                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 678                     !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
 679                     (!max_offset || max_offset >
 680                      adev->mc.visible_vram_size)) {
 681                         if (WARN_ON_ONCE(min_offset >
 682                                          adev->mc.visible_vram_size))
 683                                 return -EINVAL;
 684                         fpfn = min_offset >> PAGE_SHIFT;
 685                         lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 686                 } else {
 687                         fpfn = min_offset >> PAGE_SHIFT;
 688                         lpfn = max_offset >> PAGE_SHIFT;
 689                 }
 690                 if (fpfn > bo->placements[i].fpfn)
 691                         bo->placements[i].fpfn = fpfn;
 692                 if (!bo->placements[i].lpfn ||
 693                     (lpfn && lpfn < bo->placements[i].lpfn))
 694                         bo->placements[i].lpfn = lpfn;
 695                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 696         }
 697
 698         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 699         if (unlikely(r)) {
 700                 dev_err(adev->dev, "%p pin failed\n", bo);
 701                 goto error;
 702         }
 703         r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
 704         if (unlikely(r)) {
 705                 dev_err(adev->dev, "%p bind failed\n", bo);
 706                 goto error;
 707         }
 708
 709         bo->pin_count = 1;
 710         if (gpu_addr != NULL)
 711                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 712         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 713                 adev->vram_pin_size += amdgpu_bo_size(bo);
 714                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 715                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 716         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 717                 adev->gart_pin_size += amdgpu_bo_size(bo);
 718         }
 719
 720 error:
 721         return r;
 722 }
 723
 724 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 725 {
 726         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 727 }
 728
 729 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 730 {
 731         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 732         int r, i;
 733
 734         if (!bo->pin_count) {
 735                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 736                 return 0;
 737         }
 738         bo->pin_count--;
 739         if (bo->pin_count)
 740                 return 0;
 741         for (i = 0; i < bo->placement.num_placement; i++) {
 742                 bo->placements[i].lpfn = 0;
 743                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 744         }
 745         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 746         if (unlikely(r)) {
 747                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 748                 goto error;
 749         }
 750
 751         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 752                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 753                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 754                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 755         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 756                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 757         }
 758
 759 error:
 760         return r;
 761 }
 762
 763 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 764 {
 765         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 766         if (0 && (adev->flags & AMD_IS_APU)) {
 767                 /* Useless to evict on IGP chips */
 768                 return 0;
 769         }
 770         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 771 }
 772
 773 static const char *amdgpu_vram_names[] = {
 774         "UNKNOWN",
 775         "GDDR1",
 776         "DDR2",
 777         "GDDR3",
 778         "GDDR4",
 779         "GDDR5",
 780         "HBM",
 781         "DDR3"
 782 };
 783
 784 int amdgpu_bo_init(struct amdgpu_device *adev)
 785 {
 786         /* reserve PAT memory space to WC for VRAM */
 787         arch_io_reserve_memtype_wc(adev->mc.aper_base,
 788                                    adev->mc.aper_size);
 789
 790         /* Add an MTRR for the VRAM */
 791         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 792                                               adev->mc.aper_size);
 793         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 794                 adev->mc.mc_vram_size >> 20,
 795                 (unsigned long long)adev->mc.aper_size >> 20);
 796         DRM_INFO("RAM width %dbits %s\n",
 797                  adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
 798         return amdgpu_ttm_init(adev);
 799 }
 800
 801 void amdgpu_bo_fini(struct amdgpu_device *adev)
 802 {
 803         amdgpu_ttm_fini(adev);
 804         arch_phys_wc_del(adev->mc.vram_mtrr);
 805         arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size);
 806 }
 807
 808 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 809                              struct vm_area_struct *vma)
 810 {
 811         return ttm_fbdev_mmap(vma, &bo->tbo);
 812 }
 813
 814 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 815 {
 816         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 817
 818         if (adev->family <= AMDGPU_FAMILY_CZ &&
 819             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 820                 return -EINVAL;
 821
 822         bo->tiling_flags = tiling_flags;
 823         return 0;
 824 }
 825
 826 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 827 {
 828         lockdep_assert_held(&bo->tbo.resv->lock.base);
 829
 830         if (tiling_flags)
 831                 *tiling_flags = bo->tiling_flags;
 832 }
 833
 834 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 835                             uint32_t metadata_size, uint64_t flags)
 836 {
 837         void *buffer;
 838
 839         if (!metadata_size) {
 840                 if (bo->metadata_size) {
 841                         kfree(bo->metadata);
 842                         bo->metadata = NULL;
 843                         bo->metadata_size = 0;
 844                 }
 845                 return 0;
 846         }
 847
 848         if (metadata == NULL)
 849                 return -EINVAL;
 850
 851         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 852         if (buffer == NULL)
 853                 return -ENOMEM;
 854
 855         kfree(bo->metadata);
 856         bo->metadata_flags = flags;
 857         bo->metadata = buffer;
 858         bo->metadata_size = metadata_size;
 859
 860         return 0;
 861 }
 862
 863 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 864                            size_t buffer_size, uint32_t *metadata_size,
 865                            uint64_t *flags)
 866 {
 867         if (!buffer && !metadata_size)
 868                 return -EINVAL;
 869
 870         if (buffer) {
 871                 if (buffer_size < bo->metadata_size)
 872                         return -EINVAL;
 873
 874                 if (bo->metadata_size)
 875                         memcpy(buffer, bo->metadata, bo->metadata_size);
 876         }
 877
 878         if (metadata_size)
 879                 *metadata_size = bo->metadata_size;
 880         if (flags)
 881                 *flags = bo->metadata_flags;
 882
 883         return 0;
 884 }
 885
 886 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 887                            bool evict,
 888                            struct ttm_mem_reg *new_mem)
 889 {
 890         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 891         struct amdgpu_bo *abo;
 892         struct ttm_mem_reg *old_mem = &bo->mem;
 893
 894         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 895                 return;
 896
 897         abo = container_of(bo, struct amdgpu_bo, tbo);
 898         amdgpu_vm_bo_invalidate(adev, abo);
 899
 900         /* remember the eviction */
 901         if (evict)
 902                 atomic64_inc(&adev->num_evictions);
 903
 904         /* update statistics */
 905         if (!new_mem)
 906                 return;
 907
 908         /* move_notify is called before move happens */
 909         amdgpu_update_memory_usage(adev, &bo->mem, new_mem);
 910
 911         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 912 }
 913
 914 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 915 {
 916         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 917         struct amdgpu_bo *abo;
 918         unsigned long offset, size, lpfn;
 919         int i, r;
 920
 921         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 922                 return 0;
 923
 924         abo = container_of(bo, struct amdgpu_bo, tbo);
 925         if (bo->mem.mem_type != TTM_PL_VRAM)
 926                 return 0;
 927
 928         size = bo->mem.num_pages << PAGE_SHIFT;
 929         offset = bo->mem.start << PAGE_SHIFT;
 930         /* TODO: figure out how to map scattered VRAM to the CPU */
 931         if ((offset + size) <= adev->mc.visible_vram_size &&
 932             (abo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS))
 933                 return 0;
 934
 935         /* Can't move a pinned BO to visible VRAM */
 936         if (abo->pin_count > 0)
 937                 return -EINVAL;
 938
 939         /* hurrah the memory is not visible ! */
 940         abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 941         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
 942         lpfn =  adev->mc.visible_vram_size >> PAGE_SHIFT;
 943         for (i = 0; i < abo->placement.num_placement; i++) {
 944                 /* Force into visible VRAM */
 945                 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 946                     (!abo->placements[i].lpfn ||
 947                      abo->placements[i].lpfn > lpfn))
 948                         abo->placements[i].lpfn = lpfn;
 949         }
 950         r = ttm_bo_validate(bo, &abo->placement, false, false);
 951         if (unlikely(r == -ENOMEM)) {
 952                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 953                 return ttm_bo_validate(bo, &abo->placement, false, false);
 954         } else if (unlikely(r != 0)) {
 955                 return r;
 956         }
 957
 958         offset = bo->mem.start << PAGE_SHIFT;
 959         /* this should never happen */
 960         if ((offset + size) > adev->mc.visible_vram_size)
 961                 return -EINVAL;
 962
 963         return 0;
 964 }
 965
 966 /**
 967  * amdgpu_bo_fence - add fence to buffer object
 968  *
 969  * @bo: buffer object in question
 970  * @fence: fence to add
 971  * @shared: true if fence should be added shared
 972  *
 973  */
 974 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
 975                      bool shared)
 976 {
 977         struct reservation_object *resv = bo->tbo.resv;
 978
 979         if (shared)
 980                 reservation_object_add_shared_fence(resv, fence);
 981         else
 982                 reservation_object_add_excl_fence(resv, fence);
 983 }
 984
 985 /**
 986  * amdgpu_bo_gpu_offset - return GPU offset of bo
 987  * @bo: amdgpu object for which we query the offset
 988  *
 989  * Returns current GPU offset of the object.
 990  *
 991  * Note: object should either be pinned or reserved when calling this
 992  * function, it might be useful to add check for this for debugging.
 993  */
 994 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 995 {
 996         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
 997         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
 998                      !amdgpu_ttm_is_bound(bo->tbo.ttm));
 999         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1000                      !bo->pin_count);
1001         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1002         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1003                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1004
1005         return bo->tbo.offset;
1006 }