drivers/gpu/drm/amd/amdgpu/navi10_ih.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/pci.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_ih.h"
  28
  29 #include "oss/osssys_5_0_0_offset.h"
  30 #include "oss/osssys_5_0_0_sh_mask.h"
  31
  32 #include "soc15_common.h"
  33 #include "navi10_ih.h"
  34
  35 #define MAX_REARM_RETRY 10
  36
  37 #define mmIH_CHICKEN_Sienna_Cichlid                 0x018d
  38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX        0
  39
  40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
  41
  42 /**
  43  * navi10_ih_init_register_offset - Initialize register offset for ih rings
  44  *
  45  * @adev: amdgpu_device pointer
  46  *
  47  * Initialize register offset ih rings (NAVI10).
  48  */
  49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev)
  50 {
  51         struct amdgpu_ih_regs *ih_regs;
  52
  53         if (adev->irq.ih.ring_size) {
  54                 ih_regs = &adev->irq.ih.ih_regs;
  55                 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
  56                 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
  57                 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
  58                 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
  59                 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
  60                 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
  61                 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
  62                 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
  63                 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
  64         }
  65
  66         if (adev->irq.ih1.ring_size) {
  67                 ih_regs = &adev->irq.ih1.ih_regs;
  68                 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
  69                 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
  70                 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
  71                 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
  72                 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
  73                 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
  74                 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
  75         }
  76
  77         if (adev->irq.ih2.ring_size) {
  78                 ih_regs = &adev->irq.ih2.ih_regs;
  79                 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
  80                 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
  81                 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
  82                 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
  83                 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
  84                 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
  85                 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
  86         }
  87 }
  88
  89 /**
  90  * force_update_wptr_for_self_int - Force update the wptr for self interrupt
  91  *
  92  * @adev: amdgpu_device pointer
  93  * @threshold: threshold to trigger the wptr reporting
  94  * @timeout: timeout to trigger the wptr reporting
  95  * @enabled: Enable/disable timeout flush mechanism
  96  *
  97  * threshold input range: 0 ~ 15, default 0,
  98  * real_threshold = 2^threshold
  99  * timeout input range: 0 ~ 20, default 8,
 100  * real_timeout = (2^timeout) * 1024 / (socclk_freq)
 101  *
 102  * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
 103  */
 104 static void
 105 force_update_wptr_for_self_int(struct amdgpu_device *adev,
 106                                u32 threshold, u32 timeout, bool enabled)
 107 {
 108         u32 ih_cntl, ih_rb_cntl;
 109
 110         if (adev->ip_versions[OSSSYS_HWIP][0] < IP_VERSION(5, 0, 3))
 111                 return;
 112
 113         ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
 114         ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
 115
 116         ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
 117                                 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout);
 118         ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
 119                                 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled);
 120         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
 121                                    RB_USED_INT_THRESHOLD, threshold);
 122
 123         if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
 124                 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
 125                         return;
 126         } else {
 127                 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
 128         }
 129
 130         ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
 131         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
 132                                    RB_USED_INT_THRESHOLD, threshold);
 133         if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
 134                 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl))
 135                         return;
 136         } else {
 137                 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
 138         }
 139
 140         WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
 141 }
 142
 143 /**
 144  * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
 145  *
 146  * @adev: amdgpu_device pointer
 147  * @ih: amdgpu_ih_ring pointet
 148  * @enable: true - enable the interrupts, false - disable the interrupts
 149  *
 150  * Toggle the interrupt ring buffer (NAVI10)
 151  */
 152 static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
 153                                             struct amdgpu_ih_ring *ih,
 154                                             bool enable)
 155 {
 156         struct amdgpu_ih_regs *ih_regs;
 157         uint32_t tmp;
 158
 159         ih_regs = &ih->ih_regs;
 160
 161         tmp = RREG32(ih_regs->ih_rb_cntl);
 162         tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
 163         /* enable_intr field is only valid in ring0 */
 164         if (ih == &adev->irq.ih)
 165                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
 166
 167         if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
 168                 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
 169                         return -ETIMEDOUT;
 170         } else {
 171                 WREG32(ih_regs->ih_rb_cntl, tmp);
 172         }
 173
 174         if (enable) {
 175                 ih->enabled = true;
 176         } else {
 177                 /* set rptr, wptr to 0 */
 178                 WREG32(ih_regs->ih_rb_rptr, 0);
 179                 WREG32(ih_regs->ih_rb_wptr, 0);
 180                 ih->enabled = false;
 181                 ih->rptr = 0;
 182         }
 183
 184         return 0;
 185 }
 186
 187 /**
 188  * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
 189  *
 190  * @adev: amdgpu_device pointer
 191  * @enable: enable or disable interrupt ring buffers
 192  *
 193  * Toggle all the available interrupt ring buffers (NAVI10).
 194  */
 195 static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
 196 {
 197         struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
 198         int i;
 199         int r;
 200
 201         for (i = 0; i < ARRAY_SIZE(ih); i++) {
 202                 if (ih[i]->ring_size) {
 203                         r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable);
 204                         if (r)
 205                                 return r;
 206                 }
 207         }
 208
 209         return 0;
 210 }
 211
 212 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
 213 {
 214         int rb_bufsz = order_base_2(ih->ring_size / 4);
 215
 216         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
 217                                    MC_SPACE, ih->use_bus_addr ? 1 : 4);
 218         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
 219                                    WPTR_OVERFLOW_CLEAR, 1);
 220         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
 221                                    WPTR_OVERFLOW_ENABLE, 1);
 222         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
 223         /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
 224          * value is written to memory
 225          */
 226         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
 227                                    WPTR_WRITEBACK_ENABLE, 1);
 228         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
 229         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
 230         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
 231
 232         return ih_rb_cntl;
 233 }
 234
 235 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
 236 {
 237         u32 ih_doorbell_rtpr = 0;
 238
 239         if (ih->use_doorbell) {
 240                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
 241                                                  IH_DOORBELL_RPTR, OFFSET,
 242                                                  ih->doorbell_index);
 243                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
 244                                                  IH_DOORBELL_RPTR,
 245                                                  ENABLE, 1);
 246         } else {
 247                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
 248                                                  IH_DOORBELL_RPTR,
 249                                                  ENABLE, 0);
 250         }
 251         return ih_doorbell_rtpr;
 252 }
 253
 254 /**
 255  * navi10_ih_enable_ring - enable an ih ring buffer
 256  *
 257  * @adev: amdgpu_device pointer
 258  * @ih: amdgpu_ih_ring pointer
 259  *
 260  * Enable an ih ring buffer (NAVI10)
 261  */
 262 static int navi10_ih_enable_ring(struct amdgpu_device *adev,
 263                                  struct amdgpu_ih_ring *ih)
 264 {
 265         struct amdgpu_ih_regs *ih_regs;
 266         uint32_t tmp;
 267
 268         ih_regs = &ih->ih_regs;
 269
 270         /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
 271         WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
 272         WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
 273
 274         tmp = RREG32(ih_regs->ih_rb_cntl);
 275         tmp = navi10_ih_rb_cntl(ih, tmp);
 276         if (ih == &adev->irq.ih)
 277                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
 278         if (ih == &adev->irq.ih1) {
 279                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
 280                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
 281         }
 282
 283         if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
 284                 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
 285                         DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
 286                         return -ETIMEDOUT;
 287                 }
 288         } else {
 289                 WREG32(ih_regs->ih_rb_cntl, tmp);
 290         }
 291
 292         if (ih == &adev->irq.ih) {
 293                 /* set the ih ring 0 writeback address whether it's enabled or not */
 294                 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
 295                 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
 296         }
 297
 298         /* set rptr, wptr to 0 */
 299         WREG32(ih_regs->ih_rb_wptr, 0);
 300         WREG32(ih_regs->ih_rb_rptr, 0);
 301
 302         WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih));
 303
 304         return 0;
 305 }
 306
 307 /**
 308  * navi10_ih_irq_init - init and enable the interrupt ring
 309  *
 310  * @adev: amdgpu_device pointer
 311  *
 312  * Allocate a ring buffer for the interrupt controller,
 313  * enable the RLC, disable interrupts, enable the IH
 314  * ring buffer and enable it (NAVI).
 315  * Called at device load and reume.
 316  * Returns 0 for success, errors for failure.
 317  */
 318 static int navi10_ih_irq_init(struct amdgpu_device *adev)
 319 {
 320         struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
 321         u32 ih_chicken;
 322         u32 tmp;
 323         int ret;
 324         int i;
 325
 326         /* disable irqs */
 327         ret = navi10_ih_toggle_interrupts(adev, false);
 328         if (ret)
 329                 return ret;
 330
 331         adev->nbio.funcs->ih_control(adev);
 332
 333         if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
 334                 if (ih[0]->use_bus_addr) {
 335                         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
 336                         case IP_VERSION(5, 0, 3):
 337                         case IP_VERSION(5, 2, 0):
 338                         case IP_VERSION(5, 2, 1):
 339                                 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
 340                                 ih_chicken = REG_SET_FIELD(ih_chicken,
 341                                                 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
 342                                 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken);
 343                                 break;
 344                         default:
 345                                 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
 346                                 ih_chicken = REG_SET_FIELD(ih_chicken,
 347                                                 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
 348                                 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
 349                                 break;
 350                         }
 351                 }
 352         }
 353
 354         for (i = 0; i < ARRAY_SIZE(ih); i++) {
 355                 if (ih[i]->ring_size) {
 356                         ret = navi10_ih_enable_ring(adev, ih[i]);
 357                         if (ret)
 358                                 return ret;
 359                 }
 360         }
 361
 362         /* update doorbell range for ih ring 0*/
 363         adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
 364                                             ih[0]->doorbell_index);
 365
 366         tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
 367         tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
 368                             CLIENT18_IS_STORM_CLIENT, 1);
 369         WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
 370
 371         tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
 372         tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
 373         WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
 374
 375         pci_set_master(adev->pdev);
 376
 377         /* enable interrupts */
 378         ret = navi10_ih_toggle_interrupts(adev, true);
 379         if (ret)
 380                 return ret;
 381         /* enable wptr force update for self int */
 382         force_update_wptr_for_self_int(adev, 0, 8, true);
 383
 384         if (adev->irq.ih_soft.ring_size)
 385                 adev->irq.ih_soft.enabled = true;
 386
 387         return 0;
 388 }
 389
 390 /**
 391  * navi10_ih_irq_disable - disable interrupts
 392  *
 393  * @adev: amdgpu_device pointer
 394  *
 395  * Disable interrupts on the hw (NAVI10).
 396  */
 397 static void navi10_ih_irq_disable(struct amdgpu_device *adev)
 398 {
 399         force_update_wptr_for_self_int(adev, 0, 8, false);
 400         navi10_ih_toggle_interrupts(adev, false);
 401
 402         /* Wait and acknowledge irq */
 403         mdelay(1);
 404 }
 405
 406 /**
 407  * navi10_ih_get_wptr - get the IH ring buffer wptr
 408  *
 409  * @adev: amdgpu_device pointer
 410  * @ih: IH ring buffer to fetch wptr
 411  *
 412  * Get the IH ring buffer wptr from either the register
 413  * or the writeback memory buffer (NAVI10).  Also check for
 414  * ring buffer overflow and deal with it.
 415  * Returns the value of the wptr.
 416  */
 417 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
 418                               struct amdgpu_ih_ring *ih)
 419 {
 420         u32 wptr, tmp;
 421         struct amdgpu_ih_regs *ih_regs;
 422
 423         wptr = le32_to_cpu(*ih->wptr_cpu);
 424         ih_regs = &ih->ih_regs;
 425
 426         if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
 427                 goto out;
 428
 429         wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
 430         if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
 431                 goto out;
 432         wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
 433
 434         /* When a ring buffer overflow happen start parsing interrupt
 435          * from the last not overwritten vector (wptr + 32). Hopefully
 436          * this should allow us to catch up.
 437          */
 438         tmp = (wptr + 32) & ih->ptr_mask;
 439         dev_warn(adev->dev, "IH ring buffer overflow "
 440                  "(0x%08X, 0x%08X, 0x%08X)\n",
 441                  wptr, ih->rptr, tmp);
 442         ih->rptr = tmp;
 443
 444         tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
 445         tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
 446         WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
 447 out:
 448         return (wptr & ih->ptr_mask);
 449 }
 450
 451 /**
 452  * navi10_ih_irq_rearm - rearm IRQ if lost
 453  *
 454  * @adev: amdgpu_device pointer
 455  * @ih: IH ring to match
 456  *
 457  */
 458 static void navi10_ih_irq_rearm(struct amdgpu_device *adev,
 459                                struct amdgpu_ih_ring *ih)
 460 {
 461         uint32_t v = 0;
 462         uint32_t i = 0;
 463         struct amdgpu_ih_regs *ih_regs;
 464
 465         ih_regs = &ih->ih_regs;
 466
 467         /* Rearm IRQ / re-write doorbell if doorbell write is lost */
 468         for (i = 0; i < MAX_REARM_RETRY; i++) {
 469                 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
 470                 if ((v < ih->ring_size) && (v != ih->rptr))
 471                         WDOORBELL32(ih->doorbell_index, ih->rptr);
 472                 else
 473                         break;
 474         }
 475 }
 476
 477 /**
 478  * navi10_ih_set_rptr - set the IH ring buffer rptr
 479  *
 480  * @adev: amdgpu_device pointer
 481  *
 482  * @ih: IH ring buffer to set rptr
 483  * Set the IH ring buffer rptr.
 484  */
 485 static void navi10_ih_set_rptr(struct amdgpu_device *adev,
 486                                struct amdgpu_ih_ring *ih)
 487 {
 488         struct amdgpu_ih_regs *ih_regs;
 489
 490         if (ih->use_doorbell) {
 491                 /* XXX check if swapping is necessary on BE */
 492                 *ih->rptr_cpu = ih->rptr;
 493                 WDOORBELL32(ih->doorbell_index, ih->rptr);
 494
 495                 if (amdgpu_sriov_vf(adev))
 496                         navi10_ih_irq_rearm(adev, ih);
 497         } else {
 498                 ih_regs = &ih->ih_regs;
 499                 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
 500         }
 501 }
 502
 503 /**
 504  * navi10_ih_self_irq - dispatch work for ring 1 and 2
 505  *
 506  * @adev: amdgpu_device pointer
 507  * @source: irq source
 508  * @entry: IV with WPTR update
 509  *
 510  * Update the WPTR from the IV and schedule work to handle the entries.
 511  */
 512 static int navi10_ih_self_irq(struct amdgpu_device *adev,
 513                               struct amdgpu_irq_src *source,
 514                               struct amdgpu_iv_entry *entry)
 515 {
 516         uint32_t wptr = cpu_to_le32(entry->src_data[0]);
 517
 518         switch (entry->ring_id) {
 519         case 1:
 520                 *adev->irq.ih1.wptr_cpu = wptr;
 521                 schedule_work(&adev->irq.ih1_work);
 522                 break;
 523         case 2:
 524                 *adev->irq.ih2.wptr_cpu = wptr;
 525                 schedule_work(&adev->irq.ih2_work);
 526                 break;
 527         default: break;
 528         }
 529         return 0;
 530 }
 531
 532 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = {
 533         .process = navi10_ih_self_irq,
 534 };
 535
 536 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev)
 537 {
 538         adev->irq.self_irq.num_types = 0;
 539         adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs;
 540 }
 541
 542 static int navi10_ih_early_init(void *handle)
 543 {
 544         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 545
 546         navi10_ih_set_interrupt_funcs(adev);
 547         navi10_ih_set_self_irq_funcs(adev);
 548         return 0;
 549 }
 550
 551 static int navi10_ih_sw_init(void *handle)
 552 {
 553         int r;
 554         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 555         bool use_bus_addr;
 556
 557         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
 558                                 &adev->irq.self_irq);
 559
 560         if (r)
 561                 return r;
 562
 563         /* use gpu virtual address for ih ring
 564          * until ih_checken is programmed to allow
 565          * use bus address for ih ring by psp bl */
 566         if ((adev->flags & AMD_IS_APU) ||
 567             (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 568                 use_bus_addr = false;
 569         else
 570                 use_bus_addr = true;
 571         r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
 572         if (r)
 573                 return r;
 574
 575         adev->irq.ih.use_doorbell = true;
 576         adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 577
 578         adev->irq.ih1.ring_size = 0;
 579         adev->irq.ih2.ring_size = 0;
 580
 581         /* initialize ih control registers offset */
 582         navi10_ih_init_register_offset(adev);
 583
 584         r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
 585         if (r)
 586                 return r;
 587
 588         r = amdgpu_irq_init(adev);
 589
 590         return r;
 591 }
 592
 593 static int navi10_ih_sw_fini(void *handle)
 594 {
 595         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 596
 597         amdgpu_irq_fini_sw(adev);
 598
 599         return 0;
 600 }
 601
 602 static int navi10_ih_hw_init(void *handle)
 603 {
 604         int r;
 605         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 606
 607         r = navi10_ih_irq_init(adev);
 608         if (r)
 609                 return r;
 610
 611         return 0;
 612 }
 613
 614 static int navi10_ih_hw_fini(void *handle)
 615 {
 616         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 617
 618         navi10_ih_irq_disable(adev);
 619
 620         return 0;
 621 }
 622
 623 static int navi10_ih_suspend(void *handle)
 624 {
 625         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 626
 627         return navi10_ih_hw_fini(adev);
 628 }
 629
 630 static int navi10_ih_resume(void *handle)
 631 {
 632         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 633
 634         return navi10_ih_hw_init(adev);
 635 }
 636
 637 static bool navi10_ih_is_idle(void *handle)
 638 {
 639         /* todo */
 640         return true;
 641 }
 642
 643 static int navi10_ih_wait_for_idle(void *handle)
 644 {
 645         /* todo */
 646         return -ETIMEDOUT;
 647 }
 648
 649 static int navi10_ih_soft_reset(void *handle)
 650 {
 651         /* todo */
 652         return 0;
 653 }
 654
 655 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev,
 656                                                bool enable)
 657 {
 658         uint32_t data, def, field_val;
 659
 660         if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
 661                 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
 662                 field_val = enable ? 0 : 1;
 663                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 664                                      DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
 665                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 666                                      OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
 667                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 668                                      LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
 669                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 670                                      DYN_CLK_SOFT_OVERRIDE, field_val);
 671                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 672                                      REG_CLK_SOFT_OVERRIDE, field_val);
 673                 if (def != data)
 674                         WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
 675         }
 676
 677         return;
 678 }
 679
 680 static int navi10_ih_set_clockgating_state(void *handle,
 681                                            enum amd_clockgating_state state)
 682 {
 683         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 684
 685         navi10_ih_update_clockgating_state(adev,
 686                                 state == AMD_CG_STATE_GATE);
 687         return 0;
 688 }
 689
 690 static int navi10_ih_set_powergating_state(void *handle,
 691                                            enum amd_powergating_state state)
 692 {
 693         return 0;
 694 }
 695
 696 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags)
 697 {
 698         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 699
 700         if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))
 701                 *flags |= AMD_CG_SUPPORT_IH_CG;
 702
 703         return;
 704 }
 705
 706 static const struct amd_ip_funcs navi10_ih_ip_funcs = {
 707         .name = "navi10_ih",
 708         .early_init = navi10_ih_early_init,
 709         .late_init = NULL,
 710         .sw_init = navi10_ih_sw_init,
 711         .sw_fini = navi10_ih_sw_fini,
 712         .hw_init = navi10_ih_hw_init,
 713         .hw_fini = navi10_ih_hw_fini,
 714         .suspend = navi10_ih_suspend,
 715         .resume = navi10_ih_resume,
 716         .is_idle = navi10_ih_is_idle,
 717         .wait_for_idle = navi10_ih_wait_for_idle,
 718         .soft_reset = navi10_ih_soft_reset,
 719         .set_clockgating_state = navi10_ih_set_clockgating_state,
 720         .set_powergating_state = navi10_ih_set_powergating_state,
 721         .get_clockgating_state = navi10_ih_get_clockgating_state,
 722 };
 723
 724 static const struct amdgpu_ih_funcs navi10_ih_funcs = {
 725         .get_wptr = navi10_ih_get_wptr,
 726         .decode_iv = amdgpu_ih_decode_iv_helper,
 727         .set_rptr = navi10_ih_set_rptr
 728 };
 729
 730 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
 731 {
 732         if (adev->irq.ih_funcs == NULL)
 733                 adev->irq.ih_funcs = &navi10_ih_funcs;
 734 }
 735
 736 const struct amdgpu_ip_block_version navi10_ih_ip_block =
 737 {
 738         .type = AMD_IP_BLOCK_TYPE_IH,
 739         .major = 5,
 740         .minor = 0,
 741         .rev = 0,
 742         .funcs = &navi10_ih_ip_funcs,
 743 };