drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/list.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_xgmi.h"
  27 #include "amdgpu_ras.h"
  28 #include "soc15.h"
  29 #include "df/df_3_6_offset.h"
  30 #include "xgmi/xgmi_4_0_0_smn.h"
  31 #include "xgmi/xgmi_4_0_0_sh_mask.h"
  32 #include "wafl/wafl2_4_0_0_smn.h"
  33 #include "wafl/wafl2_4_0_0_sh_mask.h"
  34
  35 #define smnPCS_XGMI23_PCS_ERROR_STATUS   0x11a01210
  36 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c
  37 #define smnPCS_GOPX1_PCS_ERROR_STATUS    0x12200210
  38
  39 static DEFINE_MUTEX(xgmi_mutex);
  40
  41 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE         4
  42
  43 static LIST_HEAD(xgmi_hive_list);
  44
  45 static const int xgmi_pcs_err_status_reg_vg20[] = {
  46         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
  47         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
  48 };
  49
  50 static const int wafl_pcs_err_status_reg_vg20[] = {
  51         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
  52         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
  53 };
  54
  55 static const int xgmi_pcs_err_status_reg_arct[] = {
  56         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
  57         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
  58         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000,
  59         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000,
  60         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000,
  61         smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000,
  62 };
  63
  64 /* same as vg20*/
  65 static const int wafl_pcs_err_status_reg_arct[] = {
  66         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
  67         smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
  68 };
  69
  70 static const int xgmi23_pcs_err_status_reg_aldebaran[] = {
  71         smnPCS_XGMI23_PCS_ERROR_STATUS,
  72         smnPCS_XGMI23_PCS_ERROR_STATUS + 0x100000,
  73         smnPCS_XGMI23_PCS_ERROR_STATUS + 0x200000,
  74         smnPCS_XGMI23_PCS_ERROR_STATUS + 0x300000,
  75         smnPCS_XGMI23_PCS_ERROR_STATUS + 0x400000,
  76         smnPCS_XGMI23_PCS_ERROR_STATUS + 0x500000,
  77         smnPCS_XGMI23_PCS_ERROR_STATUS + 0x600000,
  78         smnPCS_XGMI23_PCS_ERROR_STATUS + 0x700000
  79 };
  80
  81 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = {
  82         smnPCS_XGMI3X16_PCS_ERROR_STATUS,
  83         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000,
  84         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000,
  85         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000,
  86         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000,
  87         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000,
  88         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000,
  89         smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000
  90 };
  91
  92 static const int walf_pcs_err_status_reg_aldebaran[] = {
  93         smnPCS_GOPX1_PCS_ERROR_STATUS,
  94         smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000
  95 };
  96
  97 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
  98         {"XGMI PCS DataLossErr",
  99          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
 100         {"XGMI PCS TrainingErr",
 101          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
 102         {"XGMI PCS CRCErr",
 103          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
 104         {"XGMI PCS BERExceededErr",
 105          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
 106         {"XGMI PCS TxMetaDataErr",
 107          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
 108         {"XGMI PCS ReplayBufParityErr",
 109          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
 110         {"XGMI PCS DataParityErr",
 111          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
 112         {"XGMI PCS ReplayFifoOverflowErr",
 113          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
 114         {"XGMI PCS ReplayFifoUnderflowErr",
 115          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
 116         {"XGMI PCS ElasticFifoOverflowErr",
 117          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
 118         {"XGMI PCS DeskewErr",
 119          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
 120         {"XGMI PCS DataStartupLimitErr",
 121          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
 122         {"XGMI PCS FCInitTimeoutErr",
 123          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
 124         {"XGMI PCS RecoveryTimeoutErr",
 125          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
 126         {"XGMI PCS ReadySerialTimeoutErr",
 127          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
 128         {"XGMI PCS ReadySerialAttemptErr",
 129          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
 130         {"XGMI PCS RecoveryAttemptErr",
 131          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
 132         {"XGMI PCS RecoveryRelockAttemptErr",
 133          SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
 134 };
 135
 136 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
 137         {"WAFL PCS DataLossErr",
 138          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
 139         {"WAFL PCS TrainingErr",
 140          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
 141         {"WAFL PCS CRCErr",
 142          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
 143         {"WAFL PCS BERExceededErr",
 144          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
 145         {"WAFL PCS TxMetaDataErr",
 146          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
 147         {"WAFL PCS ReplayBufParityErr",
 148          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
 149         {"WAFL PCS DataParityErr",
 150          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
 151         {"WAFL PCS ReplayFifoOverflowErr",
 152          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
 153         {"WAFL PCS ReplayFifoUnderflowErr",
 154          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
 155         {"WAFL PCS ElasticFifoOverflowErr",
 156          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
 157         {"WAFL PCS DeskewErr",
 158          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
 159         {"WAFL PCS DataStartupLimitErr",
 160          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
 161         {"WAFL PCS FCInitTimeoutErr",
 162          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
 163         {"WAFL PCS RecoveryTimeoutErr",
 164          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
 165         {"WAFL PCS ReadySerialTimeoutErr",
 166          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
 167         {"WAFL PCS ReadySerialAttemptErr",
 168          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
 169         {"WAFL PCS RecoveryAttemptErr",
 170          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
 171         {"WAFL PCS RecoveryRelockAttemptErr",
 172          SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
 173 };
 174
 175 /**
 176  * DOC: AMDGPU XGMI Support
 177  *
 178  * XGMI is a high speed interconnect that joins multiple GPU cards
 179  * into a homogeneous memory space that is organized by a collective
 180  * hive ID and individual node IDs, both of which are 64-bit numbers.
 181  *
 182  * The file xgmi_device_id contains the unique per GPU device ID and
 183  * is stored in the /sys/class/drm/card${cardno}/device/ directory.
 184  *
 185  * Inside the device directory a sub-directory 'xgmi_hive_info' is
 186  * created which contains the hive ID and the list of nodes.
 187  *
 188  * The hive ID is stored in:
 189  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
 190  *
 191  * The node information is stored in numbered directories:
 192  *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
 193  *
 194  * Each device has their own xgmi_hive_info direction with a mirror
 195  * set of node sub-directories.
 196  *
 197  * The XGMI memory space is built by contiguously adding the power of
 198  * two padded VRAM space from each node to each other.
 199  *
 200  */
 201
 202 static struct attribute amdgpu_xgmi_hive_id = {
 203         .name = "xgmi_hive_id",
 204         .mode = S_IRUGO
 205 };
 206
 207 static struct attribute *amdgpu_xgmi_hive_attrs[] = {
 208         &amdgpu_xgmi_hive_id,
 209         NULL
 210 };
 211
 212 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj,
 213         struct attribute *attr, char *buf)
 214 {
 215         struct amdgpu_hive_info *hive = container_of(
 216                 kobj, struct amdgpu_hive_info, kobj);
 217
 218         if (attr == &amdgpu_xgmi_hive_id)
 219                 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
 220
 221         return 0;
 222 }
 223
 224 static void amdgpu_xgmi_hive_release(struct kobject *kobj)
 225 {
 226         struct amdgpu_hive_info *hive = container_of(
 227                 kobj, struct amdgpu_hive_info, kobj);
 228
 229         mutex_destroy(&hive->hive_lock);
 230         kfree(hive);
 231 }
 232
 233 static const struct sysfs_ops amdgpu_xgmi_hive_ops = {
 234         .show = amdgpu_xgmi_show_attrs,
 235 };
 236
 237 struct kobj_type amdgpu_xgmi_hive_type = {
 238         .release = amdgpu_xgmi_hive_release,
 239         .sysfs_ops = &amdgpu_xgmi_hive_ops,
 240         .default_attrs = amdgpu_xgmi_hive_attrs,
 241 };
 242
 243 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
 244                                      struct device_attribute *attr,
 245                                      char *buf)
 246 {
 247         struct drm_device *ddev = dev_get_drvdata(dev);
 248         struct amdgpu_device *adev = drm_to_adev(ddev);
 249
 250         return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id);
 251
 252 }
 253
 254 #define AMDGPU_XGMI_SET_FICAA(o)        ((o) | 0x456801)
 255 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
 256                                       struct device_attribute *attr,
 257                                       char *buf)
 258 {
 259         struct drm_device *ddev = dev_get_drvdata(dev);
 260         struct amdgpu_device *adev = drm_to_adev(ddev);
 261         uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
 262         uint64_t fica_out;
 263         unsigned int error_count = 0;
 264
 265         ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
 266         ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
 267
 268         fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
 269         if (fica_out != 0x1f)
 270                 pr_err("xGMI error counters not enabled!\n");
 271
 272         fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
 273
 274         if ((fica_out & 0xffff) == 2)
 275                 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
 276
 277         adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
 278
 279         return sysfs_emit(buf, "%u\n", error_count);
 280 }
 281
 282
 283 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
 284 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
 285
 286 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
 287                                          struct amdgpu_hive_info *hive)
 288 {
 289         int ret = 0;
 290         char node[10] = { 0 };
 291
 292         /* Create xgmi device id file */
 293         ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id);
 294         if (ret) {
 295                 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n");
 296                 return ret;
 297         }
 298
 299         /* Create xgmi error file */
 300         ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
 301         if (ret)
 302                 pr_err("failed to create xgmi_error\n");
 303
 304
 305         /* Create sysfs link to hive info folder on the first device */
 306         if (hive->kobj.parent != (&adev->dev->kobj)) {
 307                 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj,
 308                                         "xgmi_hive_info");
 309                 if (ret) {
 310                         dev_err(adev->dev, "XGMI: Failed to create link to hive info");
 311                         goto remove_file;
 312                 }
 313         }
 314
 315         sprintf(node, "node%d", atomic_read(&hive->number_devices));
 316         /* Create sysfs link form the hive folder to yourself */
 317         ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node);
 318         if (ret) {
 319                 dev_err(adev->dev, "XGMI: Failed to create link from hive info");
 320                 goto remove_link;
 321         }
 322
 323         goto success;
 324
 325
 326 remove_link:
 327         sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique);
 328
 329 remove_file:
 330         device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
 331
 332 success:
 333         return ret;
 334 }
 335
 336 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
 337                                           struct amdgpu_hive_info *hive)
 338 {
 339         char node[10];
 340         memset(node, 0, sizeof(node));
 341
 342         device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
 343         device_remove_file(adev->dev, &dev_attr_xgmi_error);
 344
 345         if (hive->kobj.parent != (&adev->dev->kobj))
 346                 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
 347
 348         sprintf(node, "node%d", atomic_read(&hive->number_devices));
 349         sysfs_remove_link(&hive->kobj, node);
 350
 351 }
 352
 353
 354
 355 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
 356 {
 357         struct amdgpu_hive_info *hive = NULL;
 358         int ret;
 359
 360         if (!adev->gmc.xgmi.hive_id)
 361                 return NULL;
 362
 363         if (adev->hive) {
 364                 kobject_get(&adev->hive->kobj);
 365                 return adev->hive;
 366         }
 367
 368         mutex_lock(&xgmi_mutex);
 369
 370         list_for_each_entry(hive, &xgmi_hive_list, node)  {
 371                 if (hive->hive_id == adev->gmc.xgmi.hive_id)
 372                         goto pro_end;
 373         }
 374
 375         hive = kzalloc(sizeof(*hive), GFP_KERNEL);
 376         if (!hive) {
 377                 dev_err(adev->dev, "XGMI: allocation failed\n");
 378                 hive = NULL;
 379                 goto pro_end;
 380         }
 381
 382         /* initialize new hive if not exist */
 383         ret = kobject_init_and_add(&hive->kobj,
 384                         &amdgpu_xgmi_hive_type,
 385                         &adev->dev->kobj,
 386                         "%s", "xgmi_hive_info");
 387         if (ret) {
 388                 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
 389                 kobject_put(&hive->kobj);
 390                 kfree(hive);
 391                 hive = NULL;
 392                 goto pro_end;
 393         }
 394
 395         hive->hive_id = adev->gmc.xgmi.hive_id;
 396         INIT_LIST_HEAD(&hive->device_list);
 397         INIT_LIST_HEAD(&hive->node);
 398         mutex_init(&hive->hive_lock);
 399         atomic_set(&hive->in_reset, 0);
 400         atomic_set(&hive->number_devices, 0);
 401         task_barrier_init(&hive->tb);
 402         hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
 403         hive->hi_req_gpu = NULL;
 404         /*
 405          * hive pstate on boot is high in vega20 so we have to go to low
 406          * pstate on after boot.
 407          */
 408         hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
 409         list_add_tail(&hive->node, &xgmi_hive_list);
 410
 411 pro_end:
 412         if (hive)
 413                 kobject_get(&hive->kobj);
 414         mutex_unlock(&xgmi_mutex);
 415         return hive;
 416 }
 417
 418 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive)
 419 {
 420         if (hive)
 421                 kobject_put(&hive->kobj);
 422 }
 423
 424 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
 425 {
 426         int ret = 0;
 427         struct amdgpu_hive_info *hive;
 428         struct amdgpu_device *request_adev;
 429         bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
 430         bool init_low;
 431
 432         hive = amdgpu_get_xgmi_hive(adev);
 433         if (!hive)
 434                 return 0;
 435
 436         request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev;
 437         init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
 438         amdgpu_put_xgmi_hive(hive);
 439         /* fw bug so temporarily disable pstate switching */
 440         return 0;
 441
 442         if (!hive || adev->asic_type != CHIP_VEGA20)
 443                 return 0;
 444
 445         mutex_lock(&hive->hive_lock);
 446
 447         if (is_hi_req)
 448                 hive->hi_req_count++;
 449         else
 450                 hive->hi_req_count--;
 451
 452         /*
 453          * Vega20 only needs single peer to request pstate high for the hive to
 454          * go high but all peers must request pstate low for the hive to go low
 455          */
 456         if (hive->pstate == pstate ||
 457                         (!is_hi_req && hive->hi_req_count && !init_low))
 458                 goto out;
 459
 460         dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
 461
 462         ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
 463         if (ret) {
 464                 dev_err(request_adev->dev,
 465                         "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
 466                         request_adev->gmc.xgmi.node_id,
 467                         request_adev->gmc.xgmi.hive_id, ret);
 468                 goto out;
 469         }
 470
 471         if (init_low)
 472                 hive->pstate = hive->hi_req_count ?
 473                                         hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
 474         else {
 475                 hive->pstate = pstate;
 476                 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
 477                                                         adev : NULL;
 478         }
 479 out:
 480         mutex_unlock(&hive->hive_lock);
 481         return ret;
 482 }
 483
 484 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
 485 {
 486         int ret;
 487
 488         /* Each psp need to set the latest topology */
 489         ret = psp_xgmi_set_topology_info(&adev->psp,
 490                                          atomic_read(&hive->number_devices),
 491                                          &adev->psp.xgmi_context.top_info);
 492         if (ret)
 493                 dev_err(adev->dev,
 494                         "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
 495                         adev->gmc.xgmi.node_id,
 496                         adev->gmc.xgmi.hive_id, ret);
 497
 498         return ret;
 499 }
 500
 501
 502 /*
 503  * NOTE psp_xgmi_node_info.num_hops layout is as follows:
 504  * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved)
 505  * num_hops[5:3] = reserved
 506  * num_hops[2:0] = number of hops
 507  */
 508 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
 509                 struct amdgpu_device *peer_adev)
 510 {
 511         struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
 512         uint8_t num_hops_mask = 0x7;
 513         int i;
 514
 515         for (i = 0 ; i < top->num_nodes; ++i)
 516                 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
 517                         return top->nodes[i].num_hops & num_hops_mask;
 518         return  -EINVAL;
 519 }
 520
 521 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
 522                 struct amdgpu_device *peer_adev)
 523 {
 524         struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
 525         int i;
 526
 527         for (i = 0 ; i < top->num_nodes; ++i)
 528                 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
 529                         return top->nodes[i].num_links;
 530         return  -EINVAL;
 531 }
 532
 533 /*
 534  * Devices that support extended data require the entire hive to initialize with
 535  * the shared memory buffer flag set.
 536  *
 537  * Hive locks and conditions apply - see amdgpu_xgmi_add_device
 538  */
 539 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive,
 540                                                         bool set_extended_data)
 541 {
 542         struct amdgpu_device *tmp_adev;
 543         int ret;
 544
 545         list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 546                 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false);
 547                 if (ret) {
 548                         dev_err(tmp_adev->dev,
 549                                 "XGMI: Failed to initialize xgmi session for data partition %i\n",
 550                                 set_extended_data);
 551                         return ret;
 552                 }
 553
 554         }
 555
 556         return 0;
 557 }
 558
 559 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
 560 {
 561         struct psp_xgmi_topology_info *top_info;
 562         struct amdgpu_hive_info *hive;
 563         struct amdgpu_xgmi      *entry;
 564         struct amdgpu_device *tmp_adev = NULL;
 565
 566         int count = 0, ret = 0;
 567
 568         if (!adev->gmc.xgmi.supported)
 569                 return 0;
 570
 571         if (!adev->gmc.xgmi.pending_reset &&
 572             amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
 573                 ret = psp_xgmi_initialize(&adev->psp, false, true);
 574                 if (ret) {
 575                         dev_err(adev->dev,
 576                                 "XGMI: Failed to initialize xgmi session\n");
 577                         return ret;
 578                 }
 579
 580                 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
 581                 if (ret) {
 582                         dev_err(adev->dev,
 583                                 "XGMI: Failed to get hive id\n");
 584                         return ret;
 585                 }
 586
 587                 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
 588                 if (ret) {
 589                         dev_err(adev->dev,
 590                                 "XGMI: Failed to get node id\n");
 591                         return ret;
 592                 }
 593         } else {
 594                 adev->gmc.xgmi.hive_id = 16;
 595                 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
 596         }
 597
 598         hive = amdgpu_get_xgmi_hive(adev);
 599         if (!hive) {
 600                 ret = -EINVAL;
 601                 dev_err(adev->dev,
 602                         "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
 603                         adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
 604                 goto exit;
 605         }
 606         mutex_lock(&hive->hive_lock);
 607
 608         top_info = &adev->psp.xgmi_context.top_info;
 609
 610         list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
 611         list_for_each_entry(entry, &hive->device_list, head)
 612                 top_info->nodes[count++].node_id = entry->node_id;
 613         top_info->num_nodes = count;
 614         atomic_set(&hive->number_devices, count);
 615
 616         task_barrier_add_task(&hive->tb);
 617
 618         if (!adev->gmc.xgmi.pending_reset &&
 619             amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
 620                 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 621                         /* update node list for other device in the hive */
 622                         if (tmp_adev != adev) {
 623                                 top_info = &tmp_adev->psp.xgmi_context.top_info;
 624                                 top_info->nodes[count - 1].node_id =
 625                                         adev->gmc.xgmi.node_id;
 626                                 top_info->num_nodes = count;
 627                         }
 628                         ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
 629                         if (ret)
 630                                 goto exit_unlock;
 631                 }
 632
 633                 /* get latest topology info for each device from psp */
 634                 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 635                         ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
 636                                         &tmp_adev->psp.xgmi_context.top_info, false);
 637                         if (ret) {
 638                                 dev_err(tmp_adev->dev,
 639                                         "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
 640                                         tmp_adev->gmc.xgmi.node_id,
 641                                         tmp_adev->gmc.xgmi.hive_id, ret);
 642                                 /* To do : continue with some node failed or disable the whole hive */
 643                                 goto exit_unlock;
 644                         }
 645                 }
 646
 647                 /* get topology again for hives that support extended data */
 648                 if (adev->psp.xgmi_context.supports_extended_data) {
 649
 650                         /* initialize the hive to get extended data.  */
 651                         ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true);
 652                         if (ret)
 653                                 goto exit_unlock;
 654
 655                         /* get the extended data. */
 656                         list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
 657                                 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
 658                                                 &tmp_adev->psp.xgmi_context.top_info, true);
 659                                 if (ret) {
 660                                         dev_err(tmp_adev->dev,
 661                                                 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d",
 662                                                 tmp_adev->gmc.xgmi.node_id,
 663                                                 tmp_adev->gmc.xgmi.hive_id, ret);
 664                                         goto exit_unlock;
 665                                 }
 666                         }
 667
 668                         /* initialize the hive to get non-extended data for the next round. */
 669                         ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false);
 670                         if (ret)
 671                                 goto exit_unlock;
 672
 673                 }
 674         }
 675
 676         if (!ret && !adev->gmc.xgmi.pending_reset)
 677                 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);
 678
 679 exit_unlock:
 680         mutex_unlock(&hive->hive_lock);
 681 exit:
 682         if (!ret) {
 683                 adev->hive = hive;
 684                 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n",
 685                          adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id);
 686         } else {
 687                 amdgpu_put_xgmi_hive(hive);
 688                 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n",
 689                         adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id,
 690                         ret);
 691         }
 692
 693         return ret;
 694 }
 695
 696 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
 697 {
 698         struct amdgpu_hive_info *hive = adev->hive;
 699
 700         if (!adev->gmc.xgmi.supported)
 701                 return -EINVAL;
 702
 703         if (!hive)
 704                 return -EINVAL;
 705
 706         mutex_lock(&hive->hive_lock);
 707         task_barrier_rem_task(&hive->tb);
 708         amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
 709         if (hive->hi_req_gpu == adev)
 710                 hive->hi_req_gpu = NULL;
 711         list_del(&adev->gmc.xgmi.head);
 712         mutex_unlock(&hive->hive_lock);
 713
 714         amdgpu_put_xgmi_hive(hive);
 715         adev->hive = NULL;
 716
 717         if (atomic_dec_return(&hive->number_devices) == 0) {
 718                 /* Remove the hive from global hive list */
 719                 mutex_lock(&xgmi_mutex);
 720                 list_del(&hive->node);
 721                 mutex_unlock(&xgmi_mutex);
 722
 723                 amdgpu_put_xgmi_hive(hive);
 724         }
 725
 726         return psp_xgmi_terminate(&adev->psp);
 727 }
 728
 729 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
 730 {
 731         int r;
 732         struct ras_ih_if ih_info = {
 733                 .cb = NULL,
 734         };
 735         struct ras_fs_if fs_info = {
 736                 .sysfs_name = "xgmi_wafl_err_count",
 737         };
 738
 739         if (!adev->gmc.xgmi.supported ||
 740             adev->gmc.xgmi.num_physical_nodes == 0)
 741                 return 0;
 742
 743         adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev);
 744
 745         if (!adev->gmc.xgmi.ras_if) {
 746                 adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
 747                 if (!adev->gmc.xgmi.ras_if)
 748                         return -ENOMEM;
 749                 adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
 750                 adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 751                 adev->gmc.xgmi.ras_if->sub_block_index = 0;
 752         }
 753         ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if;
 754         r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if,
 755                                  &fs_info, &ih_info);
 756         if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) {
 757                 kfree(adev->gmc.xgmi.ras_if);
 758                 adev->gmc.xgmi.ras_if = NULL;
 759         }
 760
 761         return r;
 762 }
 763
 764 static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
 765 {
 766         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
 767                         adev->gmc.xgmi.ras_if) {
 768                 struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if;
 769                 struct ras_ih_if ih_info = {
 770                         .cb = NULL,
 771                 };
 772
 773                 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
 774                 kfree(ras_if);
 775         }
 776 }
 777
 778 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
 779                                            uint64_t addr)
 780 {
 781         struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi;
 782         return (addr + xgmi->physical_node_id * xgmi->node_segment_size);
 783 }
 784
 785 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
 786 {
 787         WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
 788         WREG32_PCIE(pcs_status_reg, 0);
 789 }
 790
 791 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
 792 {
 793         uint32_t i;
 794
 795         switch (adev->asic_type) {
 796         case CHIP_ARCTURUS:
 797                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
 798                         pcs_clear_status(adev,
 799                                          xgmi_pcs_err_status_reg_arct[i]);
 800                 break;
 801         case CHIP_VEGA20:
 802                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
 803                         pcs_clear_status(adev,
 804                                          xgmi_pcs_err_status_reg_vg20[i]);
 805                 break;
 806         case CHIP_ALDEBARAN:
 807                 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++)
 808                         pcs_clear_status(adev,
 809                                          xgmi23_pcs_err_status_reg_aldebaran[i]);
 810                 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++)
 811                         pcs_clear_status(adev,
 812                                          xgmi3x16_pcs_err_status_reg_aldebaran[i]);
 813                 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++)
 814                         pcs_clear_status(adev,
 815                                          walf_pcs_err_status_reg_aldebaran[i]);
 816                 break;
 817         default:
 818                 break;
 819         }
 820 }
 821
 822 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
 823                                               uint32_t value,
 824                                               uint32_t *ue_count,
 825                                               uint32_t *ce_count,
 826                                               bool is_xgmi_pcs)
 827 {
 828         int i;
 829         int ue_cnt;
 830
 831         if (is_xgmi_pcs) {
 832                 /* query xgmi pcs error status,
 833                  * only ue is supported */
 834                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) {
 835                         ue_cnt = (value &
 836                                   xgmi_pcs_ras_fields[i].pcs_err_mask) >>
 837                                   xgmi_pcs_ras_fields[i].pcs_err_shift;
 838                         if (ue_cnt) {
 839                                 dev_info(adev->dev, "%s detected\n",
 840                                          xgmi_pcs_ras_fields[i].err_name);
 841                                 *ue_count += ue_cnt;
 842                         }
 843                 }
 844         } else {
 845                 /* query wafl pcs error status,
 846                  * only ue is supported */
 847                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) {
 848                         ue_cnt = (value &
 849                                   wafl_pcs_ras_fields[i].pcs_err_mask) >>
 850                                   wafl_pcs_ras_fields[i].pcs_err_shift;
 851                         if (ue_cnt) {
 852                                 dev_info(adev->dev, "%s detected\n",
 853                                          wafl_pcs_ras_fields[i].err_name);
 854                                 *ue_count += ue_cnt;
 855                         }
 856                 }
 857         }
 858
 859         return 0;
 860 }
 861
 862 static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
 863                                              void *ras_error_status)
 864 {
 865         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 866         int i;
 867         uint32_t data;
 868         uint32_t ue_cnt = 0, ce_cnt = 0;
 869
 870         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
 871                 return -EINVAL;
 872
 873         err_data->ue_count = 0;
 874         err_data->ce_count = 0;
 875
 876         switch (adev->asic_type) {
 877         case CHIP_ARCTURUS:
 878                 /* check xgmi pcs error */
 879                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {
 880                         data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
 881                         if (data)
 882                                 amdgpu_xgmi_query_pcs_error_status(adev,
 883                                                 data, &ue_cnt, &ce_cnt, true);
 884                 }
 885                 /* check wafl pcs error */
 886                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {
 887                         data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
 888                         if (data)
 889                                 amdgpu_xgmi_query_pcs_error_status(adev,
 890                                                 data, &ue_cnt, &ce_cnt, false);
 891                 }
 892                 break;
 893         case CHIP_VEGA20:
 894                 /* check xgmi pcs error */
 895                 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
 896                         data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
 897                         if (data)
 898                                 amdgpu_xgmi_query_pcs_error_status(adev,
 899                                                 data, &ue_cnt, &ce_cnt, true);
 900                 }
 901                 /* check wafl pcs error */
 902                 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
 903                         data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
 904                         if (data)
 905                                 amdgpu_xgmi_query_pcs_error_status(adev,
 906                                                 data, &ue_cnt, &ce_cnt, false);
 907                 }
 908                 break;
 909         case CHIP_ALDEBARAN:
 910                 /* check xgmi23 pcs error */
 911                 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) {
 912                         data = RREG32_PCIE(xgmi23_pcs_err_status_reg_aldebaran[i]);
 913                         if (data)
 914                                 amdgpu_xgmi_query_pcs_error_status(adev,
 915                                                 data, &ue_cnt, &ce_cnt, true);
 916                 }
 917                 /* check xgmi3x16 pcs error */
 918                 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) {
 919                         data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]);
 920                         if (data)
 921                                 amdgpu_xgmi_query_pcs_error_status(adev,
 922                                                 data, &ue_cnt, &ce_cnt, true);
 923                 }
 924                 /* check wafl pcs error */
 925                 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) {
 926                         data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]);
 927                         if (data)
 928                                 amdgpu_xgmi_query_pcs_error_status(adev,
 929                                                 data, &ue_cnt, &ce_cnt, false);
 930                 }
 931                 break;
 932         default:
 933                 dev_warn(adev->dev, "XGMI RAS error query not supported");
 934                 break;
 935         }
 936
 937         adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev);
 938
 939         err_data->ue_count += ue_cnt;
 940         err_data->ce_count += ce_cnt;
 941
 942         return 0;
 943 }
 944
 945 const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs = {
 946         .ras_late_init = amdgpu_xgmi_ras_late_init,
 947         .ras_fini = amdgpu_xgmi_ras_fini,
 948         .query_ras_error_count = amdgpu_xgmi_query_ras_error_count,
 949         .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count,
 950 };