drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_object.h"
  48 #include "amdgpu_trace.h"
  49 #include "amdgpu_amdkfd.h"
  50 #include "bif/bif_4_1_d.h"
  51
  52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  53
  54 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  55                              struct ttm_mem_reg *mem, unsigned num_pages,
  56                              uint64_t offset, unsigned window,
  57                              struct amdgpu_ring *ring,
  58                              uint64_t *addr);
  59
  60 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  61 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  62
  63 /*
  64  * Global memory.
  65  */
  66 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  67 {
  68         return ttm_mem_global_init(ref->object);
  69 }
  70
  71 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  72 {
  73         ttm_mem_global_release(ref->object);
  74 }
  75
  76 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  77 {
  78         struct drm_global_reference *global_ref;
  79         struct amdgpu_ring *ring;
  80         struct drm_sched_rq *rq;
  81         int r;
  82
  83         adev->mman.mem_global_referenced = false;
  84         global_ref = &adev->mman.mem_global_ref;
  85         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  86         global_ref->size = sizeof(struct ttm_mem_global);
  87         global_ref->init = &amdgpu_ttm_mem_global_init;
  88         global_ref->release = &amdgpu_ttm_mem_global_release;
  89         r = drm_global_item_ref(global_ref);
  90         if (r) {
  91                 DRM_ERROR("Failed setting up TTM memory accounting "
  92                           "subsystem.\n");
  93                 goto error_mem;
  94         }
  95
  96         adev->mman.bo_global_ref.mem_glob =
  97                 adev->mman.mem_global_ref.object;
  98         global_ref = &adev->mman.bo_global_ref.ref;
  99         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 100         global_ref->size = sizeof(struct ttm_bo_global);
 101         global_ref->init = &ttm_bo_global_init;
 102         global_ref->release = &ttm_bo_global_release;
 103         r = drm_global_item_ref(global_ref);
 104         if (r) {
 105                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 106                 goto error_bo;
 107         }
 108
 109         mutex_init(&adev->mman.gtt_window_lock);
 110
 111         ring = adev->mman.buffer_funcs_ring;
 112         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
 113         r = drm_sched_entity_init(&ring->sched, &adev->mman.entity,
 114                                   rq, amdgpu_sched_jobs, NULL);
 115         if (r) {
 116                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 117                 goto error_entity;
 118         }
 119
 120         adev->mman.mem_global_referenced = true;
 121
 122         return 0;
 123
 124 error_entity:
 125         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 126 error_bo:
 127         drm_global_item_unref(&adev->mman.mem_global_ref);
 128 error_mem:
 129         return r;
 130 }
 131
 132 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 133 {
 134         if (adev->mman.mem_global_referenced) {
 135                 drm_sched_entity_fini(adev->mman.entity.sched,
 136                                       &adev->mman.entity);
 137                 mutex_destroy(&adev->mman.gtt_window_lock);
 138                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 139                 drm_global_item_unref(&adev->mman.mem_global_ref);
 140                 adev->mman.mem_global_referenced = false;
 141         }
 142 }
 143
 144 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 145 {
 146         return 0;
 147 }
 148
 149 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 150                                 struct ttm_mem_type_manager *man)
 151 {
 152         struct amdgpu_device *adev;
 153
 154         adev = amdgpu_ttm_adev(bdev);
 155
 156         switch (type) {
 157         case TTM_PL_SYSTEM:
 158                 /* System memory */
 159                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 160                 man->available_caching = TTM_PL_MASK_CACHING;
 161                 man->default_caching = TTM_PL_FLAG_CACHED;
 162                 break;
 163         case TTM_PL_TT:
 164                 man->func = &amdgpu_gtt_mgr_func;
 165                 man->gpu_offset = adev->gmc.gart_start;
 166                 man->available_caching = TTM_PL_MASK_CACHING;
 167                 man->default_caching = TTM_PL_FLAG_CACHED;
 168                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 169                 break;
 170         case TTM_PL_VRAM:
 171                 /* "On-card" video ram */
 172                 man->func = &amdgpu_vram_mgr_func;
 173                 man->gpu_offset = adev->gmc.vram_start;
 174                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 175                              TTM_MEMTYPE_FLAG_MAPPABLE;
 176                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 177                 man->default_caching = TTM_PL_FLAG_WC;
 178                 break;
 179         case AMDGPU_PL_GDS:
 180         case AMDGPU_PL_GWS:
 181         case AMDGPU_PL_OA:
 182                 /* On-chip GDS memory*/
 183                 man->func = &ttm_bo_manager_func;
 184                 man->gpu_offset = 0;
 185                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 186                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 187                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 188                 break;
 189         default:
 190                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 191                 return -EINVAL;
 192         }
 193         return 0;
 194 }
 195
 196 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 197                                 struct ttm_placement *placement)
 198 {
 199         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 200         struct amdgpu_bo *abo;
 201         static const struct ttm_place placements = {
 202                 .fpfn = 0,
 203                 .lpfn = 0,
 204                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 205         };
 206
 207         if (bo->type == ttm_bo_type_sg) {
 208                 placement->num_placement = 0;
 209                 placement->num_busy_placement = 0;
 210                 return;
 211         }
 212
 213         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 214                 placement->placement = &placements;
 215                 placement->busy_placement = &placements;
 216                 placement->num_placement = 1;
 217                 placement->num_busy_placement = 1;
 218                 return;
 219         }
 220         abo = ttm_to_amdgpu_bo(bo);
 221         switch (bo->mem.mem_type) {
 222         case TTM_PL_VRAM:
 223                 if (!adev->mman.buffer_funcs_enabled) {
 224                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 225                 } else if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 226                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 227                         unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 228                         struct drm_mm_node *node = bo->mem.mm_node;
 229                         unsigned long pages_left;
 230
 231                         for (pages_left = bo->mem.num_pages;
 232                              pages_left;
 233                              pages_left -= node->size, node++) {
 234                                 if (node->start < fpfn)
 235                                         break;
 236                         }
 237
 238                         if (!pages_left)
 239                                 goto gtt;
 240
 241                         /* Try evicting to the CPU inaccessible part of VRAM
 242                          * first, but only set GTT as busy placement, so this
 243                          * BO will be evicted to GTT rather than causing other
 244                          * BOs to be evicted from VRAM
 245                          */
 246                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 247                                                          AMDGPU_GEM_DOMAIN_GTT);
 248                         abo->placements[0].fpfn = fpfn;
 249                         abo->placements[0].lpfn = 0;
 250                         abo->placement.busy_placement = &abo->placements[1];
 251                         abo->placement.num_busy_placement = 1;
 252                 } else {
 253 gtt:
 254                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 255                 }
 256                 break;
 257         case TTM_PL_TT:
 258         default:
 259                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 260         }
 261         *placement = abo->placement;
 262 }
 263
 264 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 265 {
 266         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 267
 268         /*
 269          * Don't verify access for KFD BOs. They don't have a GEM
 270          * object associated with them.
 271          */
 272         if (abo->kfd_bo)
 273                 return 0;
 274
 275         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 276                 return -EPERM;
 277         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 278                                           filp->private_data);
 279 }
 280
 281 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 282                              struct ttm_mem_reg *new_mem)
 283 {
 284         struct ttm_mem_reg *old_mem = &bo->mem;
 285
 286         BUG_ON(old_mem->mm_node != NULL);
 287         *old_mem = *new_mem;
 288         new_mem->mm_node = NULL;
 289 }
 290
 291 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 292                                     struct drm_mm_node *mm_node,
 293                                     struct ttm_mem_reg *mem)
 294 {
 295         uint64_t addr = 0;
 296
 297         if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
 298                 addr = mm_node->start << PAGE_SHIFT;
 299                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 300         }
 301         return addr;
 302 }
 303
 304 /**
 305  * amdgpu_find_mm_node - Helper function finds the drm_mm_node
 306  *  corresponding to @offset. It also modifies the offset to be
 307  *  within the drm_mm_node returned
 308  */
 309 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 310                                                unsigned long *offset)
 311 {
 312         struct drm_mm_node *mm_node = mem->mm_node;
 313
 314         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 315                 *offset -= (mm_node->size << PAGE_SHIFT);
 316                 ++mm_node;
 317         }
 318         return mm_node;
 319 }
 320
 321 /**
 322  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 323  *
 324  * The function copies @size bytes from {src->mem + src->offset} to
 325  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 326  * move and different for a BO to BO copy.
 327  *
 328  * @f: Returns the last fence if multiple jobs are submitted.
 329  */
 330 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 331                                struct amdgpu_copy_mem *src,
 332                                struct amdgpu_copy_mem *dst,
 333                                uint64_t size,
 334                                struct reservation_object *resv,
 335                                struct dma_fence **f)
 336 {
 337         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 338         struct drm_mm_node *src_mm, *dst_mm;
 339         uint64_t src_node_start, dst_node_start, src_node_size,
 340                  dst_node_size, src_page_offset, dst_page_offset;
 341         struct dma_fence *fence = NULL;
 342         int r = 0;
 343         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 344                                         AMDGPU_GPU_PAGE_SIZE);
 345
 346         if (!adev->mman.buffer_funcs_enabled) {
 347                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 348                 return -EINVAL;
 349         }
 350
 351         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 352         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 353                                              src->offset;
 354         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 355         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 356
 357         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 358         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 359                                              dst->offset;
 360         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 361         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 362
 363         mutex_lock(&adev->mman.gtt_window_lock);
 364
 365         while (size) {
 366                 unsigned long cur_size;
 367                 uint64_t from = src_node_start, to = dst_node_start;
 368                 struct dma_fence *next;
 369
 370                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 371                  * begins at an offset, then adjust the size accordingly
 372                  */
 373                 cur_size = min3(min(src_node_size, dst_node_size), size,
 374                                 GTT_MAX_BYTES);
 375                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 376                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 377                         cur_size -= max(src_page_offset, dst_page_offset);
 378
 379                 /* Map only what needs to be accessed. Map src to window 0 and
 380                  * dst to window 1
 381                  */
 382                 if (src->mem->mem_type == TTM_PL_TT &&
 383                     !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
 384                         r = amdgpu_map_buffer(src->bo, src->mem,
 385                                         PFN_UP(cur_size + src_page_offset),
 386                                         src_node_start, 0, ring,
 387                                         &from);
 388                         if (r)
 389                                 goto error;
 390                         /* Adjust the offset because amdgpu_map_buffer returns
 391                          * start of mapped page
 392                          */
 393                         from += src_page_offset;
 394                 }
 395
 396                 if (dst->mem->mem_type == TTM_PL_TT &&
 397                     !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
 398                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 399                                         PFN_UP(cur_size + dst_page_offset),
 400                                         dst_node_start, 1, ring,
 401                                         &to);
 402                         if (r)
 403                                 goto error;
 404                         to += dst_page_offset;
 405                 }
 406
 407                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 408                                        resv, &next, false, true);
 409                 if (r)
 410                         goto error;
 411
 412                 dma_fence_put(fence);
 413                 fence = next;
 414
 415                 size -= cur_size;
 416                 if (!size)
 417                         break;
 418
 419                 src_node_size -= cur_size;
 420                 if (!src_node_size) {
 421                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 422                                                              src->mem);
 423                         src_node_size = (src_mm->size << PAGE_SHIFT);
 424                 } else {
 425                         src_node_start += cur_size;
 426                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 427                 }
 428                 dst_node_size -= cur_size;
 429                 if (!dst_node_size) {
 430                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 431                                                              dst->mem);
 432                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 433                 } else {
 434                         dst_node_start += cur_size;
 435                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 436                 }
 437         }
 438 error:
 439         mutex_unlock(&adev->mman.gtt_window_lock);
 440         if (f)
 441                 *f = dma_fence_get(fence);
 442         dma_fence_put(fence);
 443         return r;
 444 }
 445
 446
 447 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 448                             bool evict, bool no_wait_gpu,
 449                             struct ttm_mem_reg *new_mem,
 450                             struct ttm_mem_reg *old_mem)
 451 {
 452         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 453         struct amdgpu_copy_mem src, dst;
 454         struct dma_fence *fence = NULL;
 455         int r;
 456
 457         src.bo = bo;
 458         dst.bo = bo;
 459         src.mem = old_mem;
 460         dst.mem = new_mem;
 461         src.offset = 0;
 462         dst.offset = 0;
 463
 464         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 465                                        new_mem->num_pages << PAGE_SHIFT,
 466                                        bo->resv, &fence);
 467         if (r)
 468                 goto error;
 469
 470         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 471         dma_fence_put(fence);
 472         return r;
 473
 474 error:
 475         if (fence)
 476                 dma_fence_wait(fence, false);
 477         dma_fence_put(fence);
 478         return r;
 479 }
 480
 481 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 482                                 struct ttm_operation_ctx *ctx,
 483                                 struct ttm_mem_reg *new_mem)
 484 {
 485         struct amdgpu_device *adev;
 486         struct ttm_mem_reg *old_mem = &bo->mem;
 487         struct ttm_mem_reg tmp_mem;
 488         struct ttm_place placements;
 489         struct ttm_placement placement;
 490         int r;
 491
 492         adev = amdgpu_ttm_adev(bo->bdev);
 493         tmp_mem = *new_mem;
 494         tmp_mem.mm_node = NULL;
 495         placement.num_placement = 1;
 496         placement.placement = &placements;
 497         placement.num_busy_placement = 1;
 498         placement.busy_placement = &placements;
 499         placements.fpfn = 0;
 500         placements.lpfn = 0;
 501         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 502         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 503         if (unlikely(r)) {
 504                 return r;
 505         }
 506
 507         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 508         if (unlikely(r)) {
 509                 goto out_cleanup;
 510         }
 511
 512         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 513         if (unlikely(r)) {
 514                 goto out_cleanup;
 515         }
 516         r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, &tmp_mem, old_mem);
 517         if (unlikely(r)) {
 518                 goto out_cleanup;
 519         }
 520         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 521 out_cleanup:
 522         ttm_bo_mem_put(bo, &tmp_mem);
 523         return r;
 524 }
 525
 526 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 527                                 struct ttm_operation_ctx *ctx,
 528                                 struct ttm_mem_reg *new_mem)
 529 {
 530         struct amdgpu_device *adev;
 531         struct ttm_mem_reg *old_mem = &bo->mem;
 532         struct ttm_mem_reg tmp_mem;
 533         struct ttm_placement placement;
 534         struct ttm_place placements;
 535         int r;
 536
 537         adev = amdgpu_ttm_adev(bo->bdev);
 538         tmp_mem = *new_mem;
 539         tmp_mem.mm_node = NULL;
 540         placement.num_placement = 1;
 541         placement.placement = &placements;
 542         placement.num_busy_placement = 1;
 543         placement.busy_placement = &placements;
 544         placements.fpfn = 0;
 545         placements.lpfn = 0;
 546         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 547         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 548         if (unlikely(r)) {
 549                 return r;
 550         }
 551         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 552         if (unlikely(r)) {
 553                 goto out_cleanup;
 554         }
 555         r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, new_mem, old_mem);
 556         if (unlikely(r)) {
 557                 goto out_cleanup;
 558         }
 559 out_cleanup:
 560         ttm_bo_mem_put(bo, &tmp_mem);
 561         return r;
 562 }
 563
 564 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 565                           struct ttm_operation_ctx *ctx,
 566                           struct ttm_mem_reg *new_mem)
 567 {
 568         struct amdgpu_device *adev;
 569         struct amdgpu_bo *abo;
 570         struct ttm_mem_reg *old_mem = &bo->mem;
 571         int r;
 572
 573         /* Can't move a pinned BO */
 574         abo = ttm_to_amdgpu_bo(bo);
 575         if (WARN_ON_ONCE(abo->pin_count > 0))
 576                 return -EINVAL;
 577
 578         adev = amdgpu_ttm_adev(bo->bdev);
 579
 580         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 581                 amdgpu_move_null(bo, new_mem);
 582                 return 0;
 583         }
 584         if ((old_mem->mem_type == TTM_PL_TT &&
 585              new_mem->mem_type == TTM_PL_SYSTEM) ||
 586             (old_mem->mem_type == TTM_PL_SYSTEM &&
 587              new_mem->mem_type == TTM_PL_TT)) {
 588                 /* bind is enough */
 589                 amdgpu_move_null(bo, new_mem);
 590                 return 0;
 591         }
 592
 593         if (!adev->mman.buffer_funcs_enabled)
 594                 goto memcpy;
 595
 596         if (old_mem->mem_type == TTM_PL_VRAM &&
 597             new_mem->mem_type == TTM_PL_SYSTEM) {
 598                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 599         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 600                    new_mem->mem_type == TTM_PL_VRAM) {
 601                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 602         } else {
 603                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 604                                      new_mem, old_mem);
 605         }
 606
 607         if (r) {
 608 memcpy:
 609                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 610                 if (r) {
 611                         return r;
 612                 }
 613         }
 614
 615         if (bo->type == ttm_bo_type_device &&
 616             new_mem->mem_type == TTM_PL_VRAM &&
 617             old_mem->mem_type != TTM_PL_VRAM) {
 618                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 619                  * accesses the BO after it's moved.
 620                  */
 621                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 622         }
 623
 624         /* update statistics */
 625         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 626         return 0;
 627 }
 628
 629 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 630 {
 631         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 632         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 633         struct drm_mm_node *mm_node = mem->mm_node;
 634
 635         mem->bus.addr = NULL;
 636         mem->bus.offset = 0;
 637         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 638         mem->bus.base = 0;
 639         mem->bus.is_iomem = false;
 640         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 641                 return -EINVAL;
 642         switch (mem->mem_type) {
 643         case TTM_PL_SYSTEM:
 644                 /* system memory */
 645                 return 0;
 646         case TTM_PL_TT:
 647                 break;
 648         case TTM_PL_VRAM:
 649                 mem->bus.offset = mem->start << PAGE_SHIFT;
 650                 /* check if it's visible */
 651                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 652                         return -EINVAL;
 653                 /* Only physically contiguous buffers apply. In a contiguous
 654                  * buffer, size of the first mm_node would match the number of
 655                  * pages in ttm_mem_reg.
 656                  */
 657                 if (adev->mman.aper_base_kaddr &&
 658                     (mm_node->size == mem->num_pages))
 659                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 660                                         mem->bus.offset;
 661
 662                 mem->bus.base = adev->gmc.aper_base;
 663                 mem->bus.is_iomem = true;
 664                 break;
 665         default:
 666                 return -EINVAL;
 667         }
 668         return 0;
 669 }
 670
 671 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 672 {
 673 }
 674
 675 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 676                                            unsigned long page_offset)
 677 {
 678         struct drm_mm_node *mm;
 679         unsigned long offset = (page_offset << PAGE_SHIFT);
 680
 681         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 682         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 683                 (offset >> PAGE_SHIFT);
 684 }
 685
 686 /*
 687  * TTM backend functions.
 688  */
 689 struct amdgpu_ttm_gup_task_list {
 690         struct list_head        list;
 691         struct task_struct      *task;
 692 };
 693
 694 struct amdgpu_ttm_tt {
 695         struct ttm_dma_tt       ttm;
 696         u64                     offset;
 697         uint64_t                userptr;
 698         struct task_struct      *usertask;
 699         uint32_t                userflags;
 700         spinlock_t              guptasklock;
 701         struct list_head        guptasks;
 702         atomic_t                mmu_invalidations;
 703         uint32_t                last_set_pages;
 704 };
 705
 706 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 707 {
 708         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 709         struct mm_struct *mm = gtt->usertask->mm;
 710         unsigned int flags = 0;
 711         unsigned pinned = 0;
 712         int r;
 713
 714         if (!mm) /* Happens during process shutdown */
 715                 return -ESRCH;
 716
 717         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 718                 flags |= FOLL_WRITE;
 719
 720         down_read(&mm->mmap_sem);
 721
 722         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 723                 /* check that we only use anonymous memory
 724                    to prevent problems with writeback */
 725                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 726                 struct vm_area_struct *vma;
 727
 728                 vma = find_vma(mm, gtt->userptr);
 729                 if (!vma || vma->vm_file || vma->vm_end < end) {
 730                         up_read(&mm->mmap_sem);
 731                         return -EPERM;
 732                 }
 733         }
 734
 735         do {
 736                 unsigned num_pages = ttm->num_pages - pinned;
 737                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 738                 struct page **p = pages + pinned;
 739                 struct amdgpu_ttm_gup_task_list guptask;
 740
 741                 guptask.task = current;
 742                 spin_lock(&gtt->guptasklock);
 743                 list_add(&guptask.list, &gtt->guptasks);
 744                 spin_unlock(&gtt->guptasklock);
 745
 746                 if (mm == current->mm)
 747                         r = get_user_pages(userptr, num_pages, flags, p, NULL);
 748                 else
 749                         r = get_user_pages_remote(gtt->usertask,
 750                                         mm, userptr, num_pages,
 751                                         flags, p, NULL, NULL);
 752
 753                 spin_lock(&gtt->guptasklock);
 754                 list_del(&guptask.list);
 755                 spin_unlock(&gtt->guptasklock);
 756
 757                 if (r < 0)
 758                         goto release_pages;
 759
 760                 pinned += r;
 761
 762         } while (pinned < ttm->num_pages);
 763
 764         up_read(&mm->mmap_sem);
 765         return 0;
 766
 767 release_pages:
 768         release_pages(pages, pinned);
 769         up_read(&mm->mmap_sem);
 770         return r;
 771 }
 772
 773 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 774 {
 775         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 776         unsigned i;
 777
 778         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 779         for (i = 0; i < ttm->num_pages; ++i) {
 780                 if (ttm->pages[i])
 781                         put_page(ttm->pages[i]);
 782
 783                 ttm->pages[i] = pages ? pages[i] : NULL;
 784         }
 785 }
 786
 787 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 788 {
 789         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 790         unsigned i;
 791
 792         for (i = 0; i < ttm->num_pages; ++i) {
 793                 struct page *page = ttm->pages[i];
 794
 795                 if (!page)
 796                         continue;
 797
 798                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 799                         set_page_dirty(page);
 800
 801                 mark_page_accessed(page);
 802         }
 803 }
 804
 805 /* prepare the sg table with the user pages */
 806 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 807 {
 808         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 809         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 810         unsigned nents;
 811         int r;
 812
 813         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 814         enum dma_data_direction direction = write ?
 815                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 816
 817         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 818                                       ttm->num_pages << PAGE_SHIFT,
 819                                       GFP_KERNEL);
 820         if (r)
 821                 goto release_sg;
 822
 823         r = -ENOMEM;
 824         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 825         if (nents != ttm->sg->nents)
 826                 goto release_sg;
 827
 828         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 829                                          gtt->ttm.dma_address, ttm->num_pages);
 830
 831         return 0;
 832
 833 release_sg:
 834         kfree(ttm->sg);
 835         return r;
 836 }
 837
 838 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 839 {
 840         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 841         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 842
 843         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 844         enum dma_data_direction direction = write ?
 845                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 846
 847         /* double check that we don't free the table twice */
 848         if (!ttm->sg->sgl)
 849                 return;
 850
 851         /* free the sg table and pages again */
 852         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 853
 854         amdgpu_ttm_tt_mark_user_pages(ttm);
 855
 856         sg_free_table(ttm->sg);
 857 }
 858
 859 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 860                                    struct ttm_mem_reg *bo_mem)
 861 {
 862         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 863         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 864         uint64_t flags;
 865         int r = 0;
 866
 867         if (gtt->userptr) {
 868                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 869                 if (r) {
 870                         DRM_ERROR("failed to pin userptr\n");
 871                         return r;
 872                 }
 873         }
 874         if (!ttm->num_pages) {
 875                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 876                      ttm->num_pages, bo_mem, ttm);
 877         }
 878
 879         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 880             bo_mem->mem_type == AMDGPU_PL_GWS ||
 881             bo_mem->mem_type == AMDGPU_PL_OA)
 882                 return -EINVAL;
 883
 884         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 885                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 886                 return 0;
 887         }
 888
 889         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 890         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 891         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 892                 ttm->pages, gtt->ttm.dma_address, flags);
 893
 894         if (r)
 895                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 896                           ttm->num_pages, gtt->offset);
 897         return r;
 898 }
 899
 900 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 901 {
 902         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 903         struct ttm_operation_ctx ctx = { false, false };
 904         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
 905         struct ttm_mem_reg tmp;
 906         struct ttm_placement placement;
 907         struct ttm_place placements;
 908         uint64_t flags;
 909         int r;
 910
 911         if (bo->mem.mem_type != TTM_PL_TT ||
 912             amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
 913                 return 0;
 914
 915         tmp = bo->mem;
 916         tmp.mm_node = NULL;
 917         placement.num_placement = 1;
 918         placement.placement = &placements;
 919         placement.num_busy_placement = 1;
 920         placement.busy_placement = &placements;
 921         placements.fpfn = 0;
 922         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 923         placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
 924                 TTM_PL_FLAG_TT;
 925
 926         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 927         if (unlikely(r))
 928                 return r;
 929
 930         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
 931         gtt->offset = (u64)tmp.start << PAGE_SHIFT;
 932         r = amdgpu_gart_bind(adev, gtt->offset, bo->ttm->num_pages,
 933                              bo->ttm->pages, gtt->ttm.dma_address, flags);
 934         if (unlikely(r)) {
 935                 ttm_bo_mem_put(bo, &tmp);
 936                 return r;
 937         }
 938
 939         ttm_bo_mem_put(bo, &bo->mem);
 940         bo->mem = tmp;
 941         bo->offset = (bo->mem.start << PAGE_SHIFT) +
 942                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
 943
 944         return 0;
 945 }
 946
 947 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
 948 {
 949         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
 950         struct amdgpu_ttm_tt *gtt = (void *)tbo->ttm;
 951         uint64_t flags;
 952         int r;
 953
 954         if (!gtt)
 955                 return 0;
 956
 957         flags = amdgpu_ttm_tt_pte_flags(adev, &gtt->ttm.ttm, &tbo->mem);
 958         r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 959                              gtt->ttm.ttm.pages, gtt->ttm.dma_address, flags);
 960         if (r)
 961                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 962                           gtt->ttm.ttm.num_pages, gtt->offset);
 963         return r;
 964 }
 965
 966 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 967 {
 968         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 969         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 970         int r;
 971
 972         if (gtt->userptr)
 973                 amdgpu_ttm_tt_unpin_userptr(ttm);
 974
 975         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
 976                 return 0;
 977
 978         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 979         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
 980         if (r)
 981                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
 982                           gtt->ttm.ttm.num_pages, gtt->offset);
 983         return r;
 984 }
 985
 986 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 987 {
 988         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 989
 990         if (gtt->usertask)
 991                 put_task_struct(gtt->usertask);
 992
 993         ttm_dma_tt_fini(&gtt->ttm);
 994         kfree(gtt);
 995 }
 996
 997 static struct ttm_backend_func amdgpu_backend_func = {
 998         .bind = &amdgpu_ttm_backend_bind,
 999         .unbind = &amdgpu_ttm_backend_unbind,
1000         .destroy = &amdgpu_ttm_backend_destroy,
1001 };
1002
1003 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1004                                            uint32_t page_flags)
1005 {
1006         struct amdgpu_device *adev;
1007         struct amdgpu_ttm_tt *gtt;
1008
1009         adev = amdgpu_ttm_adev(bo->bdev);
1010
1011         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1012         if (gtt == NULL) {
1013                 return NULL;
1014         }
1015         gtt->ttm.ttm.func = &amdgpu_backend_func;
1016         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1017                 kfree(gtt);
1018                 return NULL;
1019         }
1020         return &gtt->ttm.ttm;
1021 }
1022
1023 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1024                         struct ttm_operation_ctx *ctx)
1025 {
1026         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1027         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1028         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1029
1030         if (gtt && gtt->userptr) {
1031                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1032                 if (!ttm->sg)
1033                         return -ENOMEM;
1034
1035                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1036                 ttm->state = tt_unbound;
1037                 return 0;
1038         }
1039
1040         if (slave && ttm->sg) {
1041                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1042                                                  gtt->ttm.dma_address,
1043                                                  ttm->num_pages);
1044                 ttm->state = tt_unbound;
1045                 return 0;
1046         }
1047
1048 #ifdef CONFIG_SWIOTLB
1049         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1050                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1051         }
1052 #endif
1053
1054         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1055 }
1056
1057 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1058 {
1059         struct amdgpu_device *adev;
1060         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1061         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1062
1063         if (gtt && gtt->userptr) {
1064                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1065                 kfree(ttm->sg);
1066                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1067                 return;
1068         }
1069
1070         if (slave)
1071                 return;
1072
1073         adev = amdgpu_ttm_adev(ttm->bdev);
1074
1075 #ifdef CONFIG_SWIOTLB
1076         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1077                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1078                 return;
1079         }
1080 #endif
1081
1082         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1083 }
1084
1085 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1086                               uint32_t flags)
1087 {
1088         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1089
1090         if (gtt == NULL)
1091                 return -EINVAL;
1092
1093         gtt->userptr = addr;
1094         gtt->userflags = flags;
1095
1096         if (gtt->usertask)
1097                 put_task_struct(gtt->usertask);
1098         gtt->usertask = current->group_leader;
1099         get_task_struct(gtt->usertask);
1100
1101         spin_lock_init(&gtt->guptasklock);
1102         INIT_LIST_HEAD(&gtt->guptasks);
1103         atomic_set(&gtt->mmu_invalidations, 0);
1104         gtt->last_set_pages = 0;
1105
1106         return 0;
1107 }
1108
1109 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1110 {
1111         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1112
1113         if (gtt == NULL)
1114                 return NULL;
1115
1116         if (gtt->usertask == NULL)
1117                 return NULL;
1118
1119         return gtt->usertask->mm;
1120 }
1121
1122 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1123                                   unsigned long end)
1124 {
1125         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1126         struct amdgpu_ttm_gup_task_list *entry;
1127         unsigned long size;
1128
1129         if (gtt == NULL || !gtt->userptr)
1130                 return false;
1131
1132         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1133         if (gtt->userptr > end || gtt->userptr + size <= start)
1134                 return false;
1135
1136         spin_lock(&gtt->guptasklock);
1137         list_for_each_entry(entry, &gtt->guptasks, list) {
1138                 if (entry->task == current) {
1139                         spin_unlock(&gtt->guptasklock);
1140                         return false;
1141                 }
1142         }
1143         spin_unlock(&gtt->guptasklock);
1144
1145         atomic_inc(&gtt->mmu_invalidations);
1146
1147         return true;
1148 }
1149
1150 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1151                                        int *last_invalidated)
1152 {
1153         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1154         int prev_invalidated = *last_invalidated;
1155
1156         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1157         return prev_invalidated != *last_invalidated;
1158 }
1159
1160 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1161 {
1162         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1163
1164         if (gtt == NULL || !gtt->userptr)
1165                 return false;
1166
1167         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1168 }
1169
1170 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1171 {
1172         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1173
1174         if (gtt == NULL)
1175                 return false;
1176
1177         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1178 }
1179
1180 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1181                                  struct ttm_mem_reg *mem)
1182 {
1183         uint64_t flags = 0;
1184
1185         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1186                 flags |= AMDGPU_PTE_VALID;
1187
1188         if (mem && mem->mem_type == TTM_PL_TT) {
1189                 flags |= AMDGPU_PTE_SYSTEM;
1190
1191                 if (ttm->caching_state == tt_cached)
1192                         flags |= AMDGPU_PTE_SNOOPED;
1193         }
1194
1195         flags |= adev->gart.gart_pte_flags;
1196         flags |= AMDGPU_PTE_READABLE;
1197
1198         if (!amdgpu_ttm_tt_is_readonly(ttm))
1199                 flags |= AMDGPU_PTE_WRITEABLE;
1200
1201         return flags;
1202 }
1203
1204 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1205                                             const struct ttm_place *place)
1206 {
1207         unsigned long num_pages = bo->mem.num_pages;
1208         struct drm_mm_node *node = bo->mem.mm_node;
1209         struct reservation_object_list *flist;
1210         struct dma_fence *f;
1211         int i;
1212
1213         /* If bo is a KFD BO, check if the bo belongs to the current process.
1214          * If true, then return false as any KFD process needs all its BOs to
1215          * be resident to run successfully
1216          */
1217         flist = reservation_object_get_list(bo->resv);
1218         if (flist) {
1219                 for (i = 0; i < flist->shared_count; ++i) {
1220                         f = rcu_dereference_protected(flist->shared[i],
1221                                 reservation_object_held(bo->resv));
1222                         if (amdkfd_fence_check_mm(f, current->mm))
1223                                 return false;
1224                 }
1225         }
1226
1227         switch (bo->mem.mem_type) {
1228         case TTM_PL_TT:
1229                 return true;
1230
1231         case TTM_PL_VRAM:
1232                 /* Check each drm MM node individually */
1233                 while (num_pages) {
1234                         if (place->fpfn < (node->start + node->size) &&
1235                             !(place->lpfn && place->lpfn <= node->start))
1236                                 return true;
1237
1238                         num_pages -= node->size;
1239                         ++node;
1240                 }
1241                 return false;
1242
1243         default:
1244                 break;
1245         }
1246
1247         return ttm_bo_eviction_valuable(bo, place);
1248 }
1249
1250 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1251                                     unsigned long offset,
1252                                     void *buf, int len, int write)
1253 {
1254         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1255         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1256         struct drm_mm_node *nodes;
1257         uint32_t value = 0;
1258         int ret = 0;
1259         uint64_t pos;
1260         unsigned long flags;
1261
1262         if (bo->mem.mem_type != TTM_PL_VRAM)
1263                 return -EIO;
1264
1265         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1266         pos = (nodes->start << PAGE_SHIFT) + offset;
1267
1268         while (len && pos < adev->gmc.mc_vram_size) {
1269                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1270                 uint32_t bytes = 4 - (pos & 3);
1271                 uint32_t shift = (pos & 3) * 8;
1272                 uint32_t mask = 0xffffffff << shift;
1273
1274                 if (len < bytes) {
1275                         mask &= 0xffffffff >> (bytes - len) * 8;
1276                         bytes = len;
1277                 }
1278
1279                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1280                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1281                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1282                 if (!write || mask != 0xffffffff)
1283                         value = RREG32_NO_KIQ(mmMM_DATA);
1284                 if (write) {
1285                         value &= ~mask;
1286                         value |= (*(uint32_t *)buf << shift) & mask;
1287                         WREG32_NO_KIQ(mmMM_DATA, value);
1288                 }
1289                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1290                 if (!write) {
1291                         value = (value & mask) >> shift;
1292                         memcpy(buf, &value, bytes);
1293                 }
1294
1295                 ret += bytes;
1296                 buf = (uint8_t *)buf + bytes;
1297                 pos += bytes;
1298                 len -= bytes;
1299                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1300                         ++nodes;
1301                         pos = (nodes->start << PAGE_SHIFT);
1302                 }
1303         }
1304
1305         return ret;
1306 }
1307
1308 static struct ttm_bo_driver amdgpu_bo_driver = {
1309         .ttm_tt_create = &amdgpu_ttm_tt_create,
1310         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1311         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1312         .invalidate_caches = &amdgpu_invalidate_caches,
1313         .init_mem_type = &amdgpu_init_mem_type,
1314         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1315         .evict_flags = &amdgpu_evict_flags,
1316         .move = &amdgpu_bo_move,
1317         .verify_access = &amdgpu_verify_access,
1318         .move_notify = &amdgpu_bo_move_notify,
1319         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1320         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1321         .io_mem_free = &amdgpu_ttm_io_mem_free,
1322         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1323         .access_memory = &amdgpu_ttm_access_memory
1324 };
1325
1326 /*
1327  * Firmware Reservation functions
1328  */
1329 /**
1330  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1331  *
1332  * @adev: amdgpu_device pointer
1333  *
1334  * free fw reserved vram if it has been reserved.
1335  */
1336 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1337 {
1338         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1339                 NULL, &adev->fw_vram_usage.va);
1340 }
1341
1342 /**
1343  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1344  *
1345  * @adev: amdgpu_device pointer
1346  *
1347  * create bo vram reservation from fw.
1348  */
1349 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1350 {
1351         struct ttm_operation_ctx ctx = { false, false };
1352         int r = 0;
1353         int i;
1354         u64 vram_size = adev->gmc.visible_vram_size;
1355         u64 offset = adev->fw_vram_usage.start_offset;
1356         u64 size = adev->fw_vram_usage.size;
1357         struct amdgpu_bo *bo;
1358
1359         adev->fw_vram_usage.va = NULL;
1360         adev->fw_vram_usage.reserved_bo = NULL;
1361
1362         if (adev->fw_vram_usage.size > 0 &&
1363                 adev->fw_vram_usage.size <= vram_size) {
1364
1365                 r = amdgpu_bo_create(adev, adev->fw_vram_usage.size, PAGE_SIZE,
1366                                      AMDGPU_GEM_DOMAIN_VRAM,
1367                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1368                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1369                                      ttm_bo_type_kernel, NULL,
1370                                      &adev->fw_vram_usage.reserved_bo);
1371                 if (r)
1372                         goto error_create;
1373
1374                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1375                 if (r)
1376                         goto error_reserve;
1377
1378                 /* remove the original mem node and create a new one at the
1379                  * request position
1380                  */
1381                 bo = adev->fw_vram_usage.reserved_bo;
1382                 offset = ALIGN(offset, PAGE_SIZE);
1383                 for (i = 0; i < bo->placement.num_placement; ++i) {
1384                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1385                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1386                 }
1387
1388                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1389                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1390                                      &bo->tbo.mem, &ctx);
1391                 if (r)
1392                         goto error_pin;
1393
1394                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1395                         AMDGPU_GEM_DOMAIN_VRAM,
1396                         adev->fw_vram_usage.start_offset,
1397                         (adev->fw_vram_usage.start_offset +
1398                         adev->fw_vram_usage.size), NULL);
1399                 if (r)
1400                         goto error_pin;
1401                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1402                         &adev->fw_vram_usage.va);
1403                 if (r)
1404                         goto error_kmap;
1405
1406                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1407         }
1408         return r;
1409
1410 error_kmap:
1411         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1412 error_pin:
1413         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1414 error_reserve:
1415         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1416 error_create:
1417         adev->fw_vram_usage.va = NULL;
1418         adev->fw_vram_usage.reserved_bo = NULL;
1419         return r;
1420 }
1421
1422 int amdgpu_ttm_init(struct amdgpu_device *adev)
1423 {
1424         uint64_t gtt_size;
1425         int r;
1426         u64 vis_vram_limit;
1427
1428         r = amdgpu_ttm_global_init(adev);
1429         if (r) {
1430                 return r;
1431         }
1432         /* No others user of address space so set it to 0 */
1433         r = ttm_bo_device_init(&adev->mman.bdev,
1434                                adev->mman.bo_global_ref.ref.object,
1435                                &amdgpu_bo_driver,
1436                                adev->ddev->anon_inode->i_mapping,
1437                                DRM_FILE_PAGE_OFFSET,
1438                                adev->need_dma32);
1439         if (r) {
1440                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1441                 return r;
1442         }
1443         adev->mman.initialized = true;
1444
1445         /* We opt to avoid OOM on system pages allocations */
1446         adev->mman.bdev.no_retry = true;
1447
1448         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1449                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1450         if (r) {
1451                 DRM_ERROR("Failed initializing VRAM heap.\n");
1452                 return r;
1453         }
1454
1455         /* Reduce size of CPU-visible VRAM if requested */
1456         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1457         if (amdgpu_vis_vram_limit > 0 &&
1458             vis_vram_limit <= adev->gmc.visible_vram_size)
1459                 adev->gmc.visible_vram_size = vis_vram_limit;
1460
1461         /* Change the size here instead of the init above so only lpfn is affected */
1462         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1463 #ifdef CONFIG_64BIT
1464         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1465                                                 adev->gmc.visible_vram_size);
1466 #endif
1467
1468         /*
1469          *The reserved vram for firmware must be pinned to the specified
1470          *place on the VRAM, so reserve it early.
1471          */
1472         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1473         if (r) {
1474                 return r;
1475         }
1476
1477         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1478                                     AMDGPU_GEM_DOMAIN_VRAM,
1479                                     &adev->stolen_vga_memory,
1480                                     NULL, NULL);
1481         if (r)
1482                 return r;
1483         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1484                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1485
1486         if (amdgpu_gtt_size == -1) {
1487                 struct sysinfo si;
1488
1489                 si_meminfo(&si);
1490                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1491                                adev->gmc.mc_vram_size),
1492                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1493         }
1494         else
1495                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1496         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1497         if (r) {
1498                 DRM_ERROR("Failed initializing GTT heap.\n");
1499                 return r;
1500         }
1501         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1502                  (unsigned)(gtt_size / (1024 * 1024)));
1503
1504         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1505         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1506         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1507         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1508         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1509         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1510         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1511         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1512         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1513         /* GDS Memory */
1514         if (adev->gds.mem.total_size) {
1515                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1516                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1517                 if (r) {
1518                         DRM_ERROR("Failed initializing GDS heap.\n");
1519                         return r;
1520                 }
1521         }
1522
1523         /* GWS */
1524         if (adev->gds.gws.total_size) {
1525                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1526                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1527                 if (r) {
1528                         DRM_ERROR("Failed initializing gws heap.\n");
1529                         return r;
1530                 }
1531         }
1532
1533         /* OA */
1534         if (adev->gds.oa.total_size) {
1535                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1536                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1537                 if (r) {
1538                         DRM_ERROR("Failed initializing oa heap.\n");
1539                         return r;
1540                 }
1541         }
1542
1543         r = amdgpu_ttm_debugfs_init(adev);
1544         if (r) {
1545                 DRM_ERROR("Failed to init debugfs\n");
1546                 return r;
1547         }
1548         return 0;
1549 }
1550
1551 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1552 {
1553         if (!adev->mman.initialized)
1554                 return;
1555
1556         amdgpu_ttm_debugfs_fini(adev);
1557         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1558         amdgpu_ttm_fw_reserve_vram_fini(adev);
1559         if (adev->mman.aper_base_kaddr)
1560                 iounmap(adev->mman.aper_base_kaddr);
1561         adev->mman.aper_base_kaddr = NULL;
1562
1563         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1564         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1565         if (adev->gds.mem.total_size)
1566                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1567         if (adev->gds.gws.total_size)
1568                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1569         if (adev->gds.oa.total_size)
1570                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1571         ttm_bo_device_release(&adev->mman.bdev);
1572         amdgpu_ttm_global_fini(adev);
1573         adev->mman.initialized = false;
1574         DRM_INFO("amdgpu: ttm finalized\n");
1575 }
1576
1577 /**
1578  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1579  *
1580  * @adev: amdgpu_device pointer
1581  * @enable: true when we can use buffer functions.
1582  *
1583  * Enable/disable use of buffer functions during suspend/resume. This should
1584  * only be called at bootup or when userspace isn't running.
1585  */
1586 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1587 {
1588         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1589         uint64_t size;
1590
1591         if (!adev->mman.initialized || adev->in_gpu_reset)
1592                 return;
1593
1594         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1595         if (enable)
1596                 size = adev->gmc.real_vram_size;
1597         else
1598                 size = adev->gmc.visible_vram_size;
1599         man->size = size >> PAGE_SHIFT;
1600         adev->mman.buffer_funcs_enabled = enable;
1601 }
1602
1603 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1604 {
1605         struct drm_file *file_priv;
1606         struct amdgpu_device *adev;
1607
1608         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1609                 return -EINVAL;
1610
1611         file_priv = filp->private_data;
1612         adev = file_priv->minor->dev->dev_private;
1613         if (adev == NULL)
1614                 return -EINVAL;
1615
1616         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1617 }
1618
1619 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1620                              struct ttm_mem_reg *mem, unsigned num_pages,
1621                              uint64_t offset, unsigned window,
1622                              struct amdgpu_ring *ring,
1623                              uint64_t *addr)
1624 {
1625         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1626         struct amdgpu_device *adev = ring->adev;
1627         struct ttm_tt *ttm = bo->ttm;
1628         struct amdgpu_job *job;
1629         unsigned num_dw, num_bytes;
1630         dma_addr_t *dma_address;
1631         struct dma_fence *fence;
1632         uint64_t src_addr, dst_addr;
1633         uint64_t flags;
1634         int r;
1635
1636         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1637                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1638
1639         *addr = adev->gmc.gart_start;
1640         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1641                 AMDGPU_GPU_PAGE_SIZE;
1642
1643         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1644         while (num_dw & 0x7)
1645                 num_dw++;
1646
1647         num_bytes = num_pages * 8;
1648
1649         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1650         if (r)
1651                 return r;
1652
1653         src_addr = num_dw * 4;
1654         src_addr += job->ibs[0].gpu_addr;
1655
1656         dst_addr = adev->gart.table_addr;
1657         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1658         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1659                                 dst_addr, num_bytes);
1660
1661         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1662         WARN_ON(job->ibs[0].length_dw > num_dw);
1663
1664         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1665         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1666         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1667                             &job->ibs[0].ptr[num_dw]);
1668         if (r)
1669                 goto error_free;
1670
1671         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1672                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1673         if (r)
1674                 goto error_free;
1675
1676         dma_fence_put(fence);
1677
1678         return r;
1679
1680 error_free:
1681         amdgpu_job_free(job);
1682         return r;
1683 }
1684
1685 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1686                        uint64_t dst_offset, uint32_t byte_count,
1687                        struct reservation_object *resv,
1688                        struct dma_fence **fence, bool direct_submit,
1689                        bool vm_needs_flush)
1690 {
1691         struct amdgpu_device *adev = ring->adev;
1692         struct amdgpu_job *job;
1693
1694         uint32_t max_bytes;
1695         unsigned num_loops, num_dw;
1696         unsigned i;
1697         int r;
1698
1699         if (direct_submit && !ring->ready) {
1700                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1701                 return -EINVAL;
1702         }
1703
1704         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1705         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1706         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1707
1708         /* for IB padding */
1709         while (num_dw & 0x7)
1710                 num_dw++;
1711
1712         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1713         if (r)
1714                 return r;
1715
1716         job->vm_needs_flush = vm_needs_flush;
1717         if (resv) {
1718                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1719                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1720                                      false);
1721                 if (r) {
1722                         DRM_ERROR("sync failed (%d).\n", r);
1723                         goto error_free;
1724                 }
1725         }
1726
1727         for (i = 0; i < num_loops; i++) {
1728                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1729
1730                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1731                                         dst_offset, cur_size_in_bytes);
1732
1733                 src_offset += cur_size_in_bytes;
1734                 dst_offset += cur_size_in_bytes;
1735                 byte_count -= cur_size_in_bytes;
1736         }
1737
1738         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1739         WARN_ON(job->ibs[0].length_dw > num_dw);
1740         if (direct_submit) {
1741                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1742                                        NULL, fence);
1743                 job->fence = dma_fence_get(*fence);
1744                 if (r)
1745                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1746                 amdgpu_job_free(job);
1747         } else {
1748                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1749                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1750                 if (r)
1751                         goto error_free;
1752         }
1753
1754         return r;
1755
1756 error_free:
1757         amdgpu_job_free(job);
1758         return r;
1759 }
1760
1761 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1762                        uint32_t src_data,
1763                        struct reservation_object *resv,
1764                        struct dma_fence **fence)
1765 {
1766         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1767         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1768         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1769
1770         struct drm_mm_node *mm_node;
1771         unsigned long num_pages;
1772         unsigned int num_loops, num_dw;
1773
1774         struct amdgpu_job *job;
1775         int r;
1776
1777         if (!adev->mman.buffer_funcs_enabled) {
1778                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1779                 return -EINVAL;
1780         }
1781
1782         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1783                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1784                 if (r)
1785                         return r;
1786         }
1787
1788         num_pages = bo->tbo.num_pages;
1789         mm_node = bo->tbo.mem.mm_node;
1790         num_loops = 0;
1791         while (num_pages) {
1792                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1793
1794                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1795                 num_pages -= mm_node->size;
1796                 ++mm_node;
1797         }
1798         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1799
1800         /* for IB padding */
1801         num_dw += 64;
1802
1803         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1804         if (r)
1805                 return r;
1806
1807         if (resv) {
1808                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1809                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
1810                 if (r) {
1811                         DRM_ERROR("sync failed (%d).\n", r);
1812                         goto error_free;
1813                 }
1814         }
1815
1816         num_pages = bo->tbo.num_pages;
1817         mm_node = bo->tbo.mem.mm_node;
1818
1819         while (num_pages) {
1820                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1821                 uint64_t dst_addr;
1822
1823                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1824                 while (byte_count) {
1825                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1826
1827                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1828                                                 dst_addr, cur_size_in_bytes);
1829
1830                         dst_addr += cur_size_in_bytes;
1831                         byte_count -= cur_size_in_bytes;
1832                 }
1833
1834                 num_pages -= mm_node->size;
1835                 ++mm_node;
1836         }
1837
1838         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1839         WARN_ON(job->ibs[0].length_dw > num_dw);
1840         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1841                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1842         if (r)
1843                 goto error_free;
1844
1845         return 0;
1846
1847 error_free:
1848         amdgpu_job_free(job);
1849         return r;
1850 }
1851
1852 #if defined(CONFIG_DEBUG_FS)
1853
1854 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1855 {
1856         struct drm_info_node *node = (struct drm_info_node *)m->private;
1857         unsigned ttm_pl = *(int *)node->info_ent->data;
1858         struct drm_device *dev = node->minor->dev;
1859         struct amdgpu_device *adev = dev->dev_private;
1860         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
1861         struct drm_printer p = drm_seq_file_printer(m);
1862
1863         man->func->debug(man, &p);
1864         return 0;
1865 }
1866
1867 static int ttm_pl_vram = TTM_PL_VRAM;
1868 static int ttm_pl_tt = TTM_PL_TT;
1869
1870 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1871         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1872         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1873         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1874 #ifdef CONFIG_SWIOTLB
1875         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1876 #endif
1877 };
1878
1879 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1880                                     size_t size, loff_t *pos)
1881 {
1882         struct amdgpu_device *adev = file_inode(f)->i_private;
1883         ssize_t result = 0;
1884         int r;
1885
1886         if (size & 0x3 || *pos & 0x3)
1887                 return -EINVAL;
1888
1889         if (*pos >= adev->gmc.mc_vram_size)
1890                 return -ENXIO;
1891
1892         while (size) {
1893                 unsigned long flags;
1894                 uint32_t value;
1895
1896                 if (*pos >= adev->gmc.mc_vram_size)
1897                         return result;
1898
1899                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1900                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1901                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1902                 value = RREG32_NO_KIQ(mmMM_DATA);
1903                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1904
1905                 r = put_user(value, (uint32_t *)buf);
1906                 if (r)
1907                         return r;
1908
1909                 result += 4;
1910                 buf += 4;
1911                 *pos += 4;
1912                 size -= 4;
1913         }
1914
1915         return result;
1916 }
1917
1918 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
1919                                     size_t size, loff_t *pos)
1920 {
1921         struct amdgpu_device *adev = file_inode(f)->i_private;
1922         ssize_t result = 0;
1923         int r;
1924
1925         if (size & 0x3 || *pos & 0x3)
1926                 return -EINVAL;
1927
1928         if (*pos >= adev->gmc.mc_vram_size)
1929                 return -ENXIO;
1930
1931         while (size) {
1932                 unsigned long flags;
1933                 uint32_t value;
1934
1935                 if (*pos >= adev->gmc.mc_vram_size)
1936                         return result;
1937
1938                 r = get_user(value, (uint32_t *)buf);
1939                 if (r)
1940                         return r;
1941
1942                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1943                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1944                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1945                 WREG32_NO_KIQ(mmMM_DATA, value);
1946                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1947
1948                 result += 4;
1949                 buf += 4;
1950                 *pos += 4;
1951                 size -= 4;
1952         }
1953
1954         return result;
1955 }
1956
1957 static const struct file_operations amdgpu_ttm_vram_fops = {
1958         .owner = THIS_MODULE,
1959         .read = amdgpu_ttm_vram_read,
1960         .write = amdgpu_ttm_vram_write,
1961         .llseek = default_llseek,
1962 };
1963
1964 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1965
1966 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1967                                    size_t size, loff_t *pos)
1968 {
1969         struct amdgpu_device *adev = file_inode(f)->i_private;
1970         ssize_t result = 0;
1971         int r;
1972
1973         while (size) {
1974                 loff_t p = *pos / PAGE_SIZE;
1975                 unsigned off = *pos & ~PAGE_MASK;
1976                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1977                 struct page *page;
1978                 void *ptr;
1979
1980                 if (p >= adev->gart.num_cpu_pages)
1981                         return result;
1982
1983                 page = adev->gart.pages[p];
1984                 if (page) {
1985                         ptr = kmap(page);
1986                         ptr += off;
1987
1988                         r = copy_to_user(buf, ptr, cur_size);
1989                         kunmap(adev->gart.pages[p]);
1990                 } else
1991                         r = clear_user(buf, cur_size);
1992
1993                 if (r)
1994                         return -EFAULT;
1995
1996                 result += cur_size;
1997                 buf += cur_size;
1998                 *pos += cur_size;
1999                 size -= cur_size;
2000         }
2001
2002         return result;
2003 }
2004
2005 static const struct file_operations amdgpu_ttm_gtt_fops = {
2006         .owner = THIS_MODULE,
2007         .read = amdgpu_ttm_gtt_read,
2008         .llseek = default_llseek
2009 };
2010
2011 #endif
2012
2013 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2014                                  size_t size, loff_t *pos)
2015 {
2016         struct amdgpu_device *adev = file_inode(f)->i_private;
2017         struct iommu_domain *dom;
2018         ssize_t result = 0;
2019         int r;
2020
2021         dom = iommu_get_domain_for_dev(adev->dev);
2022
2023         while (size) {
2024                 phys_addr_t addr = *pos & PAGE_MASK;
2025                 loff_t off = *pos & ~PAGE_MASK;
2026                 size_t bytes = PAGE_SIZE - off;
2027                 unsigned long pfn;
2028                 struct page *p;
2029                 void *ptr;
2030
2031                 bytes = bytes < size ? bytes : size;
2032
2033                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2034
2035                 pfn = addr >> PAGE_SHIFT;
2036                 if (!pfn_valid(pfn))
2037                         return -EPERM;
2038
2039                 p = pfn_to_page(pfn);
2040                 if (p->mapping != adev->mman.bdev.dev_mapping)
2041                         return -EPERM;
2042
2043                 ptr = kmap(p);
2044                 r = copy_to_user(buf, ptr + off, bytes);
2045                 kunmap(p);
2046                 if (r)
2047                         return -EFAULT;
2048
2049                 size -= bytes;
2050                 *pos += bytes;
2051                 result += bytes;
2052         }
2053
2054         return result;
2055 }
2056
2057 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2058                                  size_t size, loff_t *pos)
2059 {
2060         struct amdgpu_device *adev = file_inode(f)->i_private;
2061         struct iommu_domain *dom;
2062         ssize_t result = 0;
2063         int r;
2064
2065         dom = iommu_get_domain_for_dev(adev->dev);
2066
2067         while (size) {
2068                 phys_addr_t addr = *pos & PAGE_MASK;
2069                 loff_t off = *pos & ~PAGE_MASK;
2070                 size_t bytes = PAGE_SIZE - off;
2071                 unsigned long pfn;
2072                 struct page *p;
2073                 void *ptr;
2074
2075                 bytes = bytes < size ? bytes : size;
2076
2077                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2078
2079                 pfn = addr >> PAGE_SHIFT;
2080                 if (!pfn_valid(pfn))
2081                         return -EPERM;
2082
2083                 p = pfn_to_page(pfn);
2084                 if (p->mapping != adev->mman.bdev.dev_mapping)
2085                         return -EPERM;
2086
2087                 ptr = kmap(p);
2088                 r = copy_from_user(ptr + off, buf, bytes);
2089                 kunmap(p);
2090                 if (r)
2091                         return -EFAULT;
2092
2093                 size -= bytes;
2094                 *pos += bytes;
2095                 result += bytes;
2096         }
2097
2098         return result;
2099 }
2100
2101 static const struct file_operations amdgpu_ttm_iomem_fops = {
2102         .owner = THIS_MODULE,
2103         .read = amdgpu_iomem_read,
2104         .write = amdgpu_iomem_write,
2105         .llseek = default_llseek
2106 };
2107
2108 static const struct {
2109         char *name;
2110         const struct file_operations *fops;
2111         int domain;
2112 } ttm_debugfs_entries[] = {
2113         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2114 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2115         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2116 #endif
2117         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2118 };
2119
2120 #endif
2121
2122 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2123 {
2124 #if defined(CONFIG_DEBUG_FS)
2125         unsigned count;
2126
2127         struct drm_minor *minor = adev->ddev->primary;
2128         struct dentry *ent, *root = minor->debugfs_root;
2129
2130         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2131                 ent = debugfs_create_file(
2132                                 ttm_debugfs_entries[count].name,
2133                                 S_IFREG | S_IRUGO, root,
2134                                 adev,
2135                                 ttm_debugfs_entries[count].fops);
2136                 if (IS_ERR(ent))
2137                         return PTR_ERR(ent);
2138                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2139                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2140                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2141                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2142                 adev->mman.debugfs_entries[count] = ent;
2143         }
2144
2145         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2146
2147 #ifdef CONFIG_SWIOTLB
2148         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2149                 --count;
2150 #endif
2151
2152         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2153 #else
2154         return 0;
2155 #endif
2156 }
2157
2158 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2159 {
2160 #if defined(CONFIG_DEBUG_FS)
2161         unsigned i;
2162
2163         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2164                 debugfs_remove(adev->mman.debugfs_entries[i]);
2165 #endif
2166 }