2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #include "bif/bif_4_1_d.h"
57 #include <linux/pci.h>
58 #include <linux/firmware.h>
59 #include "amdgpu_vf_error.h"
61 #include "amdgpu_amdkfd.h"
62 #include "amdgpu_pm.h"
64 #include "amdgpu_xgmi.h"
65 #include "amdgpu_ras.h"
66 #include "amdgpu_pmu.h"
68 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
69 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
70 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
71 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
72 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
73 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
74 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
75 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
76 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
78 #define AMDGPU_RESUME_MS 2000
80 static const char *amdgpu_asic_name[] = {
112 * DOC: pcie_replay_count
114 * The amdgpu driver provides a sysfs API for reporting the total number
115 * of PCIe replays (NAKs)
116 * The file pcie_replay_count is used for this and returns the total
117 * number of replays as a sum of the NAKs generated and NAKs received
120 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
121 struct device_attribute *attr, char *buf)
123 struct drm_device *ddev = dev_get_drvdata(dev);
124 struct amdgpu_device *adev = ddev->dev_private;
125 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
127 return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
130 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
131 amdgpu_device_get_pcie_replay_count, NULL);
133 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
136 * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
138 * @dev: drm_device pointer
140 * Returns true if the device is a dGPU with HG/PX power control,
141 * otherwise return false.
143 bool amdgpu_device_is_px(struct drm_device *dev)
145 struct amdgpu_device *adev = dev->dev_private;
147 if (adev->flags & AMD_IS_PX)
153 * MMIO register access helper functions.
156 * amdgpu_mm_rreg - read a memory mapped IO register
158 * @adev: amdgpu_device pointer
159 * @reg: dword aligned register offset
160 * @acc_flags: access flags which require special behavior
162 * Returns the 32 bit value from the offset specified.
164 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
169 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
170 return amdgpu_virt_kiq_rreg(adev, reg);
172 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
173 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
177 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
178 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
179 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
180 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
182 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
187 * MMIO register read with bytes helper functions
188 * @offset:bytes offset from MMIO start
193 * amdgpu_mm_rreg8 - read a memory mapped IO register
195 * @adev: amdgpu_device pointer
196 * @offset: byte aligned register offset
198 * Returns the 8 bit value from the offset specified.
200 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
201 if (offset < adev->rmmio_size)
202 return (readb(adev->rmmio + offset));
207 * MMIO register write with bytes helper functions
208 * @offset:bytes offset from MMIO start
209 * @value: the value want to be written to the register
213 * amdgpu_mm_wreg8 - read a memory mapped IO register
215 * @adev: amdgpu_device pointer
216 * @offset: byte aligned register offset
217 * @value: 8 bit value to write
219 * Writes the value specified to the offset specified.
221 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
222 if (offset < adev->rmmio_size)
223 writeb(value, adev->rmmio + offset);
229 * amdgpu_mm_wreg - write to a memory mapped IO register
231 * @adev: amdgpu_device pointer
232 * @reg: dword aligned register offset
233 * @v: 32 bit value to write to the register
234 * @acc_flags: access flags which require special behavior
236 * Writes the value specified to the offset specified.
238 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
241 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
243 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
244 adev->last_mm_index = v;
247 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
248 return amdgpu_virt_kiq_wreg(adev, reg, v);
250 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
251 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
255 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
256 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
257 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
258 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
261 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
267 * amdgpu_mm_rreg64 - read a 64 bit memory mapped IO register
269 * @adev: amdgpu_device pointer
270 * @reg: dword aligned register offset
272 * Returns the 64 bit value from the offset specified.
274 uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
276 if ((reg * 4) < adev->rmmio_size)
277 return atomic64_read((atomic64_t *)(adev->rmmio + (reg * 4)));
283 * amdgpu_mm_wreg64 - write to a 64 bit memory mapped IO register
285 * @adev: amdgpu_device pointer
286 * @reg: dword aligned register offset
287 * @v: 64 bit value to write to the register
289 * Writes the value specified to the offset specified.
291 void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
293 if ((reg * 4) < adev->rmmio_size)
294 atomic64_set((atomic64_t *)(adev->rmmio + (reg * 4)), v);
300 * amdgpu_io_rreg - read an IO register
302 * @adev: amdgpu_device pointer
303 * @reg: dword aligned register offset
305 * Returns the 32 bit value from the offset specified.
307 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
309 if ((reg * 4) < adev->rio_mem_size)
310 return ioread32(adev->rio_mem + (reg * 4));
312 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
313 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
318 * amdgpu_io_wreg - write to an IO register
320 * @adev: amdgpu_device pointer
321 * @reg: dword aligned register offset
322 * @v: 32 bit value to write to the register
324 * Writes the value specified to the offset specified.
326 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
328 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
329 adev->last_mm_index = v;
332 if ((reg * 4) < adev->rio_mem_size)
333 iowrite32(v, adev->rio_mem + (reg * 4));
335 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
336 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
339 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
345 * amdgpu_mm_rdoorbell - read a doorbell dword
347 * @adev: amdgpu_device pointer
348 * @index: doorbell index
350 * Returns the value in the doorbell aperture at the
351 * requested doorbell index (CIK).
353 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
355 if (index < adev->doorbell.num_doorbells) {
356 return readl(adev->doorbell.ptr + index);
358 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
364 * amdgpu_mm_wdoorbell - write a doorbell dword
366 * @adev: amdgpu_device pointer
367 * @index: doorbell index
370 * Writes @v to the doorbell aperture at the
371 * requested doorbell index (CIK).
373 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
375 if (index < adev->doorbell.num_doorbells) {
376 writel(v, adev->doorbell.ptr + index);
378 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
383 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
385 * @adev: amdgpu_device pointer
386 * @index: doorbell index
388 * Returns the value in the doorbell aperture at the
389 * requested doorbell index (VEGA10+).
391 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
393 if (index < adev->doorbell.num_doorbells) {
394 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
396 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
402 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
404 * @adev: amdgpu_device pointer
405 * @index: doorbell index
408 * Writes @v to the doorbell aperture at the
409 * requested doorbell index (VEGA10+).
411 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
413 if (index < adev->doorbell.num_doorbells) {
414 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
416 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
421 * amdgpu_invalid_rreg - dummy reg read function
423 * @adev: amdgpu device pointer
424 * @reg: offset of register
426 * Dummy register read function. Used for register blocks
427 * that certain asics don't have (all asics).
428 * Returns the value in the register.
430 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
432 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
438 * amdgpu_invalid_wreg - dummy reg write function
440 * @adev: amdgpu device pointer
441 * @reg: offset of register
442 * @v: value to write to the register
444 * Dummy register read function. Used for register blocks
445 * that certain asics don't have (all asics).
447 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
449 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
455 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
457 * @adev: amdgpu device pointer
458 * @reg: offset of register
460 * Dummy register read function. Used for register blocks
461 * that certain asics don't have (all asics).
462 * Returns the value in the register.
464 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
466 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
472 * amdgpu_invalid_wreg64 - dummy reg write function
474 * @adev: amdgpu device pointer
475 * @reg: offset of register
476 * @v: value to write to the register
478 * Dummy register read function. Used for register blocks
479 * that certain asics don't have (all asics).
481 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
483 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
489 * amdgpu_block_invalid_rreg - dummy reg read function
491 * @adev: amdgpu device pointer
492 * @block: offset of instance
493 * @reg: offset of register
495 * Dummy register read function. Used for register blocks
496 * that certain asics don't have (all asics).
497 * Returns the value in the register.
499 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
500 uint32_t block, uint32_t reg)
502 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
509 * amdgpu_block_invalid_wreg - dummy reg write function
511 * @adev: amdgpu device pointer
512 * @block: offset of instance
513 * @reg: offset of register
514 * @v: value to write to the register
516 * Dummy register read function. Used for register blocks
517 * that certain asics don't have (all asics).
519 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
521 uint32_t reg, uint32_t v)
523 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
529 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
531 * @adev: amdgpu device pointer
533 * Allocates a scratch page of VRAM for use by various things in the
536 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
538 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
540 &adev->vram_scratch.robj,
541 &adev->vram_scratch.gpu_addr,
542 (void **)&adev->vram_scratch.ptr);
546 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
548 * @adev: amdgpu device pointer
550 * Frees the VRAM scratch page.
552 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
554 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
558 * amdgpu_device_program_register_sequence - program an array of registers.
560 * @adev: amdgpu_device pointer
561 * @registers: pointer to the register array
562 * @array_size: size of the register array
564 * Programs an array or registers with and and or masks.
565 * This is a helper for setting golden registers.
567 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
568 const u32 *registers,
569 const u32 array_size)
571 u32 tmp, reg, and_mask, or_mask;
577 for (i = 0; i < array_size; i +=3) {
578 reg = registers[i + 0];
579 and_mask = registers[i + 1];
580 or_mask = registers[i + 2];
582 if (and_mask == 0xffffffff) {
587 if (adev->family >= AMDGPU_FAMILY_AI)
588 tmp |= (or_mask & and_mask);
597 * amdgpu_device_pci_config_reset - reset the GPU
599 * @adev: amdgpu_device pointer
601 * Resets the GPU using the pci config reset sequence.
602 * Only applicable to asics prior to vega10.
604 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
606 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
610 * GPU doorbell aperture helpers function.
613 * amdgpu_device_doorbell_init - Init doorbell driver information.
615 * @adev: amdgpu_device pointer
617 * Init doorbell driver information (CIK)
618 * Returns 0 on success, error on failure.
620 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
623 /* No doorbell on SI hardware generation */
624 if (adev->asic_type < CHIP_BONAIRE) {
625 adev->doorbell.base = 0;
626 adev->doorbell.size = 0;
627 adev->doorbell.num_doorbells = 0;
628 adev->doorbell.ptr = NULL;
632 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
635 amdgpu_asic_init_doorbell_index(adev);
637 /* doorbell bar mapping */
638 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
639 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
641 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
642 adev->doorbell_index.max_assignment+1);
643 if (adev->doorbell.num_doorbells == 0)
646 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
647 * paging queue doorbell use the second page. The
648 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
649 * doorbells are in the first page. So with paging queue enabled,
650 * the max num_doorbells should + 1 page (0x400 in dword)
652 if (adev->asic_type >= CHIP_VEGA10)
653 adev->doorbell.num_doorbells += 0x400;
655 adev->doorbell.ptr = ioremap(adev->doorbell.base,
656 adev->doorbell.num_doorbells *
658 if (adev->doorbell.ptr == NULL)
665 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
667 * @adev: amdgpu_device pointer
669 * Tear down doorbell driver information (CIK)
671 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
673 iounmap(adev->doorbell.ptr);
674 adev->doorbell.ptr = NULL;
680 * amdgpu_device_wb_*()
681 * Writeback is the method by which the GPU updates special pages in memory
682 * with the status of certain GPU events (fences, ring pointers,etc.).
686 * amdgpu_device_wb_fini - Disable Writeback and free memory
688 * @adev: amdgpu_device pointer
690 * Disables Writeback and frees the Writeback memory (all asics).
691 * Used at driver shutdown.
693 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
695 if (adev->wb.wb_obj) {
696 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
698 (void **)&adev->wb.wb);
699 adev->wb.wb_obj = NULL;
704 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
706 * @adev: amdgpu_device pointer
708 * Initializes writeback and allocates writeback memory (all asics).
709 * Used at driver startup.
710 * Returns 0 on success or an -error on failure.
712 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
716 if (adev->wb.wb_obj == NULL) {
717 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
718 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
719 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
720 &adev->wb.wb_obj, &adev->wb.gpu_addr,
721 (void **)&adev->wb.wb);
723 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
727 adev->wb.num_wb = AMDGPU_MAX_WB;
728 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
730 /* clear wb memory */
731 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
738 * amdgpu_device_wb_get - Allocate a wb entry
740 * @adev: amdgpu_device pointer
743 * Allocate a wb slot for use by the driver (all asics).
744 * Returns 0 on success or -EINVAL on failure.
746 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
748 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
750 if (offset < adev->wb.num_wb) {
751 __set_bit(offset, adev->wb.used);
752 *wb = offset << 3; /* convert to dw offset */
760 * amdgpu_device_wb_free - Free a wb entry
762 * @adev: amdgpu_device pointer
765 * Free a wb slot allocated for use by the driver (all asics)
767 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
770 if (wb < adev->wb.num_wb)
771 __clear_bit(wb, adev->wb.used);
775 * amdgpu_device_resize_fb_bar - try to resize FB BAR
777 * @adev: amdgpu_device pointer
779 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
780 * to fail, but if any of the BARs is not accessible after the size we abort
781 * driver loading by returning -ENODEV.
783 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
785 u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
786 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
787 struct pci_bus *root;
788 struct resource *res;
794 if (amdgpu_sriov_vf(adev))
797 /* Check if the root BUS has 64bit memory resources */
798 root = adev->pdev->bus;
802 pci_bus_for_each_resource(root, res, i) {
803 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
804 res->start > 0x100000000ull)
808 /* Trying to resize is pointless without a root hub window above 4GB */
812 /* Disable memory decoding while we change the BAR addresses and size */
813 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
814 pci_write_config_word(adev->pdev, PCI_COMMAND,
815 cmd & ~PCI_COMMAND_MEMORY);
817 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
818 amdgpu_device_doorbell_fini(adev);
819 if (adev->asic_type >= CHIP_BONAIRE)
820 pci_release_resource(adev->pdev, 2);
822 pci_release_resource(adev->pdev, 0);
824 r = pci_resize_resource(adev->pdev, 0, rbar_size);
826 DRM_INFO("Not enough PCI address space for a large BAR.");
827 else if (r && r != -ENOTSUPP)
828 DRM_ERROR("Problem resizing BAR0 (%d).", r);
830 pci_assign_unassigned_bus_resources(adev->pdev->bus);
832 /* When the doorbell or fb BAR isn't available we have no chance of
835 r = amdgpu_device_doorbell_init(adev);
836 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
839 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
845 * GPU helpers function.
848 * amdgpu_device_need_post - check if the hw need post or not
850 * @adev: amdgpu_device pointer
852 * Check if the asic has been initialized (all asics) at driver startup
853 * or post is needed if hw reset is performed.
854 * Returns true if need or false if not.
856 bool amdgpu_device_need_post(struct amdgpu_device *adev)
860 if (amdgpu_sriov_vf(adev))
863 if (amdgpu_passthrough(adev)) {
864 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
865 * some old smc fw still need driver do vPost otherwise gpu hang, while
866 * those smc fw version above 22.15 doesn't have this flaw, so we force
867 * vpost executed for smc version below 22.15
869 if (adev->asic_type == CHIP_FIJI) {
872 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
873 /* force vPost if error occured */
877 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
878 if (fw_ver < 0x00160e00)
883 if (adev->has_hw_reset) {
884 adev->has_hw_reset = false;
888 /* bios scratch used on CIK+ */
889 if (adev->asic_type >= CHIP_BONAIRE)
890 return amdgpu_atombios_scratch_need_asic_init(adev);
892 /* check MEM_SIZE for older asics */
893 reg = amdgpu_asic_get_config_memsize(adev);
895 if ((reg != 0) && (reg != 0xffffffff))
901 /* if we get transitioned to only one device, take VGA back */
903 * amdgpu_device_vga_set_decode - enable/disable vga decode
905 * @cookie: amdgpu_device pointer
906 * @state: enable/disable vga decode
908 * Enable/disable vga decode (all asics).
909 * Returns VGA resource flags.
911 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
913 struct amdgpu_device *adev = cookie;
914 amdgpu_asic_set_vga_state(adev, state);
916 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
917 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
919 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
923 * amdgpu_device_check_block_size - validate the vm block size
925 * @adev: amdgpu_device pointer
927 * Validates the vm block size specified via module parameter.
928 * The vm block size defines number of bits in page table versus page directory,
929 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
930 * page table and the remaining bits are in the page directory.
932 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
934 /* defines number of bits in page table versus page directory,
935 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
936 * page table and the remaining bits are in the page directory */
937 if (amdgpu_vm_block_size == -1)
940 if (amdgpu_vm_block_size < 9) {
941 dev_warn(adev->dev, "VM page table size (%d) too small\n",
942 amdgpu_vm_block_size);
943 amdgpu_vm_block_size = -1;
948 * amdgpu_device_check_vm_size - validate the vm size
950 * @adev: amdgpu_device pointer
952 * Validates the vm size in GB specified via module parameter.
953 * The VM size is the size of the GPU virtual memory space in GB.
955 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
957 /* no need to check the default value */
958 if (amdgpu_vm_size == -1)
961 if (amdgpu_vm_size < 1) {
962 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
968 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
971 bool is_os_64 = (sizeof(void *) == 8) ? true : false;
972 uint64_t total_memory;
973 uint64_t dram_size_seven_GB = 0x1B8000000;
974 uint64_t dram_size_three_GB = 0xB8000000;
976 if (amdgpu_smu_memory_pool_size == 0)
980 DRM_WARN("Not 64-bit OS, feature not supported\n");
984 total_memory = (uint64_t)si.totalram * si.mem_unit;
986 if ((amdgpu_smu_memory_pool_size == 1) ||
987 (amdgpu_smu_memory_pool_size == 2)) {
988 if (total_memory < dram_size_three_GB)
990 } else if ((amdgpu_smu_memory_pool_size == 4) ||
991 (amdgpu_smu_memory_pool_size == 8)) {
992 if (total_memory < dram_size_seven_GB)
995 DRM_WARN("Smu memory pool size not supported\n");
998 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1003 DRM_WARN("No enough system memory\n");
1005 adev->pm.smu_prv_buffer_size = 0;
1009 * amdgpu_device_check_arguments - validate module params
1011 * @adev: amdgpu_device pointer
1013 * Validates certain module parameters and updates
1014 * the associated values used by the driver (all asics).
1016 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1020 if (amdgpu_sched_jobs < 4) {
1021 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1023 amdgpu_sched_jobs = 4;
1024 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1025 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1027 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1030 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1031 /* gart size must be greater or equal to 32M */
1032 dev_warn(adev->dev, "gart size (%d) too small\n",
1034 amdgpu_gart_size = -1;
1037 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1038 /* gtt size must be greater or equal to 32M */
1039 dev_warn(adev->dev, "gtt size (%d) too small\n",
1041 amdgpu_gtt_size = -1;
1044 /* valid range is between 4 and 9 inclusive */
1045 if (amdgpu_vm_fragment_size != -1 &&
1046 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1047 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1048 amdgpu_vm_fragment_size = -1;
1051 amdgpu_device_check_smu_prv_buffer_size(adev);
1053 amdgpu_device_check_vm_size(adev);
1055 amdgpu_device_check_block_size(adev);
1057 ret = amdgpu_device_get_job_timeout_settings(adev);
1059 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
1063 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1069 * amdgpu_switcheroo_set_state - set switcheroo state
1071 * @pdev: pci dev pointer
1072 * @state: vga_switcheroo state
1074 * Callback for the switcheroo driver. Suspends or resumes the
1075 * the asics before or after it is powered up using ACPI methods.
1077 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1079 struct drm_device *dev = pci_get_drvdata(pdev);
1081 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1084 if (state == VGA_SWITCHEROO_ON) {
1085 pr_info("amdgpu: switched on\n");
1086 /* don't suspend or resume card normally */
1087 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1089 amdgpu_device_resume(dev, true, true);
1091 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1092 drm_kms_helper_poll_enable(dev);
1094 pr_info("amdgpu: switched off\n");
1095 drm_kms_helper_poll_disable(dev);
1096 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1097 amdgpu_device_suspend(dev, true, true);
1098 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1103 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1105 * @pdev: pci dev pointer
1107 * Callback for the switcheroo driver. Check of the switcheroo
1108 * state can be changed.
1109 * Returns true if the state can be changed, false if not.
1111 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1113 struct drm_device *dev = pci_get_drvdata(pdev);
1116 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1117 * locking inversion with the driver load path. And the access here is
1118 * completely racy anyway. So don't bother with locking for now.
1120 return dev->open_count == 0;
1123 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1124 .set_gpu_state = amdgpu_switcheroo_set_state,
1126 .can_switch = amdgpu_switcheroo_can_switch,
1130 * amdgpu_device_ip_set_clockgating_state - set the CG state
1132 * @dev: amdgpu_device pointer
1133 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1134 * @state: clockgating state (gate or ungate)
1136 * Sets the requested clockgating state for all instances of
1137 * the hardware IP specified.
1138 * Returns the error code from the last instance.
1140 int amdgpu_device_ip_set_clockgating_state(void *dev,
1141 enum amd_ip_block_type block_type,
1142 enum amd_clockgating_state state)
1144 struct amdgpu_device *adev = dev;
1147 for (i = 0; i < adev->num_ip_blocks; i++) {
1148 if (!adev->ip_blocks[i].status.valid)
1150 if (adev->ip_blocks[i].version->type != block_type)
1152 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1154 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1155 (void *)adev, state);
1157 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1158 adev->ip_blocks[i].version->funcs->name, r);
1164 * amdgpu_device_ip_set_powergating_state - set the PG state
1166 * @dev: amdgpu_device pointer
1167 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1168 * @state: powergating state (gate or ungate)
1170 * Sets the requested powergating state for all instances of
1171 * the hardware IP specified.
1172 * Returns the error code from the last instance.
1174 int amdgpu_device_ip_set_powergating_state(void *dev,
1175 enum amd_ip_block_type block_type,
1176 enum amd_powergating_state state)
1178 struct amdgpu_device *adev = dev;
1181 for (i = 0; i < adev->num_ip_blocks; i++) {
1182 if (!adev->ip_blocks[i].status.valid)
1184 if (adev->ip_blocks[i].version->type != block_type)
1186 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1188 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1189 (void *)adev, state);
1191 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1192 adev->ip_blocks[i].version->funcs->name, r);
1198 * amdgpu_device_ip_get_clockgating_state - get the CG state
1200 * @adev: amdgpu_device pointer
1201 * @flags: clockgating feature flags
1203 * Walks the list of IPs on the device and updates the clockgating
1204 * flags for each IP.
1205 * Updates @flags with the feature flags for each hardware IP where
1206 * clockgating is enabled.
1208 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1213 for (i = 0; i < adev->num_ip_blocks; i++) {
1214 if (!adev->ip_blocks[i].status.valid)
1216 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1217 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1222 * amdgpu_device_ip_wait_for_idle - wait for idle
1224 * @adev: amdgpu_device pointer
1225 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1227 * Waits for the request hardware IP to be idle.
1228 * Returns 0 for success or a negative error code on failure.
1230 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1231 enum amd_ip_block_type block_type)
1235 for (i = 0; i < adev->num_ip_blocks; i++) {
1236 if (!adev->ip_blocks[i].status.valid)
1238 if (adev->ip_blocks[i].version->type == block_type) {
1239 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1250 * amdgpu_device_ip_is_idle - is the hardware IP idle
1252 * @adev: amdgpu_device pointer
1253 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1255 * Check if the hardware IP is idle or not.
1256 * Returns true if it the IP is idle, false if not.
1258 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1259 enum amd_ip_block_type block_type)
1263 for (i = 0; i < adev->num_ip_blocks; i++) {
1264 if (!adev->ip_blocks[i].status.valid)
1266 if (adev->ip_blocks[i].version->type == block_type)
1267 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1274 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1276 * @adev: amdgpu_device pointer
1277 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1279 * Returns a pointer to the hardware IP block structure
1280 * if it exists for the asic, otherwise NULL.
1282 struct amdgpu_ip_block *
1283 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1284 enum amd_ip_block_type type)
1288 for (i = 0; i < adev->num_ip_blocks; i++)
1289 if (adev->ip_blocks[i].version->type == type)
1290 return &adev->ip_blocks[i];
1296 * amdgpu_device_ip_block_version_cmp
1298 * @adev: amdgpu_device pointer
1299 * @type: enum amd_ip_block_type
1300 * @major: major version
1301 * @minor: minor version
1303 * return 0 if equal or greater
1304 * return 1 if smaller or the ip_block doesn't exist
1306 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1307 enum amd_ip_block_type type,
1308 u32 major, u32 minor)
1310 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1312 if (ip_block && ((ip_block->version->major > major) ||
1313 ((ip_block->version->major == major) &&
1314 (ip_block->version->minor >= minor))))
1321 * amdgpu_device_ip_block_add
1323 * @adev: amdgpu_device pointer
1324 * @ip_block_version: pointer to the IP to add
1326 * Adds the IP block driver information to the collection of IPs
1329 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1330 const struct amdgpu_ip_block_version *ip_block_version)
1332 if (!ip_block_version)
1335 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1336 ip_block_version->funcs->name);
1338 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1344 * amdgpu_device_enable_virtual_display - enable virtual display feature
1346 * @adev: amdgpu_device pointer
1348 * Enabled the virtual display feature if the user has enabled it via
1349 * the module parameter virtual_display. This feature provides a virtual
1350 * display hardware on headless boards or in virtualized environments.
1351 * This function parses and validates the configuration string specified by
1352 * the user and configues the virtual display configuration (number of
1353 * virtual connectors, crtcs, etc.) specified.
1355 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1357 adev->enable_virtual_display = false;
1359 if (amdgpu_virtual_display) {
1360 struct drm_device *ddev = adev->ddev;
1361 const char *pci_address_name = pci_name(ddev->pdev);
1362 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1364 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1365 pciaddstr_tmp = pciaddstr;
1366 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1367 pciaddname = strsep(&pciaddname_tmp, ",");
1368 if (!strcmp("all", pciaddname)
1369 || !strcmp(pci_address_name, pciaddname)) {
1373 adev->enable_virtual_display = true;
1376 res = kstrtol(pciaddname_tmp, 10,
1384 adev->mode_info.num_crtc = num_crtc;
1386 adev->mode_info.num_crtc = 1;
1392 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1393 amdgpu_virtual_display, pci_address_name,
1394 adev->enable_virtual_display, adev->mode_info.num_crtc);
1401 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1403 * @adev: amdgpu_device pointer
1405 * Parses the asic configuration parameters specified in the gpu info
1406 * firmware and makes them availale to the driver for use in configuring
1408 * Returns 0 on success, -EINVAL on failure.
1410 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1412 const char *chip_name;
1415 const struct gpu_info_firmware_header_v1_0 *hdr;
1417 adev->firmware.gpu_info_fw = NULL;
1419 switch (adev->asic_type) {
1423 case CHIP_POLARIS10:
1424 case CHIP_POLARIS11:
1425 case CHIP_POLARIS12:
1429 #ifdef CONFIG_DRM_AMDGPU_SI
1436 #ifdef CONFIG_DRM_AMDGPU_CIK
1447 chip_name = "vega10";
1450 chip_name = "vega12";
1453 if (adev->rev_id >= 8)
1454 chip_name = "raven2";
1455 else if (adev->pdev->device == 0x15d8)
1456 chip_name = "picasso";
1458 chip_name = "raven";
1461 chip_name = "arcturus";
1464 chip_name = "navi10";
1467 chip_name = "navi14";
1470 chip_name = "navi12";
1474 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1475 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1478 "Failed to load gpu_info firmware \"%s\"\n",
1482 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1485 "Failed to validate gpu_info firmware \"%s\"\n",
1490 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1491 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1493 switch (hdr->version_major) {
1496 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1497 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1498 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1500 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1501 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1502 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1503 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1504 adev->gfx.config.max_texture_channel_caches =
1505 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1506 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1507 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1508 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1509 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1510 adev->gfx.config.double_offchip_lds_buf =
1511 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1512 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1513 adev->gfx.cu_info.max_waves_per_simd =
1514 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1515 adev->gfx.cu_info.max_scratch_slots_per_cu =
1516 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1517 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1518 if (hdr->version_minor >= 1) {
1519 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1520 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1521 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1522 adev->gfx.config.num_sc_per_sh =
1523 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1524 adev->gfx.config.num_packer_per_sc =
1525 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1527 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
1528 if (hdr->version_minor == 2) {
1529 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1530 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1531 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1532 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1539 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1548 * amdgpu_device_ip_early_init - run early init for hardware IPs
1550 * @adev: amdgpu_device pointer
1552 * Early initialization pass for hardware IPs. The hardware IPs that make
1553 * up each asic are discovered each IP's early_init callback is run. This
1554 * is the first stage in initializing the asic.
1555 * Returns 0 on success, negative error code on failure.
1557 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1561 amdgpu_device_enable_virtual_display(adev);
1563 switch (adev->asic_type) {
1567 case CHIP_POLARIS10:
1568 case CHIP_POLARIS11:
1569 case CHIP_POLARIS12:
1573 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1574 adev->family = AMDGPU_FAMILY_CZ;
1576 adev->family = AMDGPU_FAMILY_VI;
1578 r = vi_set_ip_blocks(adev);
1582 #ifdef CONFIG_DRM_AMDGPU_SI
1588 adev->family = AMDGPU_FAMILY_SI;
1589 r = si_set_ip_blocks(adev);
1594 #ifdef CONFIG_DRM_AMDGPU_CIK
1600 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1601 adev->family = AMDGPU_FAMILY_CI;
1603 adev->family = AMDGPU_FAMILY_KV;
1605 r = cik_set_ip_blocks(adev);
1615 if (adev->asic_type == CHIP_RAVEN)
1616 adev->family = AMDGPU_FAMILY_RV;
1618 adev->family = AMDGPU_FAMILY_AI;
1620 r = soc15_set_ip_blocks(adev);
1627 adev->family = AMDGPU_FAMILY_NV;
1629 r = nv_set_ip_blocks(adev);
1634 /* FIXME: not supported yet */
1638 r = amdgpu_device_parse_gpu_info_fw(adev);
1642 amdgpu_amdkfd_device_probe(adev);
1644 if (amdgpu_sriov_vf(adev)) {
1645 r = amdgpu_virt_request_full_gpu(adev, true);
1650 adev->pm.pp_feature = amdgpu_pp_feature_mask;
1651 if (amdgpu_sriov_vf(adev))
1652 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1654 for (i = 0; i < adev->num_ip_blocks; i++) {
1655 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1656 DRM_ERROR("disabled ip block: %d <%s>\n",
1657 i, adev->ip_blocks[i].version->funcs->name);
1658 adev->ip_blocks[i].status.valid = false;
1660 if (adev->ip_blocks[i].version->funcs->early_init) {
1661 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1663 adev->ip_blocks[i].status.valid = false;
1665 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1666 adev->ip_blocks[i].version->funcs->name, r);
1669 adev->ip_blocks[i].status.valid = true;
1672 adev->ip_blocks[i].status.valid = true;
1675 /* get the vbios after the asic_funcs are set up */
1676 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
1678 if (!amdgpu_get_bios(adev))
1681 r = amdgpu_atombios_init(adev);
1683 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1684 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1690 adev->cg_flags &= amdgpu_cg_mask;
1691 adev->pg_flags &= amdgpu_pg_mask;
1696 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1700 for (i = 0; i < adev->num_ip_blocks; i++) {
1701 if (!adev->ip_blocks[i].status.sw)
1703 if (adev->ip_blocks[i].status.hw)
1705 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1706 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
1707 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1708 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1710 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1711 adev->ip_blocks[i].version->funcs->name, r);
1714 adev->ip_blocks[i].status.hw = true;
1721 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1725 for (i = 0; i < adev->num_ip_blocks; i++) {
1726 if (!adev->ip_blocks[i].status.sw)
1728 if (adev->ip_blocks[i].status.hw)
1730 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1732 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1733 adev->ip_blocks[i].version->funcs->name, r);
1736 adev->ip_blocks[i].status.hw = true;
1742 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1746 uint32_t smu_version;
1748 if (adev->asic_type >= CHIP_VEGA10) {
1749 for (i = 0; i < adev->num_ip_blocks; i++) {
1750 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
1753 /* no need to do the fw loading again if already done*/
1754 if (adev->ip_blocks[i].status.hw == true)
1757 if (adev->in_gpu_reset || adev->in_suspend) {
1758 r = adev->ip_blocks[i].version->funcs->resume(adev);
1760 DRM_ERROR("resume of IP block <%s> failed %d\n",
1761 adev->ip_blocks[i].version->funcs->name, r);
1765 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1767 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1768 adev->ip_blocks[i].version->funcs->name, r);
1773 adev->ip_blocks[i].status.hw = true;
1778 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
1784 * amdgpu_device_ip_init - run init for hardware IPs
1786 * @adev: amdgpu_device pointer
1788 * Main initialization pass for hardware IPs. The list of all the hardware
1789 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1790 * are run. sw_init initializes the software state associated with each IP
1791 * and hw_init initializes the hardware associated with each IP.
1792 * Returns 0 on success, negative error code on failure.
1794 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1798 r = amdgpu_ras_init(adev);
1802 for (i = 0; i < adev->num_ip_blocks; i++) {
1803 if (!adev->ip_blocks[i].status.valid)
1805 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1807 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1808 adev->ip_blocks[i].version->funcs->name, r);
1811 adev->ip_blocks[i].status.sw = true;
1813 /* need to do gmc hw init early so we can allocate gpu mem */
1814 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1815 r = amdgpu_device_vram_scratch_init(adev);
1817 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1820 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1822 DRM_ERROR("hw_init %d failed %d\n", i, r);
1825 r = amdgpu_device_wb_init(adev);
1827 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1830 adev->ip_blocks[i].status.hw = true;
1832 /* right after GMC hw init, we create CSA */
1833 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1834 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1835 AMDGPU_GEM_DOMAIN_VRAM,
1838 DRM_ERROR("allocate CSA failed %d\n", r);
1845 r = amdgpu_ib_pool_init(adev);
1847 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1848 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1852 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1856 r = amdgpu_device_ip_hw_init_phase1(adev);
1860 r = amdgpu_device_fw_loading(adev);
1864 r = amdgpu_device_ip_hw_init_phase2(adev);
1868 if (adev->gmc.xgmi.num_physical_nodes > 1)
1869 amdgpu_xgmi_add_device(adev);
1870 amdgpu_amdkfd_device_init(adev);
1873 if (amdgpu_sriov_vf(adev)) {
1875 amdgpu_virt_init_data_exchange(adev);
1876 amdgpu_virt_release_full_gpu(adev, true);
1883 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1885 * @adev: amdgpu_device pointer
1887 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
1888 * this function before a GPU reset. If the value is retained after a
1889 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
1891 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1893 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1897 * amdgpu_device_check_vram_lost - check if vram is valid
1899 * @adev: amdgpu_device pointer
1901 * Checks the reset magic value written to the gart pointer in VRAM.
1902 * The driver calls this after a GPU reset to see if the contents of
1903 * VRAM is lost or now.
1904 * returns true if vram is lost, false if not.
1906 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1908 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1909 AMDGPU_RESET_MAGIC_NUM);
1913 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1915 * @adev: amdgpu_device pointer
1917 * The list of all the hardware IPs that make up the asic is walked and the
1918 * set_clockgating_state callbacks are run.
1919 * Late initialization pass enabling clockgating for hardware IPs.
1920 * Fini or suspend, pass disabling clockgating for hardware IPs.
1921 * Returns 0 on success, negative error code on failure.
1924 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1925 enum amd_clockgating_state state)
1929 if (amdgpu_emu_mode == 1)
1932 for (j = 0; j < adev->num_ip_blocks; j++) {
1933 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1934 if (!adev->ip_blocks[i].status.late_initialized)
1936 /* skip CG for VCE/UVD, it's handled specially */
1937 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1938 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1939 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1940 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1941 /* enable clockgating to save power */
1942 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1945 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1946 adev->ip_blocks[i].version->funcs->name, r);
1955 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1959 if (amdgpu_emu_mode == 1)
1962 for (j = 0; j < adev->num_ip_blocks; j++) {
1963 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1964 if (!adev->ip_blocks[i].status.late_initialized)
1966 /* skip CG for VCE/UVD, it's handled specially */
1967 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1968 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1969 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1970 adev->ip_blocks[i].version->funcs->set_powergating_state) {
1971 /* enable powergating to save power */
1972 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1975 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1976 adev->ip_blocks[i].version->funcs->name, r);
1984 static int amdgpu_device_enable_mgpu_fan_boost(void)
1986 struct amdgpu_gpu_instance *gpu_ins;
1987 struct amdgpu_device *adev;
1990 mutex_lock(&mgpu_info.mutex);
1993 * MGPU fan boost feature should be enabled
1994 * only when there are two or more dGPUs in
1997 if (mgpu_info.num_dgpu < 2)
2000 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2001 gpu_ins = &(mgpu_info.gpu_ins[i]);
2002 adev = gpu_ins->adev;
2003 if (!(adev->flags & AMD_IS_APU) &&
2004 !gpu_ins->mgpu_fan_enabled &&
2005 adev->powerplay.pp_funcs &&
2006 adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
2007 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2011 gpu_ins->mgpu_fan_enabled = 1;
2016 mutex_unlock(&mgpu_info.mutex);
2022 * amdgpu_device_ip_late_init - run late init for hardware IPs
2024 * @adev: amdgpu_device pointer
2026 * Late initialization pass for hardware IPs. The list of all the hardware
2027 * IPs that make up the asic is walked and the late_init callbacks are run.
2028 * late_init covers any special initialization that an IP requires
2029 * after all of the have been initialized or something that needs to happen
2030 * late in the init process.
2031 * Returns 0 on success, negative error code on failure.
2033 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2037 for (i = 0; i < adev->num_ip_blocks; i++) {
2038 if (!adev->ip_blocks[i].status.hw)
2040 if (adev->ip_blocks[i].version->funcs->late_init) {
2041 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2043 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2044 adev->ip_blocks[i].version->funcs->name, r);
2048 adev->ip_blocks[i].status.late_initialized = true;
2051 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2052 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2054 amdgpu_device_fill_reset_magic(adev);
2056 r = amdgpu_device_enable_mgpu_fan_boost();
2058 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2060 /* set to low pstate by default */
2061 amdgpu_xgmi_set_pstate(adev, 0);
2067 * amdgpu_device_ip_fini - run fini for hardware IPs
2069 * @adev: amdgpu_device pointer
2071 * Main teardown pass for hardware IPs. The list of all the hardware
2072 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2073 * are run. hw_fini tears down the hardware associated with each IP
2074 * and sw_fini tears down any software state associated with each IP.
2075 * Returns 0 on success, negative error code on failure.
2077 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2081 amdgpu_ras_pre_fini(adev);
2083 if (adev->gmc.xgmi.num_physical_nodes > 1)
2084 amdgpu_xgmi_remove_device(adev);
2086 amdgpu_amdkfd_device_fini(adev);
2088 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2089 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2091 /* need to disable SMC first */
2092 for (i = 0; i < adev->num_ip_blocks; i++) {
2093 if (!adev->ip_blocks[i].status.hw)
2095 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2096 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2097 /* XXX handle errors */
2099 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2100 adev->ip_blocks[i].version->funcs->name, r);
2102 adev->ip_blocks[i].status.hw = false;
2107 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2108 if (!adev->ip_blocks[i].status.hw)
2111 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2112 /* XXX handle errors */
2114 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2115 adev->ip_blocks[i].version->funcs->name, r);
2118 adev->ip_blocks[i].status.hw = false;
2122 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2123 if (!adev->ip_blocks[i].status.sw)
2126 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2127 amdgpu_ucode_free_bo(adev);
2128 amdgpu_free_static_csa(&adev->virt.csa_obj);
2129 amdgpu_device_wb_fini(adev);
2130 amdgpu_device_vram_scratch_fini(adev);
2131 amdgpu_ib_pool_fini(adev);
2134 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2135 /* XXX handle errors */
2137 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2138 adev->ip_blocks[i].version->funcs->name, r);
2140 adev->ip_blocks[i].status.sw = false;
2141 adev->ip_blocks[i].status.valid = false;
2144 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2145 if (!adev->ip_blocks[i].status.late_initialized)
2147 if (adev->ip_blocks[i].version->funcs->late_fini)
2148 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2149 adev->ip_blocks[i].status.late_initialized = false;
2152 amdgpu_ras_fini(adev);
2154 if (amdgpu_sriov_vf(adev))
2155 if (amdgpu_virt_release_full_gpu(adev, false))
2156 DRM_ERROR("failed to release exclusive mode on fini\n");
2162 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2164 * @work: work_struct.
2166 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2168 struct amdgpu_device *adev =
2169 container_of(work, struct amdgpu_device, delayed_init_work.work);
2172 r = amdgpu_ib_ring_tests(adev);
2174 DRM_ERROR("ib ring test failed (%d).\n", r);
2177 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2179 struct amdgpu_device *adev =
2180 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2182 mutex_lock(&adev->gfx.gfx_off_mutex);
2183 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2184 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2185 adev->gfx.gfx_off_state = true;
2187 mutex_unlock(&adev->gfx.gfx_off_mutex);
2191 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2193 * @adev: amdgpu_device pointer
2195 * Main suspend function for hardware IPs. The list of all the hardware
2196 * IPs that make up the asic is walked, clockgating is disabled and the
2197 * suspend callbacks are run. suspend puts the hardware and software state
2198 * in each IP into a state suitable for suspend.
2199 * Returns 0 on success, negative error code on failure.
2201 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2205 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2206 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2208 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2209 if (!adev->ip_blocks[i].status.valid)
2211 /* displays are handled separately */
2212 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2213 /* XXX handle errors */
2214 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2215 /* XXX handle errors */
2217 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2218 adev->ip_blocks[i].version->funcs->name, r);
2221 adev->ip_blocks[i].status.hw = false;
2229 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2231 * @adev: amdgpu_device pointer
2233 * Main suspend function for hardware IPs. The list of all the hardware
2234 * IPs that make up the asic is walked, clockgating is disabled and the
2235 * suspend callbacks are run. suspend puts the hardware and software state
2236 * in each IP into a state suitable for suspend.
2237 * Returns 0 on success, negative error code on failure.
2239 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2243 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2244 if (!adev->ip_blocks[i].status.valid)
2246 /* displays are handled in phase1 */
2247 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2249 /* XXX handle errors */
2250 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2251 /* XXX handle errors */
2253 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2254 adev->ip_blocks[i].version->funcs->name, r);
2256 adev->ip_blocks[i].status.hw = false;
2257 /* handle putting the SMC in the appropriate state */
2258 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2259 if (is_support_sw_smu(adev)) {
2261 } else if (adev->powerplay.pp_funcs &&
2262 adev->powerplay.pp_funcs->set_mp1_state) {
2263 r = adev->powerplay.pp_funcs->set_mp1_state(
2264 adev->powerplay.pp_handle,
2267 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2268 adev->mp1_state, r);
2274 adev->ip_blocks[i].status.hw = false;
2281 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2283 * @adev: amdgpu_device pointer
2285 * Main suspend function for hardware IPs. The list of all the hardware
2286 * IPs that make up the asic is walked, clockgating is disabled and the
2287 * suspend callbacks are run. suspend puts the hardware and software state
2288 * in each IP into a state suitable for suspend.
2289 * Returns 0 on success, negative error code on failure.
2291 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2295 if (amdgpu_sriov_vf(adev))
2296 amdgpu_virt_request_full_gpu(adev, false);
2298 r = amdgpu_device_ip_suspend_phase1(adev);
2301 r = amdgpu_device_ip_suspend_phase2(adev);
2303 if (amdgpu_sriov_vf(adev))
2304 amdgpu_virt_release_full_gpu(adev, false);
2309 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2313 static enum amd_ip_block_type ip_order[] = {
2314 AMD_IP_BLOCK_TYPE_GMC,
2315 AMD_IP_BLOCK_TYPE_COMMON,
2316 AMD_IP_BLOCK_TYPE_PSP,
2317 AMD_IP_BLOCK_TYPE_IH,
2320 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2322 struct amdgpu_ip_block *block;
2324 for (j = 0; j < adev->num_ip_blocks; j++) {
2325 block = &adev->ip_blocks[j];
2327 block->status.hw = false;
2328 if (block->version->type != ip_order[i] ||
2329 !block->status.valid)
2332 r = block->version->funcs->hw_init(adev);
2333 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2336 block->status.hw = true;
2343 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2347 static enum amd_ip_block_type ip_order[] = {
2348 AMD_IP_BLOCK_TYPE_SMC,
2349 AMD_IP_BLOCK_TYPE_DCE,
2350 AMD_IP_BLOCK_TYPE_GFX,
2351 AMD_IP_BLOCK_TYPE_SDMA,
2352 AMD_IP_BLOCK_TYPE_UVD,
2353 AMD_IP_BLOCK_TYPE_VCE
2356 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2358 struct amdgpu_ip_block *block;
2360 for (j = 0; j < adev->num_ip_blocks; j++) {
2361 block = &adev->ip_blocks[j];
2363 if (block->version->type != ip_order[i] ||
2364 !block->status.valid ||
2368 r = block->version->funcs->hw_init(adev);
2369 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2372 block->status.hw = true;
2380 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2382 * @adev: amdgpu_device pointer
2384 * First resume function for hardware IPs. The list of all the hardware
2385 * IPs that make up the asic is walked and the resume callbacks are run for
2386 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2387 * after a suspend and updates the software state as necessary. This
2388 * function is also used for restoring the GPU after a GPU reset.
2389 * Returns 0 on success, negative error code on failure.
2391 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2395 for (i = 0; i < adev->num_ip_blocks; i++) {
2396 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2398 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2399 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2400 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2402 r = adev->ip_blocks[i].version->funcs->resume(adev);
2404 DRM_ERROR("resume of IP block <%s> failed %d\n",
2405 adev->ip_blocks[i].version->funcs->name, r);
2408 adev->ip_blocks[i].status.hw = true;
2416 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2418 * @adev: amdgpu_device pointer
2420 * First resume function for hardware IPs. The list of all the hardware
2421 * IPs that make up the asic is walked and the resume callbacks are run for
2422 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2423 * functional state after a suspend and updates the software state as
2424 * necessary. This function is also used for restoring the GPU after a GPU
2426 * Returns 0 on success, negative error code on failure.
2428 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2432 for (i = 0; i < adev->num_ip_blocks; i++) {
2433 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2435 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2436 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2437 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2438 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2440 r = adev->ip_blocks[i].version->funcs->resume(adev);
2442 DRM_ERROR("resume of IP block <%s> failed %d\n",
2443 adev->ip_blocks[i].version->funcs->name, r);
2446 adev->ip_blocks[i].status.hw = true;
2453 * amdgpu_device_ip_resume - run resume for hardware IPs
2455 * @adev: amdgpu_device pointer
2457 * Main resume function for hardware IPs. The hardware IPs
2458 * are split into two resume functions because they are
2459 * are also used in in recovering from a GPU reset and some additional
2460 * steps need to be take between them. In this case (S3/S4) they are
2462 * Returns 0 on success, negative error code on failure.
2464 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2468 r = amdgpu_device_ip_resume_phase1(adev);
2472 r = amdgpu_device_fw_loading(adev);
2476 r = amdgpu_device_ip_resume_phase2(adev);
2482 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2484 * @adev: amdgpu_device pointer
2486 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2488 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2490 if (amdgpu_sriov_vf(adev)) {
2491 if (adev->is_atom_fw) {
2492 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2493 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2495 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2496 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2499 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2500 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2505 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2507 * @asic_type: AMD asic type
2509 * Check if there is DC (new modesetting infrastructre) support for an asic.
2510 * returns true if DC has support, false if not.
2512 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2514 switch (asic_type) {
2515 #if defined(CONFIG_DRM_AMD_DC)
2521 * We have systems in the wild with these ASICs that require
2522 * LVDS and VGA support which is not supported with DC.
2524 * Fallback to the non-DC driver here by default so as not to
2525 * cause regressions.
2527 return amdgpu_dc > 0;
2531 case CHIP_POLARIS10:
2532 case CHIP_POLARIS11:
2533 case CHIP_POLARIS12:
2540 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2543 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2548 return amdgpu_dc != 0;
2556 * amdgpu_device_has_dc_support - check if dc is supported
2558 * @adev: amdgpu_device_pointer
2560 * Returns true for supported, false for not supported
2562 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2564 if (amdgpu_sriov_vf(adev))
2567 return amdgpu_device_asic_has_dc_support(adev->asic_type);
2571 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2573 struct amdgpu_device *adev =
2574 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2576 adev->asic_reset_res = amdgpu_asic_reset(adev);
2577 if (adev->asic_reset_res)
2578 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2579 adev->asic_reset_res, adev->ddev->unique);
2584 * amdgpu_device_init - initialize the driver
2586 * @adev: amdgpu_device pointer
2587 * @ddev: drm dev pointer
2588 * @pdev: pci dev pointer
2589 * @flags: driver flags
2591 * Initializes the driver info and hw (all asics).
2592 * Returns 0 for success or an error on failure.
2593 * Called at driver startup.
2595 int amdgpu_device_init(struct amdgpu_device *adev,
2596 struct drm_device *ddev,
2597 struct pci_dev *pdev,
2601 bool runtime = false;
2604 adev->shutdown = false;
2605 adev->dev = &pdev->dev;
2608 adev->flags = flags;
2609 adev->asic_type = flags & AMD_ASIC_MASK;
2610 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2611 if (amdgpu_emu_mode == 1)
2612 adev->usec_timeout *= 2;
2613 adev->gmc.gart_size = 512 * 1024 * 1024;
2614 adev->accel_working = false;
2615 adev->num_rings = 0;
2616 adev->mman.buffer_funcs = NULL;
2617 adev->mman.buffer_funcs_ring = NULL;
2618 adev->vm_manager.vm_pte_funcs = NULL;
2619 adev->vm_manager.vm_pte_num_rqs = 0;
2620 adev->gmc.gmc_funcs = NULL;
2621 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2622 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2624 adev->smc_rreg = &amdgpu_invalid_rreg;
2625 adev->smc_wreg = &amdgpu_invalid_wreg;
2626 adev->pcie_rreg = &amdgpu_invalid_rreg;
2627 adev->pcie_wreg = &amdgpu_invalid_wreg;
2628 adev->pciep_rreg = &amdgpu_invalid_rreg;
2629 adev->pciep_wreg = &amdgpu_invalid_wreg;
2630 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
2631 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
2632 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2633 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2634 adev->didt_rreg = &amdgpu_invalid_rreg;
2635 adev->didt_wreg = &amdgpu_invalid_wreg;
2636 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2637 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2638 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2639 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2641 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2642 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2643 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2645 /* mutex initialization are all done here so we
2646 * can recall function without having locking issues */
2647 atomic_set(&adev->irq.ih.lock, 0);
2648 mutex_init(&adev->firmware.mutex);
2649 mutex_init(&adev->pm.mutex);
2650 mutex_init(&adev->gfx.gpu_clock_mutex);
2651 mutex_init(&adev->srbm_mutex);
2652 mutex_init(&adev->gfx.pipe_reserve_mutex);
2653 mutex_init(&adev->gfx.gfx_off_mutex);
2654 mutex_init(&adev->grbm_idx_mutex);
2655 mutex_init(&adev->mn_lock);
2656 mutex_init(&adev->virt.vf_errors.lock);
2657 hash_init(adev->mn_hash);
2658 mutex_init(&adev->lock_reset);
2659 mutex_init(&adev->virt.dpm_mutex);
2660 mutex_init(&adev->psp.mutex);
2662 r = amdgpu_device_check_arguments(adev);
2666 spin_lock_init(&adev->mmio_idx_lock);
2667 spin_lock_init(&adev->smc_idx_lock);
2668 spin_lock_init(&adev->pcie_idx_lock);
2669 spin_lock_init(&adev->uvd_ctx_idx_lock);
2670 spin_lock_init(&adev->didt_idx_lock);
2671 spin_lock_init(&adev->gc_cac_idx_lock);
2672 spin_lock_init(&adev->se_cac_idx_lock);
2673 spin_lock_init(&adev->audio_endpt_idx_lock);
2674 spin_lock_init(&adev->mm_stats.lock);
2676 INIT_LIST_HEAD(&adev->shadow_list);
2677 mutex_init(&adev->shadow_list_lock);
2679 INIT_LIST_HEAD(&adev->ring_lru_list);
2680 spin_lock_init(&adev->ring_lru_list_lock);
2682 INIT_DELAYED_WORK(&adev->delayed_init_work,
2683 amdgpu_device_delayed_init_work_handler);
2684 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2685 amdgpu_device_delay_enable_gfx_off);
2687 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2689 adev->gfx.gfx_off_req_count = 1;
2690 adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2692 /* Registers mapping */
2693 /* TODO: block userspace mapping of io register */
2694 if (adev->asic_type >= CHIP_BONAIRE) {
2695 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2696 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2698 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2699 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2702 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2703 if (adev->rmmio == NULL) {
2706 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2707 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2709 /* io port mapping */
2710 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2711 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2712 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2713 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2717 if (adev->rio_mem == NULL)
2718 DRM_INFO("PCI I/O BAR is not found.\n");
2720 /* enable PCIE atomic ops */
2721 r = pci_enable_atomic_ops_to_root(adev->pdev,
2722 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
2723 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
2725 adev->have_atomics_support = false;
2726 DRM_INFO("PCIE atomic ops is not supported\n");
2728 adev->have_atomics_support = true;
2731 amdgpu_device_get_pcie_info(adev);
2734 DRM_INFO("MCBP is enabled\n");
2736 if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
2737 adev->enable_mes = true;
2739 if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) {
2740 r = amdgpu_discovery_init(adev);
2742 dev_err(adev->dev, "amdgpu_discovery_init failed\n");
2747 /* early init functions */
2748 r = amdgpu_device_ip_early_init(adev);
2752 /* doorbell bar mapping and doorbell index init*/
2753 amdgpu_device_doorbell_init(adev);
2755 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2756 /* this will fail for cards that aren't VGA class devices, just
2758 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2760 if (amdgpu_device_is_px(ddev))
2762 if (!pci_is_thunderbolt_attached(adev->pdev))
2763 vga_switcheroo_register_client(adev->pdev,
2764 &amdgpu_switcheroo_ops, runtime);
2766 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2768 if (amdgpu_emu_mode == 1) {
2769 /* post the asic on emulation mode */
2770 emu_soc_asic_init(adev);
2771 goto fence_driver_init;
2774 /* detect if we are with an SRIOV vbios */
2775 amdgpu_device_detect_sriov_bios(adev);
2777 /* check if we need to reset the asic
2778 * E.g., driver was not cleanly unloaded previously, etc.
2780 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2781 r = amdgpu_asic_reset(adev);
2783 dev_err(adev->dev, "asic reset on init failed\n");
2788 /* Post card if necessary */
2789 if (amdgpu_device_need_post(adev)) {
2791 dev_err(adev->dev, "no vBIOS found\n");
2795 DRM_INFO("GPU posting now...\n");
2796 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2798 dev_err(adev->dev, "gpu post error!\n");
2803 if (adev->is_atom_fw) {
2804 /* Initialize clocks */
2805 r = amdgpu_atomfirmware_get_clock_info(adev);
2807 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2808 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2812 /* Initialize clocks */
2813 r = amdgpu_atombios_get_clock_info(adev);
2815 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2816 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2819 /* init i2c buses */
2820 if (!amdgpu_device_has_dc_support(adev))
2821 amdgpu_atombios_i2c_init(adev);
2826 r = amdgpu_fence_driver_init(adev);
2828 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2829 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2833 /* init the mode config */
2834 drm_mode_config_init(adev->ddev);
2836 r = amdgpu_device_ip_init(adev);
2838 /* failed in exclusive mode due to timeout */
2839 if (amdgpu_sriov_vf(adev) &&
2840 !amdgpu_sriov_runtime(adev) &&
2841 amdgpu_virt_mmio_blocked(adev) &&
2842 !amdgpu_virt_wait_reset(adev)) {
2843 dev_err(adev->dev, "VF exclusive mode timeout\n");
2844 /* Don't send request since VF is inactive. */
2845 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2846 adev->virt.ops = NULL;
2850 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2851 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2852 if (amdgpu_virt_request_full_gpu(adev, false))
2853 amdgpu_virt_release_full_gpu(adev, false);
2857 adev->accel_working = true;
2859 amdgpu_vm_check_compute_bug(adev);
2861 /* Initialize the buffer migration limit. */
2862 if (amdgpu_moverate >= 0)
2863 max_MBps = amdgpu_moverate;
2865 max_MBps = 8; /* Allow 8 MB/s. */
2866 /* Get a log2 for easy divisions. */
2867 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2869 amdgpu_fbdev_init(adev);
2871 if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
2872 amdgpu_pm_virt_sysfs_init(adev);
2874 r = amdgpu_pm_sysfs_init(adev);
2876 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2878 r = amdgpu_ucode_sysfs_init(adev);
2880 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
2882 r = amdgpu_debugfs_gem_init(adev);
2884 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2886 r = amdgpu_debugfs_regs_init(adev);
2888 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2890 r = amdgpu_debugfs_firmware_init(adev);
2892 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2894 r = amdgpu_debugfs_init(adev);
2896 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2898 if ((amdgpu_testing & 1)) {
2899 if (adev->accel_working)
2900 amdgpu_test_moves(adev);
2902 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2904 if (amdgpu_benchmarking) {
2905 if (adev->accel_working)
2906 amdgpu_benchmark(adev, amdgpu_benchmarking);
2908 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2911 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2912 * explicit gating rather than handling it automatically.
2914 r = amdgpu_device_ip_late_init(adev);
2916 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2917 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2922 amdgpu_ras_resume(adev);
2924 queue_delayed_work(system_wq, &adev->delayed_init_work,
2925 msecs_to_jiffies(AMDGPU_RESUME_MS));
2927 r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
2929 dev_err(adev->dev, "Could not create pcie_replay_count");
2933 if (IS_ENABLED(CONFIG_PERF_EVENTS))
2934 r = amdgpu_pmu_init(adev);
2936 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
2941 amdgpu_vf_error_trans_all(adev);
2943 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2949 * amdgpu_device_fini - tear down the driver
2951 * @adev: amdgpu_device pointer
2953 * Tear down the driver info (all asics).
2954 * Called at driver shutdown.
2956 void amdgpu_device_fini(struct amdgpu_device *adev)
2960 DRM_INFO("amdgpu: finishing device.\n");
2961 adev->shutdown = true;
2962 /* disable all interrupts */
2963 amdgpu_irq_disable_all(adev);
2964 if (adev->mode_info.mode_config_initialized){
2965 if (!amdgpu_device_has_dc_support(adev))
2966 drm_helper_force_disable_all(adev->ddev);
2968 drm_atomic_helper_shutdown(adev->ddev);
2970 amdgpu_fence_driver_fini(adev);
2971 amdgpu_pm_sysfs_fini(adev);
2972 amdgpu_fbdev_fini(adev);
2973 r = amdgpu_device_ip_fini(adev);
2974 if (adev->firmware.gpu_info_fw) {
2975 release_firmware(adev->firmware.gpu_info_fw);
2976 adev->firmware.gpu_info_fw = NULL;
2978 adev->accel_working = false;
2979 cancel_delayed_work_sync(&adev->delayed_init_work);
2980 /* free i2c buses */
2981 if (!amdgpu_device_has_dc_support(adev))
2982 amdgpu_i2c_fini(adev);
2984 if (amdgpu_emu_mode != 1)
2985 amdgpu_atombios_fini(adev);
2989 if (!pci_is_thunderbolt_attached(adev->pdev))
2990 vga_switcheroo_unregister_client(adev->pdev);
2991 if (adev->flags & AMD_IS_PX)
2992 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2993 vga_client_register(adev->pdev, NULL, NULL, NULL);
2995 pci_iounmap(adev->pdev, adev->rio_mem);
2996 adev->rio_mem = NULL;
2997 iounmap(adev->rmmio);
2999 amdgpu_device_doorbell_fini(adev);
3000 if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
3001 amdgpu_pm_virt_sysfs_fini(adev);
3003 amdgpu_debugfs_regs_cleanup(adev);
3004 device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
3005 amdgpu_ucode_sysfs_fini(adev);
3006 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3007 amdgpu_pmu_fini(adev);
3008 amdgpu_debugfs_preempt_cleanup(adev);
3009 if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
3010 amdgpu_discovery_fini(adev);
3018 * amdgpu_device_suspend - initiate device suspend
3020 * @dev: drm dev pointer
3021 * @suspend: suspend state
3022 * @fbcon : notify the fbdev of suspend
3024 * Puts the hw in the suspend state (all asics).
3025 * Returns 0 for success or an error on failure.
3026 * Called at driver suspend.
3028 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
3030 struct amdgpu_device *adev;
3031 struct drm_crtc *crtc;
3032 struct drm_connector *connector;
3035 if (dev == NULL || dev->dev_private == NULL) {
3039 adev = dev->dev_private;
3041 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3044 adev->in_suspend = true;
3045 drm_kms_helper_poll_disable(dev);
3048 amdgpu_fbdev_set_suspend(adev, 1);
3050 cancel_delayed_work_sync(&adev->delayed_init_work);
3052 if (!amdgpu_device_has_dc_support(adev)) {
3053 /* turn off display hw */
3054 drm_modeset_lock_all(dev);
3055 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3056 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
3058 drm_modeset_unlock_all(dev);
3059 /* unpin the front buffers and cursors */
3060 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3061 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3062 struct drm_framebuffer *fb = crtc->primary->fb;
3063 struct amdgpu_bo *robj;
3065 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3066 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3067 r = amdgpu_bo_reserve(aobj, true);
3069 amdgpu_bo_unpin(aobj);
3070 amdgpu_bo_unreserve(aobj);
3074 if (fb == NULL || fb->obj[0] == NULL) {
3077 robj = gem_to_amdgpu_bo(fb->obj[0]);
3078 /* don't unpin kernel fb objects */
3079 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3080 r = amdgpu_bo_reserve(robj, true);
3082 amdgpu_bo_unpin(robj);
3083 amdgpu_bo_unreserve(robj);
3089 amdgpu_amdkfd_suspend(adev);
3091 amdgpu_ras_suspend(adev);
3093 r = amdgpu_device_ip_suspend_phase1(adev);
3095 /* evict vram memory */
3096 amdgpu_bo_evict_vram(adev);
3098 amdgpu_fence_driver_suspend(adev);
3100 r = amdgpu_device_ip_suspend_phase2(adev);
3102 /* evict remaining vram memory
3103 * This second call to evict vram is to evict the gart page table
3106 amdgpu_bo_evict_vram(adev);
3108 pci_save_state(dev->pdev);
3110 /* Shut down the device */
3111 pci_disable_device(dev->pdev);
3112 pci_set_power_state(dev->pdev, PCI_D3hot);
3114 r = amdgpu_asic_reset(adev);
3116 DRM_ERROR("amdgpu asic reset failed\n");
3123 * amdgpu_device_resume - initiate device resume
3125 * @dev: drm dev pointer
3126 * @resume: resume state
3127 * @fbcon : notify the fbdev of resume
3129 * Bring the hw back to operating state (all asics).
3130 * Returns 0 for success or an error on failure.
3131 * Called at driver resume.
3133 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
3135 struct drm_connector *connector;
3136 struct amdgpu_device *adev = dev->dev_private;
3137 struct drm_crtc *crtc;
3140 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3144 pci_set_power_state(dev->pdev, PCI_D0);
3145 pci_restore_state(dev->pdev);
3146 r = pci_enable_device(dev->pdev);
3152 if (amdgpu_device_need_post(adev)) {
3153 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
3155 DRM_ERROR("amdgpu asic init failed\n");
3158 r = amdgpu_device_ip_resume(adev);
3160 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
3163 amdgpu_fence_driver_resume(adev);
3166 r = amdgpu_device_ip_late_init(adev);
3170 queue_delayed_work(system_wq, &adev->delayed_init_work,
3171 msecs_to_jiffies(AMDGPU_RESUME_MS));
3173 if (!amdgpu_device_has_dc_support(adev)) {
3175 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3176 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3178 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3179 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3180 r = amdgpu_bo_reserve(aobj, true);
3182 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3184 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
3185 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3186 amdgpu_bo_unreserve(aobj);
3191 r = amdgpu_amdkfd_resume(adev);
3195 /* Make sure IB tests flushed */
3196 flush_delayed_work(&adev->delayed_init_work);
3198 /* blat the mode back in */
3200 if (!amdgpu_device_has_dc_support(adev)) {
3202 drm_helper_resume_force_mode(dev);
3204 /* turn on display hw */
3205 drm_modeset_lock_all(dev);
3206 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3207 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
3209 drm_modeset_unlock_all(dev);
3211 amdgpu_fbdev_set_suspend(adev, 0);
3214 drm_kms_helper_poll_enable(dev);
3216 amdgpu_ras_resume(adev);
3219 * Most of the connector probing functions try to acquire runtime pm
3220 * refs to ensure that the GPU is powered on when connector polling is
3221 * performed. Since we're calling this from a runtime PM callback,
3222 * trying to acquire rpm refs will cause us to deadlock.
3224 * Since we're guaranteed to be holding the rpm lock, it's safe to
3225 * temporarily disable the rpm helpers so this doesn't deadlock us.
3228 dev->dev->power.disable_depth++;
3230 if (!amdgpu_device_has_dc_support(adev))
3231 drm_helper_hpd_irq_event(dev);
3233 drm_kms_helper_hotplug_event(dev);
3235 dev->dev->power.disable_depth--;
3237 adev->in_suspend = false;
3243 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3245 * @adev: amdgpu_device pointer
3247 * The list of all the hardware IPs that make up the asic is walked and
3248 * the check_soft_reset callbacks are run. check_soft_reset determines
3249 * if the asic is still hung or not.
3250 * Returns true if any of the IPs are still in a hung state, false if not.
3252 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3255 bool asic_hang = false;
3257 if (amdgpu_sriov_vf(adev))
3260 if (amdgpu_asic_need_full_reset(adev))
3263 for (i = 0; i < adev->num_ip_blocks; i++) {
3264 if (!adev->ip_blocks[i].status.valid)
3266 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3267 adev->ip_blocks[i].status.hang =
3268 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3269 if (adev->ip_blocks[i].status.hang) {
3270 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3278 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3280 * @adev: amdgpu_device pointer
3282 * The list of all the hardware IPs that make up the asic is walked and the
3283 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3284 * handles any IP specific hardware or software state changes that are
3285 * necessary for a soft reset to succeed.
3286 * Returns 0 on success, negative error code on failure.
3288 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3292 for (i = 0; i < adev->num_ip_blocks; i++) {
3293 if (!adev->ip_blocks[i].status.valid)
3295 if (adev->ip_blocks[i].status.hang &&
3296 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3297 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3307 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3309 * @adev: amdgpu_device pointer
3311 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3312 * reset is necessary to recover.
3313 * Returns true if a full asic reset is required, false if not.
3315 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3319 if (amdgpu_asic_need_full_reset(adev))
3322 for (i = 0; i < adev->num_ip_blocks; i++) {
3323 if (!adev->ip_blocks[i].status.valid)
3325 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3326 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3327 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3328 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3329 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3330 if (adev->ip_blocks[i].status.hang) {
3331 DRM_INFO("Some block need full reset!\n");
3340 * amdgpu_device_ip_soft_reset - do a soft reset
3342 * @adev: amdgpu_device pointer
3344 * The list of all the hardware IPs that make up the asic is walked and the
3345 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3346 * IP specific hardware or software state changes that are necessary to soft
3348 * Returns 0 on success, negative error code on failure.
3350 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3354 for (i = 0; i < adev->num_ip_blocks; i++) {
3355 if (!adev->ip_blocks[i].status.valid)
3357 if (adev->ip_blocks[i].status.hang &&
3358 adev->ip_blocks[i].version->funcs->soft_reset) {
3359 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3369 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3371 * @adev: amdgpu_device pointer
3373 * The list of all the hardware IPs that make up the asic is walked and the
3374 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
3375 * handles any IP specific hardware or software state changes that are
3376 * necessary after the IP has been soft reset.
3377 * Returns 0 on success, negative error code on failure.
3379 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3383 for (i = 0; i < adev->num_ip_blocks; i++) {
3384 if (!adev->ip_blocks[i].status.valid)
3386 if (adev->ip_blocks[i].status.hang &&
3387 adev->ip_blocks[i].version->funcs->post_soft_reset)
3388 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3397 * amdgpu_device_recover_vram - Recover some VRAM contents
3399 * @adev: amdgpu_device pointer
3401 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
3402 * restore things like GPUVM page tables after a GPU reset where
3403 * the contents of VRAM might be lost.
3406 * 0 on success, negative error code on failure.
3408 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3410 struct dma_fence *fence = NULL, *next = NULL;
3411 struct amdgpu_bo *shadow;
3414 if (amdgpu_sriov_runtime(adev))
3415 tmo = msecs_to_jiffies(8000);
3417 tmo = msecs_to_jiffies(100);
3419 DRM_INFO("recover vram bo from shadow start\n");
3420 mutex_lock(&adev->shadow_list_lock);
3421 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3423 /* No need to recover an evicted BO */
3424 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3425 shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3426 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3429 r = amdgpu_bo_restore_shadow(shadow, &next);
3434 tmo = dma_fence_wait_timeout(fence, false, tmo);
3435 dma_fence_put(fence);
3440 } else if (tmo < 0) {
3448 mutex_unlock(&adev->shadow_list_lock);
3451 tmo = dma_fence_wait_timeout(fence, false, tmo);
3452 dma_fence_put(fence);
3454 if (r < 0 || tmo <= 0) {
3455 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3459 DRM_INFO("recover vram bo from shadow done\n");
3465 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3467 * @adev: amdgpu device pointer
3468 * @from_hypervisor: request from hypervisor
3470 * do VF FLR and reinitialize Asic
3471 * return 0 means succeeded otherwise failed
3473 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3474 bool from_hypervisor)
3478 if (from_hypervisor)
3479 r = amdgpu_virt_request_full_gpu(adev, true);
3481 r = amdgpu_virt_reset_gpu(adev);
3485 amdgpu_amdkfd_pre_reset(adev);
3487 /* Resume IP prior to SMC */
3488 r = amdgpu_device_ip_reinit_early_sriov(adev);
3492 /* we need recover gart prior to run SMC/CP/SDMA resume */
3493 amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3495 r = amdgpu_device_fw_loading(adev);
3499 /* now we are okay to resume SMC/CP/SDMA */
3500 r = amdgpu_device_ip_reinit_late_sriov(adev);
3504 amdgpu_irq_gpu_reset_resume_helper(adev);
3505 r = amdgpu_ib_ring_tests(adev);
3506 amdgpu_amdkfd_post_reset(adev);
3509 amdgpu_virt_init_data_exchange(adev);
3510 amdgpu_virt_release_full_gpu(adev, true);
3511 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3512 atomic_inc(&adev->vram_lost_counter);
3513 r = amdgpu_device_recover_vram(adev);
3520 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3522 * @adev: amdgpu device pointer
3524 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3527 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3529 if (!amdgpu_device_ip_check_soft_reset(adev)) {
3530 DRM_INFO("Timeout, but no hardware hang detected.\n");
3534 if (amdgpu_gpu_recovery == 0)
3537 if (amdgpu_sriov_vf(adev))
3540 if (amdgpu_gpu_recovery == -1) {
3541 switch (adev->asic_type) {
3547 case CHIP_POLARIS10:
3548 case CHIP_POLARIS11:
3549 case CHIP_POLARIS12:
3563 DRM_INFO("GPU recovery disabled.\n");
3568 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3569 struct amdgpu_job *job,
3570 bool *need_full_reset_arg)
3573 bool need_full_reset = *need_full_reset_arg;
3575 /* block all schedulers and reset given job's ring */
3576 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3577 struct amdgpu_ring *ring = adev->rings[i];
3579 if (!ring || !ring->sched.thread)
3582 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3583 amdgpu_fence_driver_force_completion(ring);
3587 drm_sched_increase_karma(&job->base);
3589 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
3590 if (!amdgpu_sriov_vf(adev)) {
3592 if (!need_full_reset)
3593 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3595 if (!need_full_reset) {
3596 amdgpu_device_ip_pre_soft_reset(adev);
3597 r = amdgpu_device_ip_soft_reset(adev);
3598 amdgpu_device_ip_post_soft_reset(adev);
3599 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3600 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3601 need_full_reset = true;
3605 if (need_full_reset)
3606 r = amdgpu_device_ip_suspend(adev);
3608 *need_full_reset_arg = need_full_reset;
3614 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3615 struct list_head *device_list_handle,
3616 bool *need_full_reset_arg)
3618 struct amdgpu_device *tmp_adev = NULL;
3619 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3623 * ASIC reset has to be done on all HGMI hive nodes ASAP
3624 * to allow proper links negotiation in FW (within 1 sec)
3626 if (need_full_reset) {
3627 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3628 /* For XGMI run all resets in parallel to speed up the process */
3629 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3630 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3633 r = amdgpu_asic_reset(tmp_adev);
3636 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3637 r, tmp_adev->ddev->unique);
3642 /* For XGMI wait for all PSP resets to complete before proceed */
3644 list_for_each_entry(tmp_adev, device_list_handle,
3646 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3647 flush_work(&tmp_adev->xgmi_reset_work);
3648 r = tmp_adev->asic_reset_res;
3654 list_for_each_entry(tmp_adev, device_list_handle,
3656 amdgpu_ras_reserve_bad_pages(tmp_adev);
3662 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3663 if (need_full_reset) {
3665 if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3666 DRM_WARN("asic atom init failed!");
3669 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3670 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3674 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3676 DRM_INFO("VRAM is lost due to GPU reset!\n");
3677 atomic_inc(&tmp_adev->vram_lost_counter);
3680 r = amdgpu_gtt_mgr_recover(
3681 &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3685 r = amdgpu_device_fw_loading(tmp_adev);
3689 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3694 amdgpu_device_fill_reset_magic(tmp_adev);
3697 * Add this ASIC as tracked as reset was already
3698 * complete successfully.
3700 amdgpu_register_gpu_instance(tmp_adev);
3702 r = amdgpu_device_ip_late_init(tmp_adev);
3707 amdgpu_ras_resume(tmp_adev);
3709 /* Update PSP FW topology after reset */
3710 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3711 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3718 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3719 r = amdgpu_ib_ring_tests(tmp_adev);
3721 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3722 r = amdgpu_device_ip_suspend(tmp_adev);
3723 need_full_reset = true;
3730 r = amdgpu_device_recover_vram(tmp_adev);
3732 tmp_adev->asic_reset_res = r;
3736 *need_full_reset_arg = need_full_reset;
3740 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
3743 if (!mutex_trylock(&adev->lock_reset))
3746 mutex_lock(&adev->lock_reset);
3748 atomic_inc(&adev->gpu_reset_counter);
3749 adev->in_gpu_reset = 1;
3750 switch (amdgpu_asic_reset_method(adev)) {
3751 case AMD_RESET_METHOD_MODE1:
3752 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
3754 case AMD_RESET_METHOD_MODE2:
3755 adev->mp1_state = PP_MP1_STATE_RESET;
3758 adev->mp1_state = PP_MP1_STATE_NONE;
3761 /* Block kfd: SRIOV would do it separately */
3762 if (!amdgpu_sriov_vf(adev))
3763 amdgpu_amdkfd_pre_reset(adev);
3768 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3770 /*unlock kfd: SRIOV would do it separately */
3771 if (!amdgpu_sriov_vf(adev))
3772 amdgpu_amdkfd_post_reset(adev);
3773 amdgpu_vf_error_trans_all(adev);
3774 adev->mp1_state = PP_MP1_STATE_NONE;
3775 adev->in_gpu_reset = 0;
3776 mutex_unlock(&adev->lock_reset);
3781 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3783 * @adev: amdgpu device pointer
3784 * @job: which job trigger hang
3786 * Attempt to reset the GPU if it has hung (all asics).
3787 * Attempt to do soft-reset or full-reset and reinitialize Asic
3788 * Returns 0 for success or an error on failure.
3791 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3792 struct amdgpu_job *job)
3794 struct list_head device_list, *device_list_handle = NULL;
3795 bool need_full_reset, job_signaled;
3796 struct amdgpu_hive_info *hive = NULL;
3797 struct amdgpu_device *tmp_adev = NULL;
3800 need_full_reset = job_signaled = false;
3801 INIT_LIST_HEAD(&device_list);
3803 dev_info(adev->dev, "GPU reset begin!\n");
3805 cancel_delayed_work_sync(&adev->delayed_init_work);
3807 hive = amdgpu_get_xgmi_hive(adev, false);
3810 * Here we trylock to avoid chain of resets executing from
3811 * either trigger by jobs on different adevs in XGMI hive or jobs on
3812 * different schedulers for same device while this TO handler is running.
3813 * We always reset all schedulers for device and all devices for XGMI
3814 * hive so that should take care of them too.
3817 if (hive && !mutex_trylock(&hive->reset_lock)) {
3818 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
3819 job->base.id, hive->hive_id);
3823 /* Start with adev pre asic reset first for soft reset check.*/
3824 if (!amdgpu_device_lock_adev(adev, !hive)) {
3825 DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
3830 /* Build list of devices to reset */
3831 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3833 amdgpu_device_unlock_adev(adev);
3838 * In case we are in XGMI hive mode device reset is done for all the
3839 * nodes in the hive to retrain all XGMI links and hence the reset
3840 * sequence is executed in loop on all nodes.
3842 device_list_handle = &hive->device_list;
3844 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3845 device_list_handle = &device_list;
3849 * Mark these ASICs to be reseted as untracked first
3850 * And add them back after reset completed
3852 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head)
3853 amdgpu_unregister_gpu_instance(tmp_adev);
3855 /* block all schedulers and reset given job's ring */
3856 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3857 /* disable ras on ALL IPs */
3858 if (amdgpu_device_ip_need_full_reset(tmp_adev))
3859 amdgpu_ras_suspend(tmp_adev);
3861 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3862 struct amdgpu_ring *ring = tmp_adev->rings[i];
3864 if (!ring || !ring->sched.thread)
3867 drm_sched_stop(&ring->sched, &job->base);
3873 * Must check guilty signal here since after this point all old
3874 * HW fences are force signaled.
3876 * job->base holds a reference to parent fence
3878 if (job && job->base.s_fence->parent &&
3879 dma_fence_is_signaled(job->base.s_fence->parent))
3880 job_signaled = true;
3882 if (!amdgpu_device_ip_need_full_reset(adev))
3883 device_list_handle = &device_list;
3886 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
3891 /* Guilty job will be freed after this*/
3892 r = amdgpu_device_pre_asic_reset(adev,
3896 /*TODO Should we stop ?*/
3897 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3898 r, adev->ddev->unique);
3899 adev->asic_reset_res = r;
3902 retry: /* Rest of adevs pre asic reset from XGMI hive. */
3903 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3905 if (tmp_adev == adev)
3908 amdgpu_device_lock_adev(tmp_adev, false);
3909 r = amdgpu_device_pre_asic_reset(tmp_adev,
3912 /*TODO Should we stop ?*/
3914 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3915 r, tmp_adev->ddev->unique);
3916 tmp_adev->asic_reset_res = r;
3920 /* Actual ASIC resets if needed.*/
3921 /* TODO Implement XGMI hive reset logic for SRIOV */
3922 if (amdgpu_sriov_vf(adev)) {
3923 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3925 adev->asic_reset_res = r;
3927 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3928 if (r && r == -EAGAIN)
3934 /* Post ASIC reset for all devs .*/
3935 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3936 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3937 struct amdgpu_ring *ring = tmp_adev->rings[i];
3939 if (!ring || !ring->sched.thread)
3942 /* No point to resubmit jobs if we didn't HW reset*/
3943 if (!tmp_adev->asic_reset_res && !job_signaled)
3944 drm_sched_resubmit_jobs(&ring->sched);
3946 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
3949 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
3950 drm_helper_resume_force_mode(tmp_adev->ddev);
3953 tmp_adev->asic_reset_res = 0;
3956 /* bad news, how to tell it to userspace ? */
3957 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3958 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3960 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
3963 amdgpu_device_unlock_adev(tmp_adev);
3967 mutex_unlock(&hive->reset_lock);
3970 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3975 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3977 * @adev: amdgpu_device pointer
3979 * Fetchs and stores in the driver the PCIE capabilities (gen speed
3980 * and lanes) of the slot the device is in. Handles APUs and
3981 * virtualized environments where PCIE config space may not be available.
3983 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3985 struct pci_dev *pdev;
3986 enum pci_bus_speed speed_cap, platform_speed_cap;
3987 enum pcie_link_width platform_link_width;
3989 if (amdgpu_pcie_gen_cap)
3990 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3992 if (amdgpu_pcie_lane_cap)
3993 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3995 /* covers APUs as well */
3996 if (pci_is_root_bus(adev->pdev->bus)) {
3997 if (adev->pm.pcie_gen_mask == 0)
3998 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3999 if (adev->pm.pcie_mlw_mask == 0)
4000 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4004 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4007 pcie_bandwidth_available(adev->pdev, NULL,
4008 &platform_speed_cap, &platform_link_width);
4010 if (adev->pm.pcie_gen_mask == 0) {
4013 speed_cap = pcie_get_speed_cap(pdev);
4014 if (speed_cap == PCI_SPEED_UNKNOWN) {
4015 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4016 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4017 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4019 if (speed_cap == PCIE_SPEED_16_0GT)
4020 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4021 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4022 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4023 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4024 else if (speed_cap == PCIE_SPEED_8_0GT)
4025 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4026 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4027 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4028 else if (speed_cap == PCIE_SPEED_5_0GT)
4029 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4030 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4032 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4035 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4036 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4037 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4039 if (platform_speed_cap == PCIE_SPEED_16_0GT)
4040 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4041 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4042 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4043 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
4044 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
4045 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4046 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4047 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
4048 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
4049 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4050 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4052 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
4056 if (adev->pm.pcie_mlw_mask == 0) {
4057 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
4058 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
4060 switch (platform_link_width) {
4062 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
4063 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4064 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4065 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4066 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4067 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4068 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4071 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4072 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4073 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4074 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4075 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4076 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4079 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4080 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4081 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4082 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4083 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4086 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4087 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4088 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4089 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4092 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4093 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4094 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4097 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4098 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4101 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;