drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/power_supply.h>
  29 #include <linux/kthread.h>
  30 #include <linux/module.h>
  31 #include <linux/console.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_probe_helper.h>
  36 #include <drm/amdgpu_drm.h>
  37 #include <linux/vgaarb.h>
  38 #include <linux/vga_switcheroo.h>
  39 #include <linux/efi.h>
  40 #include "amdgpu.h"
  41 #include "amdgpu_trace.h"
  42 #include "amdgpu_i2c.h"
  43 #include "atom.h"
  44 #include "amdgpu_atombios.h"
  45 #include "amdgpu_atomfirmware.h"
  46 #include "amd_pcie.h"
  47 #ifdef CONFIG_DRM_AMDGPU_SI
  48 #include "si.h"
  49 #endif
  50 #ifdef CONFIG_DRM_AMDGPU_CIK
  51 #include "cik.h"
  52 #endif
  53 #include "vi.h"
  54 #include "soc15.h"
  55 #include "nv.h"
  56 #include "bif/bif_4_1_d.h"
  57 #include <linux/pci.h>
  58 #include <linux/firmware.h>
  59 #include "amdgpu_vf_error.h"
  60
  61 #include "amdgpu_amdkfd.h"
  62 #include "amdgpu_pm.h"
  63
  64 #include "amdgpu_xgmi.h"
  65 #include "amdgpu_ras.h"
  66 #include "amdgpu_pmu.h"
  67
  68 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  69 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
  70 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  71 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
  72 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
  73 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
  74 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
  75 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
  76 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
  77
  78 #define AMDGPU_RESUME_MS                2000
  79
  80 static const char *amdgpu_asic_name[] = {
  81         "TAHITI",
  82         "PITCAIRN",
  83         "VERDE",
  84         "OLAND",
  85         "HAINAN",
  86         "BONAIRE",
  87         "KAVERI",
  88         "KABINI",
  89         "HAWAII",
  90         "MULLINS",
  91         "TOPAZ",
  92         "TONGA",
  93         "FIJI",
  94         "CARRIZO",
  95         "STONEY",
  96         "POLARIS10",
  97         "POLARIS11",
  98         "POLARIS12",
  99         "VEGAM",
 100         "VEGA10",
 101         "VEGA12",
 102         "VEGA20",
 103         "RAVEN",
 104         "ARCTURUS",
 105         "NAVI10",
 106         "NAVI14",
 107         "NAVI12",
 108         "LAST",
 109 };
 110
 111 /**
 112  * DOC: pcie_replay_count
 113  *
 114  * The amdgpu driver provides a sysfs API for reporting the total number
 115  * of PCIe replays (NAKs)
 116  * The file pcie_replay_count is used for this and returns the total
 117  * number of replays as a sum of the NAKs generated and NAKs received
 118  */
 119
 120 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
 121                 struct device_attribute *attr, char *buf)
 122 {
 123         struct drm_device *ddev = dev_get_drvdata(dev);
 124         struct amdgpu_device *adev = ddev->dev_private;
 125         uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
 126
 127         return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
 128 }
 129
 130 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
 131                 amdgpu_device_get_pcie_replay_count, NULL);
 132
 133 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 134
 135 /**
 136  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
 137  *
 138  * @dev: drm_device pointer
 139  *
 140  * Returns true if the device is a dGPU with HG/PX power control,
 141  * otherwise return false.
 142  */
 143 bool amdgpu_device_is_px(struct drm_device *dev)
 144 {
 145         struct amdgpu_device *adev = dev->dev_private;
 146
 147         if (adev->flags & AMD_IS_PX)
 148                 return true;
 149         return false;
 150 }
 151
 152 /*
 153  * MMIO register access helper functions.
 154  */
 155 /**
 156  * amdgpu_mm_rreg - read a memory mapped IO register
 157  *
 158  * @adev: amdgpu_device pointer
 159  * @reg: dword aligned register offset
 160  * @acc_flags: access flags which require special behavior
 161  *
 162  * Returns the 32 bit value from the offset specified.
 163  */
 164 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 165                         uint32_t acc_flags)
 166 {
 167         uint32_t ret;
 168
 169         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 170                 return amdgpu_virt_kiq_rreg(adev, reg);
 171
 172         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 173                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 174         else {
 175                 unsigned long flags;
 176
 177                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 178                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 179                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 180                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 181         }
 182         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 183         return ret;
 184 }
 185
 186 /*
 187  * MMIO register read with bytes helper functions
 188  * @offset:bytes offset from MMIO start
 189  *
 190 */
 191
 192 /**
 193  * amdgpu_mm_rreg8 - read a memory mapped IO register
 194  *
 195  * @adev: amdgpu_device pointer
 196  * @offset: byte aligned register offset
 197  *
 198  * Returns the 8 bit value from the offset specified.
 199  */
 200 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 201         if (offset < adev->rmmio_size)
 202                 return (readb(adev->rmmio + offset));
 203         BUG();
 204 }
 205
 206 /*
 207  * MMIO register write with bytes helper functions
 208  * @offset:bytes offset from MMIO start
 209  * @value: the value want to be written to the register
 210  *
 211 */
 212 /**
 213  * amdgpu_mm_wreg8 - read a memory mapped IO register
 214  *
 215  * @adev: amdgpu_device pointer
 216  * @offset: byte aligned register offset
 217  * @value: 8 bit value to write
 218  *
 219  * Writes the value specified to the offset specified.
 220  */
 221 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 222         if (offset < adev->rmmio_size)
 223                 writeb(value, adev->rmmio + offset);
 224         else
 225                 BUG();
 226 }
 227
 228 /**
 229  * amdgpu_mm_wreg - write to a memory mapped IO register
 230  *
 231  * @adev: amdgpu_device pointer
 232  * @reg: dword aligned register offset
 233  * @v: 32 bit value to write to the register
 234  * @acc_flags: access flags which require special behavior
 235  *
 236  * Writes the value specified to the offset specified.
 237  */
 238 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 239                     uint32_t acc_flags)
 240 {
 241         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 242
 243         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 244                 adev->last_mm_index = v;
 245         }
 246
 247         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 248                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 249
 250         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 251                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 252         else {
 253                 unsigned long flags;
 254
 255                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 256                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 257                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 258                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 259         }
 260
 261         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 262                 udelay(500);
 263         }
 264 }
 265
 266 /**
 267  * amdgpu_mm_rreg64 - read a 64 bit memory mapped IO register
 268  *
 269  * @adev: amdgpu_device pointer
 270  * @reg: dword aligned register offset
 271  *
 272  * Returns the 64 bit value from the offset specified.
 273  */
 274 uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
 275 {
 276         if ((reg * 4) < adev->rmmio_size)
 277                 return atomic64_read((atomic64_t *)(adev->rmmio + (reg * 4)));
 278         else
 279                 BUG();
 280 }
 281
 282 /**
 283  * amdgpu_mm_wreg64 - write to a 64 bit memory mapped IO register
 284  *
 285  * @adev: amdgpu_device pointer
 286  * @reg: dword aligned register offset
 287  * @v: 64 bit value to write to the register
 288  *
 289  * Writes the value specified to the offset specified.
 290  */
 291 void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
 292 {
 293         if ((reg * 4) < adev->rmmio_size)
 294                 atomic64_set((atomic64_t *)(adev->rmmio + (reg * 4)), v);
 295         else
 296                 BUG();
 297 }
 298
 299 /**
 300  * amdgpu_io_rreg - read an IO register
 301  *
 302  * @adev: amdgpu_device pointer
 303  * @reg: dword aligned register offset
 304  *
 305  * Returns the 32 bit value from the offset specified.
 306  */
 307 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 308 {
 309         if ((reg * 4) < adev->rio_mem_size)
 310                 return ioread32(adev->rio_mem + (reg * 4));
 311         else {
 312                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 313                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 314         }
 315 }
 316
 317 /**
 318  * amdgpu_io_wreg - write to an IO register
 319  *
 320  * @adev: amdgpu_device pointer
 321  * @reg: dword aligned register offset
 322  * @v: 32 bit value to write to the register
 323  *
 324  * Writes the value specified to the offset specified.
 325  */
 326 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 327 {
 328         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 329                 adev->last_mm_index = v;
 330         }
 331
 332         if ((reg * 4) < adev->rio_mem_size)
 333                 iowrite32(v, adev->rio_mem + (reg * 4));
 334         else {
 335                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 336                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 337         }
 338
 339         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 340                 udelay(500);
 341         }
 342 }
 343
 344 /**
 345  * amdgpu_mm_rdoorbell - read a doorbell dword
 346  *
 347  * @adev: amdgpu_device pointer
 348  * @index: doorbell index
 349  *
 350  * Returns the value in the doorbell aperture at the
 351  * requested doorbell index (CIK).
 352  */
 353 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 354 {
 355         if (index < adev->doorbell.num_doorbells) {
 356                 return readl(adev->doorbell.ptr + index);
 357         } else {
 358                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 359                 return 0;
 360         }
 361 }
 362
 363 /**
 364  * amdgpu_mm_wdoorbell - write a doorbell dword
 365  *
 366  * @adev: amdgpu_device pointer
 367  * @index: doorbell index
 368  * @v: value to write
 369  *
 370  * Writes @v to the doorbell aperture at the
 371  * requested doorbell index (CIK).
 372  */
 373 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 374 {
 375         if (index < adev->doorbell.num_doorbells) {
 376                 writel(v, adev->doorbell.ptr + index);
 377         } else {
 378                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 379         }
 380 }
 381
 382 /**
 383  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 384  *
 385  * @adev: amdgpu_device pointer
 386  * @index: doorbell index
 387  *
 388  * Returns the value in the doorbell aperture at the
 389  * requested doorbell index (VEGA10+).
 390  */
 391 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 392 {
 393         if (index < adev->doorbell.num_doorbells) {
 394                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 395         } else {
 396                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 397                 return 0;
 398         }
 399 }
 400
 401 /**
 402  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 403  *
 404  * @adev: amdgpu_device pointer
 405  * @index: doorbell index
 406  * @v: value to write
 407  *
 408  * Writes @v to the doorbell aperture at the
 409  * requested doorbell index (VEGA10+).
 410  */
 411 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 412 {
 413         if (index < adev->doorbell.num_doorbells) {
 414                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 415         } else {
 416                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 417         }
 418 }
 419
 420 /**
 421  * amdgpu_invalid_rreg - dummy reg read function
 422  *
 423  * @adev: amdgpu device pointer
 424  * @reg: offset of register
 425  *
 426  * Dummy register read function.  Used for register blocks
 427  * that certain asics don't have (all asics).
 428  * Returns the value in the register.
 429  */
 430 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 431 {
 432         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 433         BUG();
 434         return 0;
 435 }
 436
 437 /**
 438  * amdgpu_invalid_wreg - dummy reg write function
 439  *
 440  * @adev: amdgpu device pointer
 441  * @reg: offset of register
 442  * @v: value to write to the register
 443  *
 444  * Dummy register read function.  Used for register blocks
 445  * that certain asics don't have (all asics).
 446  */
 447 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 448 {
 449         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 450                   reg, v);
 451         BUG();
 452 }
 453
 454 /**
 455  * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
 456  *
 457  * @adev: amdgpu device pointer
 458  * @reg: offset of register
 459  *
 460  * Dummy register read function.  Used for register blocks
 461  * that certain asics don't have (all asics).
 462  * Returns the value in the register.
 463  */
 464 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
 465 {
 466         DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
 467         BUG();
 468         return 0;
 469 }
 470
 471 /**
 472  * amdgpu_invalid_wreg64 - dummy reg write function
 473  *
 474  * @adev: amdgpu device pointer
 475  * @reg: offset of register
 476  * @v: value to write to the register
 477  *
 478  * Dummy register read function.  Used for register blocks
 479  * that certain asics don't have (all asics).
 480  */
 481 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
 482 {
 483         DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
 484                   reg, v);
 485         BUG();
 486 }
 487
 488 /**
 489  * amdgpu_block_invalid_rreg - dummy reg read function
 490  *
 491  * @adev: amdgpu device pointer
 492  * @block: offset of instance
 493  * @reg: offset of register
 494  *
 495  * Dummy register read function.  Used for register blocks
 496  * that certain asics don't have (all asics).
 497  * Returns the value in the register.
 498  */
 499 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 500                                           uint32_t block, uint32_t reg)
 501 {
 502         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 503                   reg, block);
 504         BUG();
 505         return 0;
 506 }
 507
 508 /**
 509  * amdgpu_block_invalid_wreg - dummy reg write function
 510  *
 511  * @adev: amdgpu device pointer
 512  * @block: offset of instance
 513  * @reg: offset of register
 514  * @v: value to write to the register
 515  *
 516  * Dummy register read function.  Used for register blocks
 517  * that certain asics don't have (all asics).
 518  */
 519 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 520                                       uint32_t block,
 521                                       uint32_t reg, uint32_t v)
 522 {
 523         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 524                   reg, block, v);
 525         BUG();
 526 }
 527
 528 /**
 529  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 530  *
 531  * @adev: amdgpu device pointer
 532  *
 533  * Allocates a scratch page of VRAM for use by various things in the
 534  * driver.
 535  */
 536 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 537 {
 538         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 539                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 540                                        &adev->vram_scratch.robj,
 541                                        &adev->vram_scratch.gpu_addr,
 542                                        (void **)&adev->vram_scratch.ptr);
 543 }
 544
 545 /**
 546  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 547  *
 548  * @adev: amdgpu device pointer
 549  *
 550  * Frees the VRAM scratch page.
 551  */
 552 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 553 {
 554         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 555 }
 556
 557 /**
 558  * amdgpu_device_program_register_sequence - program an array of registers.
 559  *
 560  * @adev: amdgpu_device pointer
 561  * @registers: pointer to the register array
 562  * @array_size: size of the register array
 563  *
 564  * Programs an array or registers with and and or masks.
 565  * This is a helper for setting golden registers.
 566  */
 567 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 568                                              const u32 *registers,
 569                                              const u32 array_size)
 570 {
 571         u32 tmp, reg, and_mask, or_mask;
 572         int i;
 573
 574         if (array_size % 3)
 575                 return;
 576
 577         for (i = 0; i < array_size; i +=3) {
 578                 reg = registers[i + 0];
 579                 and_mask = registers[i + 1];
 580                 or_mask = registers[i + 2];
 581
 582                 if (and_mask == 0xffffffff) {
 583                         tmp = or_mask;
 584                 } else {
 585                         tmp = RREG32(reg);
 586                         tmp &= ~and_mask;
 587                         if (adev->family >= AMDGPU_FAMILY_AI)
 588                                 tmp |= (or_mask & and_mask);
 589                         else
 590                                 tmp |= or_mask;
 591                 }
 592                 WREG32(reg, tmp);
 593         }
 594 }
 595
 596 /**
 597  * amdgpu_device_pci_config_reset - reset the GPU
 598  *
 599  * @adev: amdgpu_device pointer
 600  *
 601  * Resets the GPU using the pci config reset sequence.
 602  * Only applicable to asics prior to vega10.
 603  */
 604 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 605 {
 606         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 607 }
 608
 609 /*
 610  * GPU doorbell aperture helpers function.
 611  */
 612 /**
 613  * amdgpu_device_doorbell_init - Init doorbell driver information.
 614  *
 615  * @adev: amdgpu_device pointer
 616  *
 617  * Init doorbell driver information (CIK)
 618  * Returns 0 on success, error on failure.
 619  */
 620 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 621 {
 622
 623         /* No doorbell on SI hardware generation */
 624         if (adev->asic_type < CHIP_BONAIRE) {
 625                 adev->doorbell.base = 0;
 626                 adev->doorbell.size = 0;
 627                 adev->doorbell.num_doorbells = 0;
 628                 adev->doorbell.ptr = NULL;
 629                 return 0;
 630         }
 631
 632         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 633                 return -EINVAL;
 634
 635         amdgpu_asic_init_doorbell_index(adev);
 636
 637         /* doorbell bar mapping */
 638         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 639         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 640
 641         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 642                                              adev->doorbell_index.max_assignment+1);
 643         if (adev->doorbell.num_doorbells == 0)
 644                 return -EINVAL;
 645
 646         /* For Vega, reserve and map two pages on doorbell BAR since SDMA
 647          * paging queue doorbell use the second page. The
 648          * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
 649          * doorbells are in the first page. So with paging queue enabled,
 650          * the max num_doorbells should + 1 page (0x400 in dword)
 651          */
 652         if (adev->asic_type >= CHIP_VEGA10)
 653                 adev->doorbell.num_doorbells += 0x400;
 654
 655         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 656                                      adev->doorbell.num_doorbells *
 657                                      sizeof(u32));
 658         if (adev->doorbell.ptr == NULL)
 659                 return -ENOMEM;
 660
 661         return 0;
 662 }
 663
 664 /**
 665  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 666  *
 667  * @adev: amdgpu_device pointer
 668  *
 669  * Tear down doorbell driver information (CIK)
 670  */
 671 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 672 {
 673         iounmap(adev->doorbell.ptr);
 674         adev->doorbell.ptr = NULL;
 675 }
 676
 677
 678
 679 /*
 680  * amdgpu_device_wb_*()
 681  * Writeback is the method by which the GPU updates special pages in memory
 682  * with the status of certain GPU events (fences, ring pointers,etc.).
 683  */
 684
 685 /**
 686  * amdgpu_device_wb_fini - Disable Writeback and free memory
 687  *
 688  * @adev: amdgpu_device pointer
 689  *
 690  * Disables Writeback and frees the Writeback memory (all asics).
 691  * Used at driver shutdown.
 692  */
 693 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 694 {
 695         if (adev->wb.wb_obj) {
 696                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 697                                       &adev->wb.gpu_addr,
 698                                       (void **)&adev->wb.wb);
 699                 adev->wb.wb_obj = NULL;
 700         }
 701 }
 702
 703 /**
 704  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 705  *
 706  * @adev: amdgpu_device pointer
 707  *
 708  * Initializes writeback and allocates writeback memory (all asics).
 709  * Used at driver startup.
 710  * Returns 0 on success or an -error on failure.
 711  */
 712 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 713 {
 714         int r;
 715
 716         if (adev->wb.wb_obj == NULL) {
 717                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 718                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 719                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 720                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 721                                             (void **)&adev->wb.wb);
 722                 if (r) {
 723                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 724                         return r;
 725                 }
 726
 727                 adev->wb.num_wb = AMDGPU_MAX_WB;
 728                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 729
 730                 /* clear wb memory */
 731                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 732         }
 733
 734         return 0;
 735 }
 736
 737 /**
 738  * amdgpu_device_wb_get - Allocate a wb entry
 739  *
 740  * @adev: amdgpu_device pointer
 741  * @wb: wb index
 742  *
 743  * Allocate a wb slot for use by the driver (all asics).
 744  * Returns 0 on success or -EINVAL on failure.
 745  */
 746 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 747 {
 748         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 749
 750         if (offset < adev->wb.num_wb) {
 751                 __set_bit(offset, adev->wb.used);
 752                 *wb = offset << 3; /* convert to dw offset */
 753                 return 0;
 754         } else {
 755                 return -EINVAL;
 756         }
 757 }
 758
 759 /**
 760  * amdgpu_device_wb_free - Free a wb entry
 761  *
 762  * @adev: amdgpu_device pointer
 763  * @wb: wb index
 764  *
 765  * Free a wb slot allocated for use by the driver (all asics)
 766  */
 767 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 768 {
 769         wb >>= 3;
 770         if (wb < adev->wb.num_wb)
 771                 __clear_bit(wb, adev->wb.used);
 772 }
 773
 774 /**
 775  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 776  *
 777  * @adev: amdgpu_device pointer
 778  *
 779  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 780  * to fail, but if any of the BARs is not accessible after the size we abort
 781  * driver loading by returning -ENODEV.
 782  */
 783 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 784 {
 785         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 786         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 787         struct pci_bus *root;
 788         struct resource *res;
 789         unsigned i;
 790         u16 cmd;
 791         int r;
 792
 793         /* Bypass for VF */
 794         if (amdgpu_sriov_vf(adev))
 795                 return 0;
 796
 797         /* Check if the root BUS has 64bit memory resources */
 798         root = adev->pdev->bus;
 799         while (root->parent)
 800                 root = root->parent;
 801
 802         pci_bus_for_each_resource(root, res, i) {
 803                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 804                     res->start > 0x100000000ull)
 805                         break;
 806         }
 807
 808         /* Trying to resize is pointless without a root hub window above 4GB */
 809         if (!res)
 810                 return 0;
 811
 812         /* Disable memory decoding while we change the BAR addresses and size */
 813         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 814         pci_write_config_word(adev->pdev, PCI_COMMAND,
 815                               cmd & ~PCI_COMMAND_MEMORY);
 816
 817         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 818         amdgpu_device_doorbell_fini(adev);
 819         if (adev->asic_type >= CHIP_BONAIRE)
 820                 pci_release_resource(adev->pdev, 2);
 821
 822         pci_release_resource(adev->pdev, 0);
 823
 824         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 825         if (r == -ENOSPC)
 826                 DRM_INFO("Not enough PCI address space for a large BAR.");
 827         else if (r && r != -ENOTSUPP)
 828                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 829
 830         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 831
 832         /* When the doorbell or fb BAR isn't available we have no chance of
 833          * using the device.
 834          */
 835         r = amdgpu_device_doorbell_init(adev);
 836         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 837                 return -ENODEV;
 838
 839         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 840
 841         return 0;
 842 }
 843
 844 /*
 845  * GPU helpers function.
 846  */
 847 /**
 848  * amdgpu_device_need_post - check if the hw need post or not
 849  *
 850  * @adev: amdgpu_device pointer
 851  *
 852  * Check if the asic has been initialized (all asics) at driver startup
 853  * or post is needed if  hw reset is performed.
 854  * Returns true if need or false if not.
 855  */
 856 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 857 {
 858         uint32_t reg;
 859
 860         if (amdgpu_sriov_vf(adev))
 861                 return false;
 862
 863         if (amdgpu_passthrough(adev)) {
 864                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 865                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 866                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 867                  * vpost executed for smc version below 22.15
 868                  */
 869                 if (adev->asic_type == CHIP_FIJI) {
 870                         int err;
 871                         uint32_t fw_ver;
 872                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 873                         /* force vPost if error occured */
 874                         if (err)
 875                                 return true;
 876
 877                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 878                         if (fw_ver < 0x00160e00)
 879                                 return true;
 880                 }
 881         }
 882
 883         if (adev->has_hw_reset) {
 884                 adev->has_hw_reset = false;
 885                 return true;
 886         }
 887
 888         /* bios scratch used on CIK+ */
 889         if (adev->asic_type >= CHIP_BONAIRE)
 890                 return amdgpu_atombios_scratch_need_asic_init(adev);
 891
 892         /* check MEM_SIZE for older asics */
 893         reg = amdgpu_asic_get_config_memsize(adev);
 894
 895         if ((reg != 0) && (reg != 0xffffffff))
 896                 return false;
 897
 898         return true;
 899 }
 900
 901 /* if we get transitioned to only one device, take VGA back */
 902 /**
 903  * amdgpu_device_vga_set_decode - enable/disable vga decode
 904  *
 905  * @cookie: amdgpu_device pointer
 906  * @state: enable/disable vga decode
 907  *
 908  * Enable/disable vga decode (all asics).
 909  * Returns VGA resource flags.
 910  */
 911 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 912 {
 913         struct amdgpu_device *adev = cookie;
 914         amdgpu_asic_set_vga_state(adev, state);
 915         if (state)
 916                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 917                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 918         else
 919                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 920 }
 921
 922 /**
 923  * amdgpu_device_check_block_size - validate the vm block size
 924  *
 925  * @adev: amdgpu_device pointer
 926  *
 927  * Validates the vm block size specified via module parameter.
 928  * The vm block size defines number of bits in page table versus page directory,
 929  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 930  * page table and the remaining bits are in the page directory.
 931  */
 932 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 933 {
 934         /* defines number of bits in page table versus page directory,
 935          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 936          * page table and the remaining bits are in the page directory */
 937         if (amdgpu_vm_block_size == -1)
 938                 return;
 939
 940         if (amdgpu_vm_block_size < 9) {
 941                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 942                          amdgpu_vm_block_size);
 943                 amdgpu_vm_block_size = -1;
 944         }
 945 }
 946
 947 /**
 948  * amdgpu_device_check_vm_size - validate the vm size
 949  *
 950  * @adev: amdgpu_device pointer
 951  *
 952  * Validates the vm size in GB specified via module parameter.
 953  * The VM size is the size of the GPU virtual memory space in GB.
 954  */
 955 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 956 {
 957         /* no need to check the default value */
 958         if (amdgpu_vm_size == -1)
 959                 return;
 960
 961         if (amdgpu_vm_size < 1) {
 962                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 963                          amdgpu_vm_size);
 964                 amdgpu_vm_size = -1;
 965         }
 966 }
 967
 968 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 969 {
 970         struct sysinfo si;
 971         bool is_os_64 = (sizeof(void *) == 8) ? true : false;
 972         uint64_t total_memory;
 973         uint64_t dram_size_seven_GB = 0x1B8000000;
 974         uint64_t dram_size_three_GB = 0xB8000000;
 975
 976         if (amdgpu_smu_memory_pool_size == 0)
 977                 return;
 978
 979         if (!is_os_64) {
 980                 DRM_WARN("Not 64-bit OS, feature not supported\n");
 981                 goto def_value;
 982         }
 983         si_meminfo(&si);
 984         total_memory = (uint64_t)si.totalram * si.mem_unit;
 985
 986         if ((amdgpu_smu_memory_pool_size == 1) ||
 987                 (amdgpu_smu_memory_pool_size == 2)) {
 988                 if (total_memory < dram_size_three_GB)
 989                         goto def_value1;
 990         } else if ((amdgpu_smu_memory_pool_size == 4) ||
 991                 (amdgpu_smu_memory_pool_size == 8)) {
 992                 if (total_memory < dram_size_seven_GB)
 993                         goto def_value1;
 994         } else {
 995                 DRM_WARN("Smu memory pool size not supported\n");
 996                 goto def_value;
 997         }
 998         adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
 999
1000         return;
1001
1002 def_value1:
1003         DRM_WARN("No enough system memory\n");
1004 def_value:
1005         adev->pm.smu_prv_buffer_size = 0;
1006 }
1007
1008 /**
1009  * amdgpu_device_check_arguments - validate module params
1010  *
1011  * @adev: amdgpu_device pointer
1012  *
1013  * Validates certain module parameters and updates
1014  * the associated values used by the driver (all asics).
1015  */
1016 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1017 {
1018         int ret = 0;
1019
1020         if (amdgpu_sched_jobs < 4) {
1021                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1022                          amdgpu_sched_jobs);
1023                 amdgpu_sched_jobs = 4;
1024         } else if (!is_power_of_2(amdgpu_sched_jobs)){
1025                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1026                          amdgpu_sched_jobs);
1027                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1028         }
1029
1030         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1031                 /* gart size must be greater or equal to 32M */
1032                 dev_warn(adev->dev, "gart size (%d) too small\n",
1033                          amdgpu_gart_size);
1034                 amdgpu_gart_size = -1;
1035         }
1036
1037         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1038                 /* gtt size must be greater or equal to 32M */
1039                 dev_warn(adev->dev, "gtt size (%d) too small\n",
1040                                  amdgpu_gtt_size);
1041                 amdgpu_gtt_size = -1;
1042         }
1043
1044         /* valid range is between 4 and 9 inclusive */
1045         if (amdgpu_vm_fragment_size != -1 &&
1046             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1047                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1048                 amdgpu_vm_fragment_size = -1;
1049         }
1050
1051         amdgpu_device_check_smu_prv_buffer_size(adev);
1052
1053         amdgpu_device_check_vm_size(adev);
1054
1055         amdgpu_device_check_block_size(adev);
1056
1057         ret = amdgpu_device_get_job_timeout_settings(adev);
1058         if (ret) {
1059                 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
1060                 return ret;
1061         }
1062
1063         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1064
1065         return ret;
1066 }
1067
1068 /**
1069  * amdgpu_switcheroo_set_state - set switcheroo state
1070  *
1071  * @pdev: pci dev pointer
1072  * @state: vga_switcheroo state
1073  *
1074  * Callback for the switcheroo driver.  Suspends or resumes the
1075  * the asics before or after it is powered up using ACPI methods.
1076  */
1077 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1078 {
1079         struct drm_device *dev = pci_get_drvdata(pdev);
1080
1081         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1082                 return;
1083
1084         if (state == VGA_SWITCHEROO_ON) {
1085                 pr_info("amdgpu: switched on\n");
1086                 /* don't suspend or resume card normally */
1087                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1088
1089                 amdgpu_device_resume(dev, true, true);
1090
1091                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1092                 drm_kms_helper_poll_enable(dev);
1093         } else {
1094                 pr_info("amdgpu: switched off\n");
1095                 drm_kms_helper_poll_disable(dev);
1096                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1097                 amdgpu_device_suspend(dev, true, true);
1098                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1099         }
1100 }
1101
1102 /**
1103  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1104  *
1105  * @pdev: pci dev pointer
1106  *
1107  * Callback for the switcheroo driver.  Check of the switcheroo
1108  * state can be changed.
1109  * Returns true if the state can be changed, false if not.
1110  */
1111 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1112 {
1113         struct drm_device *dev = pci_get_drvdata(pdev);
1114
1115         /*
1116         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1117         * locking inversion with the driver load path. And the access here is
1118         * completely racy anyway. So don't bother with locking for now.
1119         */
1120         return dev->open_count == 0;
1121 }
1122
1123 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1124         .set_gpu_state = amdgpu_switcheroo_set_state,
1125         .reprobe = NULL,
1126         .can_switch = amdgpu_switcheroo_can_switch,
1127 };
1128
1129 /**
1130  * amdgpu_device_ip_set_clockgating_state - set the CG state
1131  *
1132  * @dev: amdgpu_device pointer
1133  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1134  * @state: clockgating state (gate or ungate)
1135  *
1136  * Sets the requested clockgating state for all instances of
1137  * the hardware IP specified.
1138  * Returns the error code from the last instance.
1139  */
1140 int amdgpu_device_ip_set_clockgating_state(void *dev,
1141                                            enum amd_ip_block_type block_type,
1142                                            enum amd_clockgating_state state)
1143 {
1144         struct amdgpu_device *adev = dev;
1145         int i, r = 0;
1146
1147         for (i = 0; i < adev->num_ip_blocks; i++) {
1148                 if (!adev->ip_blocks[i].status.valid)
1149                         continue;
1150                 if (adev->ip_blocks[i].version->type != block_type)
1151                         continue;
1152                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1153                         continue;
1154                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1155                         (void *)adev, state);
1156                 if (r)
1157                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1158                                   adev->ip_blocks[i].version->funcs->name, r);
1159         }
1160         return r;
1161 }
1162
1163 /**
1164  * amdgpu_device_ip_set_powergating_state - set the PG state
1165  *
1166  * @dev: amdgpu_device pointer
1167  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1168  * @state: powergating state (gate or ungate)
1169  *
1170  * Sets the requested powergating state for all instances of
1171  * the hardware IP specified.
1172  * Returns the error code from the last instance.
1173  */
1174 int amdgpu_device_ip_set_powergating_state(void *dev,
1175                                            enum amd_ip_block_type block_type,
1176                                            enum amd_powergating_state state)
1177 {
1178         struct amdgpu_device *adev = dev;
1179         int i, r = 0;
1180
1181         for (i = 0; i < adev->num_ip_blocks; i++) {
1182                 if (!adev->ip_blocks[i].status.valid)
1183                         continue;
1184                 if (adev->ip_blocks[i].version->type != block_type)
1185                         continue;
1186                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1187                         continue;
1188                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1189                         (void *)adev, state);
1190                 if (r)
1191                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1192                                   adev->ip_blocks[i].version->funcs->name, r);
1193         }
1194         return r;
1195 }
1196
1197 /**
1198  * amdgpu_device_ip_get_clockgating_state - get the CG state
1199  *
1200  * @adev: amdgpu_device pointer
1201  * @flags: clockgating feature flags
1202  *
1203  * Walks the list of IPs on the device and updates the clockgating
1204  * flags for each IP.
1205  * Updates @flags with the feature flags for each hardware IP where
1206  * clockgating is enabled.
1207  */
1208 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1209                                             u32 *flags)
1210 {
1211         int i;
1212
1213         for (i = 0; i < adev->num_ip_blocks; i++) {
1214                 if (!adev->ip_blocks[i].status.valid)
1215                         continue;
1216                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1217                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1218         }
1219 }
1220
1221 /**
1222  * amdgpu_device_ip_wait_for_idle - wait for idle
1223  *
1224  * @adev: amdgpu_device pointer
1225  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1226  *
1227  * Waits for the request hardware IP to be idle.
1228  * Returns 0 for success or a negative error code on failure.
1229  */
1230 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1231                                    enum amd_ip_block_type block_type)
1232 {
1233         int i, r;
1234
1235         for (i = 0; i < adev->num_ip_blocks; i++) {
1236                 if (!adev->ip_blocks[i].status.valid)
1237                         continue;
1238                 if (adev->ip_blocks[i].version->type == block_type) {
1239                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1240                         if (r)
1241                                 return r;
1242                         break;
1243                 }
1244         }
1245         return 0;
1246
1247 }
1248
1249 /**
1250  * amdgpu_device_ip_is_idle - is the hardware IP idle
1251  *
1252  * @adev: amdgpu_device pointer
1253  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1254  *
1255  * Check if the hardware IP is idle or not.
1256  * Returns true if it the IP is idle, false if not.
1257  */
1258 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1259                               enum amd_ip_block_type block_type)
1260 {
1261         int i;
1262
1263         for (i = 0; i < adev->num_ip_blocks; i++) {
1264                 if (!adev->ip_blocks[i].status.valid)
1265                         continue;
1266                 if (adev->ip_blocks[i].version->type == block_type)
1267                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1268         }
1269         return true;
1270
1271 }
1272
1273 /**
1274  * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1275  *
1276  * @adev: amdgpu_device pointer
1277  * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1278  *
1279  * Returns a pointer to the hardware IP block structure
1280  * if it exists for the asic, otherwise NULL.
1281  */
1282 struct amdgpu_ip_block *
1283 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1284                               enum amd_ip_block_type type)
1285 {
1286         int i;
1287
1288         for (i = 0; i < adev->num_ip_blocks; i++)
1289                 if (adev->ip_blocks[i].version->type == type)
1290                         return &adev->ip_blocks[i];
1291
1292         return NULL;
1293 }
1294
1295 /**
1296  * amdgpu_device_ip_block_version_cmp
1297  *
1298  * @adev: amdgpu_device pointer
1299  * @type: enum amd_ip_block_type
1300  * @major: major version
1301  * @minor: minor version
1302  *
1303  * return 0 if equal or greater
1304  * return 1 if smaller or the ip_block doesn't exist
1305  */
1306 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1307                                        enum amd_ip_block_type type,
1308                                        u32 major, u32 minor)
1309 {
1310         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1311
1312         if (ip_block && ((ip_block->version->major > major) ||
1313                         ((ip_block->version->major == major) &&
1314                         (ip_block->version->minor >= minor))))
1315                 return 0;
1316
1317         return 1;
1318 }
1319
1320 /**
1321  * amdgpu_device_ip_block_add
1322  *
1323  * @adev: amdgpu_device pointer
1324  * @ip_block_version: pointer to the IP to add
1325  *
1326  * Adds the IP block driver information to the collection of IPs
1327  * on the asic.
1328  */
1329 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1330                                const struct amdgpu_ip_block_version *ip_block_version)
1331 {
1332         if (!ip_block_version)
1333                 return -EINVAL;
1334
1335         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1336                   ip_block_version->funcs->name);
1337
1338         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1339
1340         return 0;
1341 }
1342
1343 /**
1344  * amdgpu_device_enable_virtual_display - enable virtual display feature
1345  *
1346  * @adev: amdgpu_device pointer
1347  *
1348  * Enabled the virtual display feature if the user has enabled it via
1349  * the module parameter virtual_display.  This feature provides a virtual
1350  * display hardware on headless boards or in virtualized environments.
1351  * This function parses and validates the configuration string specified by
1352  * the user and configues the virtual display configuration (number of
1353  * virtual connectors, crtcs, etc.) specified.
1354  */
1355 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1356 {
1357         adev->enable_virtual_display = false;
1358
1359         if (amdgpu_virtual_display) {
1360                 struct drm_device *ddev = adev->ddev;
1361                 const char *pci_address_name = pci_name(ddev->pdev);
1362                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1363
1364                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1365                 pciaddstr_tmp = pciaddstr;
1366                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1367                         pciaddname = strsep(&pciaddname_tmp, ",");
1368                         if (!strcmp("all", pciaddname)
1369                             || !strcmp(pci_address_name, pciaddname)) {
1370                                 long num_crtc;
1371                                 int res = -1;
1372
1373                                 adev->enable_virtual_display = true;
1374
1375                                 if (pciaddname_tmp)
1376                                         res = kstrtol(pciaddname_tmp, 10,
1377                                                       &num_crtc);
1378
1379                                 if (!res) {
1380                                         if (num_crtc < 1)
1381                                                 num_crtc = 1;
1382                                         if (num_crtc > 6)
1383                                                 num_crtc = 6;
1384                                         adev->mode_info.num_crtc = num_crtc;
1385                                 } else {
1386                                         adev->mode_info.num_crtc = 1;
1387                                 }
1388                                 break;
1389                         }
1390                 }
1391
1392                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1393                          amdgpu_virtual_display, pci_address_name,
1394                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1395
1396                 kfree(pciaddstr);
1397         }
1398 }
1399
1400 /**
1401  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1402  *
1403  * @adev: amdgpu_device pointer
1404  *
1405  * Parses the asic configuration parameters specified in the gpu info
1406  * firmware and makes them availale to the driver for use in configuring
1407  * the asic.
1408  * Returns 0 on success, -EINVAL on failure.
1409  */
1410 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1411 {
1412         const char *chip_name;
1413         char fw_name[30];
1414         int err;
1415         const struct gpu_info_firmware_header_v1_0 *hdr;
1416
1417         adev->firmware.gpu_info_fw = NULL;
1418
1419         switch (adev->asic_type) {
1420         case CHIP_TOPAZ:
1421         case CHIP_TONGA:
1422         case CHIP_FIJI:
1423         case CHIP_POLARIS10:
1424         case CHIP_POLARIS11:
1425         case CHIP_POLARIS12:
1426         case CHIP_VEGAM:
1427         case CHIP_CARRIZO:
1428         case CHIP_STONEY:
1429 #ifdef CONFIG_DRM_AMDGPU_SI
1430         case CHIP_VERDE:
1431         case CHIP_TAHITI:
1432         case CHIP_PITCAIRN:
1433         case CHIP_OLAND:
1434         case CHIP_HAINAN:
1435 #endif
1436 #ifdef CONFIG_DRM_AMDGPU_CIK
1437         case CHIP_BONAIRE:
1438         case CHIP_HAWAII:
1439         case CHIP_KAVERI:
1440         case CHIP_KABINI:
1441         case CHIP_MULLINS:
1442 #endif
1443         case CHIP_VEGA20:
1444         default:
1445                 return 0;
1446         case CHIP_VEGA10:
1447                 chip_name = "vega10";
1448                 break;
1449         case CHIP_VEGA12:
1450                 chip_name = "vega12";
1451                 break;
1452         case CHIP_RAVEN:
1453                 if (adev->rev_id >= 8)
1454                         chip_name = "raven2";
1455                 else if (adev->pdev->device == 0x15d8)
1456                         chip_name = "picasso";
1457                 else
1458                         chip_name = "raven";
1459                 break;
1460         case CHIP_ARCTURUS:
1461                 chip_name = "arcturus";
1462                 break;
1463         case CHIP_NAVI10:
1464                 chip_name = "navi10";
1465                 break;
1466         case CHIP_NAVI14:
1467                 chip_name = "navi14";
1468                 break;
1469         case CHIP_NAVI12:
1470                 chip_name = "navi12";
1471                 break;
1472         }
1473
1474         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1475         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1476         if (err) {
1477                 dev_err(adev->dev,
1478                         "Failed to load gpu_info firmware \"%s\"\n",
1479                         fw_name);
1480                 goto out;
1481         }
1482         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1483         if (err) {
1484                 dev_err(adev->dev,
1485                         "Failed to validate gpu_info firmware \"%s\"\n",
1486                         fw_name);
1487                 goto out;
1488         }
1489
1490         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1491         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1492
1493         switch (hdr->version_major) {
1494         case 1:
1495         {
1496                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1497                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1498                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1499
1500                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1501                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1502                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1503                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1504                 adev->gfx.config.max_texture_channel_caches =
1505                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1506                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1507                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1508                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1509                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1510                 adev->gfx.config.double_offchip_lds_buf =
1511                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1512                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1513                 adev->gfx.cu_info.max_waves_per_simd =
1514                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1515                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1516                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1517                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1518                 if (hdr->version_minor >= 1) {
1519                         const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1520                                 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1521                                                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1522                         adev->gfx.config.num_sc_per_sh =
1523                                 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1524                         adev->gfx.config.num_packer_per_sc =
1525                                 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1526                 }
1527 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
1528                 if (hdr->version_minor == 2) {
1529                         const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1530                                 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1531                                                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1532                         adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1533                 }
1534 #endif
1535                 break;
1536         }
1537         default:
1538                 dev_err(adev->dev,
1539                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1540                 err = -EINVAL;
1541                 goto out;
1542         }
1543 out:
1544         return err;
1545 }
1546
1547 /**
1548  * amdgpu_device_ip_early_init - run early init for hardware IPs
1549  *
1550  * @adev: amdgpu_device pointer
1551  *
1552  * Early initialization pass for hardware IPs.  The hardware IPs that make
1553  * up each asic are discovered each IP's early_init callback is run.  This
1554  * is the first stage in initializing the asic.
1555  * Returns 0 on success, negative error code on failure.
1556  */
1557 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1558 {
1559         int i, r;
1560
1561         amdgpu_device_enable_virtual_display(adev);
1562
1563         switch (adev->asic_type) {
1564         case CHIP_TOPAZ:
1565         case CHIP_TONGA:
1566         case CHIP_FIJI:
1567         case CHIP_POLARIS10:
1568         case CHIP_POLARIS11:
1569         case CHIP_POLARIS12:
1570         case CHIP_VEGAM:
1571         case CHIP_CARRIZO:
1572         case CHIP_STONEY:
1573                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1574                         adev->family = AMDGPU_FAMILY_CZ;
1575                 else
1576                         adev->family = AMDGPU_FAMILY_VI;
1577
1578                 r = vi_set_ip_blocks(adev);
1579                 if (r)
1580                         return r;
1581                 break;
1582 #ifdef CONFIG_DRM_AMDGPU_SI
1583         case CHIP_VERDE:
1584         case CHIP_TAHITI:
1585         case CHIP_PITCAIRN:
1586         case CHIP_OLAND:
1587         case CHIP_HAINAN:
1588                 adev->family = AMDGPU_FAMILY_SI;
1589                 r = si_set_ip_blocks(adev);
1590                 if (r)
1591                         return r;
1592                 break;
1593 #endif
1594 #ifdef CONFIG_DRM_AMDGPU_CIK
1595         case CHIP_BONAIRE:
1596         case CHIP_HAWAII:
1597         case CHIP_KAVERI:
1598         case CHIP_KABINI:
1599         case CHIP_MULLINS:
1600                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1601                         adev->family = AMDGPU_FAMILY_CI;
1602                 else
1603                         adev->family = AMDGPU_FAMILY_KV;
1604
1605                 r = cik_set_ip_blocks(adev);
1606                 if (r)
1607                         return r;
1608                 break;
1609 #endif
1610         case CHIP_VEGA10:
1611         case CHIP_VEGA12:
1612         case CHIP_VEGA20:
1613         case CHIP_RAVEN:
1614         case CHIP_ARCTURUS:
1615                 if (adev->asic_type == CHIP_RAVEN)
1616                         adev->family = AMDGPU_FAMILY_RV;
1617                 else
1618                         adev->family = AMDGPU_FAMILY_AI;
1619
1620                 r = soc15_set_ip_blocks(adev);
1621                 if (r)
1622                         return r;
1623                 break;
1624         case  CHIP_NAVI10:
1625         case  CHIP_NAVI14:
1626         case  CHIP_NAVI12:
1627                 adev->family = AMDGPU_FAMILY_NV;
1628
1629                 r = nv_set_ip_blocks(adev);
1630                 if (r)
1631                         return r;
1632                 break;
1633         default:
1634                 /* FIXME: not supported yet */
1635                 return -EINVAL;
1636         }
1637
1638         r = amdgpu_device_parse_gpu_info_fw(adev);
1639         if (r)
1640                 return r;
1641
1642         amdgpu_amdkfd_device_probe(adev);
1643
1644         if (amdgpu_sriov_vf(adev)) {
1645                 r = amdgpu_virt_request_full_gpu(adev, true);
1646                 if (r)
1647                         return -EAGAIN;
1648         }
1649
1650         adev->pm.pp_feature = amdgpu_pp_feature_mask;
1651         if (amdgpu_sriov_vf(adev))
1652                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1653
1654         for (i = 0; i < adev->num_ip_blocks; i++) {
1655                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1656                         DRM_ERROR("disabled ip block: %d <%s>\n",
1657                                   i, adev->ip_blocks[i].version->funcs->name);
1658                         adev->ip_blocks[i].status.valid = false;
1659                 } else {
1660                         if (adev->ip_blocks[i].version->funcs->early_init) {
1661                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1662                                 if (r == -ENOENT) {
1663                                         adev->ip_blocks[i].status.valid = false;
1664                                 } else if (r) {
1665                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1666                                                   adev->ip_blocks[i].version->funcs->name, r);
1667                                         return r;
1668                                 } else {
1669                                         adev->ip_blocks[i].status.valid = true;
1670                                 }
1671                         } else {
1672                                 adev->ip_blocks[i].status.valid = true;
1673                         }
1674                 }
1675                 /* get the vbios after the asic_funcs are set up */
1676                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
1677                         /* Read BIOS */
1678                         if (!amdgpu_get_bios(adev))
1679                                 return -EINVAL;
1680
1681                         r = amdgpu_atombios_init(adev);
1682                         if (r) {
1683                                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1684                                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1685                                 return r;
1686                         }
1687                 }
1688         }
1689
1690         adev->cg_flags &= amdgpu_cg_mask;
1691         adev->pg_flags &= amdgpu_pg_mask;
1692
1693         return 0;
1694 }
1695
1696 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1697 {
1698         int i, r;
1699
1700         for (i = 0; i < adev->num_ip_blocks; i++) {
1701                 if (!adev->ip_blocks[i].status.sw)
1702                         continue;
1703                 if (adev->ip_blocks[i].status.hw)
1704                         continue;
1705                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1706                     (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
1707                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1708                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1709                         if (r) {
1710                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1711                                           adev->ip_blocks[i].version->funcs->name, r);
1712                                 return r;
1713                         }
1714                         adev->ip_blocks[i].status.hw = true;
1715                 }
1716         }
1717
1718         return 0;
1719 }
1720
1721 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1722 {
1723         int i, r;
1724
1725         for (i = 0; i < adev->num_ip_blocks; i++) {
1726                 if (!adev->ip_blocks[i].status.sw)
1727                         continue;
1728                 if (adev->ip_blocks[i].status.hw)
1729                         continue;
1730                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1731                 if (r) {
1732                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1733                                   adev->ip_blocks[i].version->funcs->name, r);
1734                         return r;
1735                 }
1736                 adev->ip_blocks[i].status.hw = true;
1737         }
1738
1739         return 0;
1740 }
1741
1742 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1743 {
1744         int r = 0;
1745         int i;
1746         uint32_t smu_version;
1747
1748         if (adev->asic_type >= CHIP_VEGA10) {
1749                 for (i = 0; i < adev->num_ip_blocks; i++) {
1750                         if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
1751                                 continue;
1752
1753                         /* no need to do the fw loading again if already done*/
1754                         if (adev->ip_blocks[i].status.hw == true)
1755                                 break;
1756
1757                         if (adev->in_gpu_reset || adev->in_suspend) {
1758                                 r = adev->ip_blocks[i].version->funcs->resume(adev);
1759                                 if (r) {
1760                                         DRM_ERROR("resume of IP block <%s> failed %d\n",
1761                                                           adev->ip_blocks[i].version->funcs->name, r);
1762                                         return r;
1763                                 }
1764                         } else {
1765                                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1766                                 if (r) {
1767                                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1768                                                           adev->ip_blocks[i].version->funcs->name, r);
1769                                         return r;
1770                                 }
1771                         }
1772
1773                         adev->ip_blocks[i].status.hw = true;
1774                         break;
1775                 }
1776         }
1777
1778         r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
1779
1780         return r;
1781 }
1782
1783 /**
1784  * amdgpu_device_ip_init - run init for hardware IPs
1785  *
1786  * @adev: amdgpu_device pointer
1787  *
1788  * Main initialization pass for hardware IPs.  The list of all the hardware
1789  * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1790  * are run.  sw_init initializes the software state associated with each IP
1791  * and hw_init initializes the hardware associated with each IP.
1792  * Returns 0 on success, negative error code on failure.
1793  */
1794 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1795 {
1796         int i, r;
1797
1798         r = amdgpu_ras_init(adev);
1799         if (r)
1800                 return r;
1801
1802         for (i = 0; i < adev->num_ip_blocks; i++) {
1803                 if (!adev->ip_blocks[i].status.valid)
1804                         continue;
1805                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1806                 if (r) {
1807                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1808                                   adev->ip_blocks[i].version->funcs->name, r);
1809                         goto init_failed;
1810                 }
1811                 adev->ip_blocks[i].status.sw = true;
1812
1813                 /* need to do gmc hw init early so we can allocate gpu mem */
1814                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1815                         r = amdgpu_device_vram_scratch_init(adev);
1816                         if (r) {
1817                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1818                                 goto init_failed;
1819                         }
1820                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1821                         if (r) {
1822                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1823                                 goto init_failed;
1824                         }
1825                         r = amdgpu_device_wb_init(adev);
1826                         if (r) {
1827                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1828                                 goto init_failed;
1829                         }
1830                         adev->ip_blocks[i].status.hw = true;
1831
1832                         /* right after GMC hw init, we create CSA */
1833                         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1834                                 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1835                                                                 AMDGPU_GEM_DOMAIN_VRAM,
1836                                                                 AMDGPU_CSA_SIZE);
1837                                 if (r) {
1838                                         DRM_ERROR("allocate CSA failed %d\n", r);
1839                                         goto init_failed;
1840                                 }
1841                         }
1842                 }
1843         }
1844
1845         r = amdgpu_ib_pool_init(adev);
1846         if (r) {
1847                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1848                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1849                 goto init_failed;
1850         }
1851
1852         r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1853         if (r)
1854                 goto init_failed;
1855
1856         r = amdgpu_device_ip_hw_init_phase1(adev);
1857         if (r)
1858                 goto init_failed;
1859
1860         r = amdgpu_device_fw_loading(adev);
1861         if (r)
1862                 goto init_failed;
1863
1864         r = amdgpu_device_ip_hw_init_phase2(adev);
1865         if (r)
1866                 goto init_failed;
1867
1868         if (adev->gmc.xgmi.num_physical_nodes > 1)
1869                 amdgpu_xgmi_add_device(adev);
1870         amdgpu_amdkfd_device_init(adev);
1871
1872 init_failed:
1873         if (amdgpu_sriov_vf(adev)) {
1874                 if (!r)
1875                         amdgpu_virt_init_data_exchange(adev);
1876                 amdgpu_virt_release_full_gpu(adev, true);
1877         }
1878
1879         return r;
1880 }
1881
1882 /**
1883  * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1884  *
1885  * @adev: amdgpu_device pointer
1886  *
1887  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
1888  * this function before a GPU reset.  If the value is retained after a
1889  * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
1890  */
1891 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1892 {
1893         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1894 }
1895
1896 /**
1897  * amdgpu_device_check_vram_lost - check if vram is valid
1898  *
1899  * @adev: amdgpu_device pointer
1900  *
1901  * Checks the reset magic value written to the gart pointer in VRAM.
1902  * The driver calls this after a GPU reset to see if the contents of
1903  * VRAM is lost or now.
1904  * returns true if vram is lost, false if not.
1905  */
1906 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1907 {
1908         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1909                         AMDGPU_RESET_MAGIC_NUM);
1910 }
1911
1912 /**
1913  * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1914  *
1915  * @adev: amdgpu_device pointer
1916  *
1917  * The list of all the hardware IPs that make up the asic is walked and the
1918  * set_clockgating_state callbacks are run.
1919  * Late initialization pass enabling clockgating for hardware IPs.
1920  * Fini or suspend, pass disabling clockgating for hardware IPs.
1921  * Returns 0 on success, negative error code on failure.
1922  */
1923
1924 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1925                                                 enum amd_clockgating_state state)
1926 {
1927         int i, j, r;
1928
1929         if (amdgpu_emu_mode == 1)
1930                 return 0;
1931
1932         for (j = 0; j < adev->num_ip_blocks; j++) {
1933                 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1934                 if (!adev->ip_blocks[i].status.late_initialized)
1935                         continue;
1936                 /* skip CG for VCE/UVD, it's handled specially */
1937                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1938                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1939                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1940                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1941                         /* enable clockgating to save power */
1942                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1943                                                                                      state);
1944                         if (r) {
1945                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1946                                           adev->ip_blocks[i].version->funcs->name, r);
1947                                 return r;
1948                         }
1949                 }
1950         }
1951
1952         return 0;
1953 }
1954
1955 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1956 {
1957         int i, j, r;
1958
1959         if (amdgpu_emu_mode == 1)
1960                 return 0;
1961
1962         for (j = 0; j < adev->num_ip_blocks; j++) {
1963                 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1964                 if (!adev->ip_blocks[i].status.late_initialized)
1965                         continue;
1966                 /* skip CG for VCE/UVD, it's handled specially */
1967                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1968                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1969                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1970                     adev->ip_blocks[i].version->funcs->set_powergating_state) {
1971                         /* enable powergating to save power */
1972                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1973                                                                                         state);
1974                         if (r) {
1975                                 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1976                                           adev->ip_blocks[i].version->funcs->name, r);
1977                                 return r;
1978                         }
1979                 }
1980         }
1981         return 0;
1982 }
1983
1984 static int amdgpu_device_enable_mgpu_fan_boost(void)
1985 {
1986         struct amdgpu_gpu_instance *gpu_ins;
1987         struct amdgpu_device *adev;
1988         int i, ret = 0;
1989
1990         mutex_lock(&mgpu_info.mutex);
1991
1992         /*
1993          * MGPU fan boost feature should be enabled
1994          * only when there are two or more dGPUs in
1995          * the system
1996          */
1997         if (mgpu_info.num_dgpu < 2)
1998                 goto out;
1999
2000         for (i = 0; i < mgpu_info.num_dgpu; i++) {
2001                 gpu_ins = &(mgpu_info.gpu_ins[i]);
2002                 adev = gpu_ins->adev;
2003                 if (!(adev->flags & AMD_IS_APU) &&
2004                     !gpu_ins->mgpu_fan_enabled &&
2005                     adev->powerplay.pp_funcs &&
2006                     adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
2007                         ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2008                         if (ret)
2009                                 break;
2010
2011                         gpu_ins->mgpu_fan_enabled = 1;
2012                 }
2013         }
2014
2015 out:
2016         mutex_unlock(&mgpu_info.mutex);
2017
2018         return ret;
2019 }
2020
2021 /**
2022  * amdgpu_device_ip_late_init - run late init for hardware IPs
2023  *
2024  * @adev: amdgpu_device pointer
2025  *
2026  * Late initialization pass for hardware IPs.  The list of all the hardware
2027  * IPs that make up the asic is walked and the late_init callbacks are run.
2028  * late_init covers any special initialization that an IP requires
2029  * after all of the have been initialized or something that needs to happen
2030  * late in the init process.
2031  * Returns 0 on success, negative error code on failure.
2032  */
2033 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2034 {
2035         int i = 0, r;
2036
2037         for (i = 0; i < adev->num_ip_blocks; i++) {
2038                 if (!adev->ip_blocks[i].status.hw)
2039                         continue;
2040                 if (adev->ip_blocks[i].version->funcs->late_init) {
2041                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2042                         if (r) {
2043                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2044                                           adev->ip_blocks[i].version->funcs->name, r);
2045                                 return r;
2046                         }
2047                 }
2048                 adev->ip_blocks[i].status.late_initialized = true;
2049         }
2050
2051         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2052         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2053
2054         amdgpu_device_fill_reset_magic(adev);
2055
2056         r = amdgpu_device_enable_mgpu_fan_boost();
2057         if (r)
2058                 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2059
2060         /* set to low pstate by default */
2061         amdgpu_xgmi_set_pstate(adev, 0);
2062
2063         return 0;
2064 }
2065
2066 /**
2067  * amdgpu_device_ip_fini - run fini for hardware IPs
2068  *
2069  * @adev: amdgpu_device pointer
2070  *
2071  * Main teardown pass for hardware IPs.  The list of all the hardware
2072  * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2073  * are run.  hw_fini tears down the hardware associated with each IP
2074  * and sw_fini tears down any software state associated with each IP.
2075  * Returns 0 on success, negative error code on failure.
2076  */
2077 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2078 {
2079         int i, r;
2080
2081         amdgpu_ras_pre_fini(adev);
2082
2083         if (adev->gmc.xgmi.num_physical_nodes > 1)
2084                 amdgpu_xgmi_remove_device(adev);
2085
2086         amdgpu_amdkfd_device_fini(adev);
2087
2088         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2089         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2090
2091         /* need to disable SMC first */
2092         for (i = 0; i < adev->num_ip_blocks; i++) {
2093                 if (!adev->ip_blocks[i].status.hw)
2094                         continue;
2095                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2096                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2097                         /* XXX handle errors */
2098                         if (r) {
2099                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2100                                           adev->ip_blocks[i].version->funcs->name, r);
2101                         }
2102                         adev->ip_blocks[i].status.hw = false;
2103                         break;
2104                 }
2105         }
2106
2107         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2108                 if (!adev->ip_blocks[i].status.hw)
2109                         continue;
2110
2111                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2112                 /* XXX handle errors */
2113                 if (r) {
2114                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2115                                   adev->ip_blocks[i].version->funcs->name, r);
2116                 }
2117
2118                 adev->ip_blocks[i].status.hw = false;
2119         }
2120
2121
2122         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2123                 if (!adev->ip_blocks[i].status.sw)
2124                         continue;
2125
2126                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2127                         amdgpu_ucode_free_bo(adev);
2128                         amdgpu_free_static_csa(&adev->virt.csa_obj);
2129                         amdgpu_device_wb_fini(adev);
2130                         amdgpu_device_vram_scratch_fini(adev);
2131                         amdgpu_ib_pool_fini(adev);
2132                 }
2133
2134                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2135                 /* XXX handle errors */
2136                 if (r) {
2137                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2138                                   adev->ip_blocks[i].version->funcs->name, r);
2139                 }
2140                 adev->ip_blocks[i].status.sw = false;
2141                 adev->ip_blocks[i].status.valid = false;
2142         }
2143
2144         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2145                 if (!adev->ip_blocks[i].status.late_initialized)
2146                         continue;
2147                 if (adev->ip_blocks[i].version->funcs->late_fini)
2148                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2149                 adev->ip_blocks[i].status.late_initialized = false;
2150         }
2151
2152         amdgpu_ras_fini(adev);
2153
2154         if (amdgpu_sriov_vf(adev))
2155                 if (amdgpu_virt_release_full_gpu(adev, false))
2156                         DRM_ERROR("failed to release exclusive mode on fini\n");
2157
2158         return 0;
2159 }
2160
2161 /**
2162  * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2163  *
2164  * @work: work_struct.
2165  */
2166 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2167 {
2168         struct amdgpu_device *adev =
2169                 container_of(work, struct amdgpu_device, delayed_init_work.work);
2170         int r;
2171
2172         r = amdgpu_ib_ring_tests(adev);
2173         if (r)
2174                 DRM_ERROR("ib ring test failed (%d).\n", r);
2175 }
2176
2177 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2178 {
2179         struct amdgpu_device *adev =
2180                 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2181
2182         mutex_lock(&adev->gfx.gfx_off_mutex);
2183         if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2184                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2185                         adev->gfx.gfx_off_state = true;
2186         }
2187         mutex_unlock(&adev->gfx.gfx_off_mutex);
2188 }
2189
2190 /**
2191  * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2192  *
2193  * @adev: amdgpu_device pointer
2194  *
2195  * Main suspend function for hardware IPs.  The list of all the hardware
2196  * IPs that make up the asic is walked, clockgating is disabled and the
2197  * suspend callbacks are run.  suspend puts the hardware and software state
2198  * in each IP into a state suitable for suspend.
2199  * Returns 0 on success, negative error code on failure.
2200  */
2201 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2202 {
2203         int i, r;
2204
2205         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2206         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2207
2208         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2209                 if (!adev->ip_blocks[i].status.valid)
2210                         continue;
2211                 /* displays are handled separately */
2212                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2213                         /* XXX handle errors */
2214                         r = adev->ip_blocks[i].version->funcs->suspend(adev);
2215                         /* XXX handle errors */
2216                         if (r) {
2217                                 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2218                                           adev->ip_blocks[i].version->funcs->name, r);
2219                                 return r;
2220                         }
2221                         adev->ip_blocks[i].status.hw = false;
2222                 }
2223         }
2224
2225         return 0;
2226 }
2227
2228 /**
2229  * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2230  *
2231  * @adev: amdgpu_device pointer
2232  *
2233  * Main suspend function for hardware IPs.  The list of all the hardware
2234  * IPs that make up the asic is walked, clockgating is disabled and the
2235  * suspend callbacks are run.  suspend puts the hardware and software state
2236  * in each IP into a state suitable for suspend.
2237  * Returns 0 on success, negative error code on failure.
2238  */
2239 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2240 {
2241         int i, r;
2242
2243         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2244                 if (!adev->ip_blocks[i].status.valid)
2245                         continue;
2246                 /* displays are handled in phase1 */
2247                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2248                         continue;
2249                 /* XXX handle errors */
2250                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2251                 /* XXX handle errors */
2252                 if (r) {
2253                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
2254                                   adev->ip_blocks[i].version->funcs->name, r);
2255                 }
2256                 adev->ip_blocks[i].status.hw = false;
2257                 /* handle putting the SMC in the appropriate state */
2258                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2259                         if (is_support_sw_smu(adev)) {
2260                                 /* todo */
2261                         } else if (adev->powerplay.pp_funcs &&
2262                                            adev->powerplay.pp_funcs->set_mp1_state) {
2263                                 r = adev->powerplay.pp_funcs->set_mp1_state(
2264                                         adev->powerplay.pp_handle,
2265                                         adev->mp1_state);
2266                                 if (r) {
2267                                         DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2268                                                   adev->mp1_state, r);
2269                                         return r;
2270                                 }
2271                         }
2272                 }
2273
2274                 adev->ip_blocks[i].status.hw = false;
2275         }
2276
2277         return 0;
2278 }
2279
2280 /**
2281  * amdgpu_device_ip_suspend - run suspend for hardware IPs
2282  *
2283  * @adev: amdgpu_device pointer
2284  *
2285  * Main suspend function for hardware IPs.  The list of all the hardware
2286  * IPs that make up the asic is walked, clockgating is disabled and the
2287  * suspend callbacks are run.  suspend puts the hardware and software state
2288  * in each IP into a state suitable for suspend.
2289  * Returns 0 on success, negative error code on failure.
2290  */
2291 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2292 {
2293         int r;
2294
2295         if (amdgpu_sriov_vf(adev))
2296                 amdgpu_virt_request_full_gpu(adev, false);
2297
2298         r = amdgpu_device_ip_suspend_phase1(adev);
2299         if (r)
2300                 return r;
2301         r = amdgpu_device_ip_suspend_phase2(adev);
2302
2303         if (amdgpu_sriov_vf(adev))
2304                 amdgpu_virt_release_full_gpu(adev, false);
2305
2306         return r;
2307 }
2308
2309 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2310 {
2311         int i, r;
2312
2313         static enum amd_ip_block_type ip_order[] = {
2314                 AMD_IP_BLOCK_TYPE_GMC,
2315                 AMD_IP_BLOCK_TYPE_COMMON,
2316                 AMD_IP_BLOCK_TYPE_PSP,
2317                 AMD_IP_BLOCK_TYPE_IH,
2318         };
2319
2320         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2321                 int j;
2322                 struct amdgpu_ip_block *block;
2323
2324                 for (j = 0; j < adev->num_ip_blocks; j++) {
2325                         block = &adev->ip_blocks[j];
2326
2327                         block->status.hw = false;
2328                         if (block->version->type != ip_order[i] ||
2329                                 !block->status.valid)
2330                                 continue;
2331
2332                         r = block->version->funcs->hw_init(adev);
2333                         DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2334                         if (r)
2335                                 return r;
2336                         block->status.hw = true;
2337                 }
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2344 {
2345         int i, r;
2346
2347         static enum amd_ip_block_type ip_order[] = {
2348                 AMD_IP_BLOCK_TYPE_SMC,
2349                 AMD_IP_BLOCK_TYPE_DCE,
2350                 AMD_IP_BLOCK_TYPE_GFX,
2351                 AMD_IP_BLOCK_TYPE_SDMA,
2352                 AMD_IP_BLOCK_TYPE_UVD,
2353                 AMD_IP_BLOCK_TYPE_VCE
2354         };
2355
2356         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2357                 int j;
2358                 struct amdgpu_ip_block *block;
2359
2360                 for (j = 0; j < adev->num_ip_blocks; j++) {
2361                         block = &adev->ip_blocks[j];
2362
2363                         if (block->version->type != ip_order[i] ||
2364                                 !block->status.valid ||
2365                                 block->status.hw)
2366                                 continue;
2367
2368                         r = block->version->funcs->hw_init(adev);
2369                         DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2370                         if (r)
2371                                 return r;
2372                         block->status.hw = true;
2373                 }
2374         }
2375
2376         return 0;
2377 }
2378
2379 /**
2380  * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2381  *
2382  * @adev: amdgpu_device pointer
2383  *
2384  * First resume function for hardware IPs.  The list of all the hardware
2385  * IPs that make up the asic is walked and the resume callbacks are run for
2386  * COMMON, GMC, and IH.  resume puts the hardware into a functional state
2387  * after a suspend and updates the software state as necessary.  This
2388  * function is also used for restoring the GPU after a GPU reset.
2389  * Returns 0 on success, negative error code on failure.
2390  */
2391 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2392 {
2393         int i, r;
2394
2395         for (i = 0; i < adev->num_ip_blocks; i++) {
2396                 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2397                         continue;
2398                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2399                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2400                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2401
2402                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2403                         if (r) {
2404                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2405                                           adev->ip_blocks[i].version->funcs->name, r);
2406                                 return r;
2407                         }
2408                         adev->ip_blocks[i].status.hw = true;
2409                 }
2410         }
2411
2412         return 0;
2413 }
2414
2415 /**
2416  * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2417  *
2418  * @adev: amdgpu_device pointer
2419  *
2420  * First resume function for hardware IPs.  The list of all the hardware
2421  * IPs that make up the asic is walked and the resume callbacks are run for
2422  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
2423  * functional state after a suspend and updates the software state as
2424  * necessary.  This function is also used for restoring the GPU after a GPU
2425  * reset.
2426  * Returns 0 on success, negative error code on failure.
2427  */
2428 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2429 {
2430         int i, r;
2431
2432         for (i = 0; i < adev->num_ip_blocks; i++) {
2433                 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2434                         continue;
2435                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2436                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2437                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2438                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2439                         continue;
2440                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2441                 if (r) {
2442                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2443                                   adev->ip_blocks[i].version->funcs->name, r);
2444                         return r;
2445                 }
2446                 adev->ip_blocks[i].status.hw = true;
2447         }
2448
2449         return 0;
2450 }
2451
2452 /**
2453  * amdgpu_device_ip_resume - run resume for hardware IPs
2454  *
2455  * @adev: amdgpu_device pointer
2456  *
2457  * Main resume function for hardware IPs.  The hardware IPs
2458  * are split into two resume functions because they are
2459  * are also used in in recovering from a GPU reset and some additional
2460  * steps need to be take between them.  In this case (S3/S4) they are
2461  * run sequentially.
2462  * Returns 0 on success, negative error code on failure.
2463  */
2464 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2465 {
2466         int r;
2467
2468         r = amdgpu_device_ip_resume_phase1(adev);
2469         if (r)
2470                 return r;
2471
2472         r = amdgpu_device_fw_loading(adev);
2473         if (r)
2474                 return r;
2475
2476         r = amdgpu_device_ip_resume_phase2(adev);
2477
2478         return r;
2479 }
2480
2481 /**
2482  * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2483  *
2484  * @adev: amdgpu_device pointer
2485  *
2486  * Query the VBIOS data tables to determine if the board supports SR-IOV.
2487  */
2488 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2489 {
2490         if (amdgpu_sriov_vf(adev)) {
2491                 if (adev->is_atom_fw) {
2492                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2493                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2494                 } else {
2495                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2496                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2497                 }
2498
2499                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2500                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2501         }
2502 }
2503
2504 /**
2505  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2506  *
2507  * @asic_type: AMD asic type
2508  *
2509  * Check if there is DC (new modesetting infrastructre) support for an asic.
2510  * returns true if DC has support, false if not.
2511  */
2512 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2513 {
2514         switch (asic_type) {
2515 #if defined(CONFIG_DRM_AMD_DC)
2516         case CHIP_BONAIRE:
2517         case CHIP_KAVERI:
2518         case CHIP_KABINI:
2519         case CHIP_MULLINS:
2520                 /*
2521                  * We have systems in the wild with these ASICs that require
2522                  * LVDS and VGA support which is not supported with DC.
2523                  *
2524                  * Fallback to the non-DC driver here by default so as not to
2525                  * cause regressions.
2526                  */
2527                 return amdgpu_dc > 0;
2528         case CHIP_HAWAII:
2529         case CHIP_CARRIZO:
2530         case CHIP_STONEY:
2531         case CHIP_POLARIS10:
2532         case CHIP_POLARIS11:
2533         case CHIP_POLARIS12:
2534         case CHIP_VEGAM:
2535         case CHIP_TONGA:
2536         case CHIP_FIJI:
2537         case CHIP_VEGA10:
2538         case CHIP_VEGA12:
2539         case CHIP_VEGA20:
2540 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2541         case CHIP_RAVEN:
2542 #endif
2543 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2544         case CHIP_NAVI10:
2545         case CHIP_NAVI14:
2546         case CHIP_NAVI12:
2547 #endif
2548                 return amdgpu_dc != 0;
2549 #endif
2550         default:
2551                 return false;
2552         }
2553 }
2554
2555 /**
2556  * amdgpu_device_has_dc_support - check if dc is supported
2557  *
2558  * @adev: amdgpu_device_pointer
2559  *
2560  * Returns true for supported, false for not supported
2561  */
2562 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2563 {
2564         if (amdgpu_sriov_vf(adev))
2565                 return false;
2566
2567         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2568 }
2569
2570
2571 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2572 {
2573         struct amdgpu_device *adev =
2574                 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2575
2576         adev->asic_reset_res =  amdgpu_asic_reset(adev);
2577         if (adev->asic_reset_res)
2578                 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2579                          adev->asic_reset_res, adev->ddev->unique);
2580 }
2581
2582
2583 /**
2584  * amdgpu_device_init - initialize the driver
2585  *
2586  * @adev: amdgpu_device pointer
2587  * @ddev: drm dev pointer
2588  * @pdev: pci dev pointer
2589  * @flags: driver flags
2590  *
2591  * Initializes the driver info and hw (all asics).
2592  * Returns 0 for success or an error on failure.
2593  * Called at driver startup.
2594  */
2595 int amdgpu_device_init(struct amdgpu_device *adev,
2596                        struct drm_device *ddev,
2597                        struct pci_dev *pdev,
2598                        uint32_t flags)
2599 {
2600         int r, i;
2601         bool runtime = false;
2602         u32 max_MBps;
2603
2604         adev->shutdown = false;
2605         adev->dev = &pdev->dev;
2606         adev->ddev = ddev;
2607         adev->pdev = pdev;
2608         adev->flags = flags;
2609         adev->asic_type = flags & AMD_ASIC_MASK;
2610         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2611         if (amdgpu_emu_mode == 1)
2612                 adev->usec_timeout *= 2;
2613         adev->gmc.gart_size = 512 * 1024 * 1024;
2614         adev->accel_working = false;
2615         adev->num_rings = 0;
2616         adev->mman.buffer_funcs = NULL;
2617         adev->mman.buffer_funcs_ring = NULL;
2618         adev->vm_manager.vm_pte_funcs = NULL;
2619         adev->vm_manager.vm_pte_num_rqs = 0;
2620         adev->gmc.gmc_funcs = NULL;
2621         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2622         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2623
2624         adev->smc_rreg = &amdgpu_invalid_rreg;
2625         adev->smc_wreg = &amdgpu_invalid_wreg;
2626         adev->pcie_rreg = &amdgpu_invalid_rreg;
2627         adev->pcie_wreg = &amdgpu_invalid_wreg;
2628         adev->pciep_rreg = &amdgpu_invalid_rreg;
2629         adev->pciep_wreg = &amdgpu_invalid_wreg;
2630         adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
2631         adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
2632         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2633         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2634         adev->didt_rreg = &amdgpu_invalid_rreg;
2635         adev->didt_wreg = &amdgpu_invalid_wreg;
2636         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2637         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2638         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2639         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2640
2641         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2642                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2643                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2644
2645         /* mutex initialization are all done here so we
2646          * can recall function without having locking issues */
2647         atomic_set(&adev->irq.ih.lock, 0);
2648         mutex_init(&adev->firmware.mutex);
2649         mutex_init(&adev->pm.mutex);
2650         mutex_init(&adev->gfx.gpu_clock_mutex);
2651         mutex_init(&adev->srbm_mutex);
2652         mutex_init(&adev->gfx.pipe_reserve_mutex);
2653         mutex_init(&adev->gfx.gfx_off_mutex);
2654         mutex_init(&adev->grbm_idx_mutex);
2655         mutex_init(&adev->mn_lock);
2656         mutex_init(&adev->virt.vf_errors.lock);
2657         hash_init(adev->mn_hash);
2658         mutex_init(&adev->lock_reset);
2659         mutex_init(&adev->virt.dpm_mutex);
2660         mutex_init(&adev->psp.mutex);
2661
2662         r = amdgpu_device_check_arguments(adev);
2663         if (r)
2664                 return r;
2665
2666         spin_lock_init(&adev->mmio_idx_lock);
2667         spin_lock_init(&adev->smc_idx_lock);
2668         spin_lock_init(&adev->pcie_idx_lock);
2669         spin_lock_init(&adev->uvd_ctx_idx_lock);
2670         spin_lock_init(&adev->didt_idx_lock);
2671         spin_lock_init(&adev->gc_cac_idx_lock);
2672         spin_lock_init(&adev->se_cac_idx_lock);
2673         spin_lock_init(&adev->audio_endpt_idx_lock);
2674         spin_lock_init(&adev->mm_stats.lock);
2675
2676         INIT_LIST_HEAD(&adev->shadow_list);
2677         mutex_init(&adev->shadow_list_lock);
2678
2679         INIT_LIST_HEAD(&adev->ring_lru_list);
2680         spin_lock_init(&adev->ring_lru_list_lock);
2681
2682         INIT_DELAYED_WORK(&adev->delayed_init_work,
2683                           amdgpu_device_delayed_init_work_handler);
2684         INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2685                           amdgpu_device_delay_enable_gfx_off);
2686
2687         INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2688
2689         adev->gfx.gfx_off_req_count = 1;
2690         adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2691
2692         /* Registers mapping */
2693         /* TODO: block userspace mapping of io register */
2694         if (adev->asic_type >= CHIP_BONAIRE) {
2695                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2696                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2697         } else {
2698                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2699                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2700         }
2701
2702         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2703         if (adev->rmmio == NULL) {
2704                 return -ENOMEM;
2705         }
2706         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2707         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2708
2709         /* io port mapping */
2710         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2711                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2712                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2713                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2714                         break;
2715                 }
2716         }
2717         if (adev->rio_mem == NULL)
2718                 DRM_INFO("PCI I/O BAR is not found.\n");
2719
2720         /* enable PCIE atomic ops */
2721         r = pci_enable_atomic_ops_to_root(adev->pdev,
2722                                           PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
2723                                           PCI_EXP_DEVCAP2_ATOMIC_COMP64);
2724         if (r) {
2725                 adev->have_atomics_support = false;
2726                 DRM_INFO("PCIE atomic ops is not supported\n");
2727         } else {
2728                 adev->have_atomics_support = true;
2729         }
2730
2731         amdgpu_device_get_pcie_info(adev);
2732
2733         if (amdgpu_mcbp)
2734                 DRM_INFO("MCBP is enabled\n");
2735
2736         if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
2737                 adev->enable_mes = true;
2738
2739         if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) {
2740                 r = amdgpu_discovery_init(adev);
2741                 if (r) {
2742                         dev_err(adev->dev, "amdgpu_discovery_init failed\n");
2743                         return r;
2744                 }
2745         }
2746
2747         /* early init functions */
2748         r = amdgpu_device_ip_early_init(adev);
2749         if (r)
2750                 return r;
2751
2752         /* doorbell bar mapping and doorbell index init*/
2753         amdgpu_device_doorbell_init(adev);
2754
2755         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2756         /* this will fail for cards that aren't VGA class devices, just
2757          * ignore it */
2758         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2759
2760         if (amdgpu_device_is_px(ddev))
2761                 runtime = true;
2762         if (!pci_is_thunderbolt_attached(adev->pdev))
2763                 vga_switcheroo_register_client(adev->pdev,
2764                                                &amdgpu_switcheroo_ops, runtime);
2765         if (runtime)
2766                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2767
2768         if (amdgpu_emu_mode == 1) {
2769                 /* post the asic on emulation mode */
2770                 emu_soc_asic_init(adev);
2771                 goto fence_driver_init;
2772         }
2773
2774         /* detect if we are with an SRIOV vbios */
2775         amdgpu_device_detect_sriov_bios(adev);
2776
2777         /* check if we need to reset the asic
2778          *  E.g., driver was not cleanly unloaded previously, etc.
2779          */
2780         if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2781                 r = amdgpu_asic_reset(adev);
2782                 if (r) {
2783                         dev_err(adev->dev, "asic reset on init failed\n");
2784                         goto failed;
2785                 }
2786         }
2787
2788         /* Post card if necessary */
2789         if (amdgpu_device_need_post(adev)) {
2790                 if (!adev->bios) {
2791                         dev_err(adev->dev, "no vBIOS found\n");
2792                         r = -EINVAL;
2793                         goto failed;
2794                 }
2795                 DRM_INFO("GPU posting now...\n");
2796                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2797                 if (r) {
2798                         dev_err(adev->dev, "gpu post error!\n");
2799                         goto failed;
2800                 }
2801         }
2802
2803         if (adev->is_atom_fw) {
2804                 /* Initialize clocks */
2805                 r = amdgpu_atomfirmware_get_clock_info(adev);
2806                 if (r) {
2807                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2808                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2809                         goto failed;
2810                 }
2811         } else {
2812                 /* Initialize clocks */
2813                 r = amdgpu_atombios_get_clock_info(adev);
2814                 if (r) {
2815                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2816                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2817                         goto failed;
2818                 }
2819                 /* init i2c buses */
2820                 if (!amdgpu_device_has_dc_support(adev))
2821                         amdgpu_atombios_i2c_init(adev);
2822         }
2823
2824 fence_driver_init:
2825         /* Fence driver */
2826         r = amdgpu_fence_driver_init(adev);
2827         if (r) {
2828                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2829                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2830                 goto failed;
2831         }
2832
2833         /* init the mode config */
2834         drm_mode_config_init(adev->ddev);
2835
2836         r = amdgpu_device_ip_init(adev);
2837         if (r) {
2838                 /* failed in exclusive mode due to timeout */
2839                 if (amdgpu_sriov_vf(adev) &&
2840                     !amdgpu_sriov_runtime(adev) &&
2841                     amdgpu_virt_mmio_blocked(adev) &&
2842                     !amdgpu_virt_wait_reset(adev)) {
2843                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2844                         /* Don't send request since VF is inactive. */
2845                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2846                         adev->virt.ops = NULL;
2847                         r = -EAGAIN;
2848                         goto failed;
2849                 }
2850                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2851                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2852                 if (amdgpu_virt_request_full_gpu(adev, false))
2853                         amdgpu_virt_release_full_gpu(adev, false);
2854                 goto failed;
2855         }
2856
2857         adev->accel_working = true;
2858
2859         amdgpu_vm_check_compute_bug(adev);
2860
2861         /* Initialize the buffer migration limit. */
2862         if (amdgpu_moverate >= 0)
2863                 max_MBps = amdgpu_moverate;
2864         else
2865                 max_MBps = 8; /* Allow 8 MB/s. */
2866         /* Get a log2 for easy divisions. */
2867         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2868
2869         amdgpu_fbdev_init(adev);
2870
2871         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
2872                 amdgpu_pm_virt_sysfs_init(adev);
2873
2874         r = amdgpu_pm_sysfs_init(adev);
2875         if (r)
2876                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2877
2878         r = amdgpu_ucode_sysfs_init(adev);
2879         if (r)
2880                 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
2881
2882         r = amdgpu_debugfs_gem_init(adev);
2883         if (r)
2884                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2885
2886         r = amdgpu_debugfs_regs_init(adev);
2887         if (r)
2888                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2889
2890         r = amdgpu_debugfs_firmware_init(adev);
2891         if (r)
2892                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2893
2894         r = amdgpu_debugfs_init(adev);
2895         if (r)
2896                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2897
2898         if ((amdgpu_testing & 1)) {
2899                 if (adev->accel_working)
2900                         amdgpu_test_moves(adev);
2901                 else
2902                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2903         }
2904         if (amdgpu_benchmarking) {
2905                 if (adev->accel_working)
2906                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2907                 else
2908                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2909         }
2910
2911         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2912          * explicit gating rather than handling it automatically.
2913          */
2914         r = amdgpu_device_ip_late_init(adev);
2915         if (r) {
2916                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2917                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2918                 goto failed;
2919         }
2920
2921         /* must succeed. */
2922         amdgpu_ras_resume(adev);
2923
2924         queue_delayed_work(system_wq, &adev->delayed_init_work,
2925                            msecs_to_jiffies(AMDGPU_RESUME_MS));
2926
2927         r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
2928         if (r) {
2929                 dev_err(adev->dev, "Could not create pcie_replay_count");
2930                 return r;
2931         }
2932
2933         if (IS_ENABLED(CONFIG_PERF_EVENTS))
2934                 r = amdgpu_pmu_init(adev);
2935         if (r)
2936                 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
2937
2938         return 0;
2939
2940 failed:
2941         amdgpu_vf_error_trans_all(adev);
2942         if (runtime)
2943                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2944
2945         return r;
2946 }
2947
2948 /**
2949  * amdgpu_device_fini - tear down the driver
2950  *
2951  * @adev: amdgpu_device pointer
2952  *
2953  * Tear down the driver info (all asics).
2954  * Called at driver shutdown.
2955  */
2956 void amdgpu_device_fini(struct amdgpu_device *adev)
2957 {
2958         int r;
2959
2960         DRM_INFO("amdgpu: finishing device.\n");
2961         adev->shutdown = true;
2962         /* disable all interrupts */
2963         amdgpu_irq_disable_all(adev);
2964         if (adev->mode_info.mode_config_initialized){
2965                 if (!amdgpu_device_has_dc_support(adev))
2966                         drm_helper_force_disable_all(adev->ddev);
2967                 else
2968                         drm_atomic_helper_shutdown(adev->ddev);
2969         }
2970         amdgpu_fence_driver_fini(adev);
2971         amdgpu_pm_sysfs_fini(adev);
2972         amdgpu_fbdev_fini(adev);
2973         r = amdgpu_device_ip_fini(adev);
2974         if (adev->firmware.gpu_info_fw) {
2975                 release_firmware(adev->firmware.gpu_info_fw);
2976                 adev->firmware.gpu_info_fw = NULL;
2977         }
2978         adev->accel_working = false;
2979         cancel_delayed_work_sync(&adev->delayed_init_work);
2980         /* free i2c buses */
2981         if (!amdgpu_device_has_dc_support(adev))
2982                 amdgpu_i2c_fini(adev);
2983
2984         if (amdgpu_emu_mode != 1)
2985                 amdgpu_atombios_fini(adev);
2986
2987         kfree(adev->bios);
2988         adev->bios = NULL;
2989         if (!pci_is_thunderbolt_attached(adev->pdev))
2990                 vga_switcheroo_unregister_client(adev->pdev);
2991         if (adev->flags & AMD_IS_PX)
2992                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2993         vga_client_register(adev->pdev, NULL, NULL, NULL);
2994         if (adev->rio_mem)
2995                 pci_iounmap(adev->pdev, adev->rio_mem);
2996         adev->rio_mem = NULL;
2997         iounmap(adev->rmmio);
2998         adev->rmmio = NULL;
2999         amdgpu_device_doorbell_fini(adev);
3000         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
3001                 amdgpu_pm_virt_sysfs_fini(adev);
3002
3003         amdgpu_debugfs_regs_cleanup(adev);
3004         device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
3005         amdgpu_ucode_sysfs_fini(adev);
3006         if (IS_ENABLED(CONFIG_PERF_EVENTS))
3007                 amdgpu_pmu_fini(adev);
3008         amdgpu_debugfs_preempt_cleanup(adev);
3009         if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
3010                 amdgpu_discovery_fini(adev);
3011 }
3012
3013
3014 /*
3015  * Suspend & resume.
3016  */
3017 /**
3018  * amdgpu_device_suspend - initiate device suspend
3019  *
3020  * @dev: drm dev pointer
3021  * @suspend: suspend state
3022  * @fbcon : notify the fbdev of suspend
3023  *
3024  * Puts the hw in the suspend state (all asics).
3025  * Returns 0 for success or an error on failure.
3026  * Called at driver suspend.
3027  */
3028 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
3029 {
3030         struct amdgpu_device *adev;
3031         struct drm_crtc *crtc;
3032         struct drm_connector *connector;
3033         int r;
3034
3035         if (dev == NULL || dev->dev_private == NULL) {
3036                 return -ENODEV;
3037         }
3038
3039         adev = dev->dev_private;
3040
3041         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3042                 return 0;
3043
3044         adev->in_suspend = true;
3045         drm_kms_helper_poll_disable(dev);
3046
3047         if (fbcon)
3048                 amdgpu_fbdev_set_suspend(adev, 1);
3049
3050         cancel_delayed_work_sync(&adev->delayed_init_work);
3051
3052         if (!amdgpu_device_has_dc_support(adev)) {
3053                 /* turn off display hw */
3054                 drm_modeset_lock_all(dev);
3055                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3056                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
3057                 }
3058                 drm_modeset_unlock_all(dev);
3059                         /* unpin the front buffers and cursors */
3060                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3061                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3062                         struct drm_framebuffer *fb = crtc->primary->fb;
3063                         struct amdgpu_bo *robj;
3064
3065                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3066                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3067                                 r = amdgpu_bo_reserve(aobj, true);
3068                                 if (r == 0) {
3069                                         amdgpu_bo_unpin(aobj);
3070                                         amdgpu_bo_unreserve(aobj);
3071                                 }
3072                         }
3073
3074                         if (fb == NULL || fb->obj[0] == NULL) {
3075                                 continue;
3076                         }
3077                         robj = gem_to_amdgpu_bo(fb->obj[0]);
3078                         /* don't unpin kernel fb objects */
3079                         if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3080                                 r = amdgpu_bo_reserve(robj, true);
3081                                 if (r == 0) {
3082                                         amdgpu_bo_unpin(robj);
3083                                         amdgpu_bo_unreserve(robj);
3084                                 }
3085                         }
3086                 }
3087         }
3088
3089         amdgpu_amdkfd_suspend(adev);
3090
3091         amdgpu_ras_suspend(adev);
3092
3093         r = amdgpu_device_ip_suspend_phase1(adev);
3094
3095         /* evict vram memory */
3096         amdgpu_bo_evict_vram(adev);
3097
3098         amdgpu_fence_driver_suspend(adev);
3099
3100         r = amdgpu_device_ip_suspend_phase2(adev);
3101
3102         /* evict remaining vram memory
3103          * This second call to evict vram is to evict the gart page table
3104          * using the CPU.
3105          */
3106         amdgpu_bo_evict_vram(adev);
3107
3108         pci_save_state(dev->pdev);
3109         if (suspend) {
3110                 /* Shut down the device */
3111                 pci_disable_device(dev->pdev);
3112                 pci_set_power_state(dev->pdev, PCI_D3hot);
3113         } else {
3114                 r = amdgpu_asic_reset(adev);
3115                 if (r)
3116                         DRM_ERROR("amdgpu asic reset failed\n");
3117         }
3118
3119         return 0;
3120 }
3121
3122 /**
3123  * amdgpu_device_resume - initiate device resume
3124  *
3125  * @dev: drm dev pointer
3126  * @resume: resume state
3127  * @fbcon : notify the fbdev of resume
3128  *
3129  * Bring the hw back to operating state (all asics).
3130  * Returns 0 for success or an error on failure.
3131  * Called at driver resume.
3132  */
3133 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
3134 {
3135         struct drm_connector *connector;
3136         struct amdgpu_device *adev = dev->dev_private;
3137         struct drm_crtc *crtc;
3138         int r = 0;
3139
3140         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3141                 return 0;
3142
3143         if (resume) {
3144                 pci_set_power_state(dev->pdev, PCI_D0);
3145                 pci_restore_state(dev->pdev);
3146                 r = pci_enable_device(dev->pdev);
3147                 if (r)
3148                         return r;
3149         }
3150
3151         /* post card */
3152         if (amdgpu_device_need_post(adev)) {
3153                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
3154                 if (r)
3155                         DRM_ERROR("amdgpu asic init failed\n");
3156         }
3157
3158         r = amdgpu_device_ip_resume(adev);
3159         if (r) {
3160                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
3161                 return r;
3162         }
3163         amdgpu_fence_driver_resume(adev);
3164
3165
3166         r = amdgpu_device_ip_late_init(adev);
3167         if (r)
3168                 return r;
3169
3170         queue_delayed_work(system_wq, &adev->delayed_init_work,
3171                            msecs_to_jiffies(AMDGPU_RESUME_MS));
3172
3173         if (!amdgpu_device_has_dc_support(adev)) {
3174                 /* pin cursors */
3175                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3176                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3177
3178                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3179                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3180                                 r = amdgpu_bo_reserve(aobj, true);
3181                                 if (r == 0) {
3182                                         r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3183                                         if (r != 0)
3184                                                 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
3185                                         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3186                                         amdgpu_bo_unreserve(aobj);
3187                                 }
3188                         }
3189                 }
3190         }
3191         r = amdgpu_amdkfd_resume(adev);
3192         if (r)
3193                 return r;
3194
3195         /* Make sure IB tests flushed */
3196         flush_delayed_work(&adev->delayed_init_work);
3197
3198         /* blat the mode back in */
3199         if (fbcon) {
3200                 if (!amdgpu_device_has_dc_support(adev)) {
3201                         /* pre DCE11 */
3202                         drm_helper_resume_force_mode(dev);
3203
3204                         /* turn on display hw */
3205                         drm_modeset_lock_all(dev);
3206                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3207                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
3208                         }
3209                         drm_modeset_unlock_all(dev);
3210                 }
3211                 amdgpu_fbdev_set_suspend(adev, 0);
3212         }
3213
3214         drm_kms_helper_poll_enable(dev);
3215
3216         amdgpu_ras_resume(adev);
3217
3218         /*
3219          * Most of the connector probing functions try to acquire runtime pm
3220          * refs to ensure that the GPU is powered on when connector polling is
3221          * performed. Since we're calling this from a runtime PM callback,
3222          * trying to acquire rpm refs will cause us to deadlock.
3223          *
3224          * Since we're guaranteed to be holding the rpm lock, it's safe to
3225          * temporarily disable the rpm helpers so this doesn't deadlock us.
3226          */
3227 #ifdef CONFIG_PM
3228         dev->dev->power.disable_depth++;
3229 #endif
3230         if (!amdgpu_device_has_dc_support(adev))
3231                 drm_helper_hpd_irq_event(dev);
3232         else
3233                 drm_kms_helper_hotplug_event(dev);
3234 #ifdef CONFIG_PM
3235         dev->dev->power.disable_depth--;
3236 #endif
3237         adev->in_suspend = false;
3238
3239         return 0;
3240 }
3241
3242 /**
3243  * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3244  *
3245  * @adev: amdgpu_device pointer
3246  *
3247  * The list of all the hardware IPs that make up the asic is walked and
3248  * the check_soft_reset callbacks are run.  check_soft_reset determines
3249  * if the asic is still hung or not.
3250  * Returns true if any of the IPs are still in a hung state, false if not.
3251  */
3252 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3253 {
3254         int i;
3255         bool asic_hang = false;
3256
3257         if (amdgpu_sriov_vf(adev))
3258                 return true;
3259
3260         if (amdgpu_asic_need_full_reset(adev))
3261                 return true;
3262
3263         for (i = 0; i < adev->num_ip_blocks; i++) {
3264                 if (!adev->ip_blocks[i].status.valid)
3265                         continue;
3266                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3267                         adev->ip_blocks[i].status.hang =
3268                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3269                 if (adev->ip_blocks[i].status.hang) {
3270                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3271                         asic_hang = true;
3272                 }
3273         }
3274         return asic_hang;
3275 }
3276
3277 /**
3278  * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3279  *
3280  * @adev: amdgpu_device pointer
3281  *
3282  * The list of all the hardware IPs that make up the asic is walked and the
3283  * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
3284  * handles any IP specific hardware or software state changes that are
3285  * necessary for a soft reset to succeed.
3286  * Returns 0 on success, negative error code on failure.
3287  */
3288 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3289 {
3290         int i, r = 0;
3291
3292         for (i = 0; i < adev->num_ip_blocks; i++) {
3293                 if (!adev->ip_blocks[i].status.valid)
3294                         continue;
3295                 if (adev->ip_blocks[i].status.hang &&
3296                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3297                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3298                         if (r)
3299                                 return r;
3300                 }
3301         }
3302
3303         return 0;
3304 }
3305
3306 /**
3307  * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3308  *
3309  * @adev: amdgpu_device pointer
3310  *
3311  * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
3312  * reset is necessary to recover.
3313  * Returns true if a full asic reset is required, false if not.
3314  */
3315 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3316 {
3317         int i;
3318
3319         if (amdgpu_asic_need_full_reset(adev))
3320                 return true;
3321
3322         for (i = 0; i < adev->num_ip_blocks; i++) {
3323                 if (!adev->ip_blocks[i].status.valid)
3324                         continue;
3325                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3326                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3327                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3328                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3329                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3330                         if (adev->ip_blocks[i].status.hang) {
3331                                 DRM_INFO("Some block need full reset!\n");
3332                                 return true;
3333                         }
3334                 }
3335         }
3336         return false;
3337 }
3338
3339 /**
3340  * amdgpu_device_ip_soft_reset - do a soft reset
3341  *
3342  * @adev: amdgpu_device pointer
3343  *
3344  * The list of all the hardware IPs that make up the asic is walked and the
3345  * soft_reset callbacks are run if the block is hung.  soft_reset handles any
3346  * IP specific hardware or software state changes that are necessary to soft
3347  * reset the IP.
3348  * Returns 0 on success, negative error code on failure.
3349  */
3350 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3351 {
3352         int i, r = 0;
3353
3354         for (i = 0; i < adev->num_ip_blocks; i++) {
3355                 if (!adev->ip_blocks[i].status.valid)
3356                         continue;
3357                 if (adev->ip_blocks[i].status.hang &&
3358                     adev->ip_blocks[i].version->funcs->soft_reset) {
3359                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3360                         if (r)
3361                                 return r;
3362                 }
3363         }
3364
3365         return 0;
3366 }
3367
3368 /**
3369  * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3370  *
3371  * @adev: amdgpu_device pointer
3372  *
3373  * The list of all the hardware IPs that make up the asic is walked and the
3374  * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
3375  * handles any IP specific hardware or software state changes that are
3376  * necessary after the IP has been soft reset.
3377  * Returns 0 on success, negative error code on failure.
3378  */
3379 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3380 {
3381         int i, r = 0;
3382
3383         for (i = 0; i < adev->num_ip_blocks; i++) {
3384                 if (!adev->ip_blocks[i].status.valid)
3385                         continue;
3386                 if (adev->ip_blocks[i].status.hang &&
3387                     adev->ip_blocks[i].version->funcs->post_soft_reset)
3388                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3389                 if (r)
3390                         return r;
3391         }
3392
3393         return 0;
3394 }
3395
3396 /**
3397  * amdgpu_device_recover_vram - Recover some VRAM contents
3398  *
3399  * @adev: amdgpu_device pointer
3400  *
3401  * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
3402  * restore things like GPUVM page tables after a GPU reset where
3403  * the contents of VRAM might be lost.
3404  *
3405  * Returns:
3406  * 0 on success, negative error code on failure.
3407  */
3408 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3409 {
3410         struct dma_fence *fence = NULL, *next = NULL;
3411         struct amdgpu_bo *shadow;
3412         long r = 1, tmo;
3413
3414         if (amdgpu_sriov_runtime(adev))
3415                 tmo = msecs_to_jiffies(8000);
3416         else
3417                 tmo = msecs_to_jiffies(100);
3418
3419         DRM_INFO("recover vram bo from shadow start\n");
3420         mutex_lock(&adev->shadow_list_lock);
3421         list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3422
3423                 /* No need to recover an evicted BO */
3424                 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3425                     shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3426                     shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3427                         continue;
3428
3429                 r = amdgpu_bo_restore_shadow(shadow, &next);
3430                 if (r)
3431                         break;
3432
3433                 if (fence) {
3434                         tmo = dma_fence_wait_timeout(fence, false, tmo);
3435                         dma_fence_put(fence);
3436                         fence = next;
3437                         if (tmo == 0) {
3438                                 r = -ETIMEDOUT;
3439                                 break;
3440                         } else if (tmo < 0) {
3441                                 r = tmo;
3442                                 break;
3443                         }
3444                 } else {
3445                         fence = next;
3446                 }
3447         }
3448         mutex_unlock(&adev->shadow_list_lock);
3449
3450         if (fence)
3451                 tmo = dma_fence_wait_timeout(fence, false, tmo);
3452         dma_fence_put(fence);
3453
3454         if (r < 0 || tmo <= 0) {
3455                 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3456                 return -EIO;
3457         }
3458
3459         DRM_INFO("recover vram bo from shadow done\n");
3460         return 0;
3461 }
3462
3463
3464 /**
3465  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3466  *
3467  * @adev: amdgpu device pointer
3468  * @from_hypervisor: request from hypervisor
3469  *
3470  * do VF FLR and reinitialize Asic
3471  * return 0 means succeeded otherwise failed
3472  */
3473 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3474                                      bool from_hypervisor)
3475 {
3476         int r;
3477
3478         if (from_hypervisor)
3479                 r = amdgpu_virt_request_full_gpu(adev, true);
3480         else
3481                 r = amdgpu_virt_reset_gpu(adev);
3482         if (r)
3483                 return r;
3484
3485         amdgpu_amdkfd_pre_reset(adev);
3486
3487         /* Resume IP prior to SMC */
3488         r = amdgpu_device_ip_reinit_early_sriov(adev);
3489         if (r)
3490                 goto error;
3491
3492         /* we need recover gart prior to run SMC/CP/SDMA resume */
3493         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3494
3495         r = amdgpu_device_fw_loading(adev);
3496         if (r)
3497                 return r;
3498
3499         /* now we are okay to resume SMC/CP/SDMA */
3500         r = amdgpu_device_ip_reinit_late_sriov(adev);
3501         if (r)
3502                 goto error;
3503
3504         amdgpu_irq_gpu_reset_resume_helper(adev);
3505         r = amdgpu_ib_ring_tests(adev);
3506         amdgpu_amdkfd_post_reset(adev);
3507
3508 error:
3509         amdgpu_virt_init_data_exchange(adev);
3510         amdgpu_virt_release_full_gpu(adev, true);
3511         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3512                 atomic_inc(&adev->vram_lost_counter);
3513                 r = amdgpu_device_recover_vram(adev);
3514         }
3515
3516         return r;
3517 }
3518
3519 /**
3520  * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3521  *
3522  * @adev: amdgpu device pointer
3523  *
3524  * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3525  * a hung GPU.
3526  */
3527 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3528 {
3529         if (!amdgpu_device_ip_check_soft_reset(adev)) {
3530                 DRM_INFO("Timeout, but no hardware hang detected.\n");
3531                 return false;
3532         }
3533
3534         if (amdgpu_gpu_recovery == 0)
3535                 goto disabled;
3536
3537         if (amdgpu_sriov_vf(adev))
3538                 return true;
3539
3540         if (amdgpu_gpu_recovery == -1) {
3541                 switch (adev->asic_type) {
3542                 case CHIP_BONAIRE:
3543                 case CHIP_HAWAII:
3544                 case CHIP_TOPAZ:
3545                 case CHIP_TONGA:
3546                 case CHIP_FIJI:
3547                 case CHIP_POLARIS10:
3548                 case CHIP_POLARIS11:
3549                 case CHIP_POLARIS12:
3550                 case CHIP_VEGAM:
3551                 case CHIP_VEGA20:
3552                 case CHIP_VEGA10:
3553                 case CHIP_VEGA12:
3554                         break;
3555                 default:
3556                         goto disabled;
3557                 }
3558         }
3559
3560         return true;
3561
3562 disabled:
3563                 DRM_INFO("GPU recovery disabled.\n");
3564                 return false;
3565 }
3566
3567
3568 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3569                                         struct amdgpu_job *job,
3570                                         bool *need_full_reset_arg)
3571 {
3572         int i, r = 0;
3573         bool need_full_reset  = *need_full_reset_arg;
3574
3575         /* block all schedulers and reset given job's ring */
3576         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3577                 struct amdgpu_ring *ring = adev->rings[i];
3578
3579                 if (!ring || !ring->sched.thread)
3580                         continue;
3581
3582                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3583                 amdgpu_fence_driver_force_completion(ring);
3584         }
3585
3586         if(job)
3587                 drm_sched_increase_karma(&job->base);
3588
3589         /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
3590         if (!amdgpu_sriov_vf(adev)) {
3591
3592                 if (!need_full_reset)
3593                         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3594
3595                 if (!need_full_reset) {
3596                         amdgpu_device_ip_pre_soft_reset(adev);
3597                         r = amdgpu_device_ip_soft_reset(adev);
3598                         amdgpu_device_ip_post_soft_reset(adev);
3599                         if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3600                                 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3601                                 need_full_reset = true;
3602                         }
3603                 }
3604
3605                 if (need_full_reset)
3606                         r = amdgpu_device_ip_suspend(adev);
3607
3608                 *need_full_reset_arg = need_full_reset;
3609         }
3610
3611         return r;
3612 }
3613
3614 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3615                                struct list_head *device_list_handle,
3616                                bool *need_full_reset_arg)
3617 {
3618         struct amdgpu_device *tmp_adev = NULL;
3619         bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3620         int r = 0;
3621
3622         /*
3623          * ASIC reset has to be done on all HGMI hive nodes ASAP
3624          * to allow proper links negotiation in FW (within 1 sec)
3625          */
3626         if (need_full_reset) {
3627                 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3628                         /* For XGMI run all resets in parallel to speed up the process */
3629                         if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3630                                 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3631                                         r = -EALREADY;
3632                         } else
3633                                 r = amdgpu_asic_reset(tmp_adev);
3634
3635                         if (r) {
3636                                 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3637                                          r, tmp_adev->ddev->unique);
3638                                 break;
3639                         }
3640                 }
3641
3642                 /* For XGMI wait for all PSP resets to complete before proceed */
3643                 if (!r) {
3644                         list_for_each_entry(tmp_adev, device_list_handle,
3645                                             gmc.xgmi.head) {
3646                                 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3647                                         flush_work(&tmp_adev->xgmi_reset_work);
3648                                         r = tmp_adev->asic_reset_res;
3649                                         if (r)
3650                                                 break;
3651                                 }
3652                         }
3653
3654                         list_for_each_entry(tmp_adev, device_list_handle,
3655                                         gmc.xgmi.head) {
3656                                 amdgpu_ras_reserve_bad_pages(tmp_adev);
3657                         }
3658                 }
3659         }
3660
3661
3662         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3663                 if (need_full_reset) {
3664                         /* post card */
3665                         if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3666                                 DRM_WARN("asic atom init failed!");
3667
3668                         if (!r) {
3669                                 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3670                                 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3671                                 if (r)
3672                                         goto out;
3673
3674                                 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3675                                 if (vram_lost) {
3676                                         DRM_INFO("VRAM is lost due to GPU reset!\n");
3677                                         atomic_inc(&tmp_adev->vram_lost_counter);
3678                                 }
3679
3680                                 r = amdgpu_gtt_mgr_recover(
3681                                         &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3682                                 if (r)
3683                                         goto out;
3684
3685                                 r = amdgpu_device_fw_loading(tmp_adev);
3686                                 if (r)
3687                                         return r;
3688
3689                                 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3690                                 if (r)
3691                                         goto out;
3692
3693                                 if (vram_lost)
3694                                         amdgpu_device_fill_reset_magic(tmp_adev);
3695
3696                                 /*
3697                                  * Add this ASIC as tracked as reset was already
3698                                  * complete successfully.
3699                                  */
3700                                 amdgpu_register_gpu_instance(tmp_adev);
3701
3702                                 r = amdgpu_device_ip_late_init(tmp_adev);
3703                                 if (r)
3704                                         goto out;
3705
3706                                 /* must succeed. */
3707                                 amdgpu_ras_resume(tmp_adev);
3708
3709                                 /* Update PSP FW topology after reset */
3710                                 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3711                                         r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3712                         }
3713                 }
3714
3715
3716 out:
3717                 if (!r) {
3718                         amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3719                         r = amdgpu_ib_ring_tests(tmp_adev);
3720                         if (r) {
3721                                 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3722                                 r = amdgpu_device_ip_suspend(tmp_adev);
3723                                 need_full_reset = true;
3724                                 r = -EAGAIN;
3725                                 goto end;
3726                         }
3727                 }
3728
3729                 if (!r)
3730                         r = amdgpu_device_recover_vram(tmp_adev);
3731                 else
3732                         tmp_adev->asic_reset_res = r;
3733         }
3734
3735 end:
3736         *need_full_reset_arg = need_full_reset;
3737         return r;
3738 }
3739
3740 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
3741 {
3742         if (trylock) {
3743                 if (!mutex_trylock(&adev->lock_reset))
3744                         return false;
3745         } else
3746                 mutex_lock(&adev->lock_reset);
3747
3748         atomic_inc(&adev->gpu_reset_counter);
3749         adev->in_gpu_reset = 1;
3750         switch (amdgpu_asic_reset_method(adev)) {
3751         case AMD_RESET_METHOD_MODE1:
3752                 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
3753                 break;
3754         case AMD_RESET_METHOD_MODE2:
3755                 adev->mp1_state = PP_MP1_STATE_RESET;
3756                 break;
3757         default:
3758                 adev->mp1_state = PP_MP1_STATE_NONE;
3759                 break;
3760         }
3761         /* Block kfd: SRIOV would do it separately */
3762         if (!amdgpu_sriov_vf(adev))
3763                 amdgpu_amdkfd_pre_reset(adev);
3764
3765         return true;
3766 }
3767
3768 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3769 {
3770         /*unlock kfd: SRIOV would do it separately */
3771         if (!amdgpu_sriov_vf(adev))
3772                 amdgpu_amdkfd_post_reset(adev);
3773         amdgpu_vf_error_trans_all(adev);
3774         adev->mp1_state = PP_MP1_STATE_NONE;
3775         adev->in_gpu_reset = 0;
3776         mutex_unlock(&adev->lock_reset);
3777 }
3778
3779
3780 /**
3781  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3782  *
3783  * @adev: amdgpu device pointer
3784  * @job: which job trigger hang
3785  *
3786  * Attempt to reset the GPU if it has hung (all asics).
3787  * Attempt to do soft-reset or full-reset and reinitialize Asic
3788  * Returns 0 for success or an error on failure.
3789  */
3790
3791 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3792                               struct amdgpu_job *job)
3793 {
3794         struct list_head device_list, *device_list_handle =  NULL;
3795         bool need_full_reset, job_signaled;
3796         struct amdgpu_hive_info *hive = NULL;
3797         struct amdgpu_device *tmp_adev = NULL;
3798         int i, r = 0;
3799
3800         need_full_reset = job_signaled = false;
3801         INIT_LIST_HEAD(&device_list);
3802
3803         dev_info(adev->dev, "GPU reset begin!\n");
3804
3805         cancel_delayed_work_sync(&adev->delayed_init_work);
3806
3807         hive = amdgpu_get_xgmi_hive(adev, false);
3808
3809         /*
3810          * Here we trylock to avoid chain of resets executing from
3811          * either trigger by jobs on different adevs in XGMI hive or jobs on
3812          * different schedulers for same device while this TO handler is running.
3813          * We always reset all schedulers for device and all devices for XGMI
3814          * hive so that should take care of them too.
3815          */
3816
3817         if (hive && !mutex_trylock(&hive->reset_lock)) {
3818                 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
3819                          job->base.id, hive->hive_id);
3820                 return 0;
3821         }
3822
3823         /* Start with adev pre asic reset first for soft reset check.*/
3824         if (!amdgpu_device_lock_adev(adev, !hive)) {
3825                 DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
3826                                          job->base.id);
3827                 return 0;
3828         }
3829
3830         /* Build list of devices to reset */
3831         if  (adev->gmc.xgmi.num_physical_nodes > 1) {
3832                 if (!hive) {
3833                         amdgpu_device_unlock_adev(adev);
3834                         return -ENODEV;
3835                 }
3836
3837                 /*
3838                  * In case we are in XGMI hive mode device reset is done for all the
3839                  * nodes in the hive to retrain all XGMI links and hence the reset
3840                  * sequence is executed in loop on all nodes.
3841                  */
3842                 device_list_handle = &hive->device_list;
3843         } else {
3844                 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3845                 device_list_handle = &device_list;
3846         }
3847
3848         /*
3849          * Mark these ASICs to be reseted as untracked first
3850          * And add them back after reset completed
3851          */
3852         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head)
3853                 amdgpu_unregister_gpu_instance(tmp_adev);
3854
3855         /* block all schedulers and reset given job's ring */
3856         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3857                 /* disable ras on ALL IPs */
3858                 if (amdgpu_device_ip_need_full_reset(tmp_adev))
3859                         amdgpu_ras_suspend(tmp_adev);
3860
3861                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3862                         struct amdgpu_ring *ring = tmp_adev->rings[i];
3863
3864                         if (!ring || !ring->sched.thread)
3865                                 continue;
3866
3867                         drm_sched_stop(&ring->sched, &job->base);
3868                 }
3869         }
3870
3871
3872         /*
3873          * Must check guilty signal here since after this point all old
3874          * HW fences are force signaled.
3875          *
3876          * job->base holds a reference to parent fence
3877          */
3878         if (job && job->base.s_fence->parent &&
3879             dma_fence_is_signaled(job->base.s_fence->parent))
3880                 job_signaled = true;
3881
3882         if (!amdgpu_device_ip_need_full_reset(adev))
3883                 device_list_handle = &device_list;
3884
3885         if (job_signaled) {
3886                 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
3887                 goto skip_hw_reset;
3888         }
3889
3890
3891         /* Guilty job will be freed after this*/
3892         r = amdgpu_device_pre_asic_reset(adev,
3893                                          job,
3894                                          &need_full_reset);
3895         if (r) {
3896                 /*TODO Should we stop ?*/
3897                 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3898                           r, adev->ddev->unique);
3899                 adev->asic_reset_res = r;
3900         }
3901
3902 retry:  /* Rest of adevs pre asic reset from XGMI hive. */
3903         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3904
3905                 if (tmp_adev == adev)
3906                         continue;
3907
3908                 amdgpu_device_lock_adev(tmp_adev, false);
3909                 r = amdgpu_device_pre_asic_reset(tmp_adev,
3910                                                  NULL,
3911                                                  &need_full_reset);
3912                 /*TODO Should we stop ?*/
3913                 if (r) {
3914                         DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3915                                   r, tmp_adev->ddev->unique);
3916                         tmp_adev->asic_reset_res = r;
3917                 }
3918         }
3919
3920         /* Actual ASIC resets if needed.*/
3921         /* TODO Implement XGMI hive reset logic for SRIOV */
3922         if (amdgpu_sriov_vf(adev)) {
3923                 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3924                 if (r)
3925                         adev->asic_reset_res = r;
3926         } else {
3927                 r  = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3928                 if (r && r == -EAGAIN)
3929                         goto retry;
3930         }
3931
3932 skip_hw_reset:
3933
3934         /* Post ASIC reset for all devs .*/
3935         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3936                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3937                         struct amdgpu_ring *ring = tmp_adev->rings[i];
3938
3939                         if (!ring || !ring->sched.thread)
3940                                 continue;
3941
3942                         /* No point to resubmit jobs if we didn't HW reset*/
3943                         if (!tmp_adev->asic_reset_res && !job_signaled)
3944                                 drm_sched_resubmit_jobs(&ring->sched);
3945
3946                         drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
3947                 }
3948
3949                 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
3950                         drm_helper_resume_force_mode(tmp_adev->ddev);
3951                 }
3952
3953                 tmp_adev->asic_reset_res = 0;
3954
3955                 if (r) {
3956                         /* bad news, how to tell it to userspace ? */
3957                         dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3958                         amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3959                 } else {
3960                         dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
3961                 }
3962
3963                 amdgpu_device_unlock_adev(tmp_adev);
3964         }
3965
3966         if (hive)
3967                 mutex_unlock(&hive->reset_lock);
3968
3969         if (r)
3970                 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3971         return r;
3972 }
3973
3974 /**
3975  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3976  *
3977  * @adev: amdgpu_device pointer
3978  *
3979  * Fetchs and stores in the driver the PCIE capabilities (gen speed
3980  * and lanes) of the slot the device is in. Handles APUs and
3981  * virtualized environments where PCIE config space may not be available.
3982  */
3983 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3984 {
3985         struct pci_dev *pdev;
3986         enum pci_bus_speed speed_cap, platform_speed_cap;
3987         enum pcie_link_width platform_link_width;
3988
3989         if (amdgpu_pcie_gen_cap)
3990                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3991
3992         if (amdgpu_pcie_lane_cap)
3993                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3994
3995         /* covers APUs as well */
3996         if (pci_is_root_bus(adev->pdev->bus)) {
3997                 if (adev->pm.pcie_gen_mask == 0)
3998                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3999                 if (adev->pm.pcie_mlw_mask == 0)
4000                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4001                 return;
4002         }
4003
4004         if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4005                 return;
4006
4007         pcie_bandwidth_available(adev->pdev, NULL,
4008                                  &platform_speed_cap, &platform_link_width);
4009
4010         if (adev->pm.pcie_gen_mask == 0) {
4011                 /* asic caps */
4012                 pdev = adev->pdev;
4013                 speed_cap = pcie_get_speed_cap(pdev);
4014                 if (speed_cap == PCI_SPEED_UNKNOWN) {
4015                         adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4016                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4017                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4018                 } else {
4019                         if (speed_cap == PCIE_SPEED_16_0GT)
4020                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4021                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4022                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4023                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4024                         else if (speed_cap == PCIE_SPEED_8_0GT)
4025                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4026                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4027                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4028                         else if (speed_cap == PCIE_SPEED_5_0GT)
4029                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4030                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4031                         else
4032                                 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4033                 }
4034                 /* platform caps */
4035                 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4036                         adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4037                                                    CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4038                 } else {
4039                         if (platform_speed_cap == PCIE_SPEED_16_0GT)
4040                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4041                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4042                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4043                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
4044                         else if (platform_speed_cap == PCIE_SPEED_8_0GT)
4045                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4046                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4047                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
4048                         else if (platform_speed_cap == PCIE_SPEED_5_0GT)
4049                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4050                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4051                         else
4052                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
4053
4054                 }
4055         }
4056         if (adev->pm.pcie_mlw_mask == 0) {
4057                 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
4058                         adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
4059                 } else {
4060                         switch (platform_link_width) {
4061                         case PCIE_LNK_X32:
4062                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
4063                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4064                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4065                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4066                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4067                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4068                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4069                                 break;
4070                         case PCIE_LNK_X16:
4071                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4072                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4073                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4074                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4075                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4076                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4077                                 break;
4078                         case PCIE_LNK_X12:
4079                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4080                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4081                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4082                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4083                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4084                                 break;
4085                         case PCIE_LNK_X8:
4086                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4087                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4088                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4089                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4090                                 break;
4091                         case PCIE_LNK_X4:
4092                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4093                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4094                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4095                                 break;
4096                         case PCIE_LNK_X2:
4097                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4098                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4099                                 break;
4100                         case PCIE_LNK_X1:
4101                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
4102                                 break;
4103                         default:
4104                                 break;
4105                         }
4106                 }
4107         }
4108 }
4109