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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2023 Intel Corporation. */
3 #ifndef _LINUX_CXL_EVENT_H
4 #define _LINUX_CXL_EVENT_H
5
6 #include <linux/types.h>
7 #include <linux/uuid.h>
8 #include <linux/workqueue_types.h>
9
10 /*
11  * Common Event Record Format
12  * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
13  */
14 struct cxl_event_record_hdr {
15         u8 length;
16         u8 flags[3];
17         __le16 handle;
18         __le16 related_handle;
19         __le64 timestamp;
20         u8 maint_op_class;
21         u8 reserved[15];
22 } __packed;
23
24 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50
25 struct cxl_event_generic {
26         struct cxl_event_record_hdr hdr;
27         u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
28 } __packed;
29
30 /*
31  * General Media Event Record
32  * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
33  */
34 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE  0x10
35 struct cxl_event_gen_media {
36         struct cxl_event_record_hdr hdr;
37         __le64 phys_addr;
38         u8 descriptor;
39         u8 type;
40         u8 transaction_type;
41         u8 validity_flags[2];
42         u8 channel;
43         u8 rank;
44         u8 device[3];
45         u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
46         u8 reserved[46];
47 } __packed;
48
49 /*
50  * DRAM Event Record - DER
51  * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
52  */
53 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE      0x20
54 struct cxl_event_dram {
55         struct cxl_event_record_hdr hdr;
56         __le64 phys_addr;
57         u8 descriptor;
58         u8 type;
59         u8 transaction_type;
60         u8 validity_flags[2];
61         u8 channel;
62         u8 rank;
63         u8 nibble_mask[3];
64         u8 bank_group;
65         u8 bank;
66         u8 row[3];
67         u8 column[2];
68         u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
69         u8 reserved[0x17];
70 } __packed;
71
72 /*
73  * Get Health Info Record
74  * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
75  */
76 struct cxl_get_health_info {
77         u8 health_status;
78         u8 media_status;
79         u8 add_status;
80         u8 life_used;
81         u8 device_temp[2];
82         u8 dirty_shutdown_cnt[4];
83         u8 cor_vol_err_cnt[4];
84         u8 cor_per_err_cnt[4];
85 } __packed;
86
87 /*
88  * Memory Module Event Record
89  * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
90  */
91 struct cxl_event_mem_module {
92         struct cxl_event_record_hdr hdr;
93         u8 event_type;
94         struct cxl_get_health_info info;
95         u8 reserved[0x3d];
96 } __packed;
97
98 /*
99  * General Media or DRAM Event Common Fields
100  * - provides common access to phys_addr
101  */
102 struct cxl_event_common {
103         struct cxl_event_record_hdr hdr;
104         __le64 phys_addr;
105 } __packed;
106
107 union cxl_event {
108         struct cxl_event_generic generic;
109         struct cxl_event_gen_media gen_media;
110         struct cxl_event_dram dram;
111         struct cxl_event_mem_module mem_module;
112         struct cxl_event_common common;
113 } __packed;
114
115 /*
116  * Common Event Record Format; in event logs
117  * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
118  */
119 struct cxl_event_record_raw {
120         uuid_t id;
121         union cxl_event event;
122 } __packed;
123
124 enum cxl_event_type {
125         CXL_CPER_EVENT_GENERIC,
126         CXL_CPER_EVENT_GEN_MEDIA,
127         CXL_CPER_EVENT_DRAM,
128         CXL_CPER_EVENT_MEM_MODULE,
129 };
130
131 #define CPER_CXL_DEVICE_ID_VALID                BIT(0)
132 #define CPER_CXL_DEVICE_SN_VALID                BIT(1)
133 #define CPER_CXL_COMP_EVENT_LOG_VALID           BIT(2)
134 struct cxl_cper_event_rec {
135         struct {
136                 u32 length;
137                 u64 validation_bits;
138                 struct cper_cxl_event_devid {
139                         u16 vendor_id;
140                         u16 device_id;
141                         u8 func_num;
142                         u8 device_num;
143                         u8 bus_num;
144                         u16 segment_num;
145                         u16 slot_num; /* bits 2:0 reserved */
146                         u8 reserved;
147                 } __packed device_id;
148                 struct cper_cxl_event_sn {
149                         u32 lower_dw;
150                         u32 upper_dw;
151                 } __packed dev_serial_num;
152         } __packed hdr;
153
154         union cxl_event event;
155 } __packed;
156
157 struct cxl_cper_work_data {
158         enum cxl_event_type event_type;
159         struct cxl_cper_event_rec rec;
160 };
161
162 #ifdef CONFIG_ACPI_APEI_GHES
163 int cxl_cper_register_work(struct work_struct *work);
164 int cxl_cper_unregister_work(struct work_struct *work);
165 int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd);
166 #else
167 static inline int cxl_cper_register_work(struct work_struct *work)
168 {
169         return 0;
170 }
171
172 static inline int cxl_cper_unregister_work(struct work_struct *work)
173 {
174         return 0;
175 }
176 static inline int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd)
177 {
178         return 0;
179 }
180 #endif
181
182 #endif /* _LINUX_CXL_EVENT_H */
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