drivers/spi/spi-stm32.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // STMicroelectronics STM32 SPI Controller driver
   4 //
   5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6 // Author(s): Amelie Delaunay <[email protected]> for STMicroelectronics.
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/reset.h>
  21 #include <linux/spi/spi.h>
  22
  23 #define DRIVER_NAME "spi_stm32"
  24
  25 /* STM32F4/7 SPI registers */
  26 #define STM32FX_SPI_CR1                 0x00
  27 #define STM32FX_SPI_CR2                 0x04
  28 #define STM32FX_SPI_SR                  0x08
  29 #define STM32FX_SPI_DR                  0x0C
  30 #define STM32FX_SPI_I2SCFGR             0x1C
  31
  32 /* STM32FX_SPI_CR1 bit fields */
  33 #define STM32FX_SPI_CR1_CPHA            BIT(0)
  34 #define STM32FX_SPI_CR1_CPOL            BIT(1)
  35 #define STM32FX_SPI_CR1_MSTR            BIT(2)
  36 #define STM32FX_SPI_CR1_BR_SHIFT        3
  37 #define STM32FX_SPI_CR1_BR              GENMASK(5, 3)
  38 #define STM32FX_SPI_CR1_SPE             BIT(6)
  39 #define STM32FX_SPI_CR1_LSBFRST         BIT(7)
  40 #define STM32FX_SPI_CR1_SSI             BIT(8)
  41 #define STM32FX_SPI_CR1_SSM             BIT(9)
  42 #define STM32FX_SPI_CR1_RXONLY          BIT(10)
  43 #define STM32F4_SPI_CR1_DFF             BIT(11)
  44 #define STM32F7_SPI_CR1_CRCL            BIT(11)
  45 #define STM32FX_SPI_CR1_CRCNEXT         BIT(12)
  46 #define STM32FX_SPI_CR1_CRCEN           BIT(13)
  47 #define STM32FX_SPI_CR1_BIDIOE          BIT(14)
  48 #define STM32FX_SPI_CR1_BIDIMODE        BIT(15)
  49 #define STM32FX_SPI_CR1_BR_MIN          0
  50 #define STM32FX_SPI_CR1_BR_MAX          (GENMASK(5, 3) >> 3)
  51
  52 /* STM32FX_SPI_CR2 bit fields */
  53 #define STM32FX_SPI_CR2_RXDMAEN         BIT(0)
  54 #define STM32FX_SPI_CR2_TXDMAEN         BIT(1)
  55 #define STM32FX_SPI_CR2_SSOE            BIT(2)
  56 #define STM32FX_SPI_CR2_FRF             BIT(4)
  57 #define STM32FX_SPI_CR2_ERRIE           BIT(5)
  58 #define STM32FX_SPI_CR2_RXNEIE          BIT(6)
  59 #define STM32FX_SPI_CR2_TXEIE           BIT(7)
  60 #define STM32F7_SPI_CR2_DS              GENMASK(11, 8)
  61 #define STM32F7_SPI_CR2_FRXTH           BIT(12)
  62 #define STM32F7_SPI_CR2_LDMA_RX         BIT(13)
  63 #define STM32F7_SPI_CR2_LDMA_TX         BIT(14)
  64
  65 /* STM32FX_SPI_SR bit fields */
  66 #define STM32FX_SPI_SR_RXNE             BIT(0)
  67 #define STM32FX_SPI_SR_TXE              BIT(1)
  68 #define STM32FX_SPI_SR_CHSIDE           BIT(2)
  69 #define STM32FX_SPI_SR_UDR              BIT(3)
  70 #define STM32FX_SPI_SR_CRCERR           BIT(4)
  71 #define STM32FX_SPI_SR_MODF             BIT(5)
  72 #define STM32FX_SPI_SR_OVR              BIT(6)
  73 #define STM32FX_SPI_SR_BSY              BIT(7)
  74 #define STM32FX_SPI_SR_FRE              BIT(8)
  75 #define STM32F7_SPI_SR_FRLVL            GENMASK(10, 9)
  76 #define STM32F7_SPI_SR_FTLVL            GENMASK(12, 11)
  77
  78 /* STM32FX_SPI_I2SCFGR bit fields */
  79 #define STM32FX_SPI_I2SCFGR_I2SMOD      BIT(11)
  80
  81 /* STM32F4 SPI Baud Rate min/max divisor */
  82 #define STM32FX_SPI_BR_DIV_MIN          (2 << STM32FX_SPI_CR1_BR_MIN)
  83 #define STM32FX_SPI_BR_DIV_MAX          (2 << STM32FX_SPI_CR1_BR_MAX)
  84
  85 /* STM32H7 SPI registers */
  86 #define STM32H7_SPI_CR1                 0x00
  87 #define STM32H7_SPI_CR2                 0x04
  88 #define STM32H7_SPI_CFG1                0x08
  89 #define STM32H7_SPI_CFG2                0x0C
  90 #define STM32H7_SPI_IER                 0x10
  91 #define STM32H7_SPI_SR                  0x14
  92 #define STM32H7_SPI_IFCR                0x18
  93 #define STM32H7_SPI_TXDR                0x20
  94 #define STM32H7_SPI_RXDR                0x30
  95 #define STM32H7_SPI_I2SCFGR             0x50
  96
  97 /* STM32H7_SPI_CR1 bit fields */
  98 #define STM32H7_SPI_CR1_SPE             BIT(0)
  99 #define STM32H7_SPI_CR1_MASRX           BIT(8)
 100 #define STM32H7_SPI_CR1_CSTART          BIT(9)
 101 #define STM32H7_SPI_CR1_CSUSP           BIT(10)
 102 #define STM32H7_SPI_CR1_HDDIR           BIT(11)
 103 #define STM32H7_SPI_CR1_SSI             BIT(12)
 104
 105 /* STM32H7_SPI_CR2 bit fields */
 106 #define STM32H7_SPI_CR2_TSIZE           GENMASK(15, 0)
 107 #define STM32H7_SPI_TSIZE_MAX           GENMASK(15, 0)
 108
 109 /* STM32H7_SPI_CFG1 bit fields */
 110 #define STM32H7_SPI_CFG1_DSIZE          GENMASK(4, 0)
 111 #define STM32H7_SPI_CFG1_FTHLV          GENMASK(8, 5)
 112 #define STM32H7_SPI_CFG1_RXDMAEN        BIT(14)
 113 #define STM32H7_SPI_CFG1_TXDMAEN        BIT(15)
 114 #define STM32H7_SPI_CFG1_MBR            GENMASK(30, 28)
 115 #define STM32H7_SPI_CFG1_MBR_SHIFT      28
 116 #define STM32H7_SPI_CFG1_MBR_MIN        0
 117 #define STM32H7_SPI_CFG1_MBR_MAX        (GENMASK(30, 28) >> 28)
 118
 119 /* STM32H7_SPI_CFG2 bit fields */
 120 #define STM32H7_SPI_CFG2_MIDI           GENMASK(7, 4)
 121 #define STM32H7_SPI_CFG2_COMM           GENMASK(18, 17)
 122 #define STM32H7_SPI_CFG2_SP             GENMASK(21, 19)
 123 #define STM32H7_SPI_CFG2_MASTER         BIT(22)
 124 #define STM32H7_SPI_CFG2_LSBFRST        BIT(23)
 125 #define STM32H7_SPI_CFG2_CPHA           BIT(24)
 126 #define STM32H7_SPI_CFG2_CPOL           BIT(25)
 127 #define STM32H7_SPI_CFG2_SSM            BIT(26)
 128 #define STM32H7_SPI_CFG2_SSIOP          BIT(28)
 129 #define STM32H7_SPI_CFG2_AFCNTR         BIT(31)
 130
 131 /* STM32H7_SPI_IER bit fields */
 132 #define STM32H7_SPI_IER_RXPIE           BIT(0)
 133 #define STM32H7_SPI_IER_TXPIE           BIT(1)
 134 #define STM32H7_SPI_IER_DXPIE           BIT(2)
 135 #define STM32H7_SPI_IER_EOTIE           BIT(3)
 136 #define STM32H7_SPI_IER_TXTFIE          BIT(4)
 137 #define STM32H7_SPI_IER_OVRIE           BIT(6)
 138 #define STM32H7_SPI_IER_MODFIE          BIT(9)
 139 #define STM32H7_SPI_IER_ALL             GENMASK(10, 0)
 140
 141 /* STM32H7_SPI_SR bit fields */
 142 #define STM32H7_SPI_SR_RXP              BIT(0)
 143 #define STM32H7_SPI_SR_TXP              BIT(1)
 144 #define STM32H7_SPI_SR_EOT              BIT(3)
 145 #define STM32H7_SPI_SR_OVR              BIT(6)
 146 #define STM32H7_SPI_SR_MODF             BIT(9)
 147 #define STM32H7_SPI_SR_SUSP             BIT(11)
 148 #define STM32H7_SPI_SR_RXPLVL           GENMASK(14, 13)
 149 #define STM32H7_SPI_SR_RXWNE            BIT(15)
 150
 151 /* STM32H7_SPI_IFCR bit fields */
 152 #define STM32H7_SPI_IFCR_ALL            GENMASK(11, 3)
 153
 154 /* STM32H7_SPI_I2SCFGR bit fields */
 155 #define STM32H7_SPI_I2SCFGR_I2SMOD      BIT(0)
 156
 157 /* STM32MP25 SPI registers bit fields */
 158 #define STM32MP25_SPI_HWCFGR1                   0x3F0
 159
 160 /* STM32MP25_SPI_CR2 bit fields */
 161 #define STM32MP25_SPI_TSIZE_MAX_LIMITED         GENMASK(9, 0)
 162
 163 /* STM32MP25_SPI_HWCFGR1 */
 164 #define STM32MP25_SPI_HWCFGR1_FULLCFG           GENMASK(27, 24)
 165 #define STM32MP25_SPI_HWCFGR1_FULLCFG_LIMITED   0x0
 166 #define STM32MP25_SPI_HWCFGR1_FULLCFG_FULL      0x1
 167 #define STM32MP25_SPI_HWCFGR1_DSCFG             GENMASK(19, 16)
 168 #define STM32MP25_SPI_HWCFGR1_DSCFG_16_B        0x0
 169 #define STM32MP25_SPI_HWCFGR1_DSCFG_32_B        0x1
 170
 171 /* STM32H7 SPI Master Baud Rate min/max divisor */
 172 #define STM32H7_SPI_MBR_DIV_MIN         (2 << STM32H7_SPI_CFG1_MBR_MIN)
 173 #define STM32H7_SPI_MBR_DIV_MAX         (2 << STM32H7_SPI_CFG1_MBR_MAX)
 174
 175 /* STM32H7 SPI Communication mode */
 176 #define STM32H7_SPI_FULL_DUPLEX         0
 177 #define STM32H7_SPI_SIMPLEX_TX          1
 178 #define STM32H7_SPI_SIMPLEX_RX          2
 179 #define STM32H7_SPI_HALF_DUPLEX         3
 180
 181 /* SPI Communication type */
 182 #define SPI_FULL_DUPLEX         0
 183 #define SPI_SIMPLEX_TX          1
 184 #define SPI_SIMPLEX_RX          2
 185 #define SPI_3WIRE_TX            3
 186 #define SPI_3WIRE_RX            4
 187
 188 #define STM32_SPI_AUTOSUSPEND_DELAY             1       /* 1 ms */
 189
 190 /*
 191  * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
 192  * without fifo buffers.
 193  */
 194 #define SPI_DMA_MIN_BYTES       16
 195
 196 /* STM32 SPI driver helpers */
 197 #define STM32_SPI_HOST_MODE(stm32_spi) (!(stm32_spi)->device_mode)
 198 #define STM32_SPI_DEVICE_MODE(stm32_spi) ((stm32_spi)->device_mode)
 199
 200 /**
 201  * struct stm32_spi_reg - stm32 SPI register & bitfield desc
 202  * @reg:                register offset
 203  * @mask:               bitfield mask
 204  * @shift:              left shift
 205  */
 206 struct stm32_spi_reg {
 207         int reg;
 208         int mask;
 209         int shift;
 210 };
 211
 212 /**
 213  * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
 214  * @en: enable register and SPI enable bit
 215  * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
 216  * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
 217  * @cpol: clock polarity register and polarity bit
 218  * @cpha: clock phase register and phase bit
 219  * @lsb_first: LSB transmitted first register and bit
 220  * @cs_high: chips select active value
 221  * @br: baud rate register and bitfields
 222  * @rx: SPI RX data register
 223  * @tx: SPI TX data register
 224  * @fullcfg: SPI full or limited feature set register
 225  */
 226 struct stm32_spi_regspec {
 227         const struct stm32_spi_reg en;
 228         const struct stm32_spi_reg dma_rx_en;
 229         const struct stm32_spi_reg dma_tx_en;
 230         const struct stm32_spi_reg cpol;
 231         const struct stm32_spi_reg cpha;
 232         const struct stm32_spi_reg lsb_first;
 233         const struct stm32_spi_reg cs_high;
 234         const struct stm32_spi_reg br;
 235         const struct stm32_spi_reg rx;
 236         const struct stm32_spi_reg tx;
 237         const struct stm32_spi_reg fullcfg;
 238 };
 239
 240 struct stm32_spi;
 241
 242 /**
 243  * struct stm32_spi_cfg - stm32 compatible configuration data
 244  * @regs: registers descriptions
 245  * @get_fifo_size: routine to get fifo size
 246  * @get_bpw_mask: routine to get bits per word mask
 247  * @disable: routine to disable controller
 248  * @config: routine to configure controller as SPI Host
 249  * @set_bpw: routine to configure registers to for bits per word
 250  * @set_mode: routine to configure registers to desired mode
 251  * @set_data_idleness: optional routine to configure registers to desired idle
 252  * time between frames (if driver has this functionality)
 253  * @set_number_of_data: optional routine to configure registers to desired
 254  * number of data (if driver has this functionality)
 255  * @write_tx: routine to write to transmit register/FIFO
 256  * @read_rx: routine to read from receive register/FIFO
 257  * @transfer_one_dma_start: routine to start transfer a single spi_transfer
 258  * using DMA
 259  * @dma_rx_cb: routine to call after DMA RX channel operation is complete
 260  * @dma_tx_cb: routine to call after DMA TX channel operation is complete
 261  * @transfer_one_irq: routine to configure interrupts for driver
 262  * @irq_handler_event: Interrupt handler for SPI controller events
 263  * @irq_handler_thread: thread of interrupt handler for SPI controller
 264  * @baud_rate_div_min: minimum baud rate divisor
 265  * @baud_rate_div_max: maximum baud rate divisor
 266  * @has_fifo: boolean to know if fifo is used for driver
 267  * @has_device_mode: is this compatible capable to switch on device mode
 268  * @flags: compatible specific SPI controller flags used at registration time
 269  * @prevent_dma_burst: boolean to indicate to prevent DMA burst
 270  */
 271 struct stm32_spi_cfg {
 272         const struct stm32_spi_regspec *regs;
 273         int (*get_fifo_size)(struct stm32_spi *spi);
 274         int (*get_bpw_mask)(struct stm32_spi *spi);
 275         void (*disable)(struct stm32_spi *spi);
 276         int (*config)(struct stm32_spi *spi);
 277         void (*set_bpw)(struct stm32_spi *spi);
 278         int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
 279         void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
 280         int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
 281         void (*write_tx)(struct stm32_spi *spi);
 282         void (*read_rx)(struct stm32_spi *spi);
 283         void (*transfer_one_dma_start)(struct stm32_spi *spi);
 284         void (*dma_rx_cb)(void *data);
 285         void (*dma_tx_cb)(void *data);
 286         int (*transfer_one_irq)(struct stm32_spi *spi);
 287         irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
 288         irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
 289         unsigned int baud_rate_div_min;
 290         unsigned int baud_rate_div_max;
 291         bool has_fifo;
 292         bool has_device_mode;
 293         u16 flags;
 294         bool prevent_dma_burst;
 295 };
 296
 297 /**
 298  * struct stm32_spi - private data of the SPI controller
 299  * @dev: driver model representation of the controller
 300  * @ctrl: controller interface
 301  * @cfg: compatible configuration data
 302  * @base: virtual memory area
 303  * @clk: hw kernel clock feeding the SPI clock generator
 304  * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
 305  * @lock: prevent I/O concurrent access
 306  * @irq: SPI controller interrupt line
 307  * @fifo_size: size of the embedded fifo in bytes
 308  * @t_size_max: maximum number of data of one transfer
 309  * @feature_set: SPI full or limited feature set
 310  * @cur_midi: host inter-data idleness in ns
 311  * @cur_speed: speed configured in Hz
 312  * @cur_half_period: time of a half bit in us
 313  * @cur_bpw: number of bits in a single SPI data frame
 314  * @cur_fthlv: fifo threshold level (data frames in a single data packet)
 315  * @cur_comm: SPI communication mode
 316  * @cur_xferlen: current transfer length in bytes
 317  * @cur_usedma: boolean to know if dma is used in current transfer
 318  * @tx_buf: data to be written, or NULL
 319  * @rx_buf: data to be read, or NULL
 320  * @tx_len: number of data to be written in bytes
 321  * @rx_len: number of data to be read in bytes
 322  * @dma_tx: dma channel for TX transfer
 323  * @dma_rx: dma channel for RX transfer
 324  * @phys_addr: SPI registers physical base address
 325  * @device_mode: the controller is configured as SPI device
 326  */
 327 struct stm32_spi {
 328         struct device *dev;
 329         struct spi_controller *ctrl;
 330         const struct stm32_spi_cfg *cfg;
 331         void __iomem *base;
 332         struct clk *clk;
 333         u32 clk_rate;
 334         spinlock_t lock; /* prevent I/O concurrent access */
 335         int irq;
 336         unsigned int fifo_size;
 337         unsigned int t_size_max;
 338         unsigned int feature_set;
 339 #define STM32_SPI_FEATURE_LIMITED       STM32MP25_SPI_HWCFGR1_FULLCFG_LIMITED   /* 0x0 */
 340 #define STM32_SPI_FEATURE_FULL          STM32MP25_SPI_HWCFGR1_FULLCFG_FULL      /* 0x1 */
 341
 342         unsigned int cur_midi;
 343         unsigned int cur_speed;
 344         unsigned int cur_half_period;
 345         unsigned int cur_bpw;
 346         unsigned int cur_fthlv;
 347         unsigned int cur_comm;
 348         unsigned int cur_xferlen;
 349         bool cur_usedma;
 350
 351         const void *tx_buf;
 352         void *rx_buf;
 353         int tx_len;
 354         int rx_len;
 355         struct dma_chan *dma_tx;
 356         struct dma_chan *dma_rx;
 357         dma_addr_t phys_addr;
 358
 359         bool device_mode;
 360 };
 361
 362 static const struct stm32_spi_regspec stm32fx_spi_regspec = {
 363         .en = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_SPE },
 364
 365         .dma_rx_en = { STM32FX_SPI_CR2, STM32FX_SPI_CR2_RXDMAEN },
 366         .dma_tx_en = { STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXDMAEN },
 367
 368         .cpol = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_CPOL },
 369         .cpha = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_CPHA },
 370         .lsb_first = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_LSBFRST },
 371         .cs_high = {},
 372         .br = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_BR, STM32FX_SPI_CR1_BR_SHIFT },
 373
 374         .rx = { STM32FX_SPI_DR },
 375         .tx = { STM32FX_SPI_DR },
 376 };
 377
 378 static const struct stm32_spi_regspec stm32h7_spi_regspec = {
 379         /* SPI data transfer is enabled but spi_ker_ck is idle.
 380          * CFG1 and CFG2 registers are write protected when SPE is enabled.
 381          */
 382         .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
 383
 384         .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
 385         .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
 386
 387         .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
 388         .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
 389         .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
 390         .cs_high = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_SSIOP },
 391         .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
 392                 STM32H7_SPI_CFG1_MBR_SHIFT },
 393
 394         .rx = { STM32H7_SPI_RXDR },
 395         .tx = { STM32H7_SPI_TXDR },
 396 };
 397
 398 static const struct stm32_spi_regspec stm32mp25_spi_regspec = {
 399         /* SPI data transfer is enabled but spi_ker_ck is idle.
 400          * CFG1 and CFG2 registers are write protected when SPE is enabled.
 401          */
 402         .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
 403
 404         .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
 405         .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
 406
 407         .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
 408         .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
 409         .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
 410         .cs_high = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_SSIOP },
 411         .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
 412                 STM32H7_SPI_CFG1_MBR_SHIFT },
 413
 414         .rx = { STM32H7_SPI_RXDR },
 415         .tx = { STM32H7_SPI_TXDR },
 416
 417         .fullcfg = { STM32MP25_SPI_HWCFGR1, STM32MP25_SPI_HWCFGR1_FULLCFG },
 418 };
 419
 420 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
 421                                       u32 offset, u32 bits)
 422 {
 423         writel_relaxed(readl_relaxed(spi->base + offset) | bits,
 424                        spi->base + offset);
 425 }
 426
 427 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
 428                                       u32 offset, u32 bits)
 429 {
 430         writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
 431                        spi->base + offset);
 432 }
 433
 434 /**
 435  * stm32h7_spi_get_fifo_size - Return fifo size
 436  * @spi: pointer to the spi controller data structure
 437  */
 438 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
 439 {
 440         unsigned long flags;
 441         u32 count = 0;
 442
 443         spin_lock_irqsave(&spi->lock, flags);
 444
 445         stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
 446
 447         while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
 448                 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
 449
 450         stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
 451
 452         spin_unlock_irqrestore(&spi->lock, flags);
 453
 454         dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
 455
 456         return count;
 457 }
 458
 459 /**
 460  * stm32f4_spi_get_bpw_mask - Return bits per word mask
 461  * @spi: pointer to the spi controller data structure
 462  */
 463 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
 464 {
 465         dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
 466         return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 467 }
 468
 469 /**
 470  * stm32f7_spi_get_bpw_mask - Return bits per word mask
 471  * @spi: pointer to the spi controller data structure
 472  */
 473 static int stm32f7_spi_get_bpw_mask(struct stm32_spi *spi)
 474 {
 475         dev_dbg(spi->dev, "16-bit maximum data frame\n");
 476         return SPI_BPW_RANGE_MASK(4, 16);
 477 }
 478
 479 /**
 480  * stm32h7_spi_get_bpw_mask - Return bits per word mask
 481  * @spi: pointer to the spi controller data structure
 482  */
 483 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
 484 {
 485         unsigned long flags;
 486         u32 cfg1, max_bpw;
 487
 488         spin_lock_irqsave(&spi->lock, flags);
 489
 490         /*
 491          * The most significant bit at DSIZE bit field is reserved when the
 492          * maximum data size of periperal instances is limited to 16-bit
 493          */
 494         stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
 495
 496         cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
 497         max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
 498
 499         spin_unlock_irqrestore(&spi->lock, flags);
 500
 501         dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
 502
 503         return SPI_BPW_RANGE_MASK(4, max_bpw);
 504 }
 505
 506 /**
 507  * stm32mp25_spi_get_bpw_mask - Return bits per word mask
 508  * @spi: pointer to the spi controller data structure
 509  */
 510 static int stm32mp25_spi_get_bpw_mask(struct stm32_spi *spi)
 511 {
 512         u32 dscfg, max_bpw;
 513
 514         if (spi->feature_set == STM32_SPI_FEATURE_LIMITED) {
 515                 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
 516                 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 517         }
 518
 519         dscfg = FIELD_GET(STM32MP25_SPI_HWCFGR1_DSCFG,
 520                           readl_relaxed(spi->base + STM32MP25_SPI_HWCFGR1));
 521         max_bpw = 16;
 522         if (dscfg == STM32MP25_SPI_HWCFGR1_DSCFG_32_B)
 523                 max_bpw = 32;
 524         dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
 525         return SPI_BPW_RANGE_MASK(4, max_bpw);
 526 }
 527
 528 /**
 529  * stm32_spi_prepare_mbr - Determine baud rate divisor value
 530  * @spi: pointer to the spi controller data structure
 531  * @speed_hz: requested speed
 532  * @min_div: minimum baud rate divisor
 533  * @max_div: maximum baud rate divisor
 534  *
 535  * Return baud rate divisor value in case of success or -EINVAL
 536  */
 537 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
 538                                  u32 min_div, u32 max_div)
 539 {
 540         u32 div, mbrdiv;
 541
 542         /* Ensure spi->clk_rate is even */
 543         div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
 544
 545         /*
 546          * SPI framework set xfer->speed_hz to ctrl->max_speed_hz if
 547          * xfer->speed_hz is greater than ctrl->max_speed_hz, and it returns
 548          * an error when xfer->speed_hz is lower than ctrl->min_speed_hz, so
 549          * no need to check it there.
 550          * However, we need to ensure the following calculations.
 551          */
 552         if ((div < min_div) || (div > max_div))
 553                 return -EINVAL;
 554
 555         /* Determine the first power of 2 greater than or equal to div */
 556         if (div & (div - 1))
 557                 mbrdiv = fls(div);
 558         else
 559                 mbrdiv = fls(div) - 1;
 560
 561         spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
 562
 563         spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed);
 564
 565         return mbrdiv - 1;
 566 }
 567
 568 /**
 569  * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
 570  * @spi: pointer to the spi controller data structure
 571  * @xfer_len: length of the message to be transferred
 572  */
 573 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
 574 {
 575         u32 packet, bpw;
 576
 577         /* data packet should not exceed 1/2 of fifo space */
 578         packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
 579
 580         /* align packet size with data registers access */
 581         bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
 582         return DIV_ROUND_UP(packet, bpw);
 583 }
 584
 585 /**
 586  * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
 587  * @spi: pointer to the spi controller data structure
 588  *
 589  * Read from tx_buf depends on remaining bytes to avoid to read beyond
 590  * tx_buf end.
 591  */
 592 static void stm32f4_spi_write_tx(struct stm32_spi *spi)
 593 {
 594         if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) &
 595                                   STM32FX_SPI_SR_TXE)) {
 596                 u32 offs = spi->cur_xferlen - spi->tx_len;
 597
 598                 if (spi->cur_bpw == 16) {
 599                         const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
 600
 601                         writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR);
 602                         spi->tx_len -= sizeof(u16);
 603                 } else {
 604                         const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
 605
 606                         writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR);
 607                         spi->tx_len -= sizeof(u8);
 608                 }
 609         }
 610
 611         dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
 612 }
 613
 614 /**
 615  * stm32f7_spi_write_tx - Write bytes to Transmit Data Register
 616  * @spi: pointer to the spi controller data structure
 617  *
 618  * Read from tx_buf depends on remaining bytes to avoid to read beyond
 619  * tx_buf end.
 620  */
 621 static void stm32f7_spi_write_tx(struct stm32_spi *spi)
 622 {
 623         if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) &
 624                                   STM32FX_SPI_SR_TXE)) {
 625                 u32 offs = spi->cur_xferlen - spi->tx_len;
 626
 627                 if (spi->tx_len >= sizeof(u16)) {
 628                         const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
 629
 630                         writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR);
 631                         spi->tx_len -= sizeof(u16);
 632                 } else {
 633                         const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
 634
 635                         writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR);
 636                         spi->tx_len -= sizeof(u8);
 637                 }
 638         }
 639
 640         dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
 641 }
 642
 643 /**
 644  * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
 645  * @spi: pointer to the spi controller data structure
 646  *
 647  * Read from tx_buf depends on remaining bytes to avoid to read beyond
 648  * tx_buf end.
 649  */
 650 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
 651 {
 652         while ((spi->tx_len > 0) &&
 653                        (readl_relaxed(spi->base + STM32H7_SPI_SR) &
 654                         STM32H7_SPI_SR_TXP)) {
 655                 u32 offs = spi->cur_xferlen - spi->tx_len;
 656
 657                 if (spi->tx_len >= sizeof(u32)) {
 658                         const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
 659
 660                         writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
 661                         spi->tx_len -= sizeof(u32);
 662                 } else if (spi->tx_len >= sizeof(u16)) {
 663                         const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
 664
 665                         writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
 666                         spi->tx_len -= sizeof(u16);
 667                 } else {
 668                         const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
 669
 670                         writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
 671                         spi->tx_len -= sizeof(u8);
 672                 }
 673         }
 674
 675         dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
 676 }
 677
 678 /**
 679  * stm32f4_spi_read_rx - Read bytes from Receive Data Register
 680  * @spi: pointer to the spi controller data structure
 681  *
 682  * Write in rx_buf depends on remaining bytes to avoid to write beyond
 683  * rx_buf end.
 684  */
 685 static void stm32f4_spi_read_rx(struct stm32_spi *spi)
 686 {
 687         if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) &
 688                                   STM32FX_SPI_SR_RXNE)) {
 689                 u32 offs = spi->cur_xferlen - spi->rx_len;
 690
 691                 if (spi->cur_bpw == 16) {
 692                         u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
 693
 694                         *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR);
 695                         spi->rx_len -= sizeof(u16);
 696                 } else {
 697                         u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
 698
 699                         *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR);
 700                         spi->rx_len -= sizeof(u8);
 701                 }
 702         }
 703
 704         dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
 705 }
 706
 707 /**
 708  * stm32f7_spi_read_rx - Read bytes from Receive Data Register
 709  * @spi: pointer to the spi controller data structure
 710  *
 711  * Write in rx_buf depends on remaining bytes to avoid to write beyond
 712  * rx_buf end.
 713  */
 714 static void stm32f7_spi_read_rx(struct stm32_spi *spi)
 715 {
 716         u32 sr = readl_relaxed(spi->base + STM32FX_SPI_SR);
 717         u32 frlvl = FIELD_GET(STM32F7_SPI_SR_FRLVL, sr);
 718
 719         while ((spi->rx_len > 0) && (frlvl > 0)) {
 720                 u32 offs = spi->cur_xferlen - spi->rx_len;
 721
 722                 if ((spi->rx_len >= sizeof(u16)) && (frlvl >= 2)) {
 723                         u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
 724
 725                         *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR);
 726                         spi->rx_len -= sizeof(u16);
 727                 } else {
 728                         u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
 729
 730                         *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR);
 731                         spi->rx_len -= sizeof(u8);
 732                 }
 733
 734                 sr = readl_relaxed(spi->base + STM32FX_SPI_SR);
 735                 frlvl = FIELD_GET(STM32F7_SPI_SR_FRLVL, sr);
 736         }
 737
 738         if (spi->rx_len >= sizeof(u16))
 739                 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);
 740         else
 741                 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);
 742
 743         dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
 744                 __func__, spi->rx_len, sr);
 745 }
 746
 747 /**
 748  * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
 749  * @spi: pointer to the spi controller data structure
 750  *
 751  * Write in rx_buf depends on remaining bytes to avoid to write beyond
 752  * rx_buf end.
 753  */
 754 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi)
 755 {
 756         u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
 757         u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
 758
 759         while ((spi->rx_len > 0) &&
 760                ((sr & STM32H7_SPI_SR_RXP) ||
 761                 ((sr & STM32H7_SPI_SR_EOT) &&
 762                  ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
 763                 u32 offs = spi->cur_xferlen - spi->rx_len;
 764
 765                 if ((spi->rx_len >= sizeof(u32)) ||
 766                     (sr & STM32H7_SPI_SR_RXWNE)) {
 767                         u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
 768
 769                         *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
 770                         spi->rx_len -= sizeof(u32);
 771                 } else if ((spi->rx_len >= sizeof(u16)) ||
 772                            (!(sr & STM32H7_SPI_SR_RXWNE) &&
 773                             (rxplvl >= 2 || spi->cur_bpw > 8))) {
 774                         u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
 775
 776                         *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
 777                         spi->rx_len -= sizeof(u16);
 778                 } else {
 779                         u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
 780
 781                         *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
 782                         spi->rx_len -= sizeof(u8);
 783                 }
 784
 785                 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
 786                 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
 787         }
 788
 789         dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
 790                 __func__, spi->rx_len, sr);
 791 }
 792
 793 /**
 794  * stm32_spi_enable - Enable SPI controller
 795  * @spi: pointer to the spi controller data structure
 796  */
 797 static void stm32_spi_enable(struct stm32_spi *spi)
 798 {
 799         dev_dbg(spi->dev, "enable controller\n");
 800
 801         stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
 802                            spi->cfg->regs->en.mask);
 803 }
 804
 805 /**
 806  * stm32fx_spi_disable - Disable SPI controller
 807  * @spi: pointer to the spi controller data structure
 808  */
 809 static void stm32fx_spi_disable(struct stm32_spi *spi)
 810 {
 811         unsigned long flags;
 812         u32 sr;
 813
 814         dev_dbg(spi->dev, "disable controller\n");
 815
 816         spin_lock_irqsave(&spi->lock, flags);
 817
 818         if (!(readl_relaxed(spi->base + STM32FX_SPI_CR1) &
 819               STM32FX_SPI_CR1_SPE)) {
 820                 spin_unlock_irqrestore(&spi->lock, flags);
 821                 return;
 822         }
 823
 824         /* Disable interrupts */
 825         stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXEIE |
 826                                                  STM32FX_SPI_CR2_RXNEIE |
 827                                                  STM32FX_SPI_CR2_ERRIE);
 828
 829         /* Wait until BSY = 0 */
 830         if (readl_relaxed_poll_timeout_atomic(spi->base + STM32FX_SPI_SR,
 831                                               sr, !(sr & STM32FX_SPI_SR_BSY),
 832                                               10, 100000) < 0) {
 833                 dev_warn(spi->dev, "disabling condition timeout\n");
 834         }
 835
 836         if (spi->cur_usedma && spi->dma_tx)
 837                 dmaengine_terminate_async(spi->dma_tx);
 838         if (spi->cur_usedma && spi->dma_rx)
 839                 dmaengine_terminate_async(spi->dma_rx);
 840
 841         stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, STM32FX_SPI_CR1_SPE);
 842
 843         stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXDMAEN |
 844                                                  STM32FX_SPI_CR2_RXDMAEN);
 845
 846         /* Sequence to clear OVR flag */
 847         readl_relaxed(spi->base + STM32FX_SPI_DR);
 848         readl_relaxed(spi->base + STM32FX_SPI_SR);
 849
 850         spin_unlock_irqrestore(&spi->lock, flags);
 851 }
 852
 853 /**
 854  * stm32h7_spi_disable - Disable SPI controller
 855  * @spi: pointer to the spi controller data structure
 856  *
 857  * RX-Fifo is flushed when SPI controller is disabled.
 858  */
 859 static void stm32h7_spi_disable(struct stm32_spi *spi)
 860 {
 861         unsigned long flags;
 862         u32 cr1;
 863
 864         dev_dbg(spi->dev, "disable controller\n");
 865
 866         spin_lock_irqsave(&spi->lock, flags);
 867
 868         cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
 869
 870         if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
 871                 spin_unlock_irqrestore(&spi->lock, flags);
 872                 return;
 873         }
 874
 875         /* Add a delay to make sure that transmission is ended. */
 876         if (spi->cur_half_period)
 877                 udelay(spi->cur_half_period);
 878
 879         if (spi->cur_usedma && spi->dma_tx)
 880                 dmaengine_terminate_async(spi->dma_tx);
 881         if (spi->cur_usedma && spi->dma_rx)
 882                 dmaengine_terminate_async(spi->dma_rx);
 883
 884         stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
 885
 886         stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
 887                                                 STM32H7_SPI_CFG1_RXDMAEN);
 888
 889         /* Disable interrupts and clear status flags */
 890         writel_relaxed(0, spi->base + STM32H7_SPI_IER);
 891         writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
 892
 893         spin_unlock_irqrestore(&spi->lock, flags);
 894 }
 895
 896 /**
 897  * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
 898  * @ctrl: controller interface
 899  * @spi_dev: pointer to the spi device
 900  * @transfer: pointer to spi transfer
 901  *
 902  * If driver has fifo and the current transfer size is greater than fifo size,
 903  * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
 904  */
 905 static bool stm32_spi_can_dma(struct spi_controller *ctrl,
 906                               struct spi_device *spi_dev,
 907                               struct spi_transfer *transfer)
 908 {
 909         unsigned int dma_size;
 910         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
 911
 912         if (spi->cfg->has_fifo)
 913                 dma_size = spi->fifo_size;
 914         else
 915                 dma_size = SPI_DMA_MIN_BYTES;
 916
 917         dev_dbg(spi->dev, "%s: %s\n", __func__,
 918                 (transfer->len > dma_size) ? "true" : "false");
 919
 920         return (transfer->len > dma_size);
 921 }
 922
 923 /**
 924  * stm32fx_spi_irq_event - Interrupt handler for SPI controller events
 925  * @irq: interrupt line
 926  * @dev_id: SPI controller ctrl interface
 927  */
 928 static irqreturn_t stm32fx_spi_irq_event(int irq, void *dev_id)
 929 {
 930         struct spi_controller *ctrl = dev_id;
 931         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
 932         u32 sr, mask = 0;
 933         bool end = false;
 934
 935         spin_lock(&spi->lock);
 936
 937         sr = readl_relaxed(spi->base + STM32FX_SPI_SR);
 938         /*
 939          * BSY flag is not handled in interrupt but it is normal behavior when
 940          * this flag is set.
 941          */
 942         sr &= ~STM32FX_SPI_SR_BSY;
 943
 944         if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
 945                                  spi->cur_comm == SPI_3WIRE_TX)) {
 946                 /* OVR flag shouldn't be handled for TX only mode */
 947                 sr &= ~(STM32FX_SPI_SR_OVR | STM32FX_SPI_SR_RXNE);
 948                 mask |= STM32FX_SPI_SR_TXE;
 949         }
 950
 951         if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
 952                                 spi->cur_comm == SPI_SIMPLEX_RX ||
 953                                 spi->cur_comm == SPI_3WIRE_RX)) {
 954                 /* TXE flag is set and is handled when RXNE flag occurs */
 955                 sr &= ~STM32FX_SPI_SR_TXE;
 956                 mask |= STM32FX_SPI_SR_RXNE | STM32FX_SPI_SR_OVR;
 957         }
 958
 959         if (!(sr & mask)) {
 960                 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
 961                 spin_unlock(&spi->lock);
 962                 return IRQ_NONE;
 963         }
 964
 965         if (sr & STM32FX_SPI_SR_OVR) {
 966                 dev_warn(spi->dev, "Overrun: received value discarded\n");
 967
 968                 /* Sequence to clear OVR flag */
 969                 readl_relaxed(spi->base + STM32FX_SPI_DR);
 970                 readl_relaxed(spi->base + STM32FX_SPI_SR);
 971
 972                 /*
 973                  * If overrun is detected, it means that something went wrong,
 974                  * so stop the current transfer. Transfer can wait for next
 975                  * RXNE but DR is already read and end never happens.
 976                  */
 977                 end = true;
 978                 goto end_irq;
 979         }
 980
 981         if (sr & STM32FX_SPI_SR_TXE) {
 982                 if (spi->tx_buf)
 983                         spi->cfg->write_tx(spi);
 984                 if (spi->tx_len == 0)
 985                         end = true;
 986         }
 987
 988         if (sr & STM32FX_SPI_SR_RXNE) {
 989                 spi->cfg->read_rx(spi);
 990                 if (spi->rx_len == 0)
 991                         end = true;
 992                 else if (spi->tx_buf)/* Load data for discontinuous mode */
 993                         spi->cfg->write_tx(spi);
 994         }
 995
 996 end_irq:
 997         if (end) {
 998                 /* Immediately disable interrupts to do not generate new one */
 999                 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2,
1000                                         STM32FX_SPI_CR2_TXEIE |
1001                                         STM32FX_SPI_CR2_RXNEIE |
1002                                         STM32FX_SPI_CR2_ERRIE);
1003                 spin_unlock(&spi->lock);
1004                 return IRQ_WAKE_THREAD;
1005         }
1006
1007         spin_unlock(&spi->lock);
1008         return IRQ_HANDLED;
1009 }
1010
1011 /**
1012  * stm32fx_spi_irq_thread - Thread of interrupt handler for SPI controller
1013  * @irq: interrupt line
1014  * @dev_id: SPI controller interface
1015  */
1016 static irqreturn_t stm32fx_spi_irq_thread(int irq, void *dev_id)
1017 {
1018         struct spi_controller *ctrl = dev_id;
1019
1020         spi_finalize_current_transfer(ctrl);
1021
1022         return IRQ_HANDLED;
1023 }
1024
1025 /**
1026  * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
1027  * @irq: interrupt line
1028  * @dev_id: SPI controller interface
1029  */
1030 static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
1031 {
1032         struct spi_controller *ctrl = dev_id;
1033         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1034         u32 sr, ier, mask;
1035         unsigned long flags;
1036         bool end = false;
1037
1038         spin_lock_irqsave(&spi->lock, flags);
1039
1040         sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
1041         ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
1042
1043         mask = ier;
1044         /*
1045          * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
1046          * SUSP to acknowledge it later. TXC is automatically cleared
1047          */
1048
1049         mask |= STM32H7_SPI_SR_SUSP;
1050         /*
1051          * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
1052          * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
1053          */
1054         if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
1055                 mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
1056
1057         if (!(sr & mask)) {
1058                 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
1059                          sr, ier);
1060                 spin_unlock_irqrestore(&spi->lock, flags);
1061                 return IRQ_NONE;
1062         }
1063
1064         if (sr & STM32H7_SPI_SR_SUSP) {
1065                 static DEFINE_RATELIMIT_STATE(rs,
1066                                               DEFAULT_RATELIMIT_INTERVAL * 10,
1067                                               1);
1068                 ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
1069                 if (__ratelimit(&rs))
1070                         dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
1071                 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
1072                         stm32h7_spi_read_rxfifo(spi);
1073                 /*
1074                  * If communication is suspended while using DMA, it means
1075                  * that something went wrong, so stop the current transfer
1076                  */
1077                 if (spi->cur_usedma)
1078                         end = true;
1079         }
1080
1081         if (sr & STM32H7_SPI_SR_MODF) {
1082                 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
1083                 end = true;
1084         }
1085
1086         if (sr & STM32H7_SPI_SR_OVR) {
1087                 dev_err(spi->dev, "Overrun: RX data lost\n");
1088                 end = true;
1089         }
1090
1091         if (sr & STM32H7_SPI_SR_EOT) {
1092                 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
1093                         stm32h7_spi_read_rxfifo(spi);
1094                 if (!spi->cur_usedma ||
1095                     (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX))
1096                         end = true;
1097         }
1098
1099         if (sr & STM32H7_SPI_SR_TXP)
1100                 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
1101                         stm32h7_spi_write_txfifo(spi);
1102
1103         if (sr & STM32H7_SPI_SR_RXP)
1104                 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
1105                         stm32h7_spi_read_rxfifo(spi);
1106
1107         writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
1108
1109         spin_unlock_irqrestore(&spi->lock, flags);
1110
1111         if (end) {
1112                 stm32h7_spi_disable(spi);
1113                 spi_finalize_current_transfer(ctrl);
1114         }
1115
1116         return IRQ_HANDLED;
1117 }
1118
1119 static int stm32_spi_optimize_message(struct spi_message *msg)
1120 {
1121         struct spi_controller *ctrl = msg->spi->controller;
1122         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1123
1124         /* On STM32H7, messages should not exceed a maximum size set
1125          * later via the set_number_of_data function. In order to
1126          * ensure that, split large messages into several messages
1127          */
1128         if (spi->cfg->set_number_of_data)
1129                 return spi_split_transfers_maxwords(ctrl, msg, spi->t_size_max);
1130
1131         return 0;
1132 }
1133
1134 /**
1135  * stm32_spi_prepare_msg - set up the controller to transfer a single message
1136  * @ctrl: controller interface
1137  * @msg: pointer to spi message
1138  */
1139 static int stm32_spi_prepare_msg(struct spi_controller *ctrl,
1140                                  struct spi_message *msg)
1141 {
1142         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1143         struct spi_device *spi_dev = msg->spi;
1144         struct device_node *np = spi_dev->dev.of_node;
1145         unsigned long flags;
1146         u32 clrb = 0, setb = 0;
1147
1148         /* SPI target device may need time between data frames */
1149         spi->cur_midi = 0;
1150         if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
1151                 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
1152
1153         if (spi_dev->mode & SPI_CPOL)
1154                 setb |= spi->cfg->regs->cpol.mask;
1155         else
1156                 clrb |= spi->cfg->regs->cpol.mask;
1157
1158         if (spi_dev->mode & SPI_CPHA)
1159                 setb |= spi->cfg->regs->cpha.mask;
1160         else
1161                 clrb |= spi->cfg->regs->cpha.mask;
1162
1163         if (spi_dev->mode & SPI_LSB_FIRST)
1164                 setb |= spi->cfg->regs->lsb_first.mask;
1165         else
1166                 clrb |= spi->cfg->regs->lsb_first.mask;
1167
1168         if (STM32_SPI_DEVICE_MODE(spi) && spi_dev->mode & SPI_CS_HIGH)
1169                 setb |= spi->cfg->regs->cs_high.mask;
1170         else
1171                 clrb |= spi->cfg->regs->cs_high.mask;
1172
1173         dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1174                 !!(spi_dev->mode & SPI_CPOL),
1175                 !!(spi_dev->mode & SPI_CPHA),
1176                 !!(spi_dev->mode & SPI_LSB_FIRST),
1177                 !!(spi_dev->mode & SPI_CS_HIGH));
1178
1179         spin_lock_irqsave(&spi->lock, flags);
1180
1181         /* CPOL, CPHA and LSB FIRST bits have common register */
1182         if (clrb || setb)
1183                 writel_relaxed(
1184                         (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1185                          ~clrb) | setb,
1186                         spi->base + spi->cfg->regs->cpol.reg);
1187
1188         stm32_spi_enable(spi);
1189
1190         spin_unlock_irqrestore(&spi->lock, flags);
1191
1192         return 0;
1193 }
1194
1195 /**
1196  * stm32fx_spi_dma_tx_cb - dma callback
1197  * @data: pointer to the spi controller data structure
1198  *
1199  * DMA callback is called when the transfer is complete for DMA TX channel.
1200  */
1201 static void stm32fx_spi_dma_tx_cb(void *data)
1202 {
1203         struct stm32_spi *spi = data;
1204
1205         if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1206                 spi_finalize_current_transfer(spi->ctrl);
1207         }
1208 }
1209
1210 /**
1211  * stm32_spi_dma_rx_cb - dma callback
1212  * @data: pointer to the spi controller data structure
1213  *
1214  * DMA callback is called when the transfer is complete for DMA RX channel.
1215  */
1216 static void stm32_spi_dma_rx_cb(void *data)
1217 {
1218         struct stm32_spi *spi = data;
1219
1220         spi_finalize_current_transfer(spi->ctrl);
1221 }
1222
1223 /**
1224  * stm32_spi_dma_config - configure dma slave channel depending on current
1225  *                        transfer bits_per_word.
1226  * @spi: pointer to the spi controller data structure
1227  * @dma_chan: pointer to the DMA channel
1228  * @dma_conf: pointer to the dma_slave_config structure
1229  * @dir: direction of the dma transfer
1230  */
1231 static void stm32_spi_dma_config(struct stm32_spi *spi,
1232                                  struct dma_chan *dma_chan,
1233                                  struct dma_slave_config *dma_conf,
1234                                  enum dma_transfer_direction dir)
1235 {
1236         enum dma_slave_buswidth buswidth;
1237         struct dma_slave_caps caps;
1238         u32 maxburst = 1;
1239         int ret;
1240
1241         if (spi->cur_bpw <= 8)
1242                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1243         else if (spi->cur_bpw <= 16)
1244                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1245         else
1246                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1247
1248         /* Valid for DMA Half or Full Fifo threshold */
1249         if (!spi->cfg->prevent_dma_burst && spi->cfg->has_fifo && spi->cur_fthlv != 2)
1250                 maxburst = spi->cur_fthlv;
1251
1252         /* Get the DMA channel caps, and adjust maxburst if possible */
1253         ret = dma_get_slave_caps(dma_chan, &caps);
1254         if (!ret)
1255                 maxburst = min(maxburst, caps.max_burst);
1256
1257         memset(dma_conf, 0, sizeof(struct dma_slave_config));
1258         dma_conf->direction = dir;
1259         if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1260                 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1261                 dma_conf->src_addr_width = buswidth;
1262                 dma_conf->src_maxburst = maxburst;
1263
1264                 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1265                         buswidth, maxburst);
1266         } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1267                 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1268                 dma_conf->dst_addr_width = buswidth;
1269                 dma_conf->dst_maxburst = maxburst;
1270
1271                 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1272                         buswidth, maxburst);
1273         }
1274 }
1275
1276 /**
1277  * stm32fx_spi_transfer_one_irq - transfer a single spi_transfer using
1278  *                                interrupts
1279  * @spi: pointer to the spi controller data structure
1280  *
1281  * It must returns 0 if the transfer is finished or 1 if the transfer is still
1282  * in progress.
1283  */
1284 static int stm32fx_spi_transfer_one_irq(struct stm32_spi *spi)
1285 {
1286         unsigned long flags;
1287         u32 cr2 = 0;
1288
1289         /* Enable the interrupts relative to the current communication mode */
1290         if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1291                 cr2 |= STM32FX_SPI_CR2_TXEIE;
1292         } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1293                                 spi->cur_comm == SPI_SIMPLEX_RX ||
1294                                 spi->cur_comm == SPI_3WIRE_RX) {
1295                 /* In transmit-only mode, the OVR flag is set in the SR register
1296                  * since the received data are never read. Therefore set OVR
1297                  * interrupt only when rx buffer is available.
1298                  */
1299                 cr2 |= STM32FX_SPI_CR2_RXNEIE | STM32FX_SPI_CR2_ERRIE;
1300         } else {
1301                 return -EINVAL;
1302         }
1303
1304         spin_lock_irqsave(&spi->lock, flags);
1305
1306         stm32_spi_set_bits(spi, STM32FX_SPI_CR2, cr2);
1307
1308         /* starting data transfer when buffer is loaded */
1309         if (spi->tx_buf)
1310                 spi->cfg->write_tx(spi);
1311
1312         spin_unlock_irqrestore(&spi->lock, flags);
1313
1314         return 1;
1315 }
1316
1317 /**
1318  * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1319  *                                interrupts
1320  * @spi: pointer to the spi controller data structure
1321  *
1322  * It must returns 0 if the transfer is finished or 1 if the transfer is still
1323  * in progress.
1324  */
1325 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1326 {
1327         unsigned long flags;
1328         u32 ier = 0;
1329
1330         /* Enable the interrupts relative to the current communication mode */
1331         if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1332                 ier |= STM32H7_SPI_IER_DXPIE;
1333         else if (spi->tx_buf)           /* Half-Duplex TX dir or Simplex TX */
1334                 ier |= STM32H7_SPI_IER_TXPIE;
1335         else if (spi->rx_buf)           /* Half-Duplex RX dir or Simplex RX */
1336                 ier |= STM32H7_SPI_IER_RXPIE;
1337
1338         /* Enable the interrupts relative to the end of transfer */
1339         ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1340                STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1341
1342         spin_lock_irqsave(&spi->lock, flags);
1343
1344         /* Be sure to have data in fifo before starting data transfer */
1345         if (spi->tx_buf)
1346                 stm32h7_spi_write_txfifo(spi);
1347
1348         if (STM32_SPI_HOST_MODE(spi))
1349                 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1350
1351         writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1352
1353         spin_unlock_irqrestore(&spi->lock, flags);
1354
1355         return 1;
1356 }
1357
1358 /**
1359  * stm32fx_spi_transfer_one_dma_start - Set SPI driver registers to start
1360  *                                      transfer using DMA
1361  * @spi: pointer to the spi controller data structure
1362  */
1363 static void stm32fx_spi_transfer_one_dma_start(struct stm32_spi *spi)
1364 {
1365         /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1366         if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1367             spi->cur_comm == SPI_FULL_DUPLEX) {
1368                 /*
1369                  * In transmit-only mode, the OVR flag is set in the SR register
1370                  * since the received data are never read. Therefore set OVR
1371                  * interrupt only when rx buffer is available.
1372                  */
1373                 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_ERRIE);
1374         }
1375 }
1376
1377 /**
1378  * stm32f7_spi_transfer_one_dma_start - Set SPI driver registers to start
1379  *                                      transfer using DMA
1380  * @spi: pointer to the spi controller data structure
1381  */
1382 static void stm32f7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1383 {
1384         /* Configure DMA request trigger threshold according to DMA width */
1385         if (spi->cur_bpw <= 8)
1386                 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);
1387         else
1388                 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);
1389
1390         stm32fx_spi_transfer_one_dma_start(spi);
1391 }
1392
1393 /**
1394  * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1395  *                                      transfer using DMA
1396  * @spi: pointer to the spi controller data structure
1397  */
1398 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1399 {
1400         uint32_t ier = STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1401
1402         /* Enable the interrupts */
1403         if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
1404                 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
1405
1406         stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
1407
1408         if (STM32_SPI_HOST_MODE(spi))
1409                 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1410 }
1411
1412 /**
1413  * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1414  * @spi: pointer to the spi controller data structure
1415  * @xfer: pointer to the spi_transfer structure
1416  *
1417  * It must returns 0 if the transfer is finished or 1 if the transfer is still
1418  * in progress.
1419  */
1420 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1421                                       struct spi_transfer *xfer)
1422 {
1423         struct dma_slave_config tx_dma_conf, rx_dma_conf;
1424         struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1425         unsigned long flags;
1426
1427         spin_lock_irqsave(&spi->lock, flags);
1428
1429         rx_dma_desc = NULL;
1430         if (spi->rx_buf && spi->dma_rx) {
1431                 stm32_spi_dma_config(spi, spi->dma_rx, &rx_dma_conf, DMA_DEV_TO_MEM);
1432                 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1433
1434                 /* Enable Rx DMA request */
1435                 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1436                                    spi->cfg->regs->dma_rx_en.mask);
1437
1438                 rx_dma_desc = dmaengine_prep_slave_sg(
1439                                         spi->dma_rx, xfer->rx_sg.sgl,
1440                                         xfer->rx_sg.nents,
1441                                         rx_dma_conf.direction,
1442                                         DMA_PREP_INTERRUPT);
1443         }
1444
1445         tx_dma_desc = NULL;
1446         if (spi->tx_buf && spi->dma_tx) {
1447                 stm32_spi_dma_config(spi, spi->dma_tx, &tx_dma_conf, DMA_MEM_TO_DEV);
1448                 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1449
1450                 tx_dma_desc = dmaengine_prep_slave_sg(
1451                                         spi->dma_tx, xfer->tx_sg.sgl,
1452                                         xfer->tx_sg.nents,
1453                                         tx_dma_conf.direction,
1454                                         DMA_PREP_INTERRUPT);
1455         }
1456
1457         if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1458             (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1459                 goto dma_desc_error;
1460
1461         if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1462                 goto dma_desc_error;
1463
1464         if (rx_dma_desc) {
1465                 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1466                 rx_dma_desc->callback_param = spi;
1467
1468                 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1469                         dev_err(spi->dev, "Rx DMA submit failed\n");
1470                         goto dma_desc_error;
1471                 }
1472                 /* Enable Rx DMA channel */
1473                 dma_async_issue_pending(spi->dma_rx);
1474         }
1475
1476         if (tx_dma_desc) {
1477                 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1478                     spi->cur_comm == SPI_3WIRE_TX) {
1479                         tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1480                         tx_dma_desc->callback_param = spi;
1481                 }
1482
1483                 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1484                         dev_err(spi->dev, "Tx DMA submit failed\n");
1485                         goto dma_submit_error;
1486                 }
1487                 /* Enable Tx DMA channel */
1488                 dma_async_issue_pending(spi->dma_tx);
1489
1490                 /* Enable Tx DMA request */
1491                 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1492                                    spi->cfg->regs->dma_tx_en.mask);
1493         }
1494
1495         spi->cfg->transfer_one_dma_start(spi);
1496
1497         spin_unlock_irqrestore(&spi->lock, flags);
1498
1499         return 1;
1500
1501 dma_submit_error:
1502         if (spi->dma_rx)
1503                 dmaengine_terminate_sync(spi->dma_rx);
1504
1505 dma_desc_error:
1506         stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1507                            spi->cfg->regs->dma_rx_en.mask);
1508
1509         spin_unlock_irqrestore(&spi->lock, flags);
1510
1511         dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1512
1513         spi->cur_usedma = false;
1514         return spi->cfg->transfer_one_irq(spi);
1515 }
1516
1517 /**
1518  * stm32f4_spi_set_bpw - Configure bits per word
1519  * @spi: pointer to the spi controller data structure
1520  */
1521 static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1522 {
1523         if (spi->cur_bpw == 16)
1524                 stm32_spi_set_bits(spi, STM32FX_SPI_CR1, STM32F4_SPI_CR1_DFF);
1525         else
1526                 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, STM32F4_SPI_CR1_DFF);
1527 }
1528
1529 /**
1530  * stm32f7_spi_set_bpw - Configure bits per word
1531  * @spi: pointer to the spi controller data structure
1532  */
1533 static void stm32f7_spi_set_bpw(struct stm32_spi *spi)
1534 {
1535         u32 bpw;
1536         u32 cr2_clrb = 0, cr2_setb = 0;
1537
1538         bpw = spi->cur_bpw - 1;
1539
1540         cr2_clrb |= STM32F7_SPI_CR2_DS;
1541         cr2_setb |= FIELD_PREP(STM32F7_SPI_CR2_DS, bpw);
1542
1543         if (spi->rx_len >= sizeof(u16))
1544                 cr2_clrb |= STM32F7_SPI_CR2_FRXTH;
1545         else
1546                 cr2_setb |= STM32F7_SPI_CR2_FRXTH;
1547
1548         writel_relaxed(
1549                 (readl_relaxed(spi->base + STM32FX_SPI_CR2) &
1550                  ~cr2_clrb) | cr2_setb,
1551                 spi->base + STM32FX_SPI_CR2);
1552 }
1553
1554 /**
1555  * stm32h7_spi_set_bpw - configure bits per word
1556  * @spi: pointer to the spi controller data structure
1557  */
1558 static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1559 {
1560         u32 bpw, fthlv;
1561         u32 cfg1_clrb = 0, cfg1_setb = 0;
1562
1563         bpw = spi->cur_bpw - 1;
1564
1565         cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1566         cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
1567
1568         spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1569         fthlv = spi->cur_fthlv - 1;
1570
1571         cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1572         cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
1573
1574         writel_relaxed(
1575                 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1576                  ~cfg1_clrb) | cfg1_setb,
1577                 spi->base + STM32H7_SPI_CFG1);
1578 }
1579
1580 /**
1581  * stm32_spi_set_mbr - Configure baud rate divisor in host mode
1582  * @spi: pointer to the spi controller data structure
1583  * @mbrdiv: baud rate divisor value
1584  */
1585 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1586 {
1587         u32 clrb = 0, setb = 0;
1588
1589         clrb |= spi->cfg->regs->br.mask;
1590         setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1591
1592         writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1593                         ~clrb) | setb,
1594                        spi->base + spi->cfg->regs->br.reg);
1595 }
1596
1597 /**
1598  * stm32_spi_communication_type - return transfer communication type
1599  * @spi_dev: pointer to the spi device
1600  * @transfer: pointer to spi transfer
1601  */
1602 static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1603                                                  struct spi_transfer *transfer)
1604 {
1605         unsigned int type = SPI_FULL_DUPLEX;
1606
1607         if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1608                 /*
1609                  * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1610                  * is forbidden and unvalidated by SPI subsystem so depending
1611                  * on the valid buffer, we can determine the direction of the
1612                  * transfer.
1613                  */
1614                 if (!transfer->tx_buf)
1615                         type = SPI_3WIRE_RX;
1616                 else
1617                         type = SPI_3WIRE_TX;
1618         } else {
1619                 if (!transfer->tx_buf)
1620                         type = SPI_SIMPLEX_RX;
1621                 else if (!transfer->rx_buf)
1622                         type = SPI_SIMPLEX_TX;
1623         }
1624
1625         return type;
1626 }
1627
1628 /**
1629  * stm32fx_spi_set_mode - configure communication mode
1630  * @spi: pointer to the spi controller data structure
1631  * @comm_type: type of communication to configure
1632  */
1633 static int stm32fx_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1634 {
1635         if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1636                 stm32_spi_set_bits(spi, STM32FX_SPI_CR1,
1637                                         STM32FX_SPI_CR1_BIDIMODE |
1638                                         STM32FX_SPI_CR1_BIDIOE);
1639         } else if (comm_type == SPI_FULL_DUPLEX ||
1640                                 comm_type == SPI_SIMPLEX_RX) {
1641                 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1,
1642                                         STM32FX_SPI_CR1_BIDIMODE |
1643                                         STM32FX_SPI_CR1_BIDIOE);
1644         } else if (comm_type == SPI_3WIRE_RX) {
1645                 stm32_spi_set_bits(spi, STM32FX_SPI_CR1,
1646                                         STM32FX_SPI_CR1_BIDIMODE);
1647                 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1,
1648                                         STM32FX_SPI_CR1_BIDIOE);
1649         } else {
1650                 return -EINVAL;
1651         }
1652
1653         return 0;
1654 }
1655
1656 /**
1657  * stm32h7_spi_set_mode - configure communication mode
1658  * @spi: pointer to the spi controller data structure
1659  * @comm_type: type of communication to configure
1660  */
1661 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1662 {
1663         u32 mode;
1664         u32 cfg2_clrb = 0, cfg2_setb = 0;
1665
1666         if (comm_type == SPI_3WIRE_RX) {
1667                 mode = STM32H7_SPI_HALF_DUPLEX;
1668                 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1669         } else if (comm_type == SPI_3WIRE_TX) {
1670                 mode = STM32H7_SPI_HALF_DUPLEX;
1671                 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1672         } else if (comm_type == SPI_SIMPLEX_RX) {
1673                 mode = STM32H7_SPI_SIMPLEX_RX;
1674         } else if (comm_type == SPI_SIMPLEX_TX) {
1675                 mode = STM32H7_SPI_SIMPLEX_TX;
1676         } else {
1677                 mode = STM32H7_SPI_FULL_DUPLEX;
1678         }
1679
1680         cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1681         cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
1682
1683         writel_relaxed(
1684                 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1685                  ~cfg2_clrb) | cfg2_setb,
1686                 spi->base + STM32H7_SPI_CFG2);
1687
1688         return 0;
1689 }
1690
1691 /**
1692  * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1693  *                             consecutive data frames in host mode
1694  * @spi: pointer to the spi controller data structure
1695  * @len: transfer len
1696  */
1697 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1698 {
1699         u32 cfg2_clrb = 0, cfg2_setb = 0;
1700
1701         cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1702         if ((len > 1) && (spi->cur_midi > 0)) {
1703                 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
1704                 u32 midi = min_t(u32,
1705                                  DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1706                                  FIELD_GET(STM32H7_SPI_CFG2_MIDI,
1707                                  STM32H7_SPI_CFG2_MIDI));
1708
1709
1710                 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1711                         sck_period_ns, midi, midi * sck_period_ns);
1712                 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
1713         }
1714
1715         writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1716                         ~cfg2_clrb) | cfg2_setb,
1717                        spi->base + STM32H7_SPI_CFG2);
1718 }
1719
1720 /**
1721  * stm32h7_spi_number_of_data - configure number of data at current transfer
1722  * @spi: pointer to the spi controller data structure
1723  * @nb_words: transfer length (in words)
1724  */
1725 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1726 {
1727         if (nb_words <= spi->t_size_max) {
1728                 writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
1729                                spi->base + STM32H7_SPI_CR2);
1730         } else {
1731                 return -EMSGSIZE;
1732         }
1733
1734         return 0;
1735 }
1736
1737 /**
1738  * stm32_spi_transfer_one_setup - common setup to transfer a single
1739  *                                spi_transfer either using DMA or
1740  *                                interrupts.
1741  * @spi: pointer to the spi controller data structure
1742  * @spi_dev: pointer to the spi device
1743  * @transfer: pointer to spi transfer
1744  */
1745 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1746                                         struct spi_device *spi_dev,
1747                                         struct spi_transfer *transfer)
1748 {
1749         unsigned long flags;
1750         unsigned int comm_type;
1751         int nb_words, ret = 0;
1752         int mbr;
1753
1754         spin_lock_irqsave(&spi->lock, flags);
1755
1756         spi->cur_xferlen = transfer->len;
1757
1758         spi->cur_bpw = transfer->bits_per_word;
1759         spi->cfg->set_bpw(spi);
1760
1761         /* Update spi->cur_speed with real clock speed */
1762         if (STM32_SPI_HOST_MODE(spi)) {
1763                 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1764                                             spi->cfg->baud_rate_div_min,
1765                                             spi->cfg->baud_rate_div_max);
1766                 if (mbr < 0) {
1767                         ret = mbr;
1768                         goto out;
1769                 }
1770
1771                 transfer->speed_hz = spi->cur_speed;
1772                 stm32_spi_set_mbr(spi, mbr);
1773         }
1774
1775         comm_type = stm32_spi_communication_type(spi_dev, transfer);
1776         ret = spi->cfg->set_mode(spi, comm_type);
1777         if (ret < 0)
1778                 goto out;
1779
1780         spi->cur_comm = comm_type;
1781
1782         if (STM32_SPI_HOST_MODE(spi) && spi->cfg->set_data_idleness)
1783                 spi->cfg->set_data_idleness(spi, transfer->len);
1784
1785         if (spi->cur_bpw <= 8)
1786                 nb_words = transfer->len;
1787         else if (spi->cur_bpw <= 16)
1788                 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1789         else
1790                 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1791
1792         if (spi->cfg->set_number_of_data) {
1793                 ret = spi->cfg->set_number_of_data(spi, nb_words);
1794                 if (ret < 0)
1795                         goto out;
1796         }
1797
1798         dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1799                 spi->cur_comm);
1800         dev_dbg(spi->dev,
1801                 "data frame of %d-bit, data packet of %d data frames\n",
1802                 spi->cur_bpw, spi->cur_fthlv);
1803         if (STM32_SPI_HOST_MODE(spi))
1804                 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1805         dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1806                 spi->cur_xferlen, nb_words);
1807         dev_dbg(spi->dev, "dma %s\n",
1808                 (spi->cur_usedma) ? "enabled" : "disabled");
1809
1810 out:
1811         spin_unlock_irqrestore(&spi->lock, flags);
1812
1813         return ret;
1814 }
1815
1816 /**
1817  * stm32_spi_transfer_one - transfer a single spi_transfer
1818  * @ctrl: controller interface
1819  * @spi_dev: pointer to the spi device
1820  * @transfer: pointer to spi transfer
1821  *
1822  * It must return 0 if the transfer is finished or 1 if the transfer is still
1823  * in progress.
1824  */
1825 static int stm32_spi_transfer_one(struct spi_controller *ctrl,
1826                                   struct spi_device *spi_dev,
1827                                   struct spi_transfer *transfer)
1828 {
1829         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1830         int ret;
1831
1832         spi->tx_buf = transfer->tx_buf;
1833         spi->rx_buf = transfer->rx_buf;
1834         spi->tx_len = spi->tx_buf ? transfer->len : 0;
1835         spi->rx_len = spi->rx_buf ? transfer->len : 0;
1836
1837         spi->cur_usedma = (ctrl->can_dma &&
1838                            ctrl->can_dma(ctrl, spi_dev, transfer));
1839
1840         ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1841         if (ret) {
1842                 dev_err(spi->dev, "SPI transfer setup failed\n");
1843                 return ret;
1844         }
1845
1846         if (spi->cur_usedma)
1847                 return stm32_spi_transfer_one_dma(spi, transfer);
1848         else
1849                 return spi->cfg->transfer_one_irq(spi);
1850 }
1851
1852 /**
1853  * stm32_spi_unprepare_msg - relax the hardware
1854  * @ctrl: controller interface
1855  * @msg: pointer to the spi message
1856  */
1857 static int stm32_spi_unprepare_msg(struct spi_controller *ctrl,
1858                                    struct spi_message *msg)
1859 {
1860         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1861
1862         spi->cfg->disable(spi);
1863
1864         return 0;
1865 }
1866
1867 /**
1868  * stm32fx_spi_config - Configure SPI controller as SPI host
1869  * @spi: pointer to the spi controller data structure
1870  */
1871 static int stm32fx_spi_config(struct stm32_spi *spi)
1872 {
1873         unsigned long flags;
1874
1875         spin_lock_irqsave(&spi->lock, flags);
1876
1877         /* Ensure I2SMOD bit is kept cleared */
1878         stm32_spi_clr_bits(spi, STM32FX_SPI_I2SCFGR,
1879                            STM32FX_SPI_I2SCFGR_I2SMOD);
1880
1881         /*
1882          * - SS input value high
1883          * - transmitter half duplex direction
1884          * - Set the host mode (default Motorola mode)
1885          * - Consider 1 host/n targets configuration and
1886          *   SS input value is determined by the SSI bit
1887          */
1888         stm32_spi_set_bits(spi, STM32FX_SPI_CR1, STM32FX_SPI_CR1_SSI |
1889                                                  STM32FX_SPI_CR1_BIDIOE |
1890                                                  STM32FX_SPI_CR1_MSTR |
1891                                                  STM32FX_SPI_CR1_SSM);
1892
1893         spin_unlock_irqrestore(&spi->lock, flags);
1894
1895         return 0;
1896 }
1897
1898 /**
1899  * stm32h7_spi_config - Configure SPI controller
1900  * @spi: pointer to the spi controller data structure
1901  */
1902 static int stm32h7_spi_config(struct stm32_spi *spi)
1903 {
1904         unsigned long flags;
1905         u32 cr1 = 0, cfg2 = 0;
1906
1907         spin_lock_irqsave(&spi->lock, flags);
1908
1909         /* Ensure I2SMOD bit is kept cleared */
1910         stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1911                            STM32H7_SPI_I2SCFGR_I2SMOD);
1912
1913         if (STM32_SPI_DEVICE_MODE(spi)) {
1914                 /* Use native device select */
1915                 cfg2 &= ~STM32H7_SPI_CFG2_SSM;
1916         } else {
1917                 /*
1918                  * - Transmitter half duplex direction
1919                  * - Automatic communication suspend when RX-Fifo is full
1920                  * - SS input value high
1921                  */
1922                 cr1 |= STM32H7_SPI_CR1_HDDIR | STM32H7_SPI_CR1_MASRX | STM32H7_SPI_CR1_SSI;
1923
1924                 /*
1925                  * - Set the host mode (default Motorola mode)
1926                  * - Consider 1 host/n devices configuration and
1927                  *   SS input value is determined by the SSI bit
1928                  * - keep control of all associated GPIOs
1929                  */
1930                 cfg2 |= STM32H7_SPI_CFG2_MASTER | STM32H7_SPI_CFG2_SSM | STM32H7_SPI_CFG2_AFCNTR;
1931         }
1932
1933         stm32_spi_set_bits(spi, STM32H7_SPI_CR1, cr1);
1934         stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, cfg2);
1935
1936         spin_unlock_irqrestore(&spi->lock, flags);
1937
1938         return 0;
1939 }
1940
1941 static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1942         .regs = &stm32fx_spi_regspec,
1943         .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1944         .disable = stm32fx_spi_disable,
1945         .config = stm32fx_spi_config,
1946         .set_bpw = stm32f4_spi_set_bpw,
1947         .set_mode = stm32fx_spi_set_mode,
1948         .write_tx = stm32f4_spi_write_tx,
1949         .read_rx = stm32f4_spi_read_rx,
1950         .transfer_one_dma_start = stm32fx_spi_transfer_one_dma_start,
1951         .dma_tx_cb = stm32fx_spi_dma_tx_cb,
1952         .dma_rx_cb = stm32_spi_dma_rx_cb,
1953         .transfer_one_irq = stm32fx_spi_transfer_one_irq,
1954         .irq_handler_event = stm32fx_spi_irq_event,
1955         .irq_handler_thread = stm32fx_spi_irq_thread,
1956         .baud_rate_div_min = STM32FX_SPI_BR_DIV_MIN,
1957         .baud_rate_div_max = STM32FX_SPI_BR_DIV_MAX,
1958         .has_fifo = false,
1959         .has_device_mode = false,
1960         .flags = SPI_CONTROLLER_MUST_TX,
1961 };
1962
1963 static const struct stm32_spi_cfg stm32f7_spi_cfg = {
1964         .regs = &stm32fx_spi_regspec,
1965         .get_bpw_mask = stm32f7_spi_get_bpw_mask,
1966         .disable = stm32fx_spi_disable,
1967         .config = stm32fx_spi_config,
1968         .set_bpw = stm32f7_spi_set_bpw,
1969         .set_mode = stm32fx_spi_set_mode,
1970         .write_tx = stm32f7_spi_write_tx,
1971         .read_rx = stm32f7_spi_read_rx,
1972         .transfer_one_dma_start = stm32f7_spi_transfer_one_dma_start,
1973         .dma_tx_cb = stm32fx_spi_dma_tx_cb,
1974         .dma_rx_cb = stm32_spi_dma_rx_cb,
1975         .transfer_one_irq = stm32fx_spi_transfer_one_irq,
1976         .irq_handler_event = stm32fx_spi_irq_event,
1977         .irq_handler_thread = stm32fx_spi_irq_thread,
1978         .baud_rate_div_min = STM32FX_SPI_BR_DIV_MIN,
1979         .baud_rate_div_max = STM32FX_SPI_BR_DIV_MAX,
1980         .has_fifo = false,
1981         .flags = SPI_CONTROLLER_MUST_TX,
1982 };
1983
1984 static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1985         .regs = &stm32h7_spi_regspec,
1986         .get_fifo_size = stm32h7_spi_get_fifo_size,
1987         .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1988         .disable = stm32h7_spi_disable,
1989         .config = stm32h7_spi_config,
1990         .set_bpw = stm32h7_spi_set_bpw,
1991         .set_mode = stm32h7_spi_set_mode,
1992         .set_data_idleness = stm32h7_spi_data_idleness,
1993         .set_number_of_data = stm32h7_spi_number_of_data,
1994         .write_tx = stm32h7_spi_write_txfifo,
1995         .read_rx = stm32h7_spi_read_rxfifo,
1996         .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1997         .dma_rx_cb = stm32_spi_dma_rx_cb,
1998         /*
1999          * dma_tx_cb is not necessary since in case of TX, dma is followed by
2000          * SPI access hence handling is performed within the SPI interrupt
2001          */
2002         .transfer_one_irq = stm32h7_spi_transfer_one_irq,
2003         .irq_handler_thread = stm32h7_spi_irq_thread,
2004         .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
2005         .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
2006         .has_fifo = true,
2007         .has_device_mode = true,
2008 };
2009
2010 /*
2011  * STM32MP2 is compatible with the STM32H7 except:
2012  * - enforce the DMA maxburst value to 1
2013  * - spi8 have limited feature set (TSIZE_MAX = 1024, BPW of 8 OR 16)
2014  */
2015 static const struct stm32_spi_cfg stm32mp25_spi_cfg = {
2016         .regs = &stm32mp25_spi_regspec,
2017         .get_fifo_size = stm32h7_spi_get_fifo_size,
2018         .get_bpw_mask = stm32mp25_spi_get_bpw_mask,
2019         .disable = stm32h7_spi_disable,
2020         .config = stm32h7_spi_config,
2021         .set_bpw = stm32h7_spi_set_bpw,
2022         .set_mode = stm32h7_spi_set_mode,
2023         .set_data_idleness = stm32h7_spi_data_idleness,
2024         .set_number_of_data = stm32h7_spi_number_of_data,
2025         .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
2026         .dma_rx_cb = stm32_spi_dma_rx_cb,
2027         /*
2028          * dma_tx_cb is not necessary since in case of TX, dma is followed by
2029          * SPI access hence handling is performed within the SPI interrupt
2030          */
2031         .transfer_one_irq = stm32h7_spi_transfer_one_irq,
2032         .irq_handler_thread = stm32h7_spi_irq_thread,
2033         .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
2034         .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
2035         .has_fifo = true,
2036         .prevent_dma_burst = true,
2037 };
2038
2039 static const struct of_device_id stm32_spi_of_match[] = {
2040         { .compatible = "st,stm32mp25-spi", .data = (void *)&stm32mp25_spi_cfg },
2041         { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
2042         { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
2043         { .compatible = "st,stm32f7-spi", .data = (void *)&stm32f7_spi_cfg },
2044         {},
2045 };
2046 MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
2047
2048 static int stm32h7_spi_device_abort(struct spi_controller *ctrl)
2049 {
2050         spi_finalize_current_transfer(ctrl);
2051         return 0;
2052 }
2053
2054 static int stm32_spi_probe(struct platform_device *pdev)
2055 {
2056         struct spi_controller *ctrl;
2057         struct stm32_spi *spi;
2058         struct resource *res;
2059         struct reset_control *rst;
2060         struct device_node *np = pdev->dev.of_node;
2061         bool device_mode;
2062         int ret;
2063         const struct stm32_spi_cfg *cfg = of_device_get_match_data(&pdev->dev);
2064
2065         device_mode = of_property_read_bool(np, "spi-slave");
2066         if (!cfg->has_device_mode && device_mode) {
2067                 dev_err(&pdev->dev, "spi-slave not supported\n");
2068                 return -EPERM;
2069         }
2070
2071         if (device_mode)
2072                 ctrl = devm_spi_alloc_target(&pdev->dev, sizeof(struct stm32_spi));
2073         else
2074                 ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(struct stm32_spi));
2075         if (!ctrl) {
2076                 dev_err(&pdev->dev, "spi controller allocation failed\n");
2077                 return -ENOMEM;
2078         }
2079         platform_set_drvdata(pdev, ctrl);
2080
2081         spi = spi_controller_get_devdata(ctrl);
2082         spi->dev = &pdev->dev;
2083         spi->ctrl = ctrl;
2084         spi->device_mode = device_mode;
2085         spin_lock_init(&spi->lock);
2086
2087         spi->cfg = cfg;
2088
2089         spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2090         if (IS_ERR(spi->base))
2091                 return PTR_ERR(spi->base);
2092
2093         spi->phys_addr = (dma_addr_t)res->start;
2094
2095         spi->irq = platform_get_irq(pdev, 0);
2096         if (spi->irq <= 0)
2097                 return spi->irq;
2098
2099         ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
2100                                         spi->cfg->irq_handler_event,
2101                                         spi->cfg->irq_handler_thread,
2102                                         IRQF_ONESHOT, pdev->name, ctrl);
2103         if (ret) {
2104                 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
2105                         ret);
2106                 return ret;
2107         }
2108
2109         spi->clk = devm_clk_get(&pdev->dev, NULL);
2110         if (IS_ERR(spi->clk)) {
2111                 ret = PTR_ERR(spi->clk);
2112                 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
2113                 return ret;
2114         }
2115
2116         ret = clk_prepare_enable(spi->clk);
2117         if (ret) {
2118                 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
2119                 return ret;
2120         }
2121         spi->clk_rate = clk_get_rate(spi->clk);
2122         if (!spi->clk_rate) {
2123                 dev_err(&pdev->dev, "clk rate = 0\n");
2124                 ret = -EINVAL;
2125                 goto err_clk_disable;
2126         }
2127
2128         rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
2129         if (rst) {
2130                 if (IS_ERR(rst)) {
2131                         ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2132                                             "failed to get reset\n");
2133                         goto err_clk_disable;
2134                 }
2135
2136                 reset_control_assert(rst);
2137                 udelay(2);
2138                 reset_control_deassert(rst);
2139         }
2140
2141         if (spi->cfg->has_fifo)
2142                 spi->fifo_size = spi->cfg->get_fifo_size(spi);
2143
2144         spi->feature_set = STM32_SPI_FEATURE_FULL;
2145         if (spi->cfg->regs->fullcfg.reg) {
2146                 spi->feature_set =
2147                         FIELD_GET(STM32MP25_SPI_HWCFGR1_FULLCFG,
2148                                   readl_relaxed(spi->base + spi->cfg->regs->fullcfg.reg));
2149
2150                 dev_dbg(spi->dev, "%s feature set\n",
2151                         spi->feature_set == STM32_SPI_FEATURE_FULL ? "full" : "limited");
2152         }
2153
2154         /* Only for STM32H7 and after */
2155         spi->t_size_max = spi->feature_set == STM32_SPI_FEATURE_FULL ?
2156                                 STM32H7_SPI_TSIZE_MAX :
2157                                 STM32MP25_SPI_TSIZE_MAX_LIMITED;
2158         dev_dbg(spi->dev, "one message max size %d\n", spi->t_size_max);
2159
2160         ret = spi->cfg->config(spi);
2161         if (ret) {
2162                 dev_err(&pdev->dev, "controller configuration failed: %d\n",
2163                         ret);
2164                 goto err_clk_disable;
2165         }
2166
2167         ctrl->dev.of_node = pdev->dev.of_node;
2168         ctrl->auto_runtime_pm = true;
2169         ctrl->bus_num = pdev->id;
2170         ctrl->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
2171                           SPI_3WIRE;
2172         ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
2173         ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
2174         ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
2175         ctrl->use_gpio_descriptors = true;
2176         ctrl->optimize_message = stm32_spi_optimize_message;
2177         ctrl->prepare_message = stm32_spi_prepare_msg;
2178         ctrl->transfer_one = stm32_spi_transfer_one;
2179         ctrl->unprepare_message = stm32_spi_unprepare_msg;
2180         ctrl->flags = spi->cfg->flags;
2181         if (STM32_SPI_DEVICE_MODE(spi))
2182                 ctrl->target_abort = stm32h7_spi_device_abort;
2183
2184         spi->dma_tx = dma_request_chan(spi->dev, "tx");
2185         if (IS_ERR(spi->dma_tx)) {
2186                 ret = PTR_ERR(spi->dma_tx);
2187                 spi->dma_tx = NULL;
2188                 if (ret == -EPROBE_DEFER)
2189                         goto err_clk_disable;
2190
2191                 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
2192         } else {
2193                 ctrl->dma_tx = spi->dma_tx;
2194         }
2195
2196         spi->dma_rx = dma_request_chan(spi->dev, "rx");
2197         if (IS_ERR(spi->dma_rx)) {
2198                 ret = PTR_ERR(spi->dma_rx);
2199                 spi->dma_rx = NULL;
2200                 if (ret == -EPROBE_DEFER)
2201                         goto err_dma_release;
2202
2203                 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
2204         } else {
2205                 ctrl->dma_rx = spi->dma_rx;
2206         }
2207
2208         if (spi->dma_tx || spi->dma_rx)
2209                 ctrl->can_dma = stm32_spi_can_dma;
2210
2211         pm_runtime_set_autosuspend_delay(&pdev->dev,
2212                                          STM32_SPI_AUTOSUSPEND_DELAY);
2213         pm_runtime_use_autosuspend(&pdev->dev);
2214         pm_runtime_set_active(&pdev->dev);
2215         pm_runtime_get_noresume(&pdev->dev);
2216         pm_runtime_enable(&pdev->dev);
2217
2218         ret = spi_register_controller(ctrl);
2219         if (ret) {
2220                 dev_err(&pdev->dev, "spi controller registration failed: %d\n",
2221                         ret);
2222                 goto err_pm_disable;
2223         }
2224
2225         pm_runtime_mark_last_busy(&pdev->dev);
2226         pm_runtime_put_autosuspend(&pdev->dev);
2227
2228         dev_info(&pdev->dev, "driver initialized (%s mode)\n",
2229                  STM32_SPI_HOST_MODE(spi) ? "host" : "device");
2230
2231         return 0;
2232
2233 err_pm_disable:
2234         pm_runtime_disable(&pdev->dev);
2235         pm_runtime_put_noidle(&pdev->dev);
2236         pm_runtime_set_suspended(&pdev->dev);
2237         pm_runtime_dont_use_autosuspend(&pdev->dev);
2238 err_dma_release:
2239         if (spi->dma_tx)
2240                 dma_release_channel(spi->dma_tx);
2241         if (spi->dma_rx)
2242                 dma_release_channel(spi->dma_rx);
2243 err_clk_disable:
2244         clk_disable_unprepare(spi->clk);
2245
2246         return ret;
2247 }
2248
2249 static void stm32_spi_remove(struct platform_device *pdev)
2250 {
2251         struct spi_controller *ctrl = platform_get_drvdata(pdev);
2252         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2253
2254         pm_runtime_get_sync(&pdev->dev);
2255
2256         spi_unregister_controller(ctrl);
2257         spi->cfg->disable(spi);
2258
2259         pm_runtime_disable(&pdev->dev);
2260         pm_runtime_put_noidle(&pdev->dev);
2261         pm_runtime_set_suspended(&pdev->dev);
2262         pm_runtime_dont_use_autosuspend(&pdev->dev);
2263
2264         if (ctrl->dma_tx)
2265                 dma_release_channel(ctrl->dma_tx);
2266         if (ctrl->dma_rx)
2267                 dma_release_channel(ctrl->dma_rx);
2268
2269         clk_disable_unprepare(spi->clk);
2270
2271
2272         pinctrl_pm_select_sleep_state(&pdev->dev);
2273 }
2274
2275 static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
2276 {
2277         struct spi_controller *ctrl = dev_get_drvdata(dev);
2278         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2279
2280         clk_disable_unprepare(spi->clk);
2281
2282         return pinctrl_pm_select_sleep_state(dev);
2283 }
2284
2285 static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
2286 {
2287         struct spi_controller *ctrl = dev_get_drvdata(dev);
2288         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2289         int ret;
2290
2291         ret = pinctrl_pm_select_default_state(dev);
2292         if (ret)
2293                 return ret;
2294
2295         return clk_prepare_enable(spi->clk);
2296 }
2297
2298 static int __maybe_unused stm32_spi_suspend(struct device *dev)
2299 {
2300         struct spi_controller *ctrl = dev_get_drvdata(dev);
2301         int ret;
2302
2303         ret = spi_controller_suspend(ctrl);
2304         if (ret)
2305                 return ret;
2306
2307         return pm_runtime_force_suspend(dev);
2308 }
2309
2310 static int __maybe_unused stm32_spi_resume(struct device *dev)
2311 {
2312         struct spi_controller *ctrl = dev_get_drvdata(dev);
2313         struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2314         int ret;
2315
2316         ret = pm_runtime_force_resume(dev);
2317         if (ret)
2318                 return ret;
2319
2320         ret = spi_controller_resume(ctrl);
2321         if (ret) {
2322                 clk_disable_unprepare(spi->clk);
2323                 return ret;
2324         }
2325
2326         ret = pm_runtime_resume_and_get(dev);
2327         if (ret < 0) {
2328                 dev_err(dev, "Unable to power device:%d\n", ret);
2329                 return ret;
2330         }
2331
2332         spi->cfg->config(spi);
2333
2334         pm_runtime_mark_last_busy(dev);
2335         pm_runtime_put_autosuspend(dev);
2336
2337         return 0;
2338 }
2339
2340 static const struct dev_pm_ops stm32_spi_pm_ops = {
2341         SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2342         SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2343                            stm32_spi_runtime_resume, NULL)
2344 };
2345
2346 static struct platform_driver stm32_spi_driver = {
2347         .probe = stm32_spi_probe,
2348         .remove_new = stm32_spi_remove,
2349         .driver = {
2350                 .name = DRIVER_NAME,
2351                 .pm = &stm32_spi_pm_ops,
2352                 .of_match_table = stm32_spi_of_match,
2353         },
2354 };
2355
2356 module_platform_driver(stm32_spi_driver);
2357
2358 MODULE_ALIAS("platform:" DRIVER_NAME);
2359 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2360 MODULE_AUTHOR("Amelie Delaunay <[email protected]>");
2361 MODULE_LICENSE("GPL v2");