drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  Copyright 2017-2023 Broadcom Inc. All rights reserved.
   4  */
   5 #ifndef MPI30_CNFG_H
   6 #define MPI30_CNFG_H     1
   7 #define MPI3_CONFIG_PAGETYPE_IO_UNIT                    (0x00)
   8 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING              (0x01)
   9 #define MPI3_CONFIG_PAGETYPE_IOC                        (0x02)
  10 #define MPI3_CONFIG_PAGETYPE_DRIVER                     (0x03)
  11 #define MPI3_CONFIG_PAGETYPE_SECURITY                   (0x04)
  12 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE                  (0x11)
  13 #define MPI3_CONFIG_PAGETYPE_DEVICE                     (0x12)
  14 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT                (0x20)
  15 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER               (0x21)
  16 #define MPI3_CONFIG_PAGETYPE_SAS_PHY                    (0x23)
  17 #define MPI3_CONFIG_PAGETYPE_SAS_PORT                   (0x24)
  18 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT               (0x30)
  19 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH                (0x31)
  20 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK                  (0x33)
  21 #define MPI3_CONFIG_PAGEATTR_MASK                       (0xf0)
  22 #define MPI3_CONFIG_PAGEATTR_READ_ONLY                  (0x00)
  23 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE                 (0x10)
  24 #define MPI3_CONFIG_PAGEATTR_PERSISTENT                 (0x20)
  25 #define MPI3_CONFIG_ACTION_PAGE_HEADER                  (0x00)
  26 #define MPI3_CONFIG_ACTION_READ_DEFAULT                 (0x01)
  27 #define MPI3_CONFIG_ACTION_READ_CURRENT                 (0x02)
  28 #define MPI3_CONFIG_ACTION_WRITE_CURRENT                (0x03)
  29 #define MPI3_CONFIG_ACTION_READ_PERSISTENT              (0x04)
  30 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT             (0x05)
  31 #define MPI3_DEVICE_PGAD_FORM_MASK                      (0xf0000000)
  32 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE           (0x00000000)
  33 #define MPI3_DEVICE_PGAD_FORM_HANDLE                    (0x20000000)
  34 #define MPI3_DEVICE_PGAD_HANDLE_MASK                    (0x0000ffff)
  35 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK                  (0xf0000000)
  36 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE       (0x00000000)
  37 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM        (0x10000000)
  38 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE                (0x20000000)
  39 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK                (0x00ff0000)
  40 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT               (16)
  41 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK                (0x0000ffff)
  42 #define MPI3_SAS_PHY_PGAD_FORM_MASK                     (0xf0000000)
  43 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER               (0x00000000)
  44 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK               (0x000000ff)
  45 #define MPI3_SASPORT_PGAD_FORM_MASK                     (0xf0000000)
  46 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT            (0x00000000)
  47 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM                 (0x10000000)
  48 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK              (0x000000ff)
  49 #define MPI3_ENCLOS_PGAD_FORM_MASK                      (0xf0000000)
  50 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE           (0x00000000)
  51 #define MPI3_ENCLOS_PGAD_FORM_HANDLE                    (0x10000000)
  52 #define MPI3_ENCLOS_PGAD_HANDLE_MASK                    (0x0000ffff)
  53 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK                 (0xf0000000)
  54 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE      (0x00000000)
  55 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM      (0x10000000)
  56 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE               (0x20000000)
  57 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK              (0x00ff0000)
  58 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT             (16)
  59 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK               (0x0000ffff)
  60 #define MPI3_PCIE_LINK_PGAD_FORM_MASK                   (0xf0000000)
  61 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK          (0x00000000)
  62 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM               (0x10000000)
  63 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK                (0x000000ff)
  64 #define MPI3_SECURITY_PGAD_FORM_MASK                    (0xf0000000)
  65 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT           (0x00000000)
  66 #define MPI3_SECURITY_PGAD_FORM_SLOT_NUM                (0x10000000)
  67 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK              (0x0000ff00)
  68 #define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT             (8)
  69 #define MPI3_SECURITY_PGAD_SLOT_MASK                    (0x000000ff)
  70 struct mpi3_config_request {
  71         __le16             host_tag;
  72         u8                 ioc_use_only02;
  73         u8                 function;
  74         __le16             ioc_use_only04;
  75         u8                 ioc_use_only06;
  76         u8                 msg_flags;
  77         __le16             change_count;
  78         __le16             reserved0a;
  79         u8                 page_version;
  80         u8                 page_number;
  81         u8                 page_type;
  82         u8                 action;
  83         __le32             page_address;
  84         __le16             page_length;
  85         __le16             reserved16;
  86         __le32             reserved18[2];
  87         union mpi3_sge_union  sgl;
  88 };
  89
  90 struct mpi3_config_page_header {
  91         u8                 page_version;
  92         u8                 reserved01;
  93         u8                 page_number;
  94         u8                 page_attribute;
  95         __le16             page_length;
  96         u8                 page_type;
  97         u8                 reserved07;
  98 };
  99
 100 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK             (0xf0)
 101 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT            (4)
 102 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK            (0x0f)
 103 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT           (0)
 104 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
 105 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
 106 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
 107 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
 108 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
 109 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
 110 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
 111 #define MPI3_SAS_NEG_LINK_RATE_1_5                      (0x08)
 112 #define MPI3_SAS_NEG_LINK_RATE_3_0                      (0x09)
 113 #define MPI3_SAS_NEG_LINK_RATE_6_0                      (0x0a)
 114 #define MPI3_SAS_NEG_LINK_RATE_12_0                     (0x0b)
 115 #define MPI3_SAS_NEG_LINK_RATE_22_5                     (0x0c)
 116 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
 117 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
 118 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
 119 #define MPI3_SAS_APHYINFO_REASON_MASK                   (0x0000000f)
 120 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
 121 #define MPI3_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
 122 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
 123 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
 124 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
 125 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
 126 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
 127 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
 128 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
 129 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC       (0x00000009)
 130 #define MPI3_SAS_PHYINFO_STATUS_MASK                    (0xc0000000)
 131 #define MPI3_SAS_PHYINFO_STATUS_SHIFT                   (30)
 132 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE              (0x00000000)
 133 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST               (0x40000000)
 134 #define MPI3_SAS_PHYINFO_STATUS_VACANT                  (0x80000000)
 135 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
 136 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE     (0x00000000)
 137 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL    (0x08000000)
 138 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER    (0x10000000)
 139 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK  (0x04000000)
 140 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26)
 141 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK         (0x02000000)
 142 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT        (25)
 143 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK          (0x01000000)
 144 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT         (24)
 145 #define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT                (0x00400000)
 146 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN                  (0x00200000)
 147 #define MPI3_SAS_PHYINFO_ZONING_ENABLED                       (0x00100000)
 148 #define MPI3_SAS_PHYINFO_REASON_MASK                    (0x000f0000)
 149 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
 150 #define MPI3_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
 151 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
 152 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
 153 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
 154 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
 155 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
 156 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
 157 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
 158 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC        (0x00090000)
 159 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
 160 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
 161 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
 162 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK      (0x00000f00)
 163 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT     (8)
 164 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK         (0x000000f0)
 165 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT       (0x00000000)
 166 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE  (0x00000010)
 167 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE        (0x00000020)
 168 #define MPI3_SAS_PRATE_MAX_RATE_MASK                    (0xf0)
 169 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
 170 #define MPI3_SAS_PRATE_MAX_RATE_1_5                     (0x80)
 171 #define MPI3_SAS_PRATE_MAX_RATE_3_0                     (0x90)
 172 #define MPI3_SAS_PRATE_MAX_RATE_6_0                     (0xa0)
 173 #define MPI3_SAS_PRATE_MAX_RATE_12_0                    (0xb0)
 174 #define MPI3_SAS_PRATE_MAX_RATE_22_5                    (0xc0)
 175 #define MPI3_SAS_PRATE_MIN_RATE_MASK                    (0x0f)
 176 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
 177 #define MPI3_SAS_PRATE_MIN_RATE_1_5                     (0x08)
 178 #define MPI3_SAS_PRATE_MIN_RATE_3_0                     (0x09)
 179 #define MPI3_SAS_PRATE_MIN_RATE_6_0                     (0x0a)
 180 #define MPI3_SAS_PRATE_MIN_RATE_12_0                    (0x0b)
 181 #define MPI3_SAS_PRATE_MIN_RATE_22_5                    (0x0c)
 182 #define MPI3_SAS_HWRATE_MAX_RATE_MASK                   (0xf0)
 183 #define MPI3_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
 184 #define MPI3_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
 185 #define MPI3_SAS_HWRATE_MAX_RATE_6_0                    (0xa0)
 186 #define MPI3_SAS_HWRATE_MAX_RATE_12_0                   (0xb0)
 187 #define MPI3_SAS_HWRATE_MAX_RATE_22_5                   (0xc0)
 188 #define MPI3_SAS_HWRATE_MIN_RATE_MASK                   (0x0f)
 189 #define MPI3_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
 190 #define MPI3_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
 191 #define MPI3_SAS_HWRATE_MIN_RATE_6_0                    (0x0a)
 192 #define MPI3_SAS_HWRATE_MIN_RATE_12_0                   (0x0b)
 193 #define MPI3_SAS_HWRATE_MIN_RATE_22_5                   (0x0c)
 194 #define MPI3_SLOT_INVALID                               (0xffff)
 195 #define MPI3_SLOT_INDEX_INVALID                         (0xffff)
 196 #define MPI3_LINK_CHANGE_COUNT_INVALID                   (0xffff)
 197 #define MPI3_RATE_CHANGE_COUNT_INVALID                   (0xffff)
 198 #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL              (0x0)
 199 #define MPI3_TEMP_SENSOR_LOCATION_INLET                 (0x1)
 200 #define MPI3_TEMP_SENSOR_LOCATION_OUTLET                (0x2)
 201 #define MPI3_TEMP_SENSOR_LOCATION_DRAM                  (0x3)
 202 #define MPI3_MFGPAGE_VENDORID_BROADCOM                  (0x1000)
 203 #define MPI3_MFGPAGE_DEVID_SAS4116                      (0x00a5)
 204 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI                  (0x00b3)
 205 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME                 (0x00b4)
 206 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI_MGMT             (0x00b5)
 207 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME_MGMT            (0x00b6)
 208 #define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH          (0x00b8)
 209 struct mpi3_man_page0 {
 210         struct mpi3_config_page_header         header;
 211         u8                                 chip_revision[8];
 212         u8                                 chip_name[32];
 213         u8                                 board_name[32];
 214         u8                                 board_assembly[32];
 215         u8                                 board_tracer_number[32];
 216         __le32                             board_power;
 217         __le32                             reserved94;
 218         __le32                             reserved98;
 219         u8                                 oem;
 220         u8                                 profile_identifier;
 221         __le16                             flags;
 222         u8                                 board_mfg_day;
 223         u8                                 board_mfg_month;
 224         __le16                             board_mfg_year;
 225         u8                                 board_rework_day;
 226         u8                                 board_rework_month;
 227         __le16                             board_rework_year;
 228         u8                                 board_revision[8];
 229         u8                                 e_pack_fru[16];
 230         u8                                 product_name[256];
 231 };
 232
 233 #define MPI3_MAN0_PAGEVERSION       (0x00)
 234 #define MPI3_MAN0_FLAGS_SWITCH_PRESENT                       (0x0002)
 235 #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT                     (0x0001)
 236 #define MPI3_MAN1_VPD_SIZE                                   (512)
 237 struct mpi3_man_page1 {
 238         struct mpi3_config_page_header         header;
 239         __le32                             reserved08[2];
 240         u8                                 vpd[MPI3_MAN1_VPD_SIZE];
 241 };
 242
 243 #define MPI3_MAN1_PAGEVERSION                                 (0x00)
 244 struct mpi3_man_page2 {
 245         struct mpi3_config_page_header         header;
 246         u8                                 flags;
 247         u8                                 reserved09[3];
 248         __le32                             reserved0c[3];
 249         u8                                 oem_board_tracer_number[32];
 250 };
 251 #define MPI3_MAN2_PAGEVERSION                                 (0x00)
 252 #define MPI3_MAN2_FLAGS_TRACER_PRESENT                        (0x01)
 253 struct mpi3_man5_phy_entry {
 254         __le64     ioc_wwid;
 255         __le64     device_name;
 256         __le64     sata_wwid;
 257 };
 258
 259 #ifndef MPI3_MAN5_PHY_MAX
 260 #define MPI3_MAN5_PHY_MAX                                   (1)
 261 #endif
 262 struct mpi3_man_page5 {
 263         struct mpi3_config_page_header         header;
 264         u8                                 num_phys;
 265         u8                                 reserved09[3];
 266         __le32                             reserved0c;
 267         struct mpi3_man5_phy_entry             phy[MPI3_MAN5_PHY_MAX];
 268 };
 269
 270 #define MPI3_MAN5_PAGEVERSION                                (0x00)
 271 struct mpi3_man6_gpio_entry {
 272         u8         function_code;
 273         u8         function_flags;
 274         __le16     flags;
 275         u8         param1;
 276         u8         param2;
 277         __le16     reserved06;
 278         __le32     param3;
 279 };
 280
 281 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC                                       (0x00)
 282 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE                                     (0x01)
 283 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT                                 (0x02)
 284 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY                               (0x03)
 285 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE                              (0x04)
 286 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN                             (0x05)
 287 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW                            (0x06)
 288 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT                              (0x07)
 289 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE                             (0x08)
 290 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET                                   (0x0a)
 291 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET                            (0x0b)
 292 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT                                  (0x0c)
 293 #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE                            (0x0d)
 294 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE                                  (0x0e)
 295 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT                                   (0x0f)
 296 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE                                     (0x10)
 297 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE                                       (0x11)
 298 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL                                (0x12)
 299 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP                      (0x13)
 300 #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER                               (0x14)
 301 #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY                         (0x15)
 302 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL                             (0x16)
 303 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT                               (0x17)
 304 #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE                                   (0x18)
 305 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK               (0x01)
 306 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI              (0x00)
 307 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID       (0x01)
 308 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK                        (0xf0)
 309 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC                     (0x00)
 310 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT                  (0x10)
 311 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT    (0x20)
 312 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED                       (0x02)
 313 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK                       (0x01)
 314 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE                       (0x00)
 315 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL                      (0x01)
 316 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP                    (0x00)
 317 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP            (0x01)
 318 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT             (0x00)
 319 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE        (0x01)
 320 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE          (0x02)
 321 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON                            (0x00)
 322 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK                                   (0x0100)
 323 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE                              (0x0100)
 324 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE                              (0x0000)
 325 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK                              (0x00c0)
 326 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM                            (0x0000)
 327 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM                             (0x0040)
 328 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM                             (0x0080)
 329 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM                             (0x00c0)
 330 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK                                (0x0030)
 331 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT                               (4)
 332 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH                                      (0x0008)
 333 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED                                   (0x0004)
 334 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK                                   (0x0003)
 335 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT                                  (0x0000)
 336 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT                      (0x0001)
 337 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT                     (0x0002)
 338 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT                       (0x0003)
 339 #ifndef MPI3_MAN6_GPIO_MAX
 340 #define MPI3_MAN6_GPIO_MAX                                                    (1)
 341 #endif
 342 struct mpi3_man_page6 {
 343         struct mpi3_config_page_header         header;
 344         __le16                             flags;
 345         __le16                             reserved0a;
 346         u8                                 num_gpio;
 347         u8                                 reserved0d[3];
 348         struct mpi3_man6_gpio_entry            gpio[MPI3_MAN6_GPIO_MAX];
 349 };
 350
 351 #define MPI3_MAN6_PAGEVERSION                                                 (0x00)
 352 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED                                (0x0001)
 353 struct mpi3_man7_receptacle_info {
 354         __le32                             name[4];
 355         u8                                 location;
 356         u8                                 connector_type;
 357         u8                                 ped_clk;
 358         u8                                 connector_id;
 359         __le32                             reserved14;
 360 };
 361
 362 #define MPI3_MAN7_LOCATION_UNKNOWN                         (0x00)
 363 #define MPI3_MAN7_LOCATION_INTERNAL                        (0x01)
 364 #define MPI3_MAN7_LOCATION_EXTERNAL                        (0x02)
 365 #define MPI3_MAN7_LOCATION_VIRTUAL                         (0x03)
 366 #define MPI3_MAN7_LOCATION_HOST                            (0x04)
 367 #define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO                   (0x00)
 368 #define MPI3_MAN7_PEDCLK_ROUTING_MASK                      (0x10)
 369 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT                    (0x00)
 370 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER              (0x10)
 371 #define MPI3_MAN7_PEDCLK_ID_MASK                           (0x0f)
 372 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX
 373 #define MPI3_MAN7_RECEPTACLE_INFO_MAX                      (1)
 374 #endif
 375 struct mpi3_man_page7 {
 376         struct mpi3_config_page_header         header;
 377         __le32                             flags;
 378         u8                                 num_receptacles;
 379         u8                                 reserved0d[3];
 380         __le32                             enclosure_name[4];
 381         struct mpi3_man7_receptacle_info       receptacle_info[MPI3_MAN7_RECEPTACLE_INFO_MAX];
 382 };
 383
 384 #define MPI3_MAN7_PAGEVERSION                              (0x00)
 385 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK          (0x01)
 386 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0             (0x00)
 387 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1             (0x01)
 388 struct mpi3_man8_phy_info {
 389         u8                                 receptacle_id;
 390         u8                                 connector_lane;
 391         __le16                             reserved02;
 392         __le16                             slotx1;
 393         __le16                             slotx2;
 394         __le16                             slotx4;
 395         __le16                             reserved0a;
 396         __le32                             reserved0c;
 397 };
 398
 399 #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED    (0xff)
 400 #define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED   (0xff)
 401 #ifndef MPI3_MAN8_PHY_INFO_MAX
 402 #define MPI3_MAN8_PHY_INFO_MAX                      (1)
 403 #endif
 404 struct mpi3_man_page8 {
 405         struct mpi3_config_page_header         header;
 406         __le32                             reserved08;
 407         u8                                 num_phys;
 408         u8                                 reserved0d[3];
 409         struct mpi3_man8_phy_info              phy_info[MPI3_MAN8_PHY_INFO_MAX];
 410 };
 411
 412 #define MPI3_MAN8_PAGEVERSION                   (0x00)
 413 struct mpi3_man9_rsrc_entry {
 414         __le32     maximum;
 415         __le32     decrement;
 416         __le32     minimum;
 417         __le32     actual;
 418 };
 419
 420 enum mpi3_man9_resources {
 421         MPI3_MAN9_RSRC_OUTSTANDING_REQS    = 0,
 422         MPI3_MAN9_RSRC_TARGET_CMDS         = 1,
 423         MPI3_MAN9_RSRC_RESERVED02          = 2,
 424         MPI3_MAN9_RSRC_NVME                = 3,
 425         MPI3_MAN9_RSRC_INITIATORS          = 4,
 426         MPI3_MAN9_RSRC_VDS                 = 5,
 427         MPI3_MAN9_RSRC_ENCLOSURES          = 6,
 428         MPI3_MAN9_RSRC_ENCLOSURE_PHYS      = 7,
 429         MPI3_MAN9_RSRC_EXPANDERS           = 8,
 430         MPI3_MAN9_RSRC_PCIE_SWITCHES       = 9,
 431         MPI3_MAN9_RSRC_RESERVED10          = 10,
 432         MPI3_MAN9_RSRC_HOST_PD_DRIVES      = 11,
 433         MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES  = 12,
 434         MPI3_MAN9_RSRC_RAID_PD_DRIVES      = 13,
 435         MPI3_MAN9_RSRC_DRV_DIAG_BUF        = 14,
 436         MPI3_MAN9_RSRC_NAMESPACE_COUNT     = 15,
 437         MPI3_MAN9_RSRC_NUM_RESOURCES
 438 };
 439
 440 #define MPI3_MAN9_MIN_OUTSTANDING_REQS      (1)
 441 #define MPI3_MAN9_MAX_OUTSTANDING_REQS      (65000)
 442 #define MPI3_MAN9_MIN_TARGET_CMDS           (0)
 443 #define MPI3_MAN9_MAX_TARGET_CMDS           (65535)
 444 #define MPI3_MAN9_MIN_NVME_TARGETS          (0)
 445 #define MPI3_MAN9_MIN_INITIATORS            (0)
 446 #define MPI3_MAN9_MIN_VDS                   (0)
 447 #define MPI3_MAN9_MIN_ENCLOSURES            (1)
 448 #define MPI3_MAN9_MAX_ENCLOSURES            (65535)
 449 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS        (0)
 450 #define MPI3_MAN9_MIN_EXPANDERS             (0)
 451 #define MPI3_MAN9_MAX_EXPANDERS             (65535)
 452 #define MPI3_MAN9_MIN_PCIE_SWITCHES         (0)
 453 #define MPI3_MAN9_MIN_HOST_PD_DRIVES        (0)
 454 #define MPI3_MAN9_ADV_HOST_PD_DRIVES        (0)
 455 #define MPI3_MAN9_RAID_PD_DRIVES            (0)
 456 #define MPI3_MAN9_DRIVER_DIAG_BUFFER        (0)
 457 #define MPI3_MAN9_MIN_NAMESPACE_COUNT       (1)
 458 #define MPI3_MAN9_MIN_EXPANDERS             (0)
 459 #define MPI3_MAN9_MAX_EXPANDERS             (65535)
 460 struct mpi3_man_page9 {
 461         struct mpi3_config_page_header         header;
 462         u8                                 num_resources;
 463         u8                                 reserved09;
 464         __le16                             reserved0a;
 465         __le32                             reserved0c;
 466         __le32                             reserved10;
 467         __le32                             reserved14;
 468         __le32                             reserved18;
 469         __le32                             reserved1c;
 470         struct mpi3_man9_rsrc_entry            resource[MPI3_MAN9_RSRC_NUM_RESOURCES];
 471 };
 472
 473 #define MPI3_MAN9_PAGEVERSION                   (0x00)
 474 struct mpi3_man10_istwi_ctrlr_entry {
 475         __le16     target_address;
 476         __le16     flags;
 477         u8         scl_low_override;
 478         u8         scl_high_override;
 479         __le16     reserved06;
 480 };
 481
 482 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK         (0x000c)
 483 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K         (0x0000)
 484 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K         (0x0004)
 485 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED          (0x0002)
 486 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED         (0x0001)
 487 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX
 488 #define MPI3_MAN10_ISTWI_CTRLR_MAX          (1)
 489 #endif
 490 struct mpi3_man_page10 {
 491         struct mpi3_config_page_header         header;
 492         __le32                             reserved08;
 493         u8                                 num_istwi_ctrl;
 494         u8                                 reserved0d[3];
 495         struct mpi3_man10_istwi_ctrlr_entry    istwi_controller[MPI3_MAN10_ISTWI_CTRLR_MAX];
 496 };
 497
 498 #define MPI3_MAN10_PAGEVERSION                  (0x00)
 499 struct mpi3_man11_mux_device_format {
 500         u8         max_channel;
 501         u8         reserved01[3];
 502         __le32     reserved04;
 503 };
 504
 505 struct mpi3_man11_temp_sensor_device_format {
 506         u8         type;
 507         u8         reserved01[3];
 508         u8         temp_channel[4];
 509 };
 510
 511 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654                (0x00)
 512 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442                (0x01)
 513 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476                (0x02)
 514 #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B                  (0x03)
 515 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK       (0xe0)
 516 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT      (5)
 517 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED             (0x01)
 518 struct mpi3_man11_seeprom_device_format {
 519         u8         size;
 520         u8         page_write_size;
 521         __le16     reserved02;
 522         __le32     reserved04;
 523 };
 524
 525 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS              (0x01)
 526 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS              (0x02)
 527 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS              (0x03)
 528 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS              (0x04)
 529 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS             (0x05)
 530 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS             (0x06)
 531 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS             (0x07)
 532 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS            (0x08)
 533 struct mpi3_man11_ddr_spd_device_format {
 534         u8         channel;
 535         u8         reserved01[3];
 536         __le32     reserved04;
 537 };
 538
 539 struct mpi3_man11_cable_mgmt_device_format {
 540         u8         type;
 541         u8         receptacle_id;
 542         __le16     reserved02;
 543         __le32     reserved04;
 544 };
 545
 546 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636           (0x00)
 547 struct mpi3_man11_bkplane_spec_ubm_format {
 548         __le16     flags;
 549         __le16     reserved02;
 550 };
 551
 552 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED  (0x0200)
 553 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING                 (0x0100)
 554 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK                  (0x00f0)
 555 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT                 (4)
 556 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK            (0x000f)
 557 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT           (0)
 558 struct mpi3_man11_bkplane_spec_non_ubm_format {
 559         __le16     flags;
 560         u8         reserved02;
 561         u8         type;
 562 };
 563
 564 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK                    (0xf000)
 565 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT                   (12)
 566 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED  (0x0200)
 567 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK                (0x00c0)
 568 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4                   (0x0000)
 569 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2                   (0x0040)
 570 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1                   (0x0080)
 571 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK          (0x0030)
 572 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO          (0x0000)
 573 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG           (0x0010)
 574 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK            (0x000f)
 575 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT           (0)
 576 #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP                            (0x00)
 577 union mpi3_man11_bkplane_spec_format {
 578         struct mpi3_man11_bkplane_spec_ubm_format         ubm;
 579         struct mpi3_man11_bkplane_spec_non_ubm_format     non_ubm;
 580 };
 581
 582 struct mpi3_man11_bkplane_mgmt_device_format {
 583         u8                                        type;
 584         u8                                        receptacle_id;
 585         u8                                        reset_info;
 586         u8                                        reserved03;
 587         union mpi3_man11_bkplane_spec_format         backplane_mgmt_specific;
 588 };
 589
 590 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM            (0x00)
 591 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM        (0x01)
 592 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK       (0xf0)
 593 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT      (4)
 594 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK        (0x0f)
 595 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT       (0)
 596 struct mpi3_man11_gas_gauge_device_format {
 597         u8         type;
 598         u8         reserved01[3];
 599         __le32     reserved04;
 600 };
 601
 602 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD          (0x00)
 603 struct mpi3_man11_mgmt_ctrlr_device_format {
 604         __le32     reserved00;
 605         __le32     reserved04;
 606 };
 607 struct mpi3_man11_board_fan_device_format {
 608         u8         flags;
 609         u8         reserved01;
 610         u8         min_fan_speed;
 611         u8         max_fan_speed;
 612         __le32     reserved04;
 613 };
 614 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK        (0x07)
 615 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821     (0x00)
 616 union mpi3_man11_device_specific_format {
 617         struct mpi3_man11_mux_device_format            mux;
 618         struct mpi3_man11_temp_sensor_device_format    temp_sensor;
 619         struct mpi3_man11_seeprom_device_format        seeprom;
 620         struct mpi3_man11_ddr_spd_device_format        ddr_spd;
 621         struct mpi3_man11_cable_mgmt_device_format     cable_mgmt;
 622         struct mpi3_man11_bkplane_mgmt_device_format   bkplane_mgmt;
 623         struct mpi3_man11_gas_gauge_device_format      gas_gauge;
 624         struct mpi3_man11_mgmt_ctrlr_device_format     mgmt_controller;
 625         struct mpi3_man11_board_fan_device_format      board_fan;
 626         __le32                                     words[2];
 627 };
 628 struct mpi3_man11_istwi_device_format {
 629         u8                                     device_type;
 630         u8                                     controller;
 631         u8                                     reserved02;
 632         u8                                     flags;
 633         __le16                                 device_address;
 634         u8                                     mux_channel;
 635         u8                                     mux_index;
 636         union mpi3_man11_device_specific_format   device_specific;
 637 };
 638
 639 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX                  (0x00)
 640 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR          (0x01)
 641 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM              (0x02)
 642 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD              (0x03)
 643 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT           (0x04)
 644 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT       (0x05)
 645 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE            (0x06)
 646 #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER      (0x07)
 647 #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN            (0x08)
 648 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT            (0x01)
 649 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX
 650 #define MPI3_MAN11_ISTWI_DEVICE_MAX             (1)
 651 #endif
 652 struct mpi3_man_page11 {
 653         struct mpi3_config_page_header         header;
 654         __le32                             reserved08;
 655         u8                                 num_istwi_dev;
 656         u8                                 reserved0d[3];
 657         struct mpi3_man11_istwi_device_format  istwi_device[MPI3_MAN11_ISTWI_DEVICE_MAX];
 658 };
 659
 660 #define MPI3_MAN11_PAGEVERSION                  (0x00)
 661 #ifndef MPI3_MAN12_NUM_SGPIO_MAX
 662 #define MPI3_MAN12_NUM_SGPIO_MAX                                     (1)
 663 #endif
 664 struct mpi3_man12_sgpio_info {
 665         u8                                 slot_count;
 666         u8                                 reserved01[3];
 667         __le32                             reserved04;
 668         u8                                 phy_order[32];
 669 };
 670
 671 struct mpi3_man_page12 {
 672         struct mpi3_config_page_header         header;
 673         __le32                             flags;
 674         __le32                             s_clock_freq;
 675         __le32                             activity_modulation;
 676         u8                                 num_sgpio;
 677         u8                                 reserved15[3];
 678         __le32                             reserved18;
 679         __le32                             reserved1c;
 680         __le32                             pattern[8];
 681         struct mpi3_man12_sgpio_info           sgpio_info[MPI3_MAN12_NUM_SGPIO_MAX];
 682 };
 683
 684 #define MPI3_MAN12_PAGEVERSION                                       (0x00)
 685 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED                      (0x0400)
 686 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED                     (0x0200)
 687 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED                           (0x0100)
 688 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED                      (0x0004)
 689 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK                      (0x0002)
 690 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL                 (0x0000)
 691 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN                (0x0002)
 692 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK                          (0x0001)
 693 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL                     (0x0000)
 694 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN                    (0x0001)
 695 #define MPI3_MAN12_SIO_CLK_FREQ_MIN                                  (32)
 696 #define MPI3_MAN12_SIO_CLK_FREQ_MAX                                  (100000)
 697 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK                (0x0000f000)
 698 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT               (12)
 699 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK                   (0x00000f00)
 700 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT                  (8)
 701 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK              (0x000000f0)
 702 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT             (4)
 703 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK               (0x0000000f)
 704 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT              (0)
 705 #define MPI3_MAN12_PATTERN_RATE_MASK                                 (0xe0000000)
 706 #define MPI3_MAN12_PATTERN_RATE_2_HZ                                 (0x00000000)
 707 #define MPI3_MAN12_PATTERN_RATE_4_HZ                                 (0x20000000)
 708 #define MPI3_MAN12_PATTERN_RATE_8_HZ                                 (0x40000000)
 709 #define MPI3_MAN12_PATTERN_RATE_16_HZ                                (0x60000000)
 710 #define MPI3_MAN12_PATTERN_RATE_10_HZ                                (0x80000000)
 711 #define MPI3_MAN12_PATTERN_RATE_20_HZ                                (0xa0000000)
 712 #define MPI3_MAN12_PATTERN_RATE_40_HZ                                (0xc0000000)
 713 #define MPI3_MAN12_PATTERN_LENGTH_MASK                               (0x1f000000)
 714 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT                              (24)
 715 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK                          (0x00ffffff)
 716 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT                         (0)
 717 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX
 718 #define MPI3_MAN13_NUM_TRANSLATION_MAX                               (1)
 719 #endif
 720 struct mpi3_man13_translation_info {
 721         __le32                             slot_status;
 722         __le32                             mask;
 723         u8                                 activity;
 724         u8                                 locate;
 725         u8                                 error;
 726         u8                                 reserved0b;
 727 };
 728
 729 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT                     (0x20000000)
 730 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF                (0x10000000)
 731 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY           (0x00800000)
 732 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE             (0x00400000)
 733 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING            (0x00100000)
 734 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT                    (0x00080000)
 735 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL                   (0x00040000)
 736 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY                  (0x00020000)
 737 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK                        (0x00008000)
 738 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE           (0x00004000)
 739 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE                 (0x00002000)
 740 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK         (0x00001000)
 741 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY         (0x00000800)
 742 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY           (0x00000400)
 743 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP             (0x00000200)
 744 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT       (0x00000100)
 745 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE         (0x00000040)
 746 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF                          (0x00)
 747 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON                           (0x01)
 748 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0                          (0x02)
 749 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1                          (0x03)
 750 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2                          (0x04)
 751 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3                          (0x05)
 752 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4                          (0x06)
 753 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5                          (0x07)
 754 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6                          (0x08)
 755 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7                          (0x09)
 756 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY                           (0x0a)
 757 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL                     (0x0b)
 758 struct mpi3_man_page13 {
 759         struct mpi3_config_page_header         header;
 760         u8                                 num_trans;
 761         u8                                 reserved09[3];
 762         __le32                             reserved0c;
 763         struct mpi3_man13_translation_info     translation[MPI3_MAN13_NUM_TRANSLATION_MAX];
 764 };
 765
 766 #define MPI3_MAN13_PAGEVERSION                                       (0x00)
 767 struct mpi3_man_page14 {
 768         struct mpi3_config_page_header         header;
 769         __le32                             reserved08;
 770         u8                                 num_slot_groups;
 771         u8                                 num_slots;
 772         __le16                             max_cert_chain_length;
 773         __le32                             sealed_slots;
 774         __le32                             populated_slots;
 775         __le32                             mgmt_pt_updatable_slots;
 776 };
 777 #define MPI3_MAN14_PAGEVERSION                                       (0x00)
 778 #define MPI3_MAN14_NUMSLOTS_MAX                                      (32)
 779 #ifndef MPI3_MAN15_VERSION_RECORD_MAX
 780 #define MPI3_MAN15_VERSION_RECORD_MAX      1
 781 #endif
 782 struct mpi3_man15_version_record {
 783         __le16                             spdm_version;
 784         __le16                             reserved02;
 785 };
 786
 787 struct mpi3_man_page15 {
 788         struct mpi3_config_page_header         header;
 789         u8                                 num_version_records;
 790         u8                                 reserved09[3];
 791         __le32                             reserved0c;
 792         struct mpi3_man15_version_record       version_record[MPI3_MAN15_VERSION_RECORD_MAX];
 793 };
 794
 795 #define MPI3_MAN15_PAGEVERSION                                       (0x00)
 796 #ifndef MPI3_MAN16_CERT_ALGO_MAX
 797 #define MPI3_MAN16_CERT_ALGO_MAX      1
 798 #endif
 799 struct mpi3_man16_certificate_algorithm {
 800         u8                                      slot_group;
 801         u8                                      reserved01[3];
 802         __le32                                  base_asym_algo;
 803         __le32                                  base_hash_algo;
 804         __le32                                  reserved0c[3];
 805 };
 806
 807 struct mpi3_man_page16 {
 808         struct mpi3_config_page_header              header;
 809         __le32                                  reserved08;
 810         u8                                      num_cert_algos;
 811         u8                                      reserved0d[3];
 812         struct mpi3_man16_certificate_algorithm     certificate_algorithm[MPI3_MAN16_CERT_ALGO_MAX];
 813 };
 814
 815 #define MPI3_MAN16_PAGEVERSION                                       (0x00)
 816 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX
 817 #define MPI3_MAN17_HASH_ALGORITHM_MAX      1
 818 #endif
 819 struct mpi3_man17_hash_algorithm {
 820         u8                                 meas_specification;
 821         u8                                 reserved01[3];
 822         __le32                             measurement_hash_algo;
 823         __le32                             reserved08[2];
 824 };
 825
 826 struct mpi3_man_page17 {
 827         struct mpi3_config_page_header         header;
 828         __le32                             reserved08;
 829         u8                                 num_hash_algos;
 830         u8                                 reserved0d[3];
 831         struct mpi3_man17_hash_algorithm       hash_algorithm[MPI3_MAN17_HASH_ALGORITHM_MAX];
 832 };
 833
 834 #define MPI3_MAN17_PAGEVERSION                                       (0x00)
 835 struct mpi3_man_page20 {
 836         struct mpi3_config_page_header         header;
 837         __le32                             reserved08;
 838         __le32                             nonpremium_features;
 839         u8                                 allowed_personalities;
 840         u8                                 reserved11[3];
 841 };
 842
 843 #define MPI3_MAN20_PAGEVERSION                                       (0x00)
 844 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK                           (0x02)
 845 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED                        (0x02)
 846 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED                    (0x00)
 847 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK                           (0x01)
 848 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED                        (0x01)
 849 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED                    (0x00)
 850 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK               (0x01)
 851 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED            (0x00)
 852 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED           (0x01)
 853 struct mpi3_man_page21 {
 854         struct mpi3_config_page_header         header;
 855         __le32                             reserved08;
 856         __le32                             flags;
 857 };
 858
 859 #define MPI3_MAN21_PAGEVERSION                                       (0x00)
 860 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK                     (0x00000060)
 861 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK                    (0x00000000)
 862 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW                    (0x00000020)
 863 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN                     (0x00000040)
 864 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK              (0x00000008)
 865 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW             (0x00000000)
 866 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT           (0x00000008)
 867 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK                          (0x00000001)
 868 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT                       (0x00000000)
 869 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC                  (0x00000001)
 870 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX
 871 #define MPI3_MAN_PROD_SPECIFIC_MAX                      (1)
 872 #endif
 873 struct mpi3_man_page_product_specific {
 874         struct mpi3_config_page_header         header;
 875         __le32                             product_specific_info[MPI3_MAN_PROD_SPECIFIC_MAX];
 876 };
 877
 878 struct mpi3_io_unit_page0 {
 879         struct mpi3_config_page_header         header;
 880         __le64                             unique_value;
 881         __le32                             nvdata_version_default;
 882         __le32                             nvdata_version_persistent;
 883 };
 884
 885 #define MPI3_IOUNIT0_PAGEVERSION                (0x00)
 886 struct mpi3_io_unit_page1 {
 887         struct mpi3_config_page_header         header;
 888         __le32                             flags;
 889         u8                                 dmd_io_delay;
 890         u8                                 dmd_report_pcie;
 891         u8                                 dmd_report_sata;
 892         u8                                 dmd_report_sas;
 893 };
 894
 895 #define MPI3_IOUNIT1_PAGEVERSION                (0x00)
 896 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK                   (0x00000030)
 897 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE                 (0x00000000)
 898 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE                (0x00000010)
 899 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY              (0x00000020)
 900 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK                (0x00000008)
 901 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER                       (0x00000004)
 902 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK                   (0x00000003)
 903 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE                 (0x00000000)
 904 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE                (0x00000001)
 905 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED              (0x00000002)
 906 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK                    (0x7f)
 907 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC                        (0x80)
 908 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX
 909 #define MPI3_IO_UNIT2_GPIO_VAL_MAX      (1)
 910 #endif
 911 struct mpi3_io_unit_page2 {
 912         struct mpi3_config_page_header         header;
 913         u8                                 gpio_count;
 914         u8                                 reserved09[3];
 915         __le16                             gpio_val[MPI3_IO_UNIT2_GPIO_VAL_MAX];
 916 };
 917
 918 #define MPI3_IOUNIT2_PAGEVERSION                (0x00)
 919 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK         (0xfffc)
 920 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT        (2)
 921 #define MPI3_IOUNIT2_GPIO_SETTING_MASK          (0x0001)
 922 #define MPI3_IOUNIT2_GPIO_SETTING_OFF           (0x0000)
 923 #define MPI3_IOUNIT2_GPIO_SETTING_ON            (0x0001)
 924 struct mpi3_io_unit3_sensor {
 925         __le16             flags;
 926         u8                 threshold_margin;
 927         u8                 reserved03;
 928         __le16             threshold[3];
 929         __le16             reserved0a;
 930         __le32             reserved0c;
 931         __le32             reserved10;
 932         __le32             reserved14;
 933 };
 934
 935 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED           (0x0010)
 936 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED          (0x0008)
 937 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED        (0x0004)
 938 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED       (0x0002)
 939 #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED         (0x0001)
 940 #ifndef MPI3_IO_UNIT3_SENSOR_MAX
 941 #define MPI3_IO_UNIT3_SENSOR_MAX                                (1)
 942 #endif
 943 struct mpi3_io_unit_page3 {
 944         struct mpi3_config_page_header         header;
 945         __le32                             reserved08;
 946         u8                                 num_sensors;
 947         u8                                 nominal_poll_interval;
 948         u8                                 warning_poll_interval;
 949         u8                                 reserved0f;
 950         struct mpi3_io_unit3_sensor            sensor[MPI3_IO_UNIT3_SENSOR_MAX];
 951 };
 952
 953 #define MPI3_IOUNIT3_PAGEVERSION                (0x00)
 954 struct mpi3_io_unit4_sensor {
 955         __le16             current_temperature;
 956         __le16             reserved02;
 957         u8                 flags;
 958         u8                 reserved05[3];
 959         __le16             istwi_index;
 960         u8                 channel;
 961         u8                 reserved0b;
 962         __le32             reserved0c;
 963 };
 964
 965 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK          (0xe0)
 966 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT         (5)
 967 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID        (0x01)
 968 #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL    (0xffff)
 969 #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED        (0xff)
 970 #ifndef MPI3_IO_UNIT4_SENSOR_MAX
 971 #define MPI3_IO_UNIT4_SENSOR_MAX                                (1)
 972 #endif
 973 struct mpi3_io_unit_page4 {
 974         struct mpi3_config_page_header         header;
 975         __le32                             reserved08;
 976         u8                                 num_sensors;
 977         u8                                 reserved0d[3];
 978         struct mpi3_io_unit4_sensor            sensor[MPI3_IO_UNIT4_SENSOR_MAX];
 979 };
 980
 981 #define MPI3_IOUNIT4_PAGEVERSION                (0x00)
 982 struct mpi3_io_unit5_spinup_group {
 983         u8                 max_target_spinup;
 984         u8                 spinup_delay;
 985         u8                 spinup_flags;
 986         u8                 reserved03;
 987 };
 988
 989 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE       (0x01)
 990 #ifndef MPI3_IO_UNIT5_PHY_MAX
 991 #define MPI3_IO_UNIT5_PHY_MAX       (4)
 992 #endif
 993 struct mpi3_io_unit_page5 {
 994         struct mpi3_config_page_header         header;
 995         struct mpi3_io_unit5_spinup_group      spinup_group_parameters[4];
 996         __le32                             reserved18;
 997         __le32                             reserved1c;
 998         __le16                             device_shutdown;
 999         __le16                             reserved22;
1000         u8                                 pcie_device_wait_time;
1001         u8                                 sata_device_wait_time;
1002         u8                                 spinup_encl_drive_count;
1003         u8                                 spinup_encl_delay;
1004         u8                                 num_phys;
1005         u8                                 pe_initial_spinup_delay;
1006         u8                                 topology_stable_time;
1007         u8                                 flags;
1008         u8                                 phy[MPI3_IO_UNIT5_PHY_MAX];
1009 };
1010
1011 #define MPI3_IOUNIT5_PAGEVERSION                           (0x00)
1012 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION             (0x00)
1013 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED       (0x01)
1014 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED     (0x02)
1015 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED       (0x02)
1016 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER   (0x03)
1017 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH     (0x03)
1018 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK         (0x0300)
1019 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT        (8)
1020 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK          (0x00c0)
1021 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT         (6)
1022 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK         (0x0030)
1023 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT        (4)
1024 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK         (0x000c)
1025 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT        (2)
1026 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK          (0x0003)
1027 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT         (0)
1028 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK                   (0x0c)
1029 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED          (0x00)
1030 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED          (0x04)
1031 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED         (0x08)
1032 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED                (0x0c)
1033 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP            (0x02)
1034 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE                (0x01)
1035 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK                 (0x03)
1036 struct mpi3_io_unit_page6 {
1037         struct mpi3_config_page_header         header;
1038         __le32                             board_power_requirement;
1039         __le32                             pci_slot_power_allocation;
1040         u8                                 flags;
1041         u8                                 reserved11[3];
1042 };
1043
1044 #define MPI3_IOUNIT6_PAGEVERSION                (0x00)
1045 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC    (0x01)
1046 #ifndef MPI3_IOUNIT8_DIGEST_MAX
1047 #define MPI3_IOUNIT8_DIGEST_MAX                   (1)
1048 #endif
1049 union mpi3_iounit8_digest {
1050         __le32                             dword[16];
1051         __le16                             word[32];
1052         u8                                 byte[64];
1053 };
1054
1055 struct mpi3_io_unit_page8 {
1056         struct mpi3_config_page_header         header;
1057         u8                                 sb_mode;
1058         u8                                 sb_state;
1059         __le16                             reserved0a;
1060         u8                                 num_slots;
1061         u8                                 slots_available;
1062         u8                                 current_key_encryption_algo;
1063         u8                                 key_digest_hash_algo;
1064         union mpi3_version_union              current_svn;
1065         __le32                             reserved14;
1066         __le32                             current_key[128];
1067         union mpi3_iounit8_digest             digest[MPI3_IOUNIT8_DIGEST_MAX];
1068 };
1069
1070 #define MPI3_IOUNIT8_PAGEVERSION                  (0x00)
1071 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG          (0x04)
1072 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE           (0x02)
1073 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE         (0x01)
1074 #define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING   (0x04)
1075 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING   (0x02)
1076 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED  (0x01)
1077 struct mpi3_io_unit_page9 {
1078         struct mpi3_config_page_header         header;
1079         __le32                             flags;
1080         __le16                             first_device;
1081         __le16                             reserved0e;
1082 };
1083
1084 #define MPI3_IOUNIT9_PAGEVERSION                                  (0x00)
1085 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK               (0x00000006)
1086 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT              (1)
1087 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE               (0x00000000)
1088 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE         (0x00000002)
1089 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE     (0x00000004)
1090 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED                        (0x00000001)
1091 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN                          (0xffff)
1092 struct mpi3_io_unit_page10 {
1093         struct mpi3_config_page_header         header;
1094         u8                                 flags;
1095         u8                                 reserved09[3];
1096         __le32                             silicon_id;
1097         u8                                 fw_version_minor;
1098         u8                                 fw_version_major;
1099         u8                                 hw_version_minor;
1100         u8                                 hw_version_major;
1101         u8                                 part_number[16];
1102 };
1103 #define MPI3_IOUNIT10_PAGEVERSION                  (0x00)
1104 #define MPI3_IOUNIT10_FLAGS_VALID                  (0x01)
1105 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK          (0x02)
1106 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION  (0x00)
1107 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02)
1108 #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED          (0x80)
1109 #ifndef MPI3_IOUNIT11_PROFILE_MAX
1110 #define MPI3_IOUNIT11_PROFILE_MAX                   (1)
1111 #endif
1112 struct mpi3_iounit11_profile {
1113         u8                                 profile_identifier;
1114         u8                                 reserved01[3];
1115         __le16                             max_vds;
1116         __le16                             max_host_pds;
1117         __le16                             max_adv_host_pds;
1118         __le16                             max_raid_pds;
1119         __le16                             max_nvme;
1120         __le16                             max_outstanding_requests;
1121         __le16                             subsystem_id;
1122         __le16                             reserved12;
1123         __le32                             reserved14[2];
1124 };
1125 struct mpi3_io_unit_page11 {
1126         struct mpi3_config_page_header         header;
1127         __le32                             reserved08;
1128         u8                                 num_profiles;
1129         u8                                 current_profile_identifier;
1130         __le16                             reserved0e;
1131         struct mpi3_iounit11_profile           profile[MPI3_IOUNIT11_PROFILE_MAX];
1132 };
1133 #define MPI3_IOUNIT11_PAGEVERSION                  (0x00)
1134 #ifndef MPI3_IOUNIT12_BUCKET_MAX
1135 #define MPI3_IOUNIT12_BUCKET_MAX                   (1)
1136 #endif
1137 struct mpi3_iounit12_bucket {
1138         u8                                 coalescing_depth;
1139         u8                                 coalescing_timeout;
1140         __le16                             io_count_low_boundary;
1141         __le32                             reserved04;
1142 };
1143 struct mpi3_io_unit_page12 {
1144         struct mpi3_config_page_header         header;
1145         __le32                             flags;
1146         __le32                             reserved0c[4];
1147         u8                                 num_buckets;
1148         u8                                 reserved1d[3];
1149         struct mpi3_iounit12_bucket            bucket[MPI3_IOUNIT12_BUCKET_MAX];
1150 };
1151 #define MPI3_IOUNIT12_PAGEVERSION                  (0x00)
1152 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK         (0x00000300)
1153 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT        (8)
1154 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_8            (0x00000000)
1155 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_16           (0x00000100)
1156 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32           (0x00000200)
1157 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64           (0x00000300)
1158 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK        (0x00000003)
1159 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED    (0x00000000)
1160 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US       (0x00000001)
1161 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS         (0x00000002)
1162 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS         (0x00000003)
1163 #ifndef MPI3_IOUNIT13_FUNC_MAX
1164 #define MPI3_IOUNIT13_FUNC_MAX                                     (1)
1165 #endif
1166 struct mpi3_iounit13_allowed_function {
1167         __le16                             sub_function;
1168         u8                                 function_code;
1169         u8                                 function_flags;
1170 };
1171 #define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED                 (0x04)
1172 #define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED                   (0x02)
1173 #define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED     (0x01)
1174 struct mpi3_io_unit_page13 {
1175         struct mpi3_config_page_header         header;
1176         __le16                             flags;
1177         __le16                             reserved0a;
1178         u8                                 num_allowed_functions;
1179         u8                                 reserved0d[3];
1180         struct mpi3_iounit13_allowed_function  allowed_function[MPI3_IOUNIT13_FUNC_MAX];
1181 };
1182 #define MPI3_IOUNIT13_PAGEVERSION                                  (0x00)
1183 #define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED                          (0x0002)
1184 #define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED                            (0x0001)
1185 #ifndef MPI3_IOUNIT14_MD_MAX
1186 #define MPI3_IOUNIT14_MD_MAX                                       (1)
1187 #endif
1188 struct mpi3_iounit14_pagemetadata {
1189         u8                                 page_type;
1190         u8                                 page_number;
1191         u8                                 reserved02;
1192         u8                                 page_flags;
1193 };
1194 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED      (0x02)
1195 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED     (0x01)
1196 struct mpi3_io_unit_page14 {
1197         struct mpi3_config_page_header         header;
1198         u8                                 flags;
1199         u8                                 reserved09[3];
1200         u8                                 num_pages;
1201         u8                                 reserved0d[3];
1202         struct mpi3_iounit14_pagemetadata      page_metadata[MPI3_IOUNIT14_MD_MAX];
1203 };
1204 #define MPI3_IOUNIT14_PAGEVERSION                                  (0x00)
1205 #define MPI3_IOUNIT14_FLAGS_READONLY                               (0x01)
1206 #ifndef MPI3_IOUNIT15_PBD_MAX
1207 #define MPI3_IOUNIT15_PBD_MAX                                       (1)
1208 #endif
1209 struct mpi3_io_unit_page15 {
1210         struct mpi3_config_page_header         header;
1211         u8                                 flags;
1212         u8                                 reserved09[3];
1213         __le32                             reserved0c;
1214         u8                                 power_budgeting_capability;
1215         u8                                 reserved11[3];
1216         u8                                 num_power_budget_data;
1217         u8                                 reserved15[3];
1218         __le32                             power_budget_data[MPI3_IOUNIT15_PBD_MAX];
1219 };
1220 #define MPI3_IOUNIT15_PAGEVERSION                                   (0x00)
1221 #define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED                    (0x04)
1222 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK                         (0x03)
1223 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED                (0x00)
1224 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO     (0x01)
1225 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO        (0x02)
1226 #define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED   (0x00)
1227 struct mpi3_ioc_page0 {
1228         struct mpi3_config_page_header         header;
1229         __le32                             reserved08;
1230         __le16                             vendor_id;
1231         __le16                             device_id;
1232         u8                                 revision_id;
1233         u8                                 reserved11[3];
1234         __le32                             class_code;
1235         __le16                             subsystem_vendor_id;
1236         __le16                             subsystem_id;
1237 };
1238
1239 #define MPI3_IOC0_PAGEVERSION               (0x00)
1240 struct mpi3_ioc_page1 {
1241         struct mpi3_config_page_header         header;
1242         __le32                             coalescing_timeout;
1243         u8                                 coalescing_depth;
1244         u8                                 obsolete;
1245         __le16                             reserved0e;
1246 };
1247 #define MPI3_IOC1_PAGEVERSION               (0x00)
1248 #ifndef MPI3_IOC2_EVENTMASK_WORDS
1249 #define MPI3_IOC2_EVENTMASK_WORDS           (4)
1250 #endif
1251 struct mpi3_ioc_page2 {
1252         struct mpi3_config_page_header         header;
1253         __le32                             reserved08;
1254         __le16                             sas_broadcast_primitive_masks;
1255         __le16                             sas_notify_primitive_masks;
1256         __le32                             event_masks[MPI3_IOC2_EVENTMASK_WORDS];
1257 };
1258
1259 #define MPI3_IOC2_PAGEVERSION               (0x00)
1260 #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED               (0x0010)
1261 #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED                 (0x0008)
1262 #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED                 (0x0004)
1263 #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED              (0x0002)
1264 #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED                 (0x0001)
1265 struct mpi3_allowed_cmd_scsi {
1266         __le16                             service_action;
1267         u8                                 operation_code;
1268         u8                                 command_flags;
1269 };
1270
1271 struct mpi3_allowed_cmd_ata {
1272         u8                                 subcommand;
1273         u8                                 reserved01;
1274         u8                                 command;
1275         u8                                 command_flags;
1276 };
1277
1278 struct mpi3_allowed_cmd_nvme {
1279         u8                                 reserved00;
1280         u8                                 nvme_cmd_flags;
1281         u8                                 op_code;
1282         u8                                 command_flags;
1283 };
1284
1285 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK     (0x80)
1286 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO       (0x00)
1287 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN    (0x80)
1288 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK        (0x3f)
1289 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM         (0x00)
1290 union mpi3_allowed_cmd {
1291         struct mpi3_allowed_cmd_scsi           scsi;
1292         struct mpi3_allowed_cmd_ata            ata;
1293         struct mpi3_allowed_cmd_nvme           nvme;
1294 };
1295
1296 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED    (0x20)
1297 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED      (0x10)
1298 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED      (0x08)
1299 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED   (0x04)
1300 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED      (0x02)
1301 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED    (0x01)
1302 #ifndef MPI3_ALLOWED_CMDS_MAX
1303 #define MPI3_ALLOWED_CMDS_MAX           (1)
1304 #endif
1305 struct mpi3_driver_page0 {
1306         struct mpi3_config_page_header         header;
1307         __le32                             bsd_options;
1308         u8                                 ssu_timeout;
1309         u8                                 io_timeout;
1310         u8                                 tur_retries;
1311         u8                                 tur_interval;
1312         u8                                 reserved10;
1313         u8                                 security_key_timeout;
1314         __le16                             reserved12;
1315         __le32                             reserved14;
1316         __le32                             reserved18;
1317 };
1318 #define MPI3_DRIVER0_PAGEVERSION               (0x00)
1319 #define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE         (0x00000020)
1320 #define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE             (0x00000010)
1321 #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE           (0x00000008)
1322 #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL            (0x00000004)
1323 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK              (0x00000003)
1324 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS      (0x00000000)
1325 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY          (0x00000001)
1326 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS         (0x00000002)
1327 struct mpi3_driver_page1 {
1328         struct mpi3_config_page_header         header;
1329         __le32                             flags;
1330         __le32                             reserved0c;
1331         __le16                             host_diag_trace_max_size;
1332         __le16                             host_diag_trace_min_size;
1333         __le16                             host_diag_trace_decrement_size;
1334         __le16                             reserved16;
1335         __le16                             host_diag_fw_max_size;
1336         __le16                             host_diag_fw_min_size;
1337         __le16                             host_diag_fw_decrement_size;
1338         __le16                             reserved1e;
1339         __le16                             host_diag_driver_max_size;
1340         __le16                             host_diag_driver_min_size;
1341         __le16                             host_diag_driver_decrement_size;
1342         __le16                             reserved26;
1343 };
1344
1345 #define MPI3_DRIVER1_PAGEVERSION               (0x00)
1346 #ifndef MPI3_DRIVER2_TRIGGER_MAX
1347 #define MPI3_DRIVER2_TRIGGER_MAX           (1)
1348 #endif
1349 struct mpi3_driver2_trigger_event {
1350         u8                                 type;
1351         u8                                 flags;
1352         u8                                 reserved02;
1353         u8                                 event;
1354         __le32                             reserved04[3];
1355 };
1356
1357 struct mpi3_driver2_trigger_scsi_sense {
1358         u8                                 type;
1359         u8                                 flags;
1360         __le16                             reserved02;
1361         u8                                 ascq;
1362         u8                                 asc;
1363         u8                                 sense_key;
1364         u8                                 reserved07;
1365         __le32                             reserved08[2];
1366 };
1367
1368 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL                        (0xff)
1369 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL                         (0xff)
1370 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL                   (0xff)
1371 struct mpi3_driver2_trigger_reply {
1372         u8                                 type;
1373         u8                                 flags;
1374         __le16                             ioc_status;
1375         __le32                             ioc_log_info;
1376         __le32                             ioc_log_info_mask;
1377         __le32                             reserved0c;
1378 };
1379
1380 #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL                        (0xffff)
1381 union mpi3_driver2_trigger_element {
1382         struct mpi3_driver2_trigger_event             event;
1383         struct mpi3_driver2_trigger_scsi_sense        scsi_sense;
1384         struct mpi3_driver2_trigger_reply             reply;
1385 };
1386
1387 #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT                                       (0x00)
1388 #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE                                  (0x01)
1389 #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY                                       (0x02)
1390 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE                         (0x02)
1391 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE                            (0x01)
1392 struct mpi3_driver_page2 {
1393         struct mpi3_config_page_header         header;
1394         __le64                             global_trigger;
1395         __le32                             reserved10[3];
1396         u8                                 num_triggers;
1397         u8                                 reserved1d[3];
1398         union mpi3_driver2_trigger_element    trigger[MPI3_DRIVER2_TRIGGER_MAX];
1399 };
1400
1401 #define MPI3_DRIVER2_PAGEVERSION               (0x00)
1402 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE                       (0x8000000000000000ULL)
1403 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE                          (0x4000000000000000ULL)
1404 #define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED                         (0x2000000000000000ULL)
1405 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED                 (0x1000000000000000ULL)
1406 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED                    (0x0800000000000000ULL)
1407 #define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED                   (0x0000000000000004ULL)
1408 #define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED                  (0x0000000000000002ULL)
1409 struct mpi3_driver_page10 {
1410         struct mpi3_config_page_header         header;
1411         __le16                             flags;
1412         __le16                             reserved0a;
1413         u8                                 num_allowed_commands;
1414         u8                                 reserved0d[3];
1415         union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
1416 };
1417
1418 #define MPI3_DRIVER10_PAGEVERSION               (0x00)
1419 struct mpi3_driver_page20 {
1420         struct mpi3_config_page_header         header;
1421         __le16                             flags;
1422         __le16                             reserved0a;
1423         u8                                 num_allowed_commands;
1424         u8                                 reserved0d[3];
1425         union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
1426 };
1427
1428 #define MPI3_DRIVER20_PAGEVERSION               (0x00)
1429 struct mpi3_driver_page30 {
1430         struct mpi3_config_page_header         header;
1431         __le16                             flags;
1432         __le16                             reserved0a;
1433         u8                                 num_allowed_commands;
1434         u8                                 reserved0d[3];
1435         union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
1436 };
1437
1438 #define MPI3_DRIVER30_PAGEVERSION               (0x00)
1439 union mpi3_security_mac {
1440         __le32                             dword[16];
1441         __le16                             word[32];
1442         u8                                 byte[64];
1443 };
1444
1445 union mpi3_security_nonce {
1446         __le32                             dword[16];
1447         __le16                             word[32];
1448         u8                                 byte[64];
1449 };
1450
1451 union mpi3_security_root_digest {
1452         __le32                             dword[16];
1453         __le16                             word[32];
1454         u8                                 byte[64];
1455 };
1456
1457 union mpi3_security0_cert_chain {
1458         __le32                             dword[1024];
1459         __le16                             word[2048];
1460         u8                                 byte[4096];
1461 };
1462
1463 struct mpi3_security_page0 {
1464         struct mpi3_config_page_header         header;
1465         u8                                 slot_num_group;
1466         u8                                 slot_num;
1467         __le16                             cert_chain_length;
1468         u8                                 cert_chain_flags;
1469         u8                                 reserved0d[3];
1470         __le32                             base_asym_algo;
1471         __le32                             base_hash_algo;
1472         __le32                             reserved18[4];
1473         union mpi3_security_mac               mac;
1474         union mpi3_security_nonce             nonce;
1475         union mpi3_security0_cert_chain       certificate_chain;
1476 };
1477
1478 #define MPI3_SECURITY0_PAGEVERSION               (0x00)
1479 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK       (0x0e)
1480 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED     (0x00)
1481 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS   (0x02)
1482 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM       (0x04)
1483 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED              (0x01)
1484 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX
1485 #define MPI3_SECURITY1_KEY_RECORD_MAX      1
1486 #endif
1487 #ifndef MPI3_SECURITY1_PAD_MAX
1488 #define MPI3_SECURITY1_PAD_MAX      4
1489 #endif
1490 union mpi3_security1_key_data {
1491         __le32                             dword[128];
1492         __le16                             word[256];
1493         u8                                 byte[512];
1494 };
1495
1496 struct mpi3_security1_key_record {
1497         u8                                 flags;
1498         u8                                 consumer;
1499         __le16                             key_data_size;
1500         __le32                             additional_key_data;
1501         __le32                             reserved08[2];
1502         union mpi3_security1_key_data         key_data;
1503 };
1504
1505 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK            (0x1f)
1506 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID       (0x00)
1507 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC            (0x01)
1508 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES             (0x02)
1509 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE   (0x03)
1510 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC    (0x04)
1511 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID         (0x00)
1512 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE         (0x01)
1513 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN        (0x02)
1514 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY        (0x03)
1515 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD     (0x04)
1516 struct mpi3_security_page1 {
1517         struct mpi3_config_page_header         header;
1518         __le32                             reserved08[2];
1519         union mpi3_security_mac               mac;
1520         union mpi3_security_nonce             nonce;
1521         u8                                 num_keys;
1522         u8                                 reserved91[3];
1523         __le32                             reserved94[3];
1524         struct mpi3_security1_key_record       key_record[MPI3_SECURITY1_KEY_RECORD_MAX];
1525         u8                                 pad[MPI3_SECURITY1_PAD_MAX];
1526 };
1527
1528 #define MPI3_SECURITY1_PAGEVERSION               (0x00)
1529 #ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX
1530 #define MPI3_SECURITY2_TRUSTED_ROOT_MAX      1
1531 #endif
1532 struct mpi3_security2_trusted_root {
1533         u8                                 level;
1534         u8                                 hash_algorithm;
1535         __le16                             trusted_root_flags;
1536         __le32                             reserved04[3];
1537         union mpi3_security_root_digest       root_digest;
1538 };
1539 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK            (0x0006)
1540 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT           (1)
1541 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD        (0x0000)
1542 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI             (0x0002)
1543 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES            (0x0001)
1544 struct mpi3_security_page2 {
1545         struct mpi3_config_page_header         header;
1546         __le32                             reserved08[2];
1547         union mpi3_security_mac               mac;
1548         union mpi3_security_nonce             nonce;
1549         __le32                             reserved90[3];
1550         u8                                 num_roots;
1551         u8                                 reserved9d[3];
1552         struct mpi3_security2_trusted_root     trusted_root[MPI3_SECURITY2_TRUSTED_ROOT_MAX];
1553 };
1554 #define MPI3_SECURITY2_PAGEVERSION               (0x00)
1555 struct mpi3_sas_io_unit0_phy_data {
1556         u8                 io_unit_port;
1557         u8                 port_flags;
1558         u8                 phy_flags;
1559         u8                 negotiated_link_rate;
1560         __le16             controller_phy_device_info;
1561         __le16             reserved06;
1562         __le16             attached_dev_handle;
1563         __le16             controller_dev_handle;
1564         __le32             discovery_status;
1565         __le32             reserved10;
1566 };
1567
1568 #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX
1569 #define MPI3_SAS_IO_UNIT0_PHY_MAX           (1)
1570 #endif
1571 struct mpi3_sas_io_unit_page0 {
1572         struct mpi3_config_page_header         header;
1573         __le32                             reserved08;
1574         u8                                 num_phys;
1575         u8                                 init_status;
1576         __le16                             reserved0e;
1577         struct mpi3_sas_io_unit0_phy_data      phy_data[MPI3_SAS_IO_UNIT0_PHY_MAX];
1578 };
1579
1580 #define MPI3_SASIOUNIT0_PAGEVERSION                          (0x00)
1581 #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS                 (0x00)
1582 #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION      (0x01)
1583 #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED      (0x02)
1584 #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS              (0x04)
1585 #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG        (0x05)
1586 #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED         (0x06)
1587 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN      (0xf0)
1588 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX      (0xff)
1589 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS           (0x08)
1590 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK      (0x03)
1591 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1   (0x00)
1592 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC   (0x01)
1593 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02)
1594 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT        (0x40)
1595 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT        (0x20)
1596 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED                (0x08)
1597 #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY                 (0x02)
1598 #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY                    (0x01)
1599 struct mpi3_sas_io_unit1_phy_data {
1600         u8                 io_unit_port;
1601         u8                 port_flags;
1602         u8                 phy_flags;
1603         u8                 max_min_link_rate;
1604         __le16             controller_phy_device_info;
1605         __le16             max_target_port_connect_time;
1606         __le32             reserved08;
1607 };
1608
1609 #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX
1610 #define MPI3_SAS_IO_UNIT1_PHY_MAX           (1)
1611 #endif
1612 struct mpi3_sas_io_unit_page1 {
1613         struct mpi3_config_page_header         header;
1614         __le16                             control_flags;
1615         __le16                             sas_narrow_max_queue_depth;
1616         __le16                             additional_control_flags;
1617         __le16                             sas_wide_max_queue_depth;
1618         u8                                 num_phys;
1619         u8                                 sata_max_q_depth;
1620         __le16                             reserved12;
1621         struct mpi3_sas_io_unit1_phy_data      phy_data[MPI3_SAS_IO_UNIT1_PHY_MAX];
1622 };
1623
1624 #define MPI3_SASIOUNIT1_PAGEVERSION                                 (0x00)
1625 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST         (0x8000)
1626 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
1627 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
1628 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
1629 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
1630 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
1631 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
1632 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
1633 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
1634 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK                     (0x0001)
1635 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME              (0x0000)
1636 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS              (0x0001)
1637 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT                 (0x0100)
1638 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
1639 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
1640 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
1641 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
1642 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
1643 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
1644 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
1645 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
1646 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
1647 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT               (0x40)
1648 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT               (0x20)
1649 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
1650 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK                          (0xf0)
1651 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT                         (4)
1652 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0                           (0xa0)
1653 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0                          (0xb0)
1654 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5                          (0xc0)
1655 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK                          (0x0f)
1656 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0                           (0x0a)
1657 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0                          (0x0b)
1658 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5                          (0x0c)
1659 struct mpi3_sas_io_unit2_phy_pm_settings {
1660         u8                 control_flags;
1661         u8                 reserved01;
1662         __le16             inactivity_timer_exponent;
1663         u8                 sata_partial_timeout;
1664         u8                 reserved05;
1665         u8                 sata_slumber_timeout;
1666         u8                 reserved07;
1667         u8                 sas_partial_timeout;
1668         u8                 reserved09;
1669         u8                 sas_slumber_timeout;
1670         u8                 reserved0b;
1671 };
1672
1673 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX
1674 #define MPI3_SAS_IO_UNIT2_PHY_MAX           (1)
1675 #endif
1676 struct mpi3_sas_io_unit_page2 {
1677         struct mpi3_config_page_header             header;
1678         u8                                     num_phys;
1679         u8                                     reserved09[3];
1680         __le32                                 reserved0c;
1681         struct mpi3_sas_io_unit2_phy_pm_settings   sas_phy_power_management_settings[MPI3_SAS_IO_UNIT2_PHY_MAX];
1682 };
1683
1684 #define MPI3_SASIOUNIT2_PAGEVERSION                     (0x00)
1685 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
1686 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
1687 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
1688 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
1689 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK            (0x7000)
1690 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT           (12)
1691 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK            (0x0700)
1692 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT           (8)
1693 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK           (0x0070)
1694 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT          (4)
1695 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK           (0x0007)
1696 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT          (0)
1697 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS             (7)
1698 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND              (6)
1699 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS    (5)
1700 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS        (4)
1701 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND         (3)
1702 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS    (2)
1703 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS        (1)
1704 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND         (0)
1705 struct mpi3_sas_io_unit_page3 {
1706         struct mpi3_config_page_header         header;
1707         __le32                             reserved08;
1708         __le32                             power_management_capabilities;
1709 };
1710
1711 #define MPI3_SASIOUNIT3_PAGEVERSION                     (0x00)
1712 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
1713 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
1714 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
1715 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
1716 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
1717 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
1718 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
1719 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
1720 struct mpi3_sas_expander_page0 {
1721         struct mpi3_config_page_header         header;
1722         u8                                 io_unit_port;
1723         u8                                 report_gen_length;
1724         __le16                             enclosure_handle;
1725         __le32                             reserved0c;
1726         __le64                             sas_address;
1727         __le32                             discovery_status;
1728         __le16                             dev_handle;
1729         __le16                             parent_dev_handle;
1730         __le16                             expander_change_count;
1731         __le16                             expander_route_indexes;
1732         u8                                 num_phys;
1733         u8                                 sas_level;
1734         __le16                             flags;
1735         __le16                             stp_bus_inactivity_time_limit;
1736         __le16                             stp_max_connect_time_limit;
1737         __le16                             stp_smp_nexus_loss_time;
1738         __le16                             max_num_routed_sas_addresses;
1739         __le64                             active_zone_manager_sas_address;
1740         __le16                             zone_lock_inactivity_limit;
1741         __le16                             reserved3a;
1742         u8                                 time_to_reduced_func;
1743         u8                                 initial_time_to_reduced_func;
1744         u8                                 max_reduced_func_time;
1745         u8                                 exp_status;
1746 };
1747
1748 #define MPI3_SASEXPANDER0_PAGEVERSION                       (0x00)
1749 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY       (0x2000)
1750 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED                 (0x1000)
1751 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES     (0x0800)
1752 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES      (0x0400)
1753 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT              (0x0200)
1754 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING              (0x0100)
1755 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT      (0x0080)
1756 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE        (0x0010)
1757 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG               (0x0004)
1758 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS          (0x0002)
1759 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG          (0x0001)
1760 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING                 (0x02)
1761 #define MPI3_SASEXPANDER0_ES_RESPONDING                     (0x03)
1762 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING           (0x04)
1763 struct mpi3_sas_expander_page1 {
1764         struct mpi3_config_page_header         header;
1765         u8                                 io_unit_port;
1766         u8                                 reserved09[3];
1767         u8                                 num_phys;
1768         u8                                 phy;
1769         __le16                             num_table_entries_programmed;
1770         u8                                 programmed_link_rate;
1771         u8                                 hw_link_rate;
1772         __le16                             attached_dev_handle;
1773         __le32                             phy_info;
1774         __le16                             attached_device_info;
1775         __le16                             reserved1a;
1776         __le16                             expander_dev_handle;
1777         u8                                 change_count;
1778         u8                                 negotiated_link_rate;
1779         u8                                 phy_identifier;
1780         u8                                 attached_phy_identifier;
1781         u8                                 reserved22;
1782         u8                                 discovery_info;
1783         __le32                             attached_phy_info;
1784         u8                                 zone_group;
1785         u8                                 self_config_status;
1786         __le16                             reserved2a;
1787         __le16                             slot;
1788         __le16                             slot_index;
1789 };
1790
1791 #define MPI3_SASEXPANDER1_PAGEVERSION                   (0x00)
1792 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED     (0x04)
1793 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE   (0x02)
1794 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES   (0x01)
1795 #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS
1796 #define MPI3_SASEXPANDER2_MAX_NUM_PHYS                               (1)
1797 #endif
1798 struct mpi3_sasexpander2_phy_element {
1799         u8                                 link_change_count;
1800         u8                                 reserved01;
1801         __le16                             rate_change_count;
1802         __le32                             reserved04;
1803 };
1804
1805 struct mpi3_sas_expander_page2 {
1806         struct mpi3_config_page_header         header;
1807         u8                                 num_phys;
1808         u8                                 reserved09;
1809         __le16                             dev_handle;
1810         __le32                             reserved0c;
1811         struct mpi3_sasexpander2_phy_element   phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS];
1812 };
1813
1814 #define MPI3_SASEXPANDER2_PAGEVERSION                   (0x00)
1815 struct mpi3_sas_port_page0 {
1816         struct mpi3_config_page_header         header;
1817         u8                                 port_number;
1818         u8                                 reserved09;
1819         u8                                 port_width;
1820         u8                                 reserved0b;
1821         u8                                 zone_group;
1822         u8                                 reserved0d[3];
1823         __le64                             sas_address;
1824         __le16                             device_info;
1825         __le16                             reserved1a;
1826         __le32                             reserved1c;
1827 };
1828
1829 #define MPI3_SASPORT0_PAGEVERSION                       (0x00)
1830 struct mpi3_sas_phy_page0 {
1831         struct mpi3_config_page_header         header;
1832         __le16                             owner_dev_handle;
1833         __le16                             reserved0a;
1834         __le16                             attached_dev_handle;
1835         u8                                 attached_phy_identifier;
1836         u8                                 reserved0f;
1837         __le32                             attached_phy_info;
1838         u8                                 programmed_link_rate;
1839         u8                                 hw_link_rate;
1840         u8                                 change_count;
1841         u8                                 flags;
1842         __le32                             phy_info;
1843         u8                                 negotiated_link_rate;
1844         u8                                 reserved1d[3];
1845         __le16                             slot;
1846         __le16                             slot_index;
1847 };
1848
1849 #define MPI3_SASPHY0_PAGEVERSION                        (0x00)
1850 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC      (0x01)
1851 struct mpi3_sas_phy_page1 {
1852         struct mpi3_config_page_header         header;
1853         __le32                             reserved08;
1854         __le32                             invalid_dword_count;
1855         __le32                             running_disparity_error_count;
1856         __le32                             loss_dword_synch_count;
1857         __le32                             phy_reset_problem_count;
1858 };
1859
1860 #define MPI3_SASPHY1_PAGEVERSION                        (0x00)
1861 struct mpi3_sas_phy2_phy_event {
1862         u8         phy_event_code;
1863         u8         reserved01[3];
1864         __le32     phy_event_info;
1865 };
1866
1867 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX
1868 #define MPI3_SAS_PHY2_PHY_EVENT_MAX         (1)
1869 #endif
1870 struct mpi3_sas_phy_page2 {
1871         struct mpi3_config_page_header         header;
1872         __le32                             reserved08;
1873         u8                                 num_phy_events;
1874         u8                                 reserved0d[3];
1875         struct mpi3_sas_phy2_phy_event         phy_event[MPI3_SAS_PHY2_PHY_EVENT_MAX];
1876 };
1877
1878 #define MPI3_SASPHY2_PAGEVERSION                        (0x00)
1879 struct mpi3_sas_phy3_phy_event_config {
1880         u8         phy_event_code;
1881         u8         reserved01[3];
1882         u8         counter_type;
1883         u8         threshold_window;
1884         u8         time_units;
1885         u8         reserved07;
1886         __le32     event_threshold;
1887         __le16     threshold_flags;
1888         __le16     reserved0e;
1889 };
1890
1891 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
1892 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
1893 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
1894 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
1895 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
1896 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
1897 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
1898 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS             (0x07)
1899 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC        (0x08)
1900 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
1901 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
1902 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
1903 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
1904 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
1905 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
1906 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
1907 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
1908 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
1909 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
1910 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION                  (0x2a)
1911 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2b)
1912 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2c)
1913 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2d)
1914 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2e)
1915 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN                (0x2f)
1916 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
1917 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
1918 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
1919 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
1920 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
1921 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
1922 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
1923 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
1924 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
1925 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
1926 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
1927 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
1928 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xd0)
1929 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xd1)
1930 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP                      (0xd2)
1931 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME             (0xd3)
1932 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME    (0xd4)
1933 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME                 (0xd5)
1934 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT       (0xd6)
1935 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START               (0xd7)
1936 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT        (0xd8)
1937 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN           (0xd9)
1938 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE        (0xda)
1939 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE       (0xdb)
1940 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE        (0xdc)
1941 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
1942 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
1943 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
1944 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
1945 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
1946 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
1947 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
1948 #define MPI3_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
1949 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
1950 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX
1951 #define MPI3_SAS_PHY3_PHY_EVENT_MAX         (1)
1952 #endif
1953 struct mpi3_sas_phy_page3 {
1954         struct mpi3_config_page_header         header;
1955         __le32                             reserved08;
1956         u8                                 num_phy_events;
1957         u8                                 reserved0d[3];
1958         struct mpi3_sas_phy3_phy_event_config  phy_event_config[MPI3_SAS_PHY3_PHY_EVENT_MAX];
1959 };
1960
1961 #define MPI3_SASPHY3_PAGEVERSION                        (0x00)
1962 struct mpi3_sas_phy_page4 {
1963         struct mpi3_config_page_header         header;
1964         u8                                 reserved08[3];
1965         u8                                 flags;
1966         u8                                 initial_frame[28];
1967 };
1968
1969 #define MPI3_SASPHY4_PAGEVERSION                        (0x00)
1970 #define MPI3_SASPHY4_FLAGS_FRAME_VALID                  (0x02)
1971 #define MPI3_SASPHY4_FLAGS_SATA_FRAME                   (0x01)
1972 #define MPI3_PCIE_LINK_RETIMERS_MASK                    (0x30)
1973 #define MPI3_PCIE_LINK_RETIMERS_SHIFT                   (4)
1974 #define MPI3_PCIE_NEG_LINK_RATE_MASK                    (0x0f)
1975 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN                 (0x00)
1976 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED            (0x01)
1977 #define MPI3_PCIE_NEG_LINK_RATE_2_5                     (0x02)
1978 #define MPI3_PCIE_NEG_LINK_RATE_5_0                     (0x03)
1979 #define MPI3_PCIE_NEG_LINK_RATE_8_0                     (0x04)
1980 #define MPI3_PCIE_NEG_LINK_RATE_16_0                    (0x05)
1981 #define MPI3_PCIE_NEG_LINK_RATE_32_0                    (0x06)
1982 #define MPI3_PCIE_ASPM_ENABLE_NONE                      (0x0)
1983 #define MPI3_PCIE_ASPM_ENABLE_L0S                       (0x1)
1984 #define MPI3_PCIE_ASPM_ENABLE_L1                        (0x2)
1985 #define MPI3_PCIE_ASPM_ENABLE_L0S_L1                    (0x3)
1986 #define MPI3_PCIE_ASPM_SUPPORT_NONE                     (0x0)
1987 #define MPI3_PCIE_ASPM_SUPPORT_L0S                      (0x1)
1988 #define MPI3_PCIE_ASPM_SUPPORT_L1                       (0x2)
1989 #define MPI3_PCIE_ASPM_SUPPORT_L0S_L1                   (0x3)
1990 struct mpi3_pcie_io_unit0_phy_data {
1991         u8         link;
1992         u8         link_flags;
1993         u8         phy_flags;
1994         u8         negotiated_link_rate;
1995         __le16     attached_dev_handle;
1996         __le16     controller_dev_handle;
1997         __le32     enumeration_status;
1998         u8         io_unit_port;
1999         u8         reserved0d[3];
2000 };
2001
2002 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK      (0x10)
2003 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1   (0x00)
2004 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE   (0x10)
2005 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS        (0x08)
2006 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED          (0x08)
2007 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY              (0x01)
2008 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED   (0x80000000)
2009 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED       (0x40000000)
2010 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED      (0x20000000)
2011 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES      (0x10000000)
2012 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX
2013 #define MPI3_PCIE_IO_UNIT0_PHY_MAX      (1)
2014 #endif
2015 struct mpi3_pcie_io_unit_page0 {
2016         struct mpi3_config_page_header         header;
2017         __le32                             reserved08;
2018         u8                                 num_phys;
2019         u8                                 init_status;
2020         u8                                 aspm;
2021         u8                                 reserved0f;
2022         struct mpi3_pcie_io_unit0_phy_data     phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX];
2023 };
2024
2025 #define MPI3_PCIEIOUNIT0_PAGEVERSION                        (0x00)
2026 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS               (0x00)
2027 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION    (0x01)
2028 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED    (0x02)
2029 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED   (0x03)
2030 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS            (0x04)
2031 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG      (0x05)
2032 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH      (0x06)
2033 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE    (0x07)
2034 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE       (0x08)
2035 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START         (0xf0)
2036 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END           (0xff)
2037 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK            (0xc0)
2038 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT              (6)
2039 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK            (0x30)
2040 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT              (4)
2041 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK           (0x0c)
2042 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT             (2)
2043 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK           (0x03)
2044 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT             (0)
2045 struct mpi3_pcie_io_unit1_phy_data {
2046         u8         link;
2047         u8         link_flags;
2048         u8         phy_flags;
2049         u8         max_min_link_rate;
2050         __le32     reserved04;
2051         __le32     reserved08;
2052 };
2053
2054 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK                     (0x03)
2055 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK      (0x00)
2056 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS                  (0x01)
2057 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS                  (0x02)
2058 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE                             (0x08)
2059 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK                               (0xf0)
2060 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT                                 (4)
2061 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5                                (0x20)
2062 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0                                (0x30)
2063 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0                                (0x40)
2064 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0                               (0x50)
2065 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0                               (0x60)
2066 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX
2067 #define MPI3_PCIE_IO_UNIT1_PHY_MAX                                           (1)
2068 #endif
2069 struct mpi3_pcie_io_unit_page1 {
2070         struct mpi3_config_page_header         header;
2071         __le32                             control_flags;
2072         __le32                             reserved0c;
2073         u8                                 num_phys;
2074         u8                                 reserved11;
2075         u8                                 aspm;
2076         u8                                 reserved13;
2077         struct mpi3_pcie_io_unit1_phy_data     phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX];
2078 };
2079
2080 #define MPI3_PCIEIOUNIT1_PAGEVERSION                                           (0x00)
2081 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK                     (0xe0000000)
2082 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE                     (0x00000000)
2083 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT                 (0x20000000)
2084 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT                   (0x40000000)
2085 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR          (0x60000000)
2086 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK                    (0x1c000000)
2087 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE                    (0x00000000)
2088 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT                (0x04000000)
2089 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT                  (0x08000000)
2090 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR         (0x0c000000)
2091 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE                   (0x00000080)
2092 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE                  (0x00000040)
2093 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK                (0x00000030)
2094 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT               (4)
2095 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED  (0x00000000)
2096 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED        (0x00000010)
2097 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED        (0x00000020)
2098 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK                 (0x0000000f)
2099 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE        (0x00000000)
2100 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5              (0x00000002)
2101 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0              (0x00000003)
2102 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0              (0x00000004)
2103 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0             (0x00000005)
2104 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0             (0x00000006)
2105 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK                                 (0x0c)
2106 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT                                   (2)
2107 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK                                 (0x03)
2108 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT                                   (0)
2109 struct mpi3_pcie_io_unit_page2 {
2110         struct mpi3_config_page_header         header;
2111         __le16                             nvme_max_q_dx1;
2112         __le16                             nvme_max_q_dx2;
2113         u8                                 nvme_abort_to;
2114         u8                                 reserved0d;
2115         __le16                             nvme_max_q_dx4;
2116 };
2117
2118 #define MPI3_PCIEIOUNIT2_PAGEVERSION                        (0x00)
2119 #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR               (0)
2120 #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY                     (1)
2121 #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG        (2)
2122 #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP                     (3)
2123 #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP                      (4)
2124 #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX                    (5)
2125 struct mpi3_pcie_io_unit3_error {
2126         __le16                             threshold_count;
2127         __le16                             reserved02;
2128 };
2129
2130 struct mpi3_pcie_io_unit_page3 {
2131         struct mpi3_config_page_header         header;
2132         u8                                 threshold_window;
2133         u8                                 threshold_action;
2134         u8                                 escalation_count;
2135         u8                                 escalation_action;
2136         u8                                 num_errors;
2137         u8                                 reserved0d[3];
2138         struct mpi3_pcie_io_unit3_error        error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX];
2139 };
2140
2141 #define MPI3_PCIEIOUNIT3_PAGEVERSION                        (0x00)
2142 #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION                   (0x00)
2143 #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET                   (0x01)
2144 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY       (0x02)
2145 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS  (0x03)
2146 struct mpi3_pcie_switch_page0 {
2147         struct mpi3_config_page_header     header;
2148         u8                             io_unit_port;
2149         u8                             switch_status;
2150         u8                             reserved0a[2];
2151         __le16                         dev_handle;
2152         __le16                         parent_dev_handle;
2153         u8                             num_ports;
2154         u8                             pcie_level;
2155         __le16                         reserved12;
2156         __le32                         reserved14;
2157         __le32                         reserved18;
2158         __le32                         reserved1c;
2159 };
2160
2161 #define MPI3_PCIESWITCH0_PAGEVERSION                  (0x00)
2162 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING            (0x02)
2163 #define MPI3_PCIESWITCH0_SS_RESPONDING                (0x03)
2164 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING      (0x04)
2165 struct mpi3_pcie_switch_page1 {
2166         struct mpi3_config_page_header     header;
2167         u8                             io_unit_port;
2168         u8                             flags;
2169         __le16                         reserved0a;
2170         u8                             num_ports;
2171         u8                             port_num;
2172         __le16                         attached_dev_handle;
2173         __le16                         switch_dev_handle;
2174         u8                             negotiated_port_width;
2175         u8                             negotiated_link_rate;
2176         __le16                         slot;
2177         __le16                         slot_index;
2178         __le32                         reserved18;
2179 };
2180
2181 #define MPI3_PCIESWITCH1_PAGEVERSION        (0x00)
2182 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK     (0x0c)
2183 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT    (2)
2184 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK     (0x03)
2185 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT    (0)
2186 #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS
2187 #define MPI3_PCIESWITCH2_MAX_NUM_PORTS                               (1)
2188 #endif
2189 struct mpi3_pcieswitch2_port_element {
2190         __le16                             link_change_count;
2191         __le16                             rate_change_count;
2192         __le32                             reserved04;
2193 };
2194
2195 struct mpi3_pcie_switch_page2 {
2196         struct mpi3_config_page_header         header;
2197         u8                                 num_ports;
2198         u8                                 reserved09;
2199         __le16                             dev_handle;
2200         __le32                             reserved0c;
2201         struct mpi3_pcieswitch2_port_element   port[MPI3_PCIESWITCH2_MAX_NUM_PORTS];
2202 };
2203
2204 #define MPI3_PCIESWITCH2_PAGEVERSION        (0x00)
2205 struct mpi3_pcie_link_page0 {
2206         struct mpi3_config_page_header     header;
2207         u8                             link;
2208         u8                             reserved09[3];
2209         __le32                         reserved0c;
2210         __le32                         receiver_error_count;
2211         __le32                         recovery_count;
2212         __le32                         corr_error_msg_count;
2213         __le32                         non_fatal_error_msg_count;
2214         __le32                         fatal_error_msg_count;
2215         __le32                         non_fatal_error_count;
2216         __le32                         fatal_error_count;
2217         __le32                         bad_dllp_count;
2218         __le32                         bad_tlp_count;
2219 };
2220
2221 #define MPI3_PCIELINK0_PAGEVERSION          (0x00)
2222 struct mpi3_enclosure_page0 {
2223         struct mpi3_config_page_header         header;
2224         __le64                             enclosure_logical_id;
2225         __le16                             flags;
2226         __le16                             enclosure_handle;
2227         __le16                             num_slots;
2228         __le16                             reserved16;
2229         u8                                 io_unit_port;
2230         u8                                 enclosure_level;
2231         __le16                             sep_dev_handle;
2232         u8                                 chassis_slot;
2233         u8                                 reserved1d[3];
2234 };
2235
2236 #define MPI3_ENCLOSURE0_PAGEVERSION                     (0x00)
2237 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK                (0xc000)
2238 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL             (0x0000)
2239 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS                 (0x4000)
2240 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE                (0x8000)
2241 #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID            (0x0020)
2242 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK         (0x0010)
2243 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND            (0x0000)
2244 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT              (0x0010)
2245 #define MPI3_ENCLS0_FLAGS_MNG_MASK                      (0x000f)
2246 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN                   (0x0000)
2247 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES                   (0x0001)
2248 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE             (0x0002)
2249 #define MPI3_DEVICE_DEVFORM_SAS_SATA                    (0x00)
2250 #define MPI3_DEVICE_DEVFORM_PCIE                        (0x01)
2251 #define MPI3_DEVICE_DEVFORM_VD                          (0x02)
2252 struct mpi3_device0_sas_sata_format {
2253         __le64     sas_address;
2254         __le16     flags;
2255         __le16     device_info;
2256         u8         phy_num;
2257         u8         attached_phy_identifier;
2258         u8         max_port_connections;
2259         u8         zone_group;
2260 };
2261
2262 #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400)
2263 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP          (0x0200)
2264 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP          (0x0100)
2265 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY         (0x0080)
2266 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE          (0x0040)
2267 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV           (0x0020)
2268 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA            (0x0010)
2269 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP           (0x0008)
2270 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP             (0x0004)
2271 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP             (0x0002)
2272 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP          (0x0001)
2273 struct mpi3_device0_pcie_format {
2274         u8         supported_link_rates;
2275         u8         max_port_width;
2276         u8         negotiated_port_width;
2277         u8         negotiated_link_rate;
2278         u8         port_num;
2279         u8         controller_reset_to;
2280         __le16     device_info;
2281         __le32     maximum_data_transfer_size;
2282         __le32     capabilities;
2283         __le16     noiob;
2284         u8         nvme_abort_to;
2285         u8         page_size;
2286         __le16     shutdown_latency;
2287         u8         recovery_info;
2288         u8         reserved17;
2289 };
2290
2291 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP           (0x10)
2292 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP           (0x08)
2293 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP            (0x04)
2294 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP            (0x02)
2295 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP            (0x01)
2296 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK             (0x0007)
2297 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE        (0x0000)
2298 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE      (0x0001)
2299 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE    (0x0002)
2300 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE      (0x0003)
2301 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK             (0x0030)
2302 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT            (4)
2303 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK           (0x00c0)
2304 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT          (6)
2305 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0              (0x0000)
2306 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1              (0x0040)
2307 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2              (0x0080)
2308 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3              (0x00c0)
2309 #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED    (0x00000020)
2310 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED            (0x00000010)
2311 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED      (0x00000008)
2312 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL                (0x00000004)
2313 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP                (0x00000000)
2314 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP           (0x00000002)
2315 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP                      (0x00000001)
2316 #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK                     (0x000000c0)
2317 #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT                    (6)
2318 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK               (0xe0)
2319 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT            (0x00)
2320 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT             (0x20)
2321 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK               (0x1f)
2322 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS              (0x00)
2323 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1          (0x01)
2324 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS        (0x02)
2325 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION         (0x03)
2326 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ        (0x04)
2327 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ        (0x05)
2328 struct mpi3_device0_vd_format {
2329         u8         vd_state;
2330         u8         raid_level;
2331         __le16     device_info;
2332         __le16     flags;
2333         __le16     io_throttle_group;
2334         __le16     io_throttle_group_low;
2335         __le16     io_throttle_group_high;
2336         __le32     reserved0c;
2337 };
2338 #define MPI3_DEVICE0_VD_STATE_OFFLINE                       (0x00)
2339 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED            (0x01)
2340 #define MPI3_DEVICE0_VD_STATE_DEGRADED                      (0x02)
2341 #define MPI3_DEVICE0_VD_STATE_OPTIMAL                       (0x03)
2342 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0                    (0)
2343 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1                    (1)
2344 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5                    (5)
2345 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6                    (6)
2346 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10                   (10)
2347 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50                   (50)
2348 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60                   (60)
2349 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD                     (0x0010)
2350 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD                     (0x0008)
2351 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME                    (0x0004)
2352 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA                    (0x0002)
2353 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS                     (0x0001)
2354 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK     (0xf000)
2355 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT    (12)
2356 union mpi3_device0_dev_spec_format {
2357         struct mpi3_device0_sas_sata_format        sas_sata_format;
2358         struct mpi3_device0_pcie_format            pcie_format;
2359         struct mpi3_device0_vd_format              vd_format;
2360 };
2361
2362 struct mpi3_device_page0 {
2363         struct mpi3_config_page_header         header;
2364         __le16                             dev_handle;
2365         __le16                             parent_dev_handle;
2366         __le16                             slot;
2367         __le16                             enclosure_handle;
2368         __le64                             wwid;
2369         __le16                             persistent_id;
2370         u8                                 io_unit_port;
2371         u8                                 access_status;
2372         __le16                             flags;
2373         __le16                             reserved1e;
2374         __le16                             slot_index;
2375         __le16                             queue_depth;
2376         u8                                 reserved24[3];
2377         u8                                 device_form;
2378         union mpi3_device0_dev_spec_format    device_specific;
2379 };
2380
2381 #define MPI3_DEVICE0_PAGEVERSION                        (0x00)
2382 #define MPI3_DEVICE0_PARENT_INVALID                     (0xffff)
2383 #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE      (0x0000)
2384 #define MPI3_DEVICE0_WWID_INVALID                       (0xffffffffffffffff)
2385 #define MPI3_DEVICE0_PERSISTENTID_INVALID               (0xffff)
2386 #define MPI3_DEVICE0_IOUNITPORT_INVALID                 (0xff)
2387 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS                              (0x00)
2388 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION                   (0x01)
2389 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED                        (0x02)
2390 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED                         (0x03)
2391 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED                           (0x04)
2392 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY                   (0x05)
2393 #define MPI3_DEVICE0_ASTATUS_PREPARE                                (0x06)
2394 #define MPI3_DEVICE0_ASTATUS_SAFE_MODE                              (0x07)
2395 #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX                            (0x0f)
2396 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN                            (0x10)
2397 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE                  (0x11)
2398 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE              (0x12)
2399 #define MPI3_DEVICE0_ASTATUS_SAS_MAX                                (0x1f)
2400 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN                            (0x20)
2401 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT               (0x21)
2402 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG                               (0x22)
2403 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION                     (0x23)
2404 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER                        (0x24)
2405 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN                             (0x25)
2406 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN                            (0x26)
2407 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN                            (0x27)
2408 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION                   (0x28)
2409 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE                    (0x29)
2410 #define MPI3_DEVICE0_ASTATUS_SIF_MAX                                (0x2f)
2411 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN                           (0x30)
2412 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS                  (0x31)
2413 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED                       (0x32)
2414 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED                     (0x33)
2415 #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED                     (0x34)
2416 #define MPI3_DEVICE0_ASTATUS_PCIE_MAX                               (0x3f)
2417 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN                           (0x40)
2418 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT                     (0x41)
2419 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED                (0x42)
2420 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED                   (0x43)
2421 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED                    (0x44)
2422 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED                  (0x45)
2423 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED                   (0x46)
2424 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED           (0x47)
2425 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT                      (0x48)
2426 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS               (0x49)
2427 #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER                (0x4a)
2428 #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE                   (0x4b)
2429 #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE                 (0x4c)
2430 #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION                 (0x4d)
2431 #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME                   (0x4e)
2432 #define MPI3_DEVICE0_ASTATUS_NVME_BAR                               (0x4f)
2433 #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR                     (0x50)
2434 #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS             (0x51)
2435 #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS                   (0x52)
2436 #define MPI3_DEVICE0_ASTATUS_NVME_MAX                               (0x5f)
2437 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN                             (0x80)
2438 #define MPI3_DEVICE0_ASTATUS_VD_MAX                                 (0x8f)
2439 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK          (0xe000)
2440 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT      (0x0000)
2441 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB        (0x2000)
2442 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB       (0x4000)
2443 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE        (0x0080)
2444 #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED       (0x0010)
2445 #define MPI3_DEVICE0_FLAGS_HIDDEN                       (0x0008)
2446 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL           (0x0004)
2447 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED      (0x0002)
2448 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2449 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE         (0x0000)
2450 struct mpi3_device1_sas_sata_format {
2451         __le32                             reserved00;
2452 };
2453 struct mpi3_device1_pcie_format {
2454         __le16                             vendor_id;
2455         __le16                             device_id;
2456         __le16                             subsystem_vendor_id;
2457         __le16                             subsystem_id;
2458         __le32                             reserved08;
2459         u8                                 revision_id;
2460         u8                                 reserved0d;
2461         __le16                             pci_parameters;
2462 };
2463
2464 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B              (0x0)
2465 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B              (0x1)
2466 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B              (0x2)
2467 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B             (0x3)
2468 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B             (0x4)
2469 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B             (0x5)
2470 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK           (0x01c0)
2471 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT          (6)
2472 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK       (0x0038)
2473 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT      (3)
2474 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK       (0x0007)
2475 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT      (0)
2476 struct mpi3_device1_vd_format {
2477         __le32                             reserved00;
2478 };
2479
2480 union mpi3_device1_dev_spec_format {
2481         struct mpi3_device1_sas_sata_format    sas_sata_format;
2482         struct mpi3_device1_pcie_format        pcie_format;
2483         struct mpi3_device1_vd_format          vd_format;
2484 };
2485
2486 struct mpi3_device_page1 {
2487         struct mpi3_config_page_header         header;
2488         __le16                             dev_handle;
2489         __le16                             reserved0a;
2490         __le16                             link_change_count;
2491         __le16                             rate_change_count;
2492         __le16                             tm_count;
2493         __le16                             reserved12;
2494         __le32                             reserved14[10];
2495         u8                                 reserved3c[3];
2496         u8                                 device_form;
2497         union mpi3_device1_dev_spec_format    device_specific;
2498 };
2499
2500 #define MPI3_DEVICE1_PAGEVERSION                            (0x00)
2501 #define MPI3_DEVICE1_COUNTER_MAX                            (0xfffe)
2502 #define MPI3_DEVICE1_COUNTER_INVALID                        (0xffff)
2503 #endif