drivers/mfd/cs42l43.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * CS42L43 core driver
   4  *
   5  * Copyright (C) 2022-2023 Cirrus Logic, Inc. and
   6  *                         Cirrus Logic International Semiconductor Ltd.
   7  */
   8
   9 #include <linux/array_size.h>
  10 #include <linux/bitops.h>
  11 #include <linux/build_bug.h>
  12 #include <linux/delay.h>
  13 #include <linux/device.h>
  14 #include <linux/err.h>
  15 #include <linux/firmware.h>
  16 #include <linux/gpio/consumer.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/mfd/core.h>
  19 #include <linux/mfd/cs42l43.h>
  20 #include <linux/mfd/cs42l43-regs.h>
  21 #include <linux/module.h>
  22 #include <linux/pm.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regmap.h>
  25 #include <linux/soundwire/sdw.h>
  26 #include <linux/types.h>
  27
  28 #include "cs42l43.h"
  29
  30 #define CS42L43_RESET_DELAY_MS                  20
  31
  32 #define CS42L43_SDW_ATTACH_TIMEOUT_MS           500
  33 #define CS42L43_SDW_DETACH_TIMEOUT_MS           100
  34
  35 #define CS42L43_MCU_BOOT_STAGE1                 1
  36 #define CS42L43_MCU_BOOT_STAGE2                 2
  37 #define CS42L43_MCU_BOOT_STAGE3                 3
  38 #define CS42L43_MCU_BOOT_STAGE4                 4
  39 #define CS42L43_MCU_POLL_US                     5000
  40 #define CS42L43_MCU_CMD_TIMEOUT_US              20000
  41 #define CS42L43_MCU_UPDATE_FORMAT               3
  42 #define CS42L43_MCU_UPDATE_OFFSET               0x100000
  43 #define CS42L43_MCU_UPDATE_TIMEOUT_US           500000
  44 #define CS42L43_MCU_UPDATE_RETRIES              5
  45
  46 #define CS42L43_MCU_SUPPORTED_REV               0x2105
  47 #define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV    0x2200
  48 #define CS42L43_MCU_SUPPORTED_BIOS_REV          0x0001
  49
  50 #define CS42L43_VDDP_DELAY_US                   50
  51 #define CS42L43_VDDD_DELAY_US                   1000
  52
  53 #define CS42L43_AUTOSUSPEND_TIME_MS             250
  54
  55 struct cs42l43_patch_header {
  56         __le16 version;
  57         __le16 size;
  58         __u8 reserved;
  59         __u8 secure;
  60         __le16 bss_size;
  61         __le32 apply_addr;
  62         __le32 checksum;
  63         __le32 sha;
  64         __le16 swrev;
  65         __le16 patchid;
  66         __le16 ipxid;
  67         __le16 romver;
  68         __le32 load_addr;
  69 } __packed;
  70
  71 static const struct reg_sequence cs42l43_reva_patch[] = {
  72         { 0x4000,                                       0x00000055 },
  73         { 0x4000,                                       0x000000AA },
  74         { 0x10084,                                      0x00000000 },
  75         { 0x1741C,                                      0x00CD2000 },
  76         { 0x1718C,                                      0x00000003 },
  77         { 0x4000,                                       0x00000000 },
  78         { CS42L43_CCM_BLK_CLK_CONTROL,                  0x00000002 },
  79         { CS42L43_HPPATHVOL,                            0x011B011B },
  80         { CS42L43_OSC_DIV_SEL,                          0x00000001 },
  81         { CS42L43_DACCNFG2,                             0x00000005 },
  82         { CS42L43_MIC_DETECT_CONTROL_ANDROID,           0x80790079 },
  83         { CS42L43_RELID,                                0x0000000F },
  84 };
  85
  86 const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
  87         { CS42L43_DRV_CTRL1,                            0x000186C0 },
  88         { CS42L43_DRV_CTRL3,                            0x286DB018 },
  89         { CS42L43_DRV_CTRL4,                            0x000006D8 },
  90         { CS42L43_DRV_CTRL_5,                           0x136C00C0 },
  91         { CS42L43_GPIO_CTRL1,                           0x00000707 },
  92         { CS42L43_GPIO_CTRL2,                           0x00000000 },
  93         { CS42L43_GPIO_FN_SEL,                          0x00000004 },
  94         { CS42L43_MCLK_SRC_SEL,                         0x00000000 },
  95         { CS42L43_SAMPLE_RATE1,                         0x00000003 },
  96         { CS42L43_SAMPLE_RATE2,                         0x00000003 },
  97         { CS42L43_SAMPLE_RATE3,                         0x00000003 },
  98         { CS42L43_SAMPLE_RATE4,                         0x00000003 },
  99         { CS42L43_PLL_CONTROL,                          0x00000000 },
 100         { CS42L43_FS_SELECT1,                           0x00000000 },
 101         { CS42L43_FS_SELECT2,                           0x00000000 },
 102         { CS42L43_FS_SELECT3,                           0x00000000 },
 103         { CS42L43_FS_SELECT4,                           0x00000000 },
 104         { CS42L43_PDM_CONTROL,                          0x00000000 },
 105         { CS42L43_ASP_CLK_CONFIG1,                      0x00010001 },
 106         { CS42L43_ASP_CLK_CONFIG2,                      0x00000000 },
 107         { CS42L43_OSC_DIV_SEL,                          0x00000001 },
 108         { CS42L43_ADC_B_CTRL1,                          0x00000000 },
 109         { CS42L43_ADC_B_CTRL2,                          0x00000000 },
 110         { CS42L43_DECIM_HPF_WNF_CTRL1,                  0x00000001 },
 111         { CS42L43_DECIM_HPF_WNF_CTRL2,                  0x00000001 },
 112         { CS42L43_DECIM_HPF_WNF_CTRL3,                  0x00000001 },
 113         { CS42L43_DECIM_HPF_WNF_CTRL4,                  0x00000001 },
 114         { CS42L43_DMIC_PDM_CTRL,                        0x00000000 },
 115         { CS42L43_DECIM_VOL_CTRL_CH1_CH2,               0x20122012 },
 116         { CS42L43_DECIM_VOL_CTRL_CH3_CH4,               0x20122012 },
 117         { CS42L43_INTP_VOLUME_CTRL1,                    0x00000180 },
 118         { CS42L43_INTP_VOLUME_CTRL2,                    0x00000180 },
 119         { CS42L43_AMP1_2_VOL_RAMP,                      0x00000022 },
 120         { CS42L43_ASP_CTRL,                             0x00000004 },
 121         { CS42L43_ASP_FSYNC_CTRL1,                      0x000000FA },
 122         { CS42L43_ASP_FSYNC_CTRL2,                      0x00000001 },
 123         { CS42L43_ASP_FSYNC_CTRL3,                      0x00000000 },
 124         { CS42L43_ASP_FSYNC_CTRL4,                      0x000001F4 },
 125         { CS42L43_ASP_DATA_CTRL,                        0x0000003A },
 126         { CS42L43_ASP_RX_EN,                            0x00000000 },
 127         { CS42L43_ASP_TX_EN,                            0x00000000 },
 128         { CS42L43_ASP_RX_CH1_CTRL,                      0x00170001 },
 129         { CS42L43_ASP_RX_CH2_CTRL,                      0x00170031 },
 130         { CS42L43_ASP_RX_CH3_CTRL,                      0x00170061 },
 131         { CS42L43_ASP_RX_CH4_CTRL,                      0x00170091 },
 132         { CS42L43_ASP_RX_CH5_CTRL,                      0x001700C1 },
 133         { CS42L43_ASP_RX_CH6_CTRL,                      0x001700F1 },
 134         { CS42L43_ASP_TX_CH1_CTRL,                      0x00170001 },
 135         { CS42L43_ASP_TX_CH2_CTRL,                      0x00170031 },
 136         { CS42L43_ASP_TX_CH3_CTRL,                      0x00170061 },
 137         { CS42L43_ASP_TX_CH4_CTRL,                      0x00170091 },
 138         { CS42L43_ASP_TX_CH5_CTRL,                      0x001700C1 },
 139         { CS42L43_ASP_TX_CH6_CTRL,                      0x001700F1 },
 140         { CS42L43_ASPTX1_INPUT,                         0x00000000 },
 141         { CS42L43_ASPTX2_INPUT,                         0x00000000 },
 142         { CS42L43_ASPTX3_INPUT,                         0x00000000 },
 143         { CS42L43_ASPTX4_INPUT,                         0x00000000 },
 144         { CS42L43_ASPTX5_INPUT,                         0x00000000 },
 145         { CS42L43_ASPTX6_INPUT,                         0x00000000 },
 146         { CS42L43_SWIRE_DP1_CH1_INPUT,                  0x00000000 },
 147         { CS42L43_SWIRE_DP1_CH2_INPUT,                  0x00000000 },
 148         { CS42L43_SWIRE_DP1_CH3_INPUT,                  0x00000000 },
 149         { CS42L43_SWIRE_DP1_CH4_INPUT,                  0x00000000 },
 150         { CS42L43_SWIRE_DP2_CH1_INPUT,                  0x00000000 },
 151         { CS42L43_SWIRE_DP2_CH2_INPUT,                  0x00000000 },
 152         { CS42L43_SWIRE_DP3_CH1_INPUT,                  0x00000000 },
 153         { CS42L43_SWIRE_DP3_CH2_INPUT,                  0x00000000 },
 154         { CS42L43_SWIRE_DP4_CH1_INPUT,                  0x00000000 },
 155         { CS42L43_SWIRE_DP4_CH2_INPUT,                  0x00000000 },
 156         { CS42L43_ASRC_INT1_INPUT1,                     0x00000000 },
 157         { CS42L43_ASRC_INT2_INPUT1,                     0x00000000 },
 158         { CS42L43_ASRC_INT3_INPUT1,                     0x00000000 },
 159         { CS42L43_ASRC_INT4_INPUT1,                     0x00000000 },
 160         { CS42L43_ASRC_DEC1_INPUT1,                     0x00000000 },
 161         { CS42L43_ASRC_DEC2_INPUT1,                     0x00000000 },
 162         { CS42L43_ASRC_DEC3_INPUT1,                     0x00000000 },
 163         { CS42L43_ASRC_DEC4_INPUT1,                     0x00000000 },
 164         { CS42L43_ISRC1INT1_INPUT1,                     0x00000000 },
 165         { CS42L43_ISRC1INT2_INPUT1,                     0x00000000 },
 166         { CS42L43_ISRC1DEC1_INPUT1,                     0x00000000 },
 167         { CS42L43_ISRC1DEC2_INPUT1,                     0x00000000 },
 168         { CS42L43_ISRC2INT1_INPUT1,                     0x00000000 },
 169         { CS42L43_ISRC2INT2_INPUT1,                     0x00000000 },
 170         { CS42L43_ISRC2DEC1_INPUT1,                     0x00000000 },
 171         { CS42L43_ISRC2DEC2_INPUT1,                     0x00000000 },
 172         { CS42L43_EQ1MIX_INPUT1,                        0x00800000 },
 173         { CS42L43_EQ1MIX_INPUT2,                        0x00800000 },
 174         { CS42L43_EQ1MIX_INPUT3,                        0x00800000 },
 175         { CS42L43_EQ1MIX_INPUT4,                        0x00800000 },
 176         { CS42L43_EQ2MIX_INPUT1,                        0x00800000 },
 177         { CS42L43_EQ2MIX_INPUT2,                        0x00800000 },
 178         { CS42L43_EQ2MIX_INPUT3,                        0x00800000 },
 179         { CS42L43_EQ2MIX_INPUT4,                        0x00800000 },
 180         { CS42L43_SPDIF1_INPUT1,                        0x00000000 },
 181         { CS42L43_SPDIF2_INPUT1,                        0x00000000 },
 182         { CS42L43_AMP1MIX_INPUT1,                       0x00800000 },
 183         { CS42L43_AMP1MIX_INPUT2,                       0x00800000 },
 184         { CS42L43_AMP1MIX_INPUT3,                       0x00800000 },
 185         { CS42L43_AMP1MIX_INPUT4,                       0x00800000 },
 186         { CS42L43_AMP2MIX_INPUT1,                       0x00800000 },
 187         { CS42L43_AMP2MIX_INPUT2,                       0x00800000 },
 188         { CS42L43_AMP2MIX_INPUT3,                       0x00800000 },
 189         { CS42L43_AMP2MIX_INPUT4,                       0x00800000 },
 190         { CS42L43_AMP3MIX_INPUT1,                       0x00800000 },
 191         { CS42L43_AMP3MIX_INPUT2,                       0x00800000 },
 192         { CS42L43_AMP3MIX_INPUT3,                       0x00800000 },
 193         { CS42L43_AMP3MIX_INPUT4,                       0x00800000 },
 194         { CS42L43_AMP4MIX_INPUT1,                       0x00800000 },
 195         { CS42L43_AMP4MIX_INPUT2,                       0x00800000 },
 196         { CS42L43_AMP4MIX_INPUT3,                       0x00800000 },
 197         { CS42L43_AMP4MIX_INPUT4,                       0x00800000 },
 198         { CS42L43_ASRC_INT_ENABLES,                     0x00000100 },
 199         { CS42L43_ASRC_DEC_ENABLES,                     0x00000100 },
 200         { CS42L43_PDNCNTL,                              0x00000000 },
 201         { CS42L43_RINGSENSE_DEB_CTRL,                   0x0000001B },
 202         { CS42L43_TIPSENSE_DEB_CTRL,                    0x0000001B },
 203         { CS42L43_HS2,                                  0x050106F3 },
 204         { CS42L43_STEREO_MIC_CTRL,                      0x00000000 },
 205         { CS42L43_STEREO_MIC_CLAMP_CTRL,                0x00000001 },
 206         { CS42L43_BLOCK_EN2,                            0x00000000 },
 207         { CS42L43_BLOCK_EN3,                            0x00000000 },
 208         { CS42L43_BLOCK_EN4,                            0x00000000 },
 209         { CS42L43_BLOCK_EN5,                            0x00000000 },
 210         { CS42L43_BLOCK_EN6,                            0x00000000 },
 211         { CS42L43_BLOCK_EN7,                            0x00000000 },
 212         { CS42L43_BLOCK_EN8,                            0x00000000 },
 213         { CS42L43_BLOCK_EN9,                            0x00000000 },
 214         { CS42L43_BLOCK_EN10,                           0x00000000 },
 215         { CS42L43_BLOCK_EN11,                           0x00000000 },
 216         { CS42L43_TONE_CH1_CTRL,                        0x00000000 },
 217         { CS42L43_TONE_CH2_CTRL,                        0x00000000 },
 218         { CS42L43_MIC_DETECT_CONTROL_1,                 0x00000003 },
 219         { CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL,  0x02000003 },
 220         { CS42L43_MIC_DETECT_CONTROL_ANDROID,           0x80790079 },
 221         { CS42L43_ISRC1_CTRL,                           0x00000000 },
 222         { CS42L43_ISRC2_CTRL,                           0x00000000 },
 223         { CS42L43_CTRL_REG,                             0x00000006 },
 224         { CS42L43_FDIV_FRAC,                            0x40000000 },
 225         { CS42L43_CAL_RATIO,                            0x00000080 },
 226         { CS42L43_SPI_CLK_CONFIG1,                      0x00000001 },
 227         { CS42L43_SPI_CONFIG1,                          0x00000000 },
 228         { CS42L43_SPI_CONFIG2,                          0x00000000 },
 229         { CS42L43_SPI_CONFIG3,                          0x00000001 },
 230         { CS42L43_SPI_CONFIG4,                          0x00000000 },
 231         { CS42L43_TRAN_CONFIG3,                         0x00000000 },
 232         { CS42L43_TRAN_CONFIG4,                         0x00000000 },
 233         { CS42L43_TRAN_CONFIG5,                         0x00000000 },
 234         { CS42L43_TRAN_CONFIG6,                         0x00000000 },
 235         { CS42L43_TRAN_CONFIG7,                         0x00000000 },
 236         { CS42L43_TRAN_CONFIG8,                         0x00000000 },
 237         { CS42L43_DACCNFG1,                             0x00000008 },
 238         { CS42L43_DACCNFG2,                             0x00000005 },
 239         { CS42L43_HPPATHVOL,                            0x011B011B },
 240         { CS42L43_PGAVOL,                               0x00003470 },
 241         { CS42L43_LOADDETENA,                           0x00000000 },
 242         { CS42L43_CTRL,                                 0x00000037 },
 243         { CS42L43_COEFF_DATA_IN0,                       0x00000000 },
 244         { CS42L43_COEFF_RD_WR0,                         0x00000000 },
 245         { CS42L43_START_EQZ0,                           0x00000000 },
 246         { CS42L43_MUTE_EQ_IN0,                          0x00000000 },
 247         { CS42L43_DECIM_MASK,                           0x0000000F },
 248         { CS42L43_EQ_MIX_MASK,                          0x0000000F },
 249         { CS42L43_ASP_MASK,                             0x000000FF },
 250         { CS42L43_PLL_MASK,                             0x00000003 },
 251         { CS42L43_SOFT_MASK,                            0x0000FFFF },
 252         { CS42L43_SWIRE_MASK,                           0x00007FFF },
 253         { CS42L43_MSM_MASK,                             0x00000FFF },
 254         { CS42L43_ACC_DET_MASK,                         0x00000FFF },
 255         { CS42L43_I2C_TGT_MASK,                         0x00000003 },
 256         { CS42L43_SPI_MSTR_MASK,                        0x00000007 },
 257         { CS42L43_SW_TO_SPI_BRIDGE_MASK,                0x00000001 },
 258         { CS42L43_OTP_MASK,                             0x00000007 },
 259         { CS42L43_CLASS_D_AMP_MASK,                     0x00003FFF },
 260         { CS42L43_GPIO_INT_MASK,                        0x0000003F },
 261         { CS42L43_ASRC_MASK,                            0x0000000F },
 262         { CS42L43_HPOUT_MASK,                           0x00000003 },
 263 };
 264 EXPORT_SYMBOL_NS_GPL(cs42l43_reg_default, MFD_CS42L43);
 265
 266 bool cs42l43_readable_register(struct device *dev, unsigned int reg)
 267 {
 268         switch (reg) {
 269         case CS42L43_DEVID:
 270         case CS42L43_REVID:
 271         case CS42L43_RELID:
 272         case CS42L43_SFT_RESET:
 273         case CS42L43_DRV_CTRL1:
 274         case CS42L43_DRV_CTRL3:
 275         case CS42L43_DRV_CTRL4:
 276         case CS42L43_DRV_CTRL_5:
 277         case CS42L43_GPIO_CTRL1:
 278         case CS42L43_GPIO_CTRL2:
 279         case CS42L43_GPIO_STS:
 280         case CS42L43_GPIO_FN_SEL:
 281         case CS42L43_MCLK_SRC_SEL:
 282         case CS42L43_SAMPLE_RATE1 ... CS42L43_SAMPLE_RATE4:
 283         case CS42L43_PLL_CONTROL:
 284         case CS42L43_FS_SELECT1 ... CS42L43_FS_SELECT4:
 285         case CS42L43_PDM_CONTROL:
 286         case CS42L43_ASP_CLK_CONFIG1 ... CS42L43_ASP_CLK_CONFIG2:
 287         case CS42L43_OSC_DIV_SEL:
 288         case CS42L43_ADC_B_CTRL1 ...  CS42L43_ADC_B_CTRL2:
 289         case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4:
 290         case CS42L43_DMIC_PDM_CTRL:
 291         case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4:
 292         case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2:
 293         case CS42L43_AMP1_2_VOL_RAMP:
 294         case CS42L43_ASP_CTRL:
 295         case CS42L43_ASP_FSYNC_CTRL1 ... CS42L43_ASP_FSYNC_CTRL4:
 296         case CS42L43_ASP_DATA_CTRL:
 297         case CS42L43_ASP_RX_EN ... CS42L43_ASP_TX_EN:
 298         case CS42L43_ASP_RX_CH1_CTRL ... CS42L43_ASP_RX_CH6_CTRL:
 299         case CS42L43_ASP_TX_CH1_CTRL ... CS42L43_ASP_TX_CH6_CTRL:
 300         case CS42L43_OTP_REVISION_ID:
 301         case CS42L43_ASPTX1_INPUT:
 302         case CS42L43_ASPTX2_INPUT:
 303         case CS42L43_ASPTX3_INPUT:
 304         case CS42L43_ASPTX4_INPUT:
 305         case CS42L43_ASPTX5_INPUT:
 306         case CS42L43_ASPTX6_INPUT:
 307         case CS42L43_SWIRE_DP1_CH1_INPUT:
 308         case CS42L43_SWIRE_DP1_CH2_INPUT:
 309         case CS42L43_SWIRE_DP1_CH3_INPUT:
 310         case CS42L43_SWIRE_DP1_CH4_INPUT:
 311         case CS42L43_SWIRE_DP2_CH1_INPUT:
 312         case CS42L43_SWIRE_DP2_CH2_INPUT:
 313         case CS42L43_SWIRE_DP3_CH1_INPUT:
 314         case CS42L43_SWIRE_DP3_CH2_INPUT:
 315         case CS42L43_SWIRE_DP4_CH1_INPUT:
 316         case CS42L43_SWIRE_DP4_CH2_INPUT:
 317         case CS42L43_ASRC_INT1_INPUT1:
 318         case CS42L43_ASRC_INT2_INPUT1:
 319         case CS42L43_ASRC_INT3_INPUT1:
 320         case CS42L43_ASRC_INT4_INPUT1:
 321         case CS42L43_ASRC_DEC1_INPUT1:
 322         case CS42L43_ASRC_DEC2_INPUT1:
 323         case CS42L43_ASRC_DEC3_INPUT1:
 324         case CS42L43_ASRC_DEC4_INPUT1:
 325         case CS42L43_ISRC1INT1_INPUT1:
 326         case CS42L43_ISRC1INT2_INPUT1:
 327         case CS42L43_ISRC1DEC1_INPUT1:
 328         case CS42L43_ISRC1DEC2_INPUT1:
 329         case CS42L43_ISRC2INT1_INPUT1:
 330         case CS42L43_ISRC2INT2_INPUT1:
 331         case CS42L43_ISRC2DEC1_INPUT1:
 332         case CS42L43_ISRC2DEC2_INPUT1:
 333         case CS42L43_EQ1MIX_INPUT1 ... CS42L43_EQ1MIX_INPUT4:
 334         case CS42L43_EQ2MIX_INPUT1 ... CS42L43_EQ2MIX_INPUT4:
 335         case CS42L43_SPDIF1_INPUT1:
 336         case CS42L43_SPDIF2_INPUT1:
 337         case CS42L43_AMP1MIX_INPUT1 ... CS42L43_AMP1MIX_INPUT4:
 338         case CS42L43_AMP2MIX_INPUT1 ... CS42L43_AMP2MIX_INPUT4:
 339         case CS42L43_AMP3MIX_INPUT1 ... CS42L43_AMP3MIX_INPUT4:
 340         case CS42L43_AMP4MIX_INPUT1 ... CS42L43_AMP4MIX_INPUT4:
 341         case CS42L43_ASRC_INT_ENABLES ... CS42L43_ASRC_DEC_ENABLES:
 342         case CS42L43_PDNCNTL:
 343         case CS42L43_RINGSENSE_DEB_CTRL:
 344         case CS42L43_TIPSENSE_DEB_CTRL:
 345         case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
 346         case CS42L43_HS2:
 347         case CS42L43_HS_STAT:
 348         case CS42L43_MCU_SW_INTERRUPT:
 349         case CS42L43_STEREO_MIC_CTRL:
 350         case CS42L43_STEREO_MIC_CLAMP_CTRL:
 351         case CS42L43_BLOCK_EN2 ... CS42L43_BLOCK_EN11:
 352         case CS42L43_TONE_CH1_CTRL ... CS42L43_TONE_CH2_CTRL:
 353         case CS42L43_MIC_DETECT_CONTROL_1:
 354         case CS42L43_DETECT_STATUS_1:
 355         case CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL:
 356         case CS42L43_MIC_DETECT_CONTROL_ANDROID:
 357         case CS42L43_ISRC1_CTRL:
 358         case CS42L43_ISRC2_CTRL:
 359         case CS42L43_CTRL_REG:
 360         case CS42L43_FDIV_FRAC:
 361         case CS42L43_CAL_RATIO:
 362         case CS42L43_SPI_CLK_CONFIG1:
 363         case CS42L43_SPI_CONFIG1 ... CS42L43_SPI_CONFIG4:
 364         case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
 365         case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG8:
 366         case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
 367         case CS42L43_TX_DATA:
 368         case CS42L43_RX_DATA:
 369         case CS42L43_DACCNFG1 ... CS42L43_DACCNFG2:
 370         case CS42L43_HPPATHVOL:
 371         case CS42L43_PGAVOL:
 372         case CS42L43_LOADDETRESULTS:
 373         case CS42L43_LOADDETENA:
 374         case CS42L43_CTRL:
 375         case CS42L43_COEFF_DATA_IN0:
 376         case CS42L43_COEFF_RD_WR0:
 377         case CS42L43_INIT_DONE0:
 378         case CS42L43_START_EQZ0:
 379         case CS42L43_MUTE_EQ_IN0:
 380         case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
 381         case CS42L43_DECIM_MASK ... CS42L43_HPOUT_MASK:
 382         case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
 383         case CS42L43_BOOT_CONTROL:
 384         case CS42L43_BLOCK_EN:
 385         case CS42L43_SHUTTER_CONTROL:
 386         case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
 387                 return true;
 388         default:
 389                 return false;
 390         }
 391 }
 392 EXPORT_SYMBOL_NS_GPL(cs42l43_readable_register, MFD_CS42L43);
 393
 394 bool cs42l43_precious_register(struct device *dev, unsigned int reg)
 395 {
 396         switch (reg) {
 397         case CS42L43_SFT_RESET:
 398         case CS42L43_TX_DATA:
 399         case CS42L43_RX_DATA:
 400         case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
 401         case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
 402                 return true;
 403         default:
 404                 return false;
 405         }
 406 }
 407 EXPORT_SYMBOL_NS_GPL(cs42l43_precious_register, MFD_CS42L43);
 408
 409 bool cs42l43_volatile_register(struct device *dev, unsigned int reg)
 410 {
 411         switch (reg) {
 412         case CS42L43_DEVID:
 413         case CS42L43_REVID:
 414         case CS42L43_RELID:
 415         case CS42L43_GPIO_STS:
 416         case CS42L43_OTP_REVISION_ID:
 417         case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
 418         case CS42L43_HS_STAT:
 419         case CS42L43_MCU_SW_INTERRUPT:
 420         case CS42L43_DETECT_STATUS_1:
 421         case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
 422         case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG2:
 423         case CS42L43_TRAN_CONFIG8:
 424         case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
 425         case CS42L43_LOADDETRESULTS:
 426         case CS42L43_INIT_DONE0:
 427         case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
 428         case CS42L43_BOOT_CONTROL:
 429         case CS42L43_BLOCK_EN:
 430                 return true;
 431         default:
 432                 return cs42l43_precious_register(dev, reg);
 433         }
 434 }
 435 EXPORT_SYMBOL_NS_GPL(cs42l43_volatile_register, MFD_CS42L43);
 436
 437 #define CS42L43_IRQ_OFFSET(reg) ((CS42L43_##reg##_INT) - CS42L43_DECIM_INT)
 438
 439 #define CS42L43_IRQ_REG(name, reg) REGMAP_IRQ_REG(CS42L43_##name, \
 440                                                   CS42L43_IRQ_OFFSET(reg), \
 441                                                   CS42L43_##name##_INT_MASK)
 442
 443 static const struct regmap_irq cs42l43_regmap_irqs[] = {
 444         CS42L43_IRQ_REG(PLL_LOST_LOCK,                          PLL),
 445         CS42L43_IRQ_REG(PLL_READY,                              PLL),
 446
 447         CS42L43_IRQ_REG(HP_STARTUP_DONE,                        MSM),
 448         CS42L43_IRQ_REG(HP_SHUTDOWN_DONE,                       MSM),
 449         CS42L43_IRQ_REG(HSDET_DONE,                             MSM),
 450         CS42L43_IRQ_REG(TIPSENSE_UNPLUG_DB,                     MSM),
 451         CS42L43_IRQ_REG(TIPSENSE_PLUG_DB,                       MSM),
 452         CS42L43_IRQ_REG(RINGSENSE_UNPLUG_DB,                    MSM),
 453         CS42L43_IRQ_REG(RINGSENSE_PLUG_DB,                      MSM),
 454         CS42L43_IRQ_REG(TIPSENSE_UNPLUG_PDET,                   MSM),
 455         CS42L43_IRQ_REG(TIPSENSE_PLUG_PDET,                     MSM),
 456         CS42L43_IRQ_REG(RINGSENSE_UNPLUG_PDET,                  MSM),
 457         CS42L43_IRQ_REG(RINGSENSE_PLUG_PDET,                    MSM),
 458
 459         CS42L43_IRQ_REG(HS2_BIAS_SENSE,                         ACC_DET),
 460         CS42L43_IRQ_REG(HS1_BIAS_SENSE,                         ACC_DET),
 461         CS42L43_IRQ_REG(DC_DETECT1_FALSE,                       ACC_DET),
 462         CS42L43_IRQ_REG(DC_DETECT1_TRUE,                        ACC_DET),
 463         CS42L43_IRQ_REG(HSBIAS_CLAMPED,                         ACC_DET),
 464         CS42L43_IRQ_REG(HS3_4_BIAS_SENSE,                       ACC_DET),
 465
 466         CS42L43_IRQ_REG(AMP2_CLK_STOP_FAULT,                    CLASS_D_AMP),
 467         CS42L43_IRQ_REG(AMP1_CLK_STOP_FAULT,                    CLASS_D_AMP),
 468         CS42L43_IRQ_REG(AMP2_VDDSPK_FAULT,                      CLASS_D_AMP),
 469         CS42L43_IRQ_REG(AMP1_VDDSPK_FAULT,                      CLASS_D_AMP),
 470         CS42L43_IRQ_REG(AMP2_SHUTDOWN_DONE,                     CLASS_D_AMP),
 471         CS42L43_IRQ_REG(AMP1_SHUTDOWN_DONE,                     CLASS_D_AMP),
 472         CS42L43_IRQ_REG(AMP2_STARTUP_DONE,                      CLASS_D_AMP),
 473         CS42L43_IRQ_REG(AMP1_STARTUP_DONE,                      CLASS_D_AMP),
 474         CS42L43_IRQ_REG(AMP2_THERM_SHDN,                        CLASS_D_AMP),
 475         CS42L43_IRQ_REG(AMP1_THERM_SHDN,                        CLASS_D_AMP),
 476         CS42L43_IRQ_REG(AMP2_THERM_WARN,                        CLASS_D_AMP),
 477         CS42L43_IRQ_REG(AMP1_THERM_WARN,                        CLASS_D_AMP),
 478         CS42L43_IRQ_REG(AMP2_SCDET,                             CLASS_D_AMP),
 479         CS42L43_IRQ_REG(AMP1_SCDET,                             CLASS_D_AMP),
 480
 481         CS42L43_IRQ_REG(GPIO3_FALL,                             GPIO),
 482         CS42L43_IRQ_REG(GPIO3_RISE,                             GPIO),
 483         CS42L43_IRQ_REG(GPIO2_FALL,                             GPIO),
 484         CS42L43_IRQ_REG(GPIO2_RISE,                             GPIO),
 485         CS42L43_IRQ_REG(GPIO1_FALL,                             GPIO),
 486         CS42L43_IRQ_REG(GPIO1_RISE,                             GPIO),
 487
 488         CS42L43_IRQ_REG(HP_ILIMIT,                              HPOUT),
 489         CS42L43_IRQ_REG(HP_LOADDET_DONE,                        HPOUT),
 490 };
 491
 492 static const struct regmap_irq_chip cs42l43_irq_chip = {
 493         .name = "cs42l43",
 494
 495         .status_base = CS42L43_DECIM_INT,
 496         .mask_base = CS42L43_DECIM_MASK,
 497         .num_regs = 16,
 498
 499         .irqs = cs42l43_regmap_irqs,
 500         .num_irqs = ARRAY_SIZE(cs42l43_regmap_irqs),
 501
 502         .runtime_pm = true,
 503 };
 504
 505 static const char * const cs42l43_core_supplies[] = {
 506         "vdd-a", "vdd-io", "vdd-cp",
 507 };
 508
 509 static const char * const cs42l43_parent_supplies[] = { "vdd-amp" };
 510
 511 static const struct mfd_cell cs42l43_devs[] = {
 512         { .name = "cs42l43-pinctrl", },
 513         { .name = "cs42l43-spi", },
 514         {
 515                 .name = "cs42l43-codec",
 516                 .parent_supplies = cs42l43_parent_supplies,
 517                 .num_parent_supplies = ARRAY_SIZE(cs42l43_parent_supplies),
 518         },
 519 };
 520
 521 /*
 522  * If the device is connected over Soundwire, as well as soft resetting the
 523  * device, this function will also way for the device to detach from the bus
 524  * before returning.
 525  */
 526 static int cs42l43_soft_reset(struct cs42l43 *cs42l43)
 527 {
 528         static const struct reg_sequence reset[] = {
 529                 { CS42L43_SFT_RESET, CS42L43_SFT_RESET_VAL },
 530         };
 531
 532         reinit_completion(&cs42l43->device_detach);
 533
 534         /*
 535          * Apply cache only because the soft reset will cause the device to
 536          * detach from the soundwire bus.
 537          */
 538         regcache_cache_only(cs42l43->regmap, true);
 539         regmap_multi_reg_write_bypassed(cs42l43->regmap, reset, ARRAY_SIZE(reset));
 540
 541         msleep(CS42L43_RESET_DELAY_MS);
 542
 543         if (cs42l43->sdw) {
 544                 unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_DETACH_TIMEOUT_MS);
 545                 unsigned long time;
 546
 547                 time = wait_for_completion_timeout(&cs42l43->device_detach, timeout);
 548                 if (!time) {
 549                         dev_err(cs42l43->dev, "Timed out waiting for device detach\n");
 550                         return -ETIMEDOUT;
 551                 }
 552         }
 553
 554         return -EAGAIN;
 555 }
 556
 557 /*
 558  * This function is essentially a no-op on I2C, but will wait for the device to
 559  * attach when the device is used on a SoundWire bus.
 560  */
 561 static int cs42l43_wait_for_attach(struct cs42l43 *cs42l43)
 562 {
 563         if (!cs42l43->attached) {
 564                 unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_ATTACH_TIMEOUT_MS);
 565                 unsigned long time;
 566
 567                 time = wait_for_completion_timeout(&cs42l43->device_attach, timeout);
 568                 if (!time) {
 569                         dev_err(cs42l43->dev, "Timed out waiting for device re-attach\n");
 570                         return -ETIMEDOUT;
 571                 }
 572         }
 573
 574         regcache_cache_only(cs42l43->regmap, false);
 575
 576         /* The hardware requires enabling OSC_DIV before doing any SoundWire reads. */
 577         if (cs42l43->sdw)
 578                 regmap_write(cs42l43->regmap, CS42L43_OSC_DIV_SEL,
 579                              CS42L43_OSC_DIV2_EN_MASK);
 580
 581         return 0;
 582 }
 583
 584 /*
 585  * This function will advance the firmware into boot stage 3 from boot stage 2.
 586  * Boot stage 3 is required to send commands to the firmware. This is achieved
 587  * by setting the firmware NEED configuration register to zero, this indicates
 588  * no configuration is required forcing the firmware to advance to boot stage 3.
 589  *
 590  * Later revisions of the firmware require the use of an alternative register
 591  * for this purpose, which is indicated through the shadow flag.
 592  */
 593 static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow)
 594 {
 595         unsigned int need_reg = CS42L43_NEED_CONFIGS;
 596         unsigned int val;
 597         int ret;
 598
 599         if (shadow)
 600                 need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS;
 601
 602         regmap_write(cs42l43->regmap, need_reg, 0);
 603
 604         ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_BOOT_STATUS,
 605                                        val, (val == CS42L43_MCU_BOOT_STAGE3),
 606                                        CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US);
 607         if (ret) {
 608                 dev_err(cs42l43->dev, "Failed to move to stage 3: %d, 0x%x\n", ret, val);
 609                 return ret;
 610         }
 611
 612         return -EAGAIN;
 613 }
 614
 615 /*
 616  * This function will return the firmware to boot stage 2 from boot stage 3.
 617  * Boot stage 2 is required to apply updates to the firmware. This is achieved
 618  * by setting the firmware NEED configuration register to FW_PATCH_NEED_CFG,
 619  * setting the HAVE configuration register to 0, and soft resetting. The
 620  * firmware will see it is missing a patch configuration and will pause in boot
 621  * stage 2.
 622  *
 623  * Note: Unlike cs42l43_mcu_stage_2_3 there is no need to consider the shadow
 624  * register here as the driver will only return to boot stage 2 if the firmware
 625  * requires update which means the revision does not include shadow register
 626  * support.
 627  */
 628 static int cs42l43_mcu_stage_3_2(struct cs42l43 *cs42l43)
 629 {
 630         regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_NEED_CONFIGS,
 631                      CS42L43_FW_PATCH_NEED_CFG_MASK);
 632         regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS, 0);
 633
 634         return cs42l43_soft_reset(cs42l43);
 635 }
 636
 637 /*
 638  * Disable the firmware running on the device such that the driver can access
 639  * the registers without fear of the MCU changing them under it.
 640  */
 641 static int cs42l43_mcu_disable(struct cs42l43 *cs42l43)
 642 {
 643         unsigned int val;
 644         int ret;
 645
 646         regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG,
 647                      CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL);
 648         regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION,
 649                      CS42L43_FW_MM_CTRL_MCU_SEL_MASK);
 650         regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK);
 651         regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
 652
 653         ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
 654                                        (val & CS42L43_CONTROL_APPLIED_INT_MASK),
 655                                        CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US);
 656         if (ret) {
 657                 dev_err(cs42l43->dev, "Failed to disable firmware: %d, 0x%x\n", ret, val);
 658                 return ret;
 659         }
 660
 661         /* Soft reset to clear any register state the firmware left behind. */
 662         return cs42l43_soft_reset(cs42l43);
 663 }
 664
 665 /*
 666  * Callback to load firmware updates.
 667  */
 668 static void cs42l43_mcu_load_firmware(const struct firmware *firmware, void *context)
 669 {
 670         struct cs42l43 *cs42l43 = context;
 671         const struct cs42l43_patch_header *hdr;
 672         unsigned int loadaddr, val;
 673         int ret;
 674
 675         if (!firmware) {
 676                 dev_err(cs42l43->dev, "Failed to load firmware\n");
 677                 cs42l43->firmware_error = -ENODEV;
 678                 goto err;
 679         }
 680
 681         hdr = (const struct cs42l43_patch_header *)&firmware->data[0];
 682         loadaddr = le32_to_cpu(hdr->load_addr);
 683
 684         if (le16_to_cpu(hdr->version) != CS42L43_MCU_UPDATE_FORMAT) {
 685                 dev_err(cs42l43->dev, "Bad firmware file format: %d\n", hdr->version);
 686                 cs42l43->firmware_error = -EINVAL;
 687                 goto err_release;
 688         }
 689
 690         regmap_write(cs42l43->regmap, CS42L43_PATCH_START_ADDR, loadaddr);
 691         regmap_bulk_write(cs42l43->regmap, loadaddr + CS42L43_MCU_UPDATE_OFFSET,
 692                           &firmware->data[0], firmware->size / sizeof(u32));
 693
 694         regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_PATCH_IND_MASK);
 695         regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
 696
 697         ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
 698                                        (val & CS42L43_PATCH_APPLIED_INT_MASK),
 699                                        CS42L43_MCU_POLL_US, CS42L43_MCU_UPDATE_TIMEOUT_US);
 700         if (ret) {
 701                 dev_err(cs42l43->dev, "Failed to update firmware: %d, 0x%x\n", ret, val);
 702                 cs42l43->firmware_error = ret;
 703                 goto err_release;
 704         }
 705
 706 err_release:
 707         release_firmware(firmware);
 708 err:
 709         complete(&cs42l43->firmware_download);
 710 }
 711
 712 /*
 713  * The process of updating the firmware is split into a series of steps, at the
 714  * end of each step a soft reset of the device might be required which will
 715  * require the driver to wait for the device to re-attach on the SoundWire bus,
 716  * if that control bus is being used.
 717  */
 718 static int cs42l43_mcu_update_step(struct cs42l43 *cs42l43)
 719 {
 720         unsigned int mcu_rev, bios_rev, boot_status, secure_cfg;
 721         bool patched, shadow;
 722         int ret;
 723
 724         /* Clear any stale software interrupt bits. */
 725         regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev);
 726
 727         ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_STATUS, &boot_status);
 728         if (ret) {
 729                 dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret);
 730                 return ret;
 731         }
 732
 733         ret = regmap_read(cs42l43->regmap, CS42L43_MCU_SW_REV, &mcu_rev);
 734         if (ret) {
 735                 dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret);
 736                 return ret;
 737         }
 738
 739         bios_rev = (((mcu_rev & CS42L43_BIOS_MAJOR_REV_MASK) << 12) |
 740                     ((mcu_rev & CS42L43_BIOS_MINOR_REV_MASK) << 4) |
 741                     ((mcu_rev & CS42L43_BIOS_SUBMINOR_REV_MASK) >> 8)) >>
 742                    CS42L43_BIOS_MAJOR_REV_SHIFT;
 743         mcu_rev = ((mcu_rev & CS42L43_FW_MAJOR_REV_MASK) << 12) |
 744                   ((mcu_rev & CS42L43_FW_MINOR_REV_MASK) << 4) |
 745                   ((mcu_rev & CS42L43_FW_SUBMINOR_REV_MASK) >> 8);
 746
 747         /*
 748          * The firmware has two revision numbers bringing either of them up to a
 749          * supported version will provide the features the driver requires.
 750          */
 751         patched = mcu_rev >= CS42L43_MCU_SUPPORTED_REV ||
 752                   bios_rev >= CS42L43_MCU_SUPPORTED_BIOS_REV;
 753         /*
 754          * Later versions of the firmwware require the driver to access some
 755          * features through a set of shadow registers.
 756          */
 757         shadow = mcu_rev >= CS42L43_MCU_SHADOW_REGS_REQUIRED_REV;
 758
 759         ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_CONTROL, &secure_cfg);
 760         if (ret) {
 761                 dev_err(cs42l43->dev, "Failed to read security settings: %d\n", ret);
 762                 return ret;
 763         }
 764
 765         cs42l43->hw_lock = secure_cfg & CS42L43_LOCK_HW_STS_MASK;
 766
 767         if (!patched && cs42l43->hw_lock) {
 768                 dev_err(cs42l43->dev, "Unpatched secure device\n");
 769                 return -EPERM;
 770         }
 771
 772         dev_dbg(cs42l43->dev, "Firmware(0x%x, 0x%x) in boot stage %d\n",
 773                 mcu_rev, bios_rev, boot_status);
 774
 775         switch (boot_status) {
 776         case CS42L43_MCU_BOOT_STAGE2:
 777                 if (!patched) {
 778                         ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
 779                                                       "cs42l43.bin", cs42l43->dev,
 780                                                       GFP_KERNEL, cs42l43,
 781                                                       cs42l43_mcu_load_firmware);
 782                         if (ret) {
 783                                 dev_err(cs42l43->dev, "Failed to request firmware: %d\n", ret);
 784                                 return ret;
 785                         }
 786
 787                         wait_for_completion(&cs42l43->firmware_download);
 788
 789                         if (cs42l43->firmware_error)
 790                                 return cs42l43->firmware_error;
 791
 792                         return -EAGAIN;
 793                 } else {
 794                         return cs42l43_mcu_stage_2_3(cs42l43, shadow);
 795                 }
 796         case CS42L43_MCU_BOOT_STAGE3:
 797                 if (patched)
 798                         return cs42l43_mcu_disable(cs42l43);
 799                 else
 800                         return cs42l43_mcu_stage_3_2(cs42l43);
 801         case CS42L43_MCU_BOOT_STAGE4:
 802                 return 0;
 803         default:
 804                 dev_err(cs42l43->dev, "Invalid boot status: %d\n", boot_status);
 805                 return -EINVAL;
 806         }
 807 }
 808
 809 /*
 810  * Update the firmware running on the device.
 811  */
 812 static int cs42l43_mcu_update(struct cs42l43 *cs42l43)
 813 {
 814         int i, ret;
 815
 816         for (i = 0; i < CS42L43_MCU_UPDATE_RETRIES; i++) {
 817                 ret = cs42l43_mcu_update_step(cs42l43);
 818                 if (ret != -EAGAIN)
 819                         return ret;
 820
 821                 ret = cs42l43_wait_for_attach(cs42l43);
 822                 if (ret)
 823                         return ret;
 824         }
 825
 826         dev_err(cs42l43->dev, "Failed retrying update\n");
 827         return -ETIMEDOUT;
 828 }
 829
 830 static int cs42l43_irq_config(struct cs42l43 *cs42l43)
 831 {
 832         struct irq_data *irq_data;
 833         unsigned long irq_flags;
 834         int ret;
 835
 836         if (cs42l43->sdw)
 837                 cs42l43->irq = cs42l43->sdw->irq;
 838
 839         cs42l43->irq_chip = cs42l43_irq_chip;
 840         cs42l43->irq_chip.irq_drv_data = cs42l43;
 841
 842         irq_data = irq_get_irq_data(cs42l43->irq);
 843         if (!irq_data) {
 844                 dev_err(cs42l43->dev, "Invalid IRQ: %d\n", cs42l43->irq);
 845                 return -EINVAL;
 846         }
 847
 848         irq_flags = irqd_get_trigger_type(irq_data);
 849         switch (irq_flags) {
 850         case IRQF_TRIGGER_LOW:
 851         case IRQF_TRIGGER_HIGH:
 852         case IRQF_TRIGGER_RISING:
 853         case IRQF_TRIGGER_FALLING:
 854                 break;
 855         case IRQ_TYPE_NONE:
 856         default:
 857                 irq_flags = IRQF_TRIGGER_LOW;
 858                 break;
 859         }
 860
 861         irq_flags |= IRQF_ONESHOT;
 862
 863         ret = devm_regmap_add_irq_chip(cs42l43->dev, cs42l43->regmap,
 864                                        cs42l43->irq, irq_flags, 0,
 865                                        &cs42l43->irq_chip, &cs42l43->irq_data);
 866         if (ret) {
 867                 dev_err(cs42l43->dev, "Failed to add IRQ chip: %d\n", ret);
 868                 return ret;
 869         }
 870
 871         dev_dbg(cs42l43->dev, "Configured IRQ %d with flags 0x%lx\n",
 872                 cs42l43->irq, irq_flags);
 873
 874         return 0;
 875 }
 876
 877 static void cs42l43_boot_work(struct work_struct *work)
 878 {
 879         struct cs42l43 *cs42l43 = container_of(work, struct cs42l43, boot_work);
 880         unsigned int devid, revid, otp;
 881         int ret;
 882
 883         ret = cs42l43_wait_for_attach(cs42l43);
 884         if (ret)
 885                 goto err;
 886
 887         ret = regmap_read(cs42l43->regmap, CS42L43_DEVID, &devid);
 888         if (ret) {
 889                 dev_err(cs42l43->dev, "Failed to read devid: %d\n", ret);
 890                 goto err;
 891         }
 892
 893         switch (devid) {
 894         case CS42L43_DEVID_VAL:
 895                 break;
 896         default:
 897                 dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid);
 898                 goto err;
 899         }
 900
 901         ret = regmap_read(cs42l43->regmap, CS42L43_REVID, &revid);
 902         if (ret) {
 903                 dev_err(cs42l43->dev, "Failed to read rev: %d\n", ret);
 904                 goto err;
 905         }
 906
 907         ret = regmap_read(cs42l43->regmap, CS42L43_OTP_REVISION_ID, &otp);
 908         if (ret) {
 909                 dev_err(cs42l43->dev, "Failed to read otp rev: %d\n", ret);
 910                 goto err;
 911         }
 912
 913         dev_info(cs42l43->dev,
 914                  "devid: 0x%06x, rev: 0x%02x, otp: 0x%02x\n", devid, revid, otp);
 915
 916         ret = cs42l43_mcu_update(cs42l43);
 917         if (ret)
 918                 goto err;
 919
 920         ret = regmap_register_patch(cs42l43->regmap, cs42l43_reva_patch,
 921                                     ARRAY_SIZE(cs42l43_reva_patch));
 922         if (ret) {
 923                 dev_err(cs42l43->dev, "Failed to apply register patch: %d\n", ret);
 924                 goto err;
 925         }
 926
 927         ret = cs42l43_irq_config(cs42l43);
 928         if (ret)
 929                 goto err;
 930
 931         ret = devm_mfd_add_devices(cs42l43->dev, PLATFORM_DEVID_NONE,
 932                                    cs42l43_devs, ARRAY_SIZE(cs42l43_devs),
 933                                    NULL, 0, NULL);
 934         if (ret) {
 935                 dev_err(cs42l43->dev, "Failed to add subdevices: %d\n", ret);
 936                 goto err;
 937         }
 938
 939         pm_runtime_mark_last_busy(cs42l43->dev);
 940         pm_runtime_put_autosuspend(cs42l43->dev);
 941
 942         return;
 943
 944 err:
 945         pm_runtime_put_sync(cs42l43->dev);
 946         cs42l43_dev_remove(cs42l43);
 947 }
 948
 949 static int cs42l43_power_up(struct cs42l43 *cs42l43)
 950 {
 951         int ret;
 952
 953         ret = regulator_enable(cs42l43->vdd_p);
 954         if (ret) {
 955                 dev_err(cs42l43->dev, "Failed to enable vdd-p: %d\n", ret);
 956                 return ret;
 957         }
 958
 959         /* vdd-p must be on for 50uS before any other supply */
 960         usleep_range(CS42L43_VDDP_DELAY_US, 2 * CS42L43_VDDP_DELAY_US);
 961
 962         gpiod_set_value_cansleep(cs42l43->reset, 1);
 963
 964         ret = regulator_bulk_enable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
 965         if (ret) {
 966                 dev_err(cs42l43->dev, "Failed to enable core supplies: %d\n", ret);
 967                 goto err_reset;
 968         }
 969
 970         ret = regulator_enable(cs42l43->vdd_d);
 971         if (ret) {
 972                 dev_err(cs42l43->dev, "Failed to enable vdd-d: %d\n", ret);
 973                 goto err_core_supplies;
 974         }
 975
 976         usleep_range(CS42L43_VDDD_DELAY_US, 2 * CS42L43_VDDD_DELAY_US);
 977
 978         return 0;
 979
 980 err_core_supplies:
 981         regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
 982 err_reset:
 983         gpiod_set_value_cansleep(cs42l43->reset, 0);
 984         regulator_disable(cs42l43->vdd_p);
 985
 986         return ret;
 987 }
 988
 989 static int cs42l43_power_down(struct cs42l43 *cs42l43)
 990 {
 991         int ret;
 992
 993         ret = regulator_disable(cs42l43->vdd_d);
 994         if (ret) {
 995                 dev_err(cs42l43->dev, "Failed to disable vdd-d: %d\n", ret);
 996                 return ret;
 997         }
 998
 999         ret = regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
1000         if (ret) {
1001                 dev_err(cs42l43->dev, "Failed to disable core supplies: %d\n", ret);
1002                 return ret;
1003         }
1004
1005         gpiod_set_value_cansleep(cs42l43->reset, 0);
1006
1007         ret = regulator_disable(cs42l43->vdd_p);
1008         if (ret) {
1009                 dev_err(cs42l43->dev, "Failed to disable vdd-p: %d\n", ret);
1010                 return ret;
1011         }
1012
1013         return 0;
1014 }
1015
1016 int cs42l43_dev_probe(struct cs42l43 *cs42l43)
1017 {
1018         int i, ret;
1019
1020         dev_set_drvdata(cs42l43->dev, cs42l43);
1021
1022         mutex_init(&cs42l43->pll_lock);
1023         init_completion(&cs42l43->device_attach);
1024         init_completion(&cs42l43->device_detach);
1025         init_completion(&cs42l43->firmware_download);
1026         INIT_WORK(&cs42l43->boot_work, cs42l43_boot_work);
1027
1028         regcache_cache_only(cs42l43->regmap, true);
1029
1030         cs42l43->reset = devm_gpiod_get_optional(cs42l43->dev, "reset", GPIOD_OUT_LOW);
1031         if (IS_ERR(cs42l43->reset))
1032                 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->reset),
1033                                      "Failed to get reset\n");
1034
1035         cs42l43->vdd_p = devm_regulator_get(cs42l43->dev, "vdd-p");
1036         if (IS_ERR(cs42l43->vdd_p))
1037                 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_p),
1038                                      "Failed to get vdd-p\n");
1039
1040         cs42l43->vdd_d = devm_regulator_get(cs42l43->dev, "vdd-d");
1041         if (IS_ERR(cs42l43->vdd_d))
1042                 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_d),
1043                                      "Failed to get vdd-d\n");
1044
1045         BUILD_BUG_ON(ARRAY_SIZE(cs42l43_core_supplies) != CS42L43_N_SUPPLIES);
1046
1047         for (i = 0; i < CS42L43_N_SUPPLIES; i++)
1048                 cs42l43->core_supplies[i].supply = cs42l43_core_supplies[i];
1049
1050         ret = devm_regulator_bulk_get(cs42l43->dev, CS42L43_N_SUPPLIES,
1051                                       cs42l43->core_supplies);
1052         if (ret)
1053                 return dev_err_probe(cs42l43->dev, ret,
1054                                      "Failed to get core supplies\n");
1055
1056         ret = cs42l43_power_up(cs42l43);
1057         if (ret)
1058                 return ret;
1059
1060         pm_runtime_set_autosuspend_delay(cs42l43->dev, CS42L43_AUTOSUSPEND_TIME_MS);
1061         pm_runtime_use_autosuspend(cs42l43->dev);
1062         pm_runtime_set_active(cs42l43->dev);
1063         /*
1064          * The device is already powered up, but keep it from suspending until
1065          * the boot work runs.
1066          */
1067         pm_runtime_get_noresume(cs42l43->dev);
1068         ret = devm_pm_runtime_enable(cs42l43->dev);
1069         if (ret)
1070                 return ret;
1071
1072         queue_work(system_long_wq, &cs42l43->boot_work);
1073
1074         return 0;
1075 }
1076 EXPORT_SYMBOL_NS_GPL(cs42l43_dev_probe, MFD_CS42L43);
1077
1078 void cs42l43_dev_remove(struct cs42l43 *cs42l43)
1079 {
1080         cs42l43_power_down(cs42l43);
1081 }
1082 EXPORT_SYMBOL_NS_GPL(cs42l43_dev_remove, MFD_CS42L43);
1083
1084 static int cs42l43_suspend(struct device *dev)
1085 {
1086         struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1087         int ret;
1088
1089         /*
1090          * Don't care about being resumed here, but the driver does want
1091          * force_resume to always trigger an actual resume, so that register
1092          * state for the MCU/GPIOs is returned as soon as possible after system
1093          * resume. force_resume will resume if the reference count is resumed on
1094          * suspend hence the get_noresume.
1095          */
1096         pm_runtime_get_noresume(dev);
1097
1098         ret = pm_runtime_force_suspend(dev);
1099         if (ret) {
1100                 dev_err(cs42l43->dev, "Failed to force suspend: %d\n", ret);
1101                 pm_runtime_put_noidle(dev);
1102                 return ret;
1103         }
1104
1105         pm_runtime_put_noidle(dev);
1106
1107         ret = cs42l43_power_down(cs42l43);
1108         if (ret)
1109                 return ret;
1110
1111         return 0;
1112 }
1113
1114 static int cs42l43_resume(struct device *dev)
1115 {
1116         struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1117         int ret;
1118
1119         ret = cs42l43_power_up(cs42l43);
1120         if (ret)
1121                 return ret;
1122
1123         ret = pm_runtime_force_resume(dev);
1124         if (ret) {
1125                 dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret);
1126                 return ret;
1127         }
1128
1129         return 0;
1130 }
1131
1132 static int cs42l43_runtime_suspend(struct device *dev)
1133 {
1134         struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1135
1136         /*
1137          * Whilst the driver doesn't power the chip down here, going into runtime
1138          * suspend lets the SoundWire bus power down, which means the driver
1139          * can't communicate with the device any more.
1140          */
1141         regcache_cache_only(cs42l43->regmap, true);
1142
1143         return 0;
1144 }
1145
1146 static int cs42l43_runtime_resume(struct device *dev)
1147 {
1148         struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1149         unsigned int reset_canary;
1150         int ret;
1151
1152         ret = cs42l43_wait_for_attach(cs42l43);
1153         if (ret)
1154                 return ret;
1155
1156         ret = regmap_read(cs42l43->regmap, CS42L43_RELID, &reset_canary);
1157         if (ret) {
1158                 dev_err(cs42l43->dev, "Failed to check reset canary: %d\n", ret);
1159                 goto err;
1160         }
1161
1162         if (!reset_canary) {
1163                 /*
1164                  * If the canary has cleared the chip has reset, re-handle the
1165                  * MCU and mark the cache as dirty to indicate the chip reset.
1166                  */
1167                 ret = cs42l43_mcu_update(cs42l43);
1168                 if (ret)
1169                         goto err;
1170
1171                 regcache_mark_dirty(cs42l43->regmap);
1172         }
1173
1174         ret = regcache_sync(cs42l43->regmap);
1175         if (ret) {
1176                 dev_err(cs42l43->dev, "Failed to restore register cache: %d\n", ret);
1177                 goto err;
1178         }
1179
1180         return 0;
1181
1182 err:
1183         regcache_cache_only(cs42l43->regmap, true);
1184
1185         return ret;
1186 }
1187
1188 EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = {
1189         SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume)
1190         RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL)
1191 };
1192
1193 MODULE_DESCRIPTION("CS42L43 Core Driver");
1194 MODULE_AUTHOR("Charles Keepax <[email protected]>");
1195 MODULE_LICENSE("GPL");
1196 MODULE_FIRMWARE("cs42l43.bin");