drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/io.h>
  34 #include <linux/list.h>
  35 #include <linux/slab.h>
  36
  37 #include <drm/drm_cache.h>
  38 #include <drm/drm_prime.h>
  39 #include <drm/radeon_drm.h>
  40
  41 #include "radeon.h"
  42 #include "radeon_trace.h"
  43 #include "radeon_ttm.h"
  44
  45 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  46
  47 /*
  48  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  49  * function are calling it.
  50  */
  51
  52 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  53 {
  54         struct radeon_bo *bo;
  55
  56         bo = container_of(tbo, struct radeon_bo, tbo);
  57
  58         mutex_lock(&bo->rdev->gem.mutex);
  59         list_del_init(&bo->list);
  60         mutex_unlock(&bo->rdev->gem.mutex);
  61         radeon_bo_clear_surface_reg(bo);
  62         WARN_ON_ONCE(!list_empty(&bo->va));
  63         if (bo->tbo.base.import_attach)
  64                 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
  65         drm_gem_object_release(&bo->tbo.base);
  66         kfree(bo);
  67 }
  68
  69 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  70 {
  71         if (bo->destroy == &radeon_ttm_bo_destroy)
  72                 return true;
  73         return false;
  74 }
  75
  76 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  77 {
  78         u32 c = 0, i;
  79
  80         rbo->placement.placement = rbo->placements;
  81         if (domain & RADEON_GEM_DOMAIN_VRAM) {
  82                 /* Try placing BOs which don't need CPU access outside of the
  83                  * CPU accessible part of VRAM
  84                  */
  85                 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
  86                     rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
  87                         rbo->placements[c].fpfn =
  88                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
  89                         rbo->placements[c].mem_type = TTM_PL_VRAM;
  90                         rbo->placements[c++].flags = 0;
  91                 }
  92
  93                 rbo->placements[c].fpfn = 0;
  94                 rbo->placements[c].mem_type = TTM_PL_VRAM;
  95                 rbo->placements[c++].flags = 0;
  96         }
  97
  98         if (domain & RADEON_GEM_DOMAIN_GTT) {
  99                 rbo->placements[c].fpfn = 0;
 100                 rbo->placements[c].mem_type = TTM_PL_TT;
 101                 rbo->placements[c++].flags = 0;
 102         }
 103
 104         if (domain & RADEON_GEM_DOMAIN_CPU) {
 105                 rbo->placements[c].fpfn = 0;
 106                 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 107                 rbo->placements[c++].flags = 0;
 108         }
 109         if (!c) {
 110                 rbo->placements[c].fpfn = 0;
 111                 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 112                 rbo->placements[c++].flags = 0;
 113         }
 114
 115         rbo->placement.num_placement = c;
 116
 117         for (i = 0; i < c; ++i) {
 118                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 119                     (rbo->placements[i].mem_type == TTM_PL_VRAM) &&
 120                     !rbo->placements[i].fpfn)
 121                         rbo->placements[i].lpfn =
 122                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 123                 else
 124                         rbo->placements[i].lpfn = 0;
 125         }
 126 }
 127
 128 int radeon_bo_create(struct radeon_device *rdev,
 129                      unsigned long size, int byte_align, bool kernel,
 130                      u32 domain, u32 flags, struct sg_table *sg,
 131                      struct dma_resv *resv,
 132                      struct radeon_bo **bo_ptr)
 133 {
 134         struct radeon_bo *bo;
 135         enum ttm_bo_type type;
 136         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 137         int r;
 138
 139         size = ALIGN(size, PAGE_SIZE);
 140
 141         if (kernel) {
 142                 type = ttm_bo_type_kernel;
 143         } else if (sg) {
 144                 type = ttm_bo_type_sg;
 145         } else {
 146                 type = ttm_bo_type_device;
 147         }
 148         *bo_ptr = NULL;
 149
 150         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 151         if (bo == NULL)
 152                 return -ENOMEM;
 153         drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size);
 154         bo->rdev = rdev;
 155         bo->surface_reg = -1;
 156         INIT_LIST_HEAD(&bo->list);
 157         INIT_LIST_HEAD(&bo->va);
 158         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 159                                        RADEON_GEM_DOMAIN_GTT |
 160                                        RADEON_GEM_DOMAIN_CPU);
 161
 162         bo->flags = flags;
 163         /* PCI GART is always snooped */
 164         if (!(rdev->flags & RADEON_IS_PCIE))
 165                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 166
 167         /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
 168          * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
 169          */
 170         if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
 171                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 172
 173 #ifdef CONFIG_X86_32
 174         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 175          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 176          */
 177         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 178 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 179         /* Don't try to enable write-combining when it can't work, or things
 180          * may be slow
 181          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 182          */
 183 #ifndef CONFIG_COMPILE_TEST
 184 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 185          thanks to write-combining
 186 #endif
 187
 188         if (bo->flags & RADEON_GEM_GTT_WC)
 189                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 190                               "better performance thanks to write-combining\n");
 191         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 192 #else
 193         /* For architectures that don't support WC memory,
 194          * mask out the WC flag from the BO
 195          */
 196         if (!drm_arch_can_wc_memory())
 197                 bo->flags &= ~RADEON_GEM_GTT_WC;
 198 #endif
 199
 200         radeon_ttm_placement_from_domain(bo, domain);
 201         /* Kernel allocation are uninterruptible */
 202         down_read(&rdev->pm.mclk_lock);
 203         r = ttm_bo_init_validate(&rdev->mman.bdev, &bo->tbo, type,
 204                                  &bo->placement, page_align, !kernel, sg, resv,
 205                                  &radeon_ttm_bo_destroy);
 206         up_read(&rdev->pm.mclk_lock);
 207         if (unlikely(r != 0)) {
 208                 return r;
 209         }
 210         *bo_ptr = bo;
 211
 212         trace_radeon_bo_create(bo);
 213
 214         return 0;
 215 }
 216
 217 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 218 {
 219         bool is_iomem;
 220         long r;
 221
 222         r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,
 223                                   false, MAX_SCHEDULE_TIMEOUT);
 224         if (r < 0)
 225                 return r;
 226
 227         if (bo->kptr) {
 228                 if (ptr) {
 229                         *ptr = bo->kptr;
 230                 }
 231                 return 0;
 232         }
 233         r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap);
 234         if (r) {
 235                 return r;
 236         }
 237         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 238         if (ptr) {
 239                 *ptr = bo->kptr;
 240         }
 241         radeon_bo_check_tiling(bo, 0, 0);
 242         return 0;
 243 }
 244
 245 void radeon_bo_kunmap(struct radeon_bo *bo)
 246 {
 247         if (bo->kptr == NULL)
 248                 return;
 249         bo->kptr = NULL;
 250         radeon_bo_check_tiling(bo, 0, 0);
 251         ttm_bo_kunmap(&bo->kmap);
 252 }
 253
 254 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
 255 {
 256         if (bo == NULL)
 257                 return NULL;
 258
 259         ttm_bo_get(&bo->tbo);
 260         return bo;
 261 }
 262
 263 void radeon_bo_unref(struct radeon_bo **bo)
 264 {
 265         struct ttm_buffer_object *tbo;
 266
 267         if ((*bo) == NULL)
 268                 return;
 269         tbo = &((*bo)->tbo);
 270         ttm_bo_put(tbo);
 271         *bo = NULL;
 272 }
 273
 274 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 275                              u64 *gpu_addr)
 276 {
 277         struct ttm_operation_ctx ctx = { false, false };
 278         int r, i;
 279
 280         if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm))
 281                 return -EPERM;
 282
 283         if (bo->tbo.pin_count) {
 284                 ttm_bo_pin(&bo->tbo);
 285                 if (gpu_addr)
 286                         *gpu_addr = radeon_bo_gpu_offset(bo);
 287
 288                 if (max_offset != 0) {
 289                         u64 domain_start;
 290
 291                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 292                                 domain_start = bo->rdev->mc.vram_start;
 293                         else
 294                                 domain_start = bo->rdev->mc.gtt_start;
 295                         WARN_ON_ONCE(max_offset <
 296                                      (radeon_bo_gpu_offset(bo) - domain_start));
 297                 }
 298
 299                 return 0;
 300         }
 301         if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) {
 302                 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */
 303                 return -EINVAL;
 304         }
 305
 306         radeon_ttm_placement_from_domain(bo, domain);
 307         for (i = 0; i < bo->placement.num_placement; i++) {
 308                 /* force to pin into visible video ram */
 309                 if ((bo->placements[i].mem_type == TTM_PL_VRAM) &&
 310                     !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 311                     (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 312                         bo->placements[i].lpfn =
 313                                 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 314                 else
 315                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 316         }
 317
 318         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 319         if (likely(r == 0)) {
 320                 ttm_bo_pin(&bo->tbo);
 321                 if (gpu_addr != NULL)
 322                         *gpu_addr = radeon_bo_gpu_offset(bo);
 323                 if (domain == RADEON_GEM_DOMAIN_VRAM)
 324                         bo->rdev->vram_pin_size += radeon_bo_size(bo);
 325                 else
 326                         bo->rdev->gart_pin_size += radeon_bo_size(bo);
 327         } else {
 328                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 329         }
 330         return r;
 331 }
 332
 333 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 334 {
 335         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 336 }
 337
 338 void radeon_bo_unpin(struct radeon_bo *bo)
 339 {
 340         ttm_bo_unpin(&bo->tbo);
 341         if (!bo->tbo.pin_count) {
 342                 if (bo->tbo.resource->mem_type == TTM_PL_VRAM)
 343                         bo->rdev->vram_pin_size -= radeon_bo_size(bo);
 344                 else
 345                         bo->rdev->gart_pin_size -= radeon_bo_size(bo);
 346         }
 347 }
 348
 349 int radeon_bo_evict_vram(struct radeon_device *rdev)
 350 {
 351         struct ttm_device *bdev = &rdev->mman.bdev;
 352         struct ttm_resource_manager *man;
 353
 354         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 355 #ifndef CONFIG_HIBERNATION
 356         if (rdev->flags & RADEON_IS_IGP) {
 357                 if (rdev->mc.igp_sideport_enabled == false)
 358                         /* Useless to evict on IGP chips */
 359                         return 0;
 360         }
 361 #endif
 362         man = ttm_manager_type(bdev, TTM_PL_VRAM);
 363         if (!man)
 364                 return 0;
 365         return ttm_resource_manager_evict_all(bdev, man);
 366 }
 367
 368 void radeon_bo_force_delete(struct radeon_device *rdev)
 369 {
 370         struct radeon_bo *bo, *n;
 371
 372         if (list_empty(&rdev->gem.objects)) {
 373                 return;
 374         }
 375         dev_err(rdev->dev, "Userspace still has active objects !\n");
 376         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 377                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 378                         &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size,
 379                         *((unsigned long *)&bo->tbo.base.refcount));
 380                 mutex_lock(&bo->rdev->gem.mutex);
 381                 list_del_init(&bo->list);
 382                 mutex_unlock(&bo->rdev->gem.mutex);
 383                 /* this should unref the ttm bo */
 384                 drm_gem_object_put(&bo->tbo.base);
 385         }
 386 }
 387
 388 int radeon_bo_init(struct radeon_device *rdev)
 389 {
 390         /* reserve PAT memory space to WC for VRAM */
 391         arch_io_reserve_memtype_wc(rdev->mc.aper_base,
 392                                    rdev->mc.aper_size);
 393
 394         /* Add an MTRR for the VRAM */
 395         if (!rdev->fastfb_working) {
 396                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 397                                                       rdev->mc.aper_size);
 398         }
 399         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 400                 rdev->mc.mc_vram_size >> 20,
 401                 (unsigned long long)rdev->mc.aper_size >> 20);
 402         DRM_INFO("RAM width %dbits %cDR\n",
 403                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 404         return radeon_ttm_init(rdev);
 405 }
 406
 407 void radeon_bo_fini(struct radeon_device *rdev)
 408 {
 409         radeon_ttm_fini(rdev);
 410         arch_phys_wc_del(rdev->mc.vram_mtrr);
 411         arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size);
 412 }
 413
 414 /* Returns how many bytes TTM can move per IB.
 415  */
 416 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 417 {
 418         u64 real_vram_size = rdev->mc.real_vram_size;
 419         struct ttm_resource_manager *man =
 420                 ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
 421         u64 vram_usage = ttm_resource_manager_usage(man);
 422
 423         /* This function is based on the current VRAM usage.
 424          *
 425          * - If all of VRAM is free, allow relocating the number of bytes that
 426          *   is equal to 1/4 of the size of VRAM for this IB.
 427
 428          * - If more than one half of VRAM is occupied, only allow relocating
 429          *   1 MB of data for this IB.
 430          *
 431          * - From 0 to one half of used VRAM, the threshold decreases
 432          *   linearly.
 433          *         __________________
 434          * 1/4 of -|\               |
 435          * VRAM    | \              |
 436          *         |  \             |
 437          *         |   \            |
 438          *         |    \           |
 439          *         |     \          |
 440          *         |      \         |
 441          *         |       \________|1 MB
 442          *         |----------------|
 443          *    VRAM 0 %             100 %
 444          *         used            used
 445          *
 446          * Note: It's a threshold, not a limit. The threshold must be crossed
 447          * for buffer relocations to stop, so any buffer of an arbitrary size
 448          * can be moved as long as the threshold isn't crossed before
 449          * the relocation takes place. We don't want to disable buffer
 450          * relocations completely.
 451          *
 452          * The idea is that buffers should be placed in VRAM at creation time
 453          * and TTM should only do a minimum number of relocations during
 454          * command submission. In practice, you need to submit at least
 455          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 456          *
 457          * Also, things can get pretty crazy under memory pressure and actual
 458          * VRAM usage can change a lot, so playing safe even at 50% does
 459          * consistently increase performance.
 460          */
 461
 462         u64 half_vram = real_vram_size >> 1;
 463         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 464         u64 bytes_moved_threshold = half_free_vram >> 1;
 465         return max(bytes_moved_threshold, 1024*1024ull);
 466 }
 467
 468 int radeon_bo_list_validate(struct radeon_device *rdev,
 469                             struct ww_acquire_ctx *ticket,
 470                             struct list_head *head, int ring)
 471 {
 472         struct ttm_operation_ctx ctx = { true, false };
 473         struct radeon_bo_list *lobj;
 474         struct list_head duplicates;
 475         int r;
 476         u64 bytes_moved = 0, initial_bytes_moved;
 477         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 478
 479         INIT_LIST_HEAD(&duplicates);
 480         r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
 481         if (unlikely(r != 0)) {
 482                 return r;
 483         }
 484
 485         list_for_each_entry(lobj, head, tv.head) {
 486                 struct radeon_bo *bo = lobj->robj;
 487                 if (!bo->tbo.pin_count) {
 488                         u32 domain = lobj->preferred_domains;
 489                         u32 allowed = lobj->allowed_domains;
 490                         u32 current_domain =
 491                                 radeon_mem_type_to_domain(bo->tbo.resource->mem_type);
 492
 493                         /* Check if this buffer will be moved and don't move it
 494                          * if we have moved too many buffers for this IB already.
 495                          *
 496                          * Note that this allows moving at least one buffer of
 497                          * any size, because it doesn't take the current "bo"
 498                          * into account. We don't want to disallow buffer moves
 499                          * completely.
 500                          */
 501                         if ((allowed & current_domain) != 0 &&
 502                             (domain & current_domain) == 0 && /* will be moved */
 503                             bytes_moved > bytes_moved_threshold) {
 504                                 /* don't move it */
 505                                 domain = current_domain;
 506                         }
 507
 508                 retry:
 509                         radeon_ttm_placement_from_domain(bo, domain);
 510                         if (ring == R600_RING_TYPE_UVD_INDEX)
 511                                 radeon_uvd_force_into_uvd_segment(bo, allowed);
 512
 513                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 514                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 515                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 516                                        initial_bytes_moved;
 517
 518                         if (unlikely(r)) {
 519                                 if (r != -ERESTARTSYS &&
 520                                     domain != lobj->allowed_domains) {
 521                                         domain = lobj->allowed_domains;
 522                                         goto retry;
 523                                 }
 524                                 ttm_eu_backoff_reservation(ticket, head);
 525                                 return r;
 526                         }
 527                 }
 528                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 529                 lobj->tiling_flags = bo->tiling_flags;
 530         }
 531
 532         list_for_each_entry(lobj, &duplicates, tv.head) {
 533                 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
 534                 lobj->tiling_flags = lobj->robj->tiling_flags;
 535         }
 536
 537         return 0;
 538 }
 539
 540 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 541 {
 542         struct radeon_device *rdev = bo->rdev;
 543         struct radeon_surface_reg *reg;
 544         struct radeon_bo *old_object;
 545         int steal;
 546         int i;
 547
 548         dma_resv_assert_held(bo->tbo.base.resv);
 549
 550         if (!bo->tiling_flags)
 551                 return 0;
 552
 553         if (bo->surface_reg >= 0) {
 554                 i = bo->surface_reg;
 555                 goto out;
 556         }
 557
 558         steal = -1;
 559         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 560
 561                 reg = &rdev->surface_regs[i];
 562                 if (!reg->bo)
 563                         break;
 564
 565                 old_object = reg->bo;
 566                 if (old_object->tbo.pin_count == 0)
 567                         steal = i;
 568         }
 569
 570         /* if we are all out */
 571         if (i == RADEON_GEM_MAX_SURFACES) {
 572                 if (steal == -1)
 573                         return -ENOMEM;
 574                 /* find someone with a surface reg and nuke their BO */
 575                 reg = &rdev->surface_regs[steal];
 576                 old_object = reg->bo;
 577                 /* blow away the mapping */
 578                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 579                 ttm_bo_unmap_virtual(&old_object->tbo);
 580                 old_object->surface_reg = -1;
 581                 i = steal;
 582         }
 583
 584         bo->surface_reg = i;
 585         reg->bo = bo;
 586
 587 out:
 588         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 589                                bo->tbo.resource->start << PAGE_SHIFT,
 590                                bo->tbo.base.size);
 591         return 0;
 592 }
 593
 594 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 595 {
 596         struct radeon_device *rdev = bo->rdev;
 597         struct radeon_surface_reg *reg;
 598
 599         if (bo->surface_reg == -1)
 600                 return;
 601
 602         reg = &rdev->surface_regs[bo->surface_reg];
 603         radeon_clear_surface_reg(rdev, bo->surface_reg);
 604
 605         reg->bo = NULL;
 606         bo->surface_reg = -1;
 607 }
 608
 609 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 610                                 uint32_t tiling_flags, uint32_t pitch)
 611 {
 612         struct radeon_device *rdev = bo->rdev;
 613         int r;
 614
 615         if (rdev->family >= CHIP_CEDAR) {
 616                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 617
 618                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 619                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 620                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 621                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 622                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 623                 switch (bankw) {
 624                 case 0:
 625                 case 1:
 626                 case 2:
 627                 case 4:
 628                 case 8:
 629                         break;
 630                 default:
 631                         return -EINVAL;
 632                 }
 633                 switch (bankh) {
 634                 case 0:
 635                 case 1:
 636                 case 2:
 637                 case 4:
 638                 case 8:
 639                         break;
 640                 default:
 641                         return -EINVAL;
 642                 }
 643                 switch (mtaspect) {
 644                 case 0:
 645                 case 1:
 646                 case 2:
 647                 case 4:
 648                 case 8:
 649                         break;
 650                 default:
 651                         return -EINVAL;
 652                 }
 653                 if (tilesplit > 6) {
 654                         return -EINVAL;
 655                 }
 656                 if (stilesplit > 6) {
 657                         return -EINVAL;
 658                 }
 659         }
 660         r = radeon_bo_reserve(bo, false);
 661         if (unlikely(r != 0))
 662                 return r;
 663         bo->tiling_flags = tiling_flags;
 664         bo->pitch = pitch;
 665         radeon_bo_unreserve(bo);
 666         return 0;
 667 }
 668
 669 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 670                                 uint32_t *tiling_flags,
 671                                 uint32_t *pitch)
 672 {
 673         dma_resv_assert_held(bo->tbo.base.resv);
 674
 675         if (tiling_flags)
 676                 *tiling_flags = bo->tiling_flags;
 677         if (pitch)
 678                 *pitch = bo->pitch;
 679 }
 680
 681 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 682                                 bool force_drop)
 683 {
 684         if (!force_drop)
 685                 dma_resv_assert_held(bo->tbo.base.resv);
 686
 687         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 688                 return 0;
 689
 690         if (force_drop) {
 691                 radeon_bo_clear_surface_reg(bo);
 692                 return 0;
 693         }
 694
 695         if (bo->tbo.resource->mem_type != TTM_PL_VRAM) {
 696                 if (!has_moved)
 697                         return 0;
 698
 699                 if (bo->surface_reg >= 0)
 700                         radeon_bo_clear_surface_reg(bo);
 701                 return 0;
 702         }
 703
 704         if ((bo->surface_reg >= 0) && !has_moved)
 705                 return 0;
 706
 707         return radeon_bo_get_surface_reg(bo);
 708 }
 709
 710 void radeon_bo_move_notify(struct ttm_buffer_object *bo)
 711 {
 712         struct radeon_bo *rbo;
 713
 714         if (!radeon_ttm_bo_is_radeon_bo(bo))
 715                 return;
 716
 717         rbo = container_of(bo, struct radeon_bo, tbo);
 718         radeon_bo_check_tiling(rbo, 0, 1);
 719         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 720 }
 721
 722 vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 723 {
 724         struct ttm_operation_ctx ctx = { false, false };
 725         struct radeon_device *rdev;
 726         struct radeon_bo *rbo;
 727         unsigned long offset, size, lpfn;
 728         int i, r;
 729
 730         if (!radeon_ttm_bo_is_radeon_bo(bo))
 731                 return 0;
 732         rbo = container_of(bo, struct radeon_bo, tbo);
 733         radeon_bo_check_tiling(rbo, 0, 0);
 734         rdev = rbo->rdev;
 735         if (bo->resource->mem_type != TTM_PL_VRAM)
 736                 return 0;
 737
 738         size = bo->resource->size;
 739         offset = bo->resource->start << PAGE_SHIFT;
 740         if ((offset + size) <= rdev->mc.visible_vram_size)
 741                 return 0;
 742
 743         /* Can't move a pinned BO to visible VRAM */
 744         if (rbo->tbo.pin_count > 0)
 745                 return VM_FAULT_SIGBUS;
 746
 747         /* hurrah the memory is not visible ! */
 748         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 749         lpfn =  rdev->mc.visible_vram_size >> PAGE_SHIFT;
 750         for (i = 0; i < rbo->placement.num_placement; i++) {
 751                 /* Force into visible VRAM */
 752                 if ((rbo->placements[i].mem_type == TTM_PL_VRAM) &&
 753                     (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
 754                         rbo->placements[i].lpfn = lpfn;
 755         }
 756         r = ttm_bo_validate(bo, &rbo->placement, &ctx);
 757         if (unlikely(r == -ENOMEM)) {
 758                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 759                 r = ttm_bo_validate(bo, &rbo->placement, &ctx);
 760         } else if (likely(!r)) {
 761                 offset = bo->resource->start << PAGE_SHIFT;
 762                 /* this should never happen */
 763                 if ((offset + size) > rdev->mc.visible_vram_size)
 764                         return VM_FAULT_SIGBUS;
 765         }
 766
 767         if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
 768                 return VM_FAULT_NOPAGE;
 769         else if (unlikely(r))
 770                 return VM_FAULT_SIGBUS;
 771
 772         ttm_bo_move_to_lru_tail_unlocked(bo);
 773         return 0;
 774 }
 775
 776 /**
 777  * radeon_bo_fence - add fence to buffer object
 778  *
 779  * @bo: buffer object in question
 780  * @fence: fence to add
 781  * @shared: true if fence should be added shared
 782  *
 783  */
 784 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
 785                      bool shared)
 786 {
 787         struct dma_resv *resv = bo->tbo.base.resv;
 788         int r;
 789
 790         r = dma_resv_reserve_fences(resv, 1);
 791         if (r) {
 792                 /* As last resort on OOM we block for the fence */
 793                 dma_fence_wait(&fence->base, false);
 794                 return;
 795         }
 796
 797         dma_resv_add_fence(resv, &fence->base, shared ?
 798                            DMA_RESV_USAGE_READ : DMA_RESV_USAGE_WRITE);
 799 }