drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/firmware.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/slab.h>
  35
  36 #include <drm/drm_device.h>
  37 #include <drm/drm_file.h>
  38 #include <drm/drm_fourcc.h>
  39 #include <drm/drm_framebuffer.h>
  40 #include <drm/drm_vblank.h>
  41 #include <drm/radeon_drm.h>
  42
  43 #include "atom.h"
  44 #include "r100_reg_safe.h"
  45 #include "r100d.h"
  46 #include "radeon.h"
  47 #include "radeon_asic.h"
  48 #include "radeon_reg.h"
  49 #include "rn50_reg_safe.h"
  50 #include "rs100d.h"
  51 #include "rv200d.h"
  52 #include "rv250d.h"
  53
  54 /* Firmware Names */
  55 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  56 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  57 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  58 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  59 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  60 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  61 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  62
  63 MODULE_FIRMWARE(FIRMWARE_R100);
  64 MODULE_FIRMWARE(FIRMWARE_R200);
  65 MODULE_FIRMWARE(FIRMWARE_R300);
  66 MODULE_FIRMWARE(FIRMWARE_R420);
  67 MODULE_FIRMWARE(FIRMWARE_RS690);
  68 MODULE_FIRMWARE(FIRMWARE_RS600);
  69 MODULE_FIRMWARE(FIRMWARE_R520);
  70
  71 #include "r100_track.h"
  72
  73 /* This files gather functions specifics to:
  74  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  75  * and others in some cases.
  76  */
  77
  78 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
  79 {
  80         if (crtc == 0) {
  81                 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  82                         return true;
  83                 else
  84                         return false;
  85         } else {
  86                 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
  87                         return true;
  88                 else
  89                         return false;
  90         }
  91 }
  92
  93 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
  94 {
  95         u32 vline1, vline2;
  96
  97         if (crtc == 0) {
  98                 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  99                 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
 100         } else {
 101                 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
 102                 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
 103         }
 104         if (vline1 != vline2)
 105                 return true;
 106         else
 107                 return false;
 108 }
 109
 110 /**
 111  * r100_wait_for_vblank - vblank wait asic callback.
 112  *
 113  * @rdev: radeon_device pointer
 114  * @crtc: crtc to wait for vblank on
 115  *
 116  * Wait for vblank on the requested crtc (r1xx-r4xx).
 117  */
 118 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
 119 {
 120         unsigned i = 0;
 121
 122         if (crtc >= rdev->num_crtc)
 123                 return;
 124
 125         if (crtc == 0) {
 126                 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
 127                         return;
 128         } else {
 129                 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
 130                         return;
 131         }
 132
 133         /* depending on when we hit vblank, we may be close to active; if so,
 134          * wait for another frame.
 135          */
 136         while (r100_is_in_vblank(rdev, crtc)) {
 137                 if (i++ % 100 == 0) {
 138                         if (!r100_is_counter_moving(rdev, crtc))
 139                                 break;
 140                 }
 141         }
 142
 143         while (!r100_is_in_vblank(rdev, crtc)) {
 144                 if (i++ % 100 == 0) {
 145                         if (!r100_is_counter_moving(rdev, crtc))
 146                                 break;
 147                 }
 148         }
 149 }
 150
 151 /**
 152  * r100_page_flip - pageflip callback.
 153  *
 154  * @rdev: radeon_device pointer
 155  * @crtc_id: crtc to cleanup pageflip on
 156  * @crtc_base: new address of the crtc (GPU MC address)
 157  * @async: asynchronous flip
 158  *
 159  * Does the actual pageflip (r1xx-r4xx).
 160  * During vblank we take the crtc lock and wait for the update_pending
 161  * bit to go high, when it does, we release the lock, and allow the
 162  * double buffered update to take place.
 163  */
 164 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
 165 {
 166         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 167         uint32_t crtc_pitch, pitch_pixels;
 168         struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
 169         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 170         int i;
 171
 172         /* Lock the graphics update lock */
 173         /* update the scanout addresses */
 174         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 175
 176         /* update pitch */
 177         pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
 178         crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8,
 179                                   fb->format->cpp[0] * 8 * 8);
 180         crtc_pitch |= crtc_pitch << 16;
 181         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 182
 183         /* Wait for update_pending to go high. */
 184         for (i = 0; i < rdev->usec_timeout; i++) {
 185                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 186                         break;
 187                 udelay(1);
 188         }
 189         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 190
 191         /* Unlock the lock, so double-buffering can take place inside vblank */
 192         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 193         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 194
 195 }
 196
 197 /**
 198  * r100_page_flip_pending - check if page flip is still pending
 199  *
 200  * @rdev: radeon_device pointer
 201  * @crtc_id: crtc to check
 202  *
 203  * Check if the last pagefilp is still pending (r1xx-r4xx).
 204  * Returns the current update pending status.
 205  */
 206 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
 207 {
 208         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 209
 210         /* Return current update_pending status: */
 211         return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
 212                 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
 213 }
 214
 215 /**
 216  * r100_pm_get_dynpm_state - look up dynpm power state callback.
 217  *
 218  * @rdev: radeon_device pointer
 219  *
 220  * Look up the optimal power state based on the
 221  * current state of the GPU (r1xx-r5xx).
 222  * Used for dynpm only.
 223  */
 224 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 225 {
 226         int i;
 227         rdev->pm.dynpm_can_upclock = true;
 228         rdev->pm.dynpm_can_downclock = true;
 229
 230         switch (rdev->pm.dynpm_planned_action) {
 231         case DYNPM_ACTION_MINIMUM:
 232                 rdev->pm.requested_power_state_index = 0;
 233                 rdev->pm.dynpm_can_downclock = false;
 234                 break;
 235         case DYNPM_ACTION_DOWNCLOCK:
 236                 if (rdev->pm.current_power_state_index == 0) {
 237                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 238                         rdev->pm.dynpm_can_downclock = false;
 239                 } else {
 240                         if (rdev->pm.active_crtc_count > 1) {
 241                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 242                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 243                                                 continue;
 244                                         else if (i >= rdev->pm.current_power_state_index) {
 245                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 246                                                 break;
 247                                         } else {
 248                                                 rdev->pm.requested_power_state_index = i;
 249                                                 break;
 250                                         }
 251                                 }
 252                         } else
 253                                 rdev->pm.requested_power_state_index =
 254                                         rdev->pm.current_power_state_index - 1;
 255                 }
 256                 /* don't use the power state if crtcs are active and no display flag is set */
 257                 if ((rdev->pm.active_crtc_count > 0) &&
 258                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 259                      RADEON_PM_MODE_NO_DISPLAY)) {
 260                         rdev->pm.requested_power_state_index++;
 261                 }
 262                 break;
 263         case DYNPM_ACTION_UPCLOCK:
 264                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 265                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 266                         rdev->pm.dynpm_can_upclock = false;
 267                 } else {
 268                         if (rdev->pm.active_crtc_count > 1) {
 269                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 270                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 271                                                 continue;
 272                                         else if (i <= rdev->pm.current_power_state_index) {
 273                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 274                                                 break;
 275                                         } else {
 276                                                 rdev->pm.requested_power_state_index = i;
 277                                                 break;
 278                                         }
 279                                 }
 280                         } else
 281                                 rdev->pm.requested_power_state_index =
 282                                         rdev->pm.current_power_state_index + 1;
 283                 }
 284                 break;
 285         case DYNPM_ACTION_DEFAULT:
 286                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 287                 rdev->pm.dynpm_can_upclock = false;
 288                 break;
 289         case DYNPM_ACTION_NONE:
 290         default:
 291                 DRM_ERROR("Requested mode for not defined action\n");
 292                 return;
 293         }
 294         /* only one clock mode per power state */
 295         rdev->pm.requested_clock_mode_index = 0;
 296
 297         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 298                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 299                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 300                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 301                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 302                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 303                   pcie_lanes);
 304 }
 305
 306 /**
 307  * r100_pm_init_profile - Initialize power profiles callback.
 308  *
 309  * @rdev: radeon_device pointer
 310  *
 311  * Initialize the power states used in profile mode
 312  * (r1xx-r3xx).
 313  * Used for profile mode only.
 314  */
 315 void r100_pm_init_profile(struct radeon_device *rdev)
 316 {
 317         /* default */
 318         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 319         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 320         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 321         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 322         /* low sh */
 323         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 324         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 325         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 326         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 327         /* mid sh */
 328         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 329         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 330         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 331         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 332         /* high sh */
 333         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 334         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 335         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 336         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 337         /* low mh */
 338         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 339         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 340         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 341         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 342         /* mid mh */
 343         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 344         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 345         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 346         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 347         /* high mh */
 348         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 349         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 350         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 351         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 352 }
 353
 354 /**
 355  * r100_pm_misc - set additional pm hw parameters callback.
 356  *
 357  * @rdev: radeon_device pointer
 358  *
 359  * Set non-clock parameters associated with a power state
 360  * (voltage, pcie lanes, etc.) (r1xx-r4xx).
 361  */
 362 void r100_pm_misc(struct radeon_device *rdev)
 363 {
 364         int requested_index = rdev->pm.requested_power_state_index;
 365         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 366         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 367         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 368
 369         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 370                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 371                         tmp = RREG32(voltage->gpio.reg);
 372                         if (voltage->active_high)
 373                                 tmp |= voltage->gpio.mask;
 374                         else
 375                                 tmp &= ~(voltage->gpio.mask);
 376                         WREG32(voltage->gpio.reg, tmp);
 377                         if (voltage->delay)
 378                                 udelay(voltage->delay);
 379                 } else {
 380                         tmp = RREG32(voltage->gpio.reg);
 381                         if (voltage->active_high)
 382                                 tmp &= ~voltage->gpio.mask;
 383                         else
 384                                 tmp |= voltage->gpio.mask;
 385                         WREG32(voltage->gpio.reg, tmp);
 386                         if (voltage->delay)
 387                                 udelay(voltage->delay);
 388                 }
 389         }
 390
 391         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 392         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 393         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 394         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 395         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 396         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 397                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 398                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 399                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 400                 else
 401                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 402                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 403                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 404                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 405                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 406         } else
 407                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 408
 409         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 410                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 411                 if (voltage->delay) {
 412                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 413                         switch (voltage->delay) {
 414                         case 33:
 415                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 416                                 break;
 417                         case 66:
 418                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 419                                 break;
 420                         case 99:
 421                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 422                                 break;
 423                         case 132:
 424                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 425                                 break;
 426                         }
 427                 } else
 428                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 429         } else
 430                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 431
 432         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 433                 sclk_cntl &= ~FORCE_HDP;
 434         else
 435                 sclk_cntl |= FORCE_HDP;
 436
 437         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 438         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 439         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 440
 441         /* set pcie lanes */
 442         if ((rdev->flags & RADEON_IS_PCIE) &&
 443             !(rdev->flags & RADEON_IS_IGP) &&
 444             rdev->asic->pm.set_pcie_lanes &&
 445             (ps->pcie_lanes !=
 446              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 447                 radeon_set_pcie_lanes(rdev,
 448                                       ps->pcie_lanes);
 449                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 450         }
 451 }
 452
 453 /**
 454  * r100_pm_prepare - pre-power state change callback.
 455  *
 456  * @rdev: radeon_device pointer
 457  *
 458  * Prepare for a power state change (r1xx-r4xx).
 459  */
 460 void r100_pm_prepare(struct radeon_device *rdev)
 461 {
 462         struct drm_device *ddev = rdev->ddev;
 463         struct drm_crtc *crtc;
 464         struct radeon_crtc *radeon_crtc;
 465         u32 tmp;
 466
 467         /* disable any active CRTCs */
 468         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 469                 radeon_crtc = to_radeon_crtc(crtc);
 470                 if (radeon_crtc->enabled) {
 471                         if (radeon_crtc->crtc_id) {
 472                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 473                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 474                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 475                         } else {
 476                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 477                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 478                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 479                         }
 480                 }
 481         }
 482 }
 483
 484 /**
 485  * r100_pm_finish - post-power state change callback.
 486  *
 487  * @rdev: radeon_device pointer
 488  *
 489  * Clean up after a power state change (r1xx-r4xx).
 490  */
 491 void r100_pm_finish(struct radeon_device *rdev)
 492 {
 493         struct drm_device *ddev = rdev->ddev;
 494         struct drm_crtc *crtc;
 495         struct radeon_crtc *radeon_crtc;
 496         u32 tmp;
 497
 498         /* enable any active CRTCs */
 499         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 500                 radeon_crtc = to_radeon_crtc(crtc);
 501                 if (radeon_crtc->enabled) {
 502                         if (radeon_crtc->crtc_id) {
 503                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 504                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 505                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 506                         } else {
 507                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 508                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 509                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 510                         }
 511                 }
 512         }
 513 }
 514
 515 /**
 516  * r100_gui_idle - gui idle callback.
 517  *
 518  * @rdev: radeon_device pointer
 519  *
 520  * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
 521  * Returns true if idle, false if not.
 522  */
 523 bool r100_gui_idle(struct radeon_device *rdev)
 524 {
 525         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 526                 return false;
 527         else
 528                 return true;
 529 }
 530
 531 /* hpd for digital panel detect/disconnect */
 532 /**
 533  * r100_hpd_sense - hpd sense callback.
 534  *
 535  * @rdev: radeon_device pointer
 536  * @hpd: hpd (hotplug detect) pin
 537  *
 538  * Checks if a digital monitor is connected (r1xx-r4xx).
 539  * Returns true if connected, false if not connected.
 540  */
 541 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 542 {
 543         bool connected = false;
 544
 545         switch (hpd) {
 546         case RADEON_HPD_1:
 547                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 548                         connected = true;
 549                 break;
 550         case RADEON_HPD_2:
 551                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 552                         connected = true;
 553                 break;
 554         default:
 555                 break;
 556         }
 557         return connected;
 558 }
 559
 560 /**
 561  * r100_hpd_set_polarity - hpd set polarity callback.
 562  *
 563  * @rdev: radeon_device pointer
 564  * @hpd: hpd (hotplug detect) pin
 565  *
 566  * Set the polarity of the hpd pin (r1xx-r4xx).
 567  */
 568 void r100_hpd_set_polarity(struct radeon_device *rdev,
 569                            enum radeon_hpd_id hpd)
 570 {
 571         u32 tmp;
 572         bool connected = r100_hpd_sense(rdev, hpd);
 573
 574         switch (hpd) {
 575         case RADEON_HPD_1:
 576                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 577                 if (connected)
 578                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 579                 else
 580                         tmp |= RADEON_FP_DETECT_INT_POL;
 581                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 582                 break;
 583         case RADEON_HPD_2:
 584                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 585                 if (connected)
 586                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 587                 else
 588                         tmp |= RADEON_FP2_DETECT_INT_POL;
 589                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 590                 break;
 591         default:
 592                 break;
 593         }
 594 }
 595
 596 /**
 597  * r100_hpd_init - hpd setup callback.
 598  *
 599  * @rdev: radeon_device pointer
 600  *
 601  * Setup the hpd pins used by the card (r1xx-r4xx).
 602  * Set the polarity, and enable the hpd interrupts.
 603  */
 604 void r100_hpd_init(struct radeon_device *rdev)
 605 {
 606         struct drm_device *dev = rdev->ddev;
 607         struct drm_connector *connector;
 608         unsigned enable = 0;
 609
 610         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 611                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 612                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 613                         enable |= 1 << radeon_connector->hpd.hpd;
 614                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 615         }
 616         radeon_irq_kms_enable_hpd(rdev, enable);
 617 }
 618
 619 /**
 620  * r100_hpd_fini - hpd tear down callback.
 621  *
 622  * @rdev: radeon_device pointer
 623  *
 624  * Tear down the hpd pins used by the card (r1xx-r4xx).
 625  * Disable the hpd interrupts.
 626  */
 627 void r100_hpd_fini(struct radeon_device *rdev)
 628 {
 629         struct drm_device *dev = rdev->ddev;
 630         struct drm_connector *connector;
 631         unsigned disable = 0;
 632
 633         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 634                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 635                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 636                         disable |= 1 << radeon_connector->hpd.hpd;
 637         }
 638         radeon_irq_kms_disable_hpd(rdev, disable);
 639 }
 640
 641 /*
 642  * PCI GART
 643  */
 644 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 645 {
 646         /* TODO: can we do somethings here ? */
 647         /* It seems hw only cache one entry so we should discard this
 648          * entry otherwise if first GPU GART read hit this entry it
 649          * could end up in wrong address. */
 650 }
 651
 652 int r100_pci_gart_init(struct radeon_device *rdev)
 653 {
 654         int r;
 655
 656         if (rdev->gart.ptr) {
 657                 WARN(1, "R100 PCI GART already initialized\n");
 658                 return 0;
 659         }
 660         /* Initialize common gart structure */
 661         r = radeon_gart_init(rdev);
 662         if (r)
 663                 return r;
 664         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 665         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 666         rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 667         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 668         return radeon_gart_table_ram_alloc(rdev);
 669 }
 670
 671 int r100_pci_gart_enable(struct radeon_device *rdev)
 672 {
 673         uint32_t tmp;
 674
 675         /* discard memory request outside of configured range */
 676         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 677         WREG32(RADEON_AIC_CNTL, tmp);
 678         /* set address range for PCI address translate */
 679         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 680         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 681         /* set PCI GART page-table base address */
 682         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 683         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 684         WREG32(RADEON_AIC_CNTL, tmp);
 685         r100_pci_gart_tlb_flush(rdev);
 686         DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
 687                  (unsigned)(rdev->mc.gtt_size >> 20),
 688                  (unsigned long long)rdev->gart.table_addr);
 689         rdev->gart.ready = true;
 690         return 0;
 691 }
 692
 693 void r100_pci_gart_disable(struct radeon_device *rdev)
 694 {
 695         uint32_t tmp;
 696
 697         /* discard memory request outside of configured range */
 698         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 699         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 700         WREG32(RADEON_AIC_LO_ADDR, 0);
 701         WREG32(RADEON_AIC_HI_ADDR, 0);
 702 }
 703
 704 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
 705 {
 706         return addr;
 707 }
 708
 709 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
 710                             uint64_t entry)
 711 {
 712         u32 *gtt = rdev->gart.ptr;
 713         gtt[i] = cpu_to_le32(lower_32_bits(entry));
 714 }
 715
 716 void r100_pci_gart_fini(struct radeon_device *rdev)
 717 {
 718         radeon_gart_fini(rdev);
 719         r100_pci_gart_disable(rdev);
 720         radeon_gart_table_ram_free(rdev);
 721 }
 722
 723 int r100_irq_set(struct radeon_device *rdev)
 724 {
 725         uint32_t tmp = 0;
 726
 727         if (!rdev->irq.installed) {
 728                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 729                 WREG32(R_000040_GEN_INT_CNTL, 0);
 730                 return -EINVAL;
 731         }
 732         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 733                 tmp |= RADEON_SW_INT_ENABLE;
 734         }
 735         if (rdev->irq.crtc_vblank_int[0] ||
 736             atomic_read(&rdev->irq.pflip[0])) {
 737                 tmp |= RADEON_CRTC_VBLANK_MASK;
 738         }
 739         if (rdev->irq.crtc_vblank_int[1] ||
 740             atomic_read(&rdev->irq.pflip[1])) {
 741                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 742         }
 743         if (rdev->irq.hpd[0]) {
 744                 tmp |= RADEON_FP_DETECT_MASK;
 745         }
 746         if (rdev->irq.hpd[1]) {
 747                 tmp |= RADEON_FP2_DETECT_MASK;
 748         }
 749         WREG32(RADEON_GEN_INT_CNTL, tmp);
 750
 751         /* read back to post the write */
 752         RREG32(RADEON_GEN_INT_CNTL);
 753
 754         return 0;
 755 }
 756
 757 void r100_irq_disable(struct radeon_device *rdev)
 758 {
 759         u32 tmp;
 760
 761         WREG32(R_000040_GEN_INT_CNTL, 0);
 762         /* Wait and acknowledge irq */
 763         mdelay(1);
 764         tmp = RREG32(R_000044_GEN_INT_STATUS);
 765         WREG32(R_000044_GEN_INT_STATUS, tmp);
 766 }
 767
 768 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 769 {
 770         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 771         uint32_t irq_mask = RADEON_SW_INT_TEST |
 772                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 773                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 774
 775         if (irqs) {
 776                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 777         }
 778         return irqs & irq_mask;
 779 }
 780
 781 int r100_irq_process(struct radeon_device *rdev)
 782 {
 783         uint32_t status, msi_rearm;
 784         bool queue_hotplug = false;
 785
 786         status = r100_irq_ack(rdev);
 787         if (!status) {
 788                 return IRQ_NONE;
 789         }
 790         if (rdev->shutdown) {
 791                 return IRQ_NONE;
 792         }
 793         while (status) {
 794                 /* SW interrupt */
 795                 if (status & RADEON_SW_INT_TEST) {
 796                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 797                 }
 798                 /* Vertical blank interrupts */
 799                 if (status & RADEON_CRTC_VBLANK_STAT) {
 800                         if (rdev->irq.crtc_vblank_int[0]) {
 801                                 drm_handle_vblank(rdev->ddev, 0);
 802                                 rdev->pm.vblank_sync = true;
 803                                 wake_up(&rdev->irq.vblank_queue);
 804                         }
 805                         if (atomic_read(&rdev->irq.pflip[0]))
 806                                 radeon_crtc_handle_vblank(rdev, 0);
 807                 }
 808                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 809                         if (rdev->irq.crtc_vblank_int[1]) {
 810                                 drm_handle_vblank(rdev->ddev, 1);
 811                                 rdev->pm.vblank_sync = true;
 812                                 wake_up(&rdev->irq.vblank_queue);
 813                         }
 814                         if (atomic_read(&rdev->irq.pflip[1]))
 815                                 radeon_crtc_handle_vblank(rdev, 1);
 816                 }
 817                 if (status & RADEON_FP_DETECT_STAT) {
 818                         queue_hotplug = true;
 819                         DRM_DEBUG("HPD1\n");
 820                 }
 821                 if (status & RADEON_FP2_DETECT_STAT) {
 822                         queue_hotplug = true;
 823                         DRM_DEBUG("HPD2\n");
 824                 }
 825                 status = r100_irq_ack(rdev);
 826         }
 827         if (queue_hotplug)
 828                 schedule_delayed_work(&rdev->hotplug_work, 0);
 829         if (rdev->msi_enabled) {
 830                 switch (rdev->family) {
 831                 case CHIP_RS400:
 832                 case CHIP_RS480:
 833                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 834                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 835                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 836                         break;
 837                 default:
 838                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 839                         break;
 840                 }
 841         }
 842         return IRQ_HANDLED;
 843 }
 844
 845 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 846 {
 847         if (crtc == 0)
 848                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 849         else
 850                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 851 }
 852
 853 /**
 854  * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
 855  * @rdev: radeon device structure
 856  * @ring: ring buffer struct for emitting packets
 857  */
 858 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
 859 {
 860         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 861         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
 862                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 863         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 864         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
 865 }
 866
 867 /* Who ever call radeon_fence_emit should call ring_lock and ask
 868  * for enough space (today caller are ib schedule and buffer move) */
 869 void r100_fence_ring_emit(struct radeon_device *rdev,
 870                           struct radeon_fence *fence)
 871 {
 872         struct radeon_ring *ring = &rdev->ring[fence->ring];
 873
 874         /* We have to make sure that caches are flushed before
 875          * CPU might read something from VRAM. */
 876         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 877         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
 878         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 879         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
 880         /* Wait until IDLE & CLEAN */
 881         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 882         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 883         r100_ring_hdp_flush(rdev, ring);
 884         /* Emit fence sequence & fire IRQ */
 885         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 886         radeon_ring_write(ring, fence->seq);
 887         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 888         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 889 }
 890
 891 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
 892                               struct radeon_ring *ring,
 893                               struct radeon_semaphore *semaphore,
 894                               bool emit_wait)
 895 {
 896         /* Unused on older asics, since we don't have semaphores or multiple rings */
 897         BUG();
 898         return false;
 899 }
 900
 901 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
 902                                     uint64_t src_offset,
 903                                     uint64_t dst_offset,
 904                                     unsigned num_gpu_pages,
 905                                     struct dma_resv *resv)
 906 {
 907         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 908         struct radeon_fence *fence;
 909         uint32_t cur_pages;
 910         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 911         uint32_t pitch;
 912         uint32_t stride_pixels;
 913         unsigned ndw;
 914         int num_loops;
 915         int r = 0;
 916
 917         /* radeon limited to 16k stride */
 918         stride_bytes &= 0x3fff;
 919         /* radeon pitch is /64 */
 920         pitch = stride_bytes / 64;
 921         stride_pixels = stride_bytes / 4;
 922         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 923
 924         /* Ask for enough room for blit + flush + fence */
 925         ndw = 64 + (10 * num_loops);
 926         r = radeon_ring_lock(rdev, ring, ndw);
 927         if (r) {
 928                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 929                 return ERR_PTR(-EINVAL);
 930         }
 931         while (num_gpu_pages > 0) {
 932                 cur_pages = num_gpu_pages;
 933                 if (cur_pages > 8191) {
 934                         cur_pages = 8191;
 935                 }
 936                 num_gpu_pages -= cur_pages;
 937
 938                 /* pages are in Y direction - height
 939                    page width in X direction - width */
 940                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
 941                 radeon_ring_write(ring,
 942                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 943                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 944                                   RADEON_GMC_SRC_CLIPPING |
 945                                   RADEON_GMC_DST_CLIPPING |
 946                                   RADEON_GMC_BRUSH_NONE |
 947                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 948                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 949                                   RADEON_ROP3_S |
 950                                   RADEON_DP_SRC_SOURCE_MEMORY |
 951                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 952                                   RADEON_GMC_WR_MSK_DIS);
 953                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
 954                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
 955                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 956                 radeon_ring_write(ring, 0);
 957                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 958                 radeon_ring_write(ring, num_gpu_pages);
 959                 radeon_ring_write(ring, num_gpu_pages);
 960                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
 961         }
 962         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 963         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
 964         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 965         radeon_ring_write(ring,
 966                           RADEON_WAIT_2D_IDLECLEAN |
 967                           RADEON_WAIT_HOST_IDLECLEAN |
 968                           RADEON_WAIT_DMA_GUI_IDLE);
 969         r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
 970         if (r) {
 971                 radeon_ring_unlock_undo(rdev, ring);
 972                 return ERR_PTR(r);
 973         }
 974         radeon_ring_unlock_commit(rdev, ring, false);
 975         return fence;
 976 }
 977
 978 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 979 {
 980         unsigned i;
 981         u32 tmp;
 982
 983         for (i = 0; i < rdev->usec_timeout; i++) {
 984                 tmp = RREG32(R_000E40_RBBM_STATUS);
 985                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 986                         return 0;
 987                 }
 988                 udelay(1);
 989         }
 990         return -1;
 991 }
 992
 993 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 994 {
 995         int r;
 996
 997         r = radeon_ring_lock(rdev, ring, 2);
 998         if (r) {
 999                 return;
1000         }
1001         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
1002         radeon_ring_write(ring,
1003                           RADEON_ISYNC_ANY2D_IDLE3D |
1004                           RADEON_ISYNC_ANY3D_IDLE2D |
1005                           RADEON_ISYNC_WAIT_IDLEGUI |
1006                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
1007         radeon_ring_unlock_commit(rdev, ring, false);
1008 }
1009
1010
1011 /* Load the microcode for the CP */
1012 static int r100_cp_init_microcode(struct radeon_device *rdev)
1013 {
1014         const char *fw_name = NULL;
1015         int err;
1016
1017         DRM_DEBUG_KMS("\n");
1018
1019         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1020             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1021             (rdev->family == CHIP_RS200)) {
1022                 DRM_INFO("Loading R100 Microcode\n");
1023                 fw_name = FIRMWARE_R100;
1024         } else if ((rdev->family == CHIP_R200) ||
1025                    (rdev->family == CHIP_RV250) ||
1026                    (rdev->family == CHIP_RV280) ||
1027                    (rdev->family == CHIP_RS300)) {
1028                 DRM_INFO("Loading R200 Microcode\n");
1029                 fw_name = FIRMWARE_R200;
1030         } else if ((rdev->family == CHIP_R300) ||
1031                    (rdev->family == CHIP_R350) ||
1032                    (rdev->family == CHIP_RV350) ||
1033                    (rdev->family == CHIP_RV380) ||
1034                    (rdev->family == CHIP_RS400) ||
1035                    (rdev->family == CHIP_RS480)) {
1036                 DRM_INFO("Loading R300 Microcode\n");
1037                 fw_name = FIRMWARE_R300;
1038         } else if ((rdev->family == CHIP_R420) ||
1039                    (rdev->family == CHIP_R423) ||
1040                    (rdev->family == CHIP_RV410)) {
1041                 DRM_INFO("Loading R400 Microcode\n");
1042                 fw_name = FIRMWARE_R420;
1043         } else if ((rdev->family == CHIP_RS690) ||
1044                    (rdev->family == CHIP_RS740)) {
1045                 DRM_INFO("Loading RS690/RS740 Microcode\n");
1046                 fw_name = FIRMWARE_RS690;
1047         } else if (rdev->family == CHIP_RS600) {
1048                 DRM_INFO("Loading RS600 Microcode\n");
1049                 fw_name = FIRMWARE_RS600;
1050         } else if ((rdev->family == CHIP_RV515) ||
1051                    (rdev->family == CHIP_R520) ||
1052                    (rdev->family == CHIP_RV530) ||
1053                    (rdev->family == CHIP_R580) ||
1054                    (rdev->family == CHIP_RV560) ||
1055                    (rdev->family == CHIP_RV570)) {
1056                 DRM_INFO("Loading R500 Microcode\n");
1057                 fw_name = FIRMWARE_R520;
1058         }
1059
1060         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1061         if (err) {
1062                 pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name);
1063         } else if (rdev->me_fw->size % 8) {
1064                 pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1065                        rdev->me_fw->size, fw_name);
1066                 err = -EINVAL;
1067                 release_firmware(rdev->me_fw);
1068                 rdev->me_fw = NULL;
1069         }
1070         return err;
1071 }
1072
1073 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1074                       struct radeon_ring *ring)
1075 {
1076         u32 rptr;
1077
1078         if (rdev->wb.enabled)
1079                 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1080         else
1081                 rptr = RREG32(RADEON_CP_RB_RPTR);
1082
1083         return rptr;
1084 }
1085
1086 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1087                       struct radeon_ring *ring)
1088 {
1089         return RREG32(RADEON_CP_RB_WPTR);
1090 }
1091
1092 void r100_gfx_set_wptr(struct radeon_device *rdev,
1093                        struct radeon_ring *ring)
1094 {
1095         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1096         (void)RREG32(RADEON_CP_RB_WPTR);
1097 }
1098
1099 static void r100_cp_load_microcode(struct radeon_device *rdev)
1100 {
1101         const __be32 *fw_data;
1102         int i, size;
1103
1104         if (r100_gui_wait_for_idle(rdev)) {
1105                 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1106         }
1107
1108         if (rdev->me_fw) {
1109                 size = rdev->me_fw->size / 4;
1110                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1111                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1112                 for (i = 0; i < size; i += 2) {
1113                         WREG32(RADEON_CP_ME_RAM_DATAH,
1114                                be32_to_cpup(&fw_data[i]));
1115                         WREG32(RADEON_CP_ME_RAM_DATAL,
1116                                be32_to_cpup(&fw_data[i + 1]));
1117                 }
1118         }
1119 }
1120
1121 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1122 {
1123         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1124         unsigned rb_bufsz;
1125         unsigned rb_blksz;
1126         unsigned max_fetch;
1127         unsigned pre_write_timer;
1128         unsigned pre_write_limit;
1129         unsigned indirect2_start;
1130         unsigned indirect1_start;
1131         uint32_t tmp;
1132         int r;
1133
1134         r100_debugfs_cp_init(rdev);
1135         if (!rdev->me_fw) {
1136                 r = r100_cp_init_microcode(rdev);
1137                 if (r) {
1138                         DRM_ERROR("Failed to load firmware!\n");
1139                         return r;
1140                 }
1141         }
1142
1143         /* Align ring size */
1144         rb_bufsz = order_base_2(ring_size / 8);
1145         ring_size = (1 << (rb_bufsz + 1)) * 4;
1146         r100_cp_load_microcode(rdev);
1147         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1148                              RADEON_CP_PACKET2);
1149         if (r) {
1150                 return r;
1151         }
1152         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1153          * the rptr copy in system ram */
1154         rb_blksz = 9;
1155         /* cp will read 128bytes at a time (4 dwords) */
1156         max_fetch = 1;
1157         ring->align_mask = 16 - 1;
1158         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1159         pre_write_timer = 64;
1160         /* Force CP_RB_WPTR write if written more than one time before the
1161          * delay expire
1162          */
1163         pre_write_limit = 0;
1164         /* Setup the cp cache like this (cache size is 96 dwords) :
1165          *      RING            0  to 15
1166          *      INDIRECT1       16 to 79
1167          *      INDIRECT2       80 to 95
1168          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1169          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1170          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1171          * Idea being that most of the gpu cmd will be through indirect1 buffer
1172          * so it gets the bigger cache.
1173          */
1174         indirect2_start = 80;
1175         indirect1_start = 16;
1176         /* cp setup */
1177         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1178         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1179                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1180                REG_SET(RADEON_MAX_FETCH, max_fetch));
1181 #ifdef __BIG_ENDIAN
1182         tmp |= RADEON_BUF_SWAP_32BIT;
1183 #endif
1184         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1185
1186         /* Set ring address */
1187         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1188         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1189         /* Force read & write ptr to 0 */
1190         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1191         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1192         ring->wptr = 0;
1193         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1194
1195         /* set the wb address whether it's enabled or not */
1196         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1197                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1198         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1199
1200         if (rdev->wb.enabled)
1201                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1202         else {
1203                 tmp |= RADEON_RB_NO_UPDATE;
1204                 WREG32(R_000770_SCRATCH_UMSK, 0);
1205         }
1206
1207         WREG32(RADEON_CP_RB_CNTL, tmp);
1208         udelay(10);
1209         /* Set cp mode to bus mastering & enable cp*/
1210         WREG32(RADEON_CP_CSQ_MODE,
1211                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1212                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1213         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1214         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1215         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1216
1217         /* at this point everything should be setup correctly to enable master */
1218         pci_set_master(rdev->pdev);
1219
1220         radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1221         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1222         if (r) {
1223                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1224                 return r;
1225         }
1226         ring->ready = true;
1227         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1228
1229         if (!ring->rptr_save_reg /* not resuming from suspend */
1230             && radeon_ring_supports_scratch_reg(rdev, ring)) {
1231                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1232                 if (r) {
1233                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1234                         ring->rptr_save_reg = 0;
1235                 }
1236         }
1237         return 0;
1238 }
1239
1240 void r100_cp_fini(struct radeon_device *rdev)
1241 {
1242         if (r100_cp_wait_for_idle(rdev)) {
1243                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1244         }
1245         /* Disable ring */
1246         r100_cp_disable(rdev);
1247         radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1248         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1249         DRM_INFO("radeon: cp finalized\n");
1250 }
1251
1252 void r100_cp_disable(struct radeon_device *rdev)
1253 {
1254         /* Disable ring */
1255         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1256         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1257         WREG32(RADEON_CP_CSQ_MODE, 0);
1258         WREG32(RADEON_CP_CSQ_CNTL, 0);
1259         WREG32(R_000770_SCRATCH_UMSK, 0);
1260         if (r100_gui_wait_for_idle(rdev)) {
1261                 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1262         }
1263 }
1264
1265 /*
1266  * CS functions
1267  */
1268 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1269                             struct radeon_cs_packet *pkt,
1270                             unsigned idx,
1271                             unsigned reg)
1272 {
1273         int r;
1274         u32 tile_flags = 0;
1275         u32 tmp;
1276         struct radeon_bo_list *reloc;
1277         u32 value;
1278
1279         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1280         if (r) {
1281                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1282                           idx, reg);
1283                 radeon_cs_dump_packet(p, pkt);
1284                 return r;
1285         }
1286
1287         value = radeon_get_ib_value(p, idx);
1288         tmp = value & 0x003fffff;
1289         tmp += (((u32)reloc->gpu_offset) >> 10);
1290
1291         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1292                 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1293                         tile_flags |= RADEON_DST_TILE_MACRO;
1294                 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1295                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1296                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1297                                 radeon_cs_dump_packet(p, pkt);
1298                                 return -EINVAL;
1299                         }
1300                         tile_flags |= RADEON_DST_TILE_MICRO;
1301                 }
1302
1303                 tmp |= tile_flags;
1304                 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1305         } else
1306                 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1307         return 0;
1308 }
1309
1310 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1311                              struct radeon_cs_packet *pkt,
1312                              int idx)
1313 {
1314         unsigned c, i;
1315         struct radeon_bo_list *reloc;
1316         struct r100_cs_track *track;
1317         int r = 0;
1318         volatile uint32_t *ib;
1319         u32 idx_value;
1320
1321         ib = p->ib.ptr;
1322         track = (struct r100_cs_track *)p->track;
1323         c = radeon_get_ib_value(p, idx++) & 0x1F;
1324         if (c > 16) {
1325             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1326                       pkt->opcode);
1327             radeon_cs_dump_packet(p, pkt);
1328             return -EINVAL;
1329         }
1330         track->num_arrays = c;
1331         for (i = 0; i < (c - 1); i += 2, idx += 3) {
1332                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1333                 if (r) {
1334                         DRM_ERROR("No reloc for packet3 %d\n",
1335                                   pkt->opcode);
1336                         radeon_cs_dump_packet(p, pkt);
1337                         return r;
1338                 }
1339                 idx_value = radeon_get_ib_value(p, idx);
1340                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1341
1342                 track->arrays[i + 0].esize = idx_value >> 8;
1343                 track->arrays[i + 0].robj = reloc->robj;
1344                 track->arrays[i + 0].esize &= 0x7F;
1345                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1346                 if (r) {
1347                         DRM_ERROR("No reloc for packet3 %d\n",
1348                                   pkt->opcode);
1349                         radeon_cs_dump_packet(p, pkt);
1350                         return r;
1351                 }
1352                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1353                 track->arrays[i + 1].robj = reloc->robj;
1354                 track->arrays[i + 1].esize = idx_value >> 24;
1355                 track->arrays[i + 1].esize &= 0x7F;
1356         }
1357         if (c & 1) {
1358                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1359                 if (r) {
1360                         DRM_ERROR("No reloc for packet3 %d\n",
1361                                           pkt->opcode);
1362                         radeon_cs_dump_packet(p, pkt);
1363                         return r;
1364                 }
1365                 idx_value = radeon_get_ib_value(p, idx);
1366                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1367                 track->arrays[i + 0].robj = reloc->robj;
1368                 track->arrays[i + 0].esize = idx_value >> 8;
1369                 track->arrays[i + 0].esize &= 0x7F;
1370         }
1371         return r;
1372 }
1373
1374 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1375                           struct radeon_cs_packet *pkt,
1376                           const unsigned *auth, unsigned n,
1377                           radeon_packet0_check_t check)
1378 {
1379         unsigned reg;
1380         unsigned i, j, m;
1381         unsigned idx;
1382         int r;
1383
1384         idx = pkt->idx + 1;
1385         reg = pkt->reg;
1386         /* Check that register fall into register range
1387          * determined by the number of entry (n) in the
1388          * safe register bitmap.
1389          */
1390         if (pkt->one_reg_wr) {
1391                 if ((reg >> 7) > n) {
1392                         return -EINVAL;
1393                 }
1394         } else {
1395                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1396                         return -EINVAL;
1397                 }
1398         }
1399         for (i = 0; i <= pkt->count; i++, idx++) {
1400                 j = (reg >> 7);
1401                 m = 1 << ((reg >> 2) & 31);
1402                 if (auth[j] & m) {
1403                         r = check(p, pkt, idx, reg);
1404                         if (r) {
1405                                 return r;
1406                         }
1407                 }
1408                 if (pkt->one_reg_wr) {
1409                         if (!(auth[j] & m)) {
1410                                 break;
1411                         }
1412                 } else {
1413                         reg += 4;
1414                 }
1415         }
1416         return 0;
1417 }
1418
1419 /**
1420  * r100_cs_packet_parse_vline() - parse userspace VLINE packet
1421  * @p:          parser structure holding parsing context.
1422  *
1423  * Userspace sends a special sequence for VLINE waits.
1424  * PACKET0 - VLINE_START_END + value
1425  * PACKET0 - WAIT_UNTIL +_value
1426  * RELOC (P3) - crtc_id in reloc.
1427  *
1428  * This function parses this and relocates the VLINE START END
1429  * and WAIT UNTIL packets to the correct crtc.
1430  * It also detects a switched off crtc and nulls out the
1431  * wait in that case.
1432  */
1433 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1434 {
1435         struct drm_crtc *crtc;
1436         struct radeon_crtc *radeon_crtc;
1437         struct radeon_cs_packet p3reloc, waitreloc;
1438         int crtc_id;
1439         int r;
1440         uint32_t header, h_idx, reg;
1441         volatile uint32_t *ib;
1442
1443         ib = p->ib.ptr;
1444
1445         /* parse the wait until */
1446         r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1447         if (r)
1448                 return r;
1449
1450         /* check its a wait until and only 1 count */
1451         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1452             waitreloc.count != 0) {
1453                 DRM_ERROR("vline wait had illegal wait until segment\n");
1454                 return -EINVAL;
1455         }
1456
1457         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1458                 DRM_ERROR("vline wait had illegal wait until\n");
1459                 return -EINVAL;
1460         }
1461
1462         /* jump over the NOP */
1463         r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1464         if (r)
1465                 return r;
1466
1467         h_idx = p->idx - 2;
1468         p->idx += waitreloc.count + 2;
1469         p->idx += p3reloc.count + 2;
1470
1471         header = radeon_get_ib_value(p, h_idx);
1472         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1473         reg = R100_CP_PACKET0_GET_REG(header);
1474         crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
1475         if (!crtc) {
1476                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1477                 return -ENOENT;
1478         }
1479         radeon_crtc = to_radeon_crtc(crtc);
1480         crtc_id = radeon_crtc->crtc_id;
1481
1482         if (!crtc->enabled) {
1483                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1484                 ib[h_idx + 2] = PACKET2(0);
1485                 ib[h_idx + 3] = PACKET2(0);
1486         } else if (crtc_id == 1) {
1487                 switch (reg) {
1488                 case AVIVO_D1MODE_VLINE_START_END:
1489                         header &= ~R300_CP_PACKET0_REG_MASK;
1490                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1491                         break;
1492                 case RADEON_CRTC_GUI_TRIG_VLINE:
1493                         header &= ~R300_CP_PACKET0_REG_MASK;
1494                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1495                         break;
1496                 default:
1497                         DRM_ERROR("unknown crtc reloc\n");
1498                         return -EINVAL;
1499                 }
1500                 ib[h_idx] = header;
1501                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1502         }
1503
1504         return 0;
1505 }
1506
1507 static int r100_get_vtx_size(uint32_t vtx_fmt)
1508 {
1509         int vtx_size;
1510         vtx_size = 2;
1511         /* ordered according to bits in spec */
1512         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1513                 vtx_size++;
1514         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1515                 vtx_size += 3;
1516         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1517                 vtx_size++;
1518         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1519                 vtx_size++;
1520         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1521                 vtx_size += 3;
1522         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1523                 vtx_size++;
1524         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1525                 vtx_size++;
1526         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1527                 vtx_size += 2;
1528         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1529                 vtx_size += 2;
1530         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1531                 vtx_size++;
1532         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1533                 vtx_size += 2;
1534         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1535                 vtx_size++;
1536         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1537                 vtx_size += 2;
1538         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1539                 vtx_size++;
1540         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1541                 vtx_size++;
1542         /* blend weight */
1543         if (vtx_fmt & (0x7 << 15))
1544                 vtx_size += (vtx_fmt >> 15) & 0x7;
1545         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1546                 vtx_size += 3;
1547         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1548                 vtx_size += 2;
1549         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1550                 vtx_size++;
1551         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1552                 vtx_size++;
1553         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1554                 vtx_size++;
1555         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1556                 vtx_size++;
1557         return vtx_size;
1558 }
1559
1560 static int r100_packet0_check(struct radeon_cs_parser *p,
1561                               struct radeon_cs_packet *pkt,
1562                               unsigned idx, unsigned reg)
1563 {
1564         struct radeon_bo_list *reloc;
1565         struct r100_cs_track *track;
1566         volatile uint32_t *ib;
1567         uint32_t tmp;
1568         int r;
1569         int i, face;
1570         u32 tile_flags = 0;
1571         u32 idx_value;
1572
1573         ib = p->ib.ptr;
1574         track = (struct r100_cs_track *)p->track;
1575
1576         idx_value = radeon_get_ib_value(p, idx);
1577
1578         switch (reg) {
1579         case RADEON_CRTC_GUI_TRIG_VLINE:
1580                 r = r100_cs_packet_parse_vline(p);
1581                 if (r) {
1582                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1583                                   idx, reg);
1584                         radeon_cs_dump_packet(p, pkt);
1585                         return r;
1586                 }
1587                 break;
1588                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1589                  * range access */
1590         case RADEON_DST_PITCH_OFFSET:
1591         case RADEON_SRC_PITCH_OFFSET:
1592                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1593                 if (r)
1594                         return r;
1595                 break;
1596         case RADEON_RB3D_DEPTHOFFSET:
1597                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1598                 if (r) {
1599                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1600                                   idx, reg);
1601                         radeon_cs_dump_packet(p, pkt);
1602                         return r;
1603                 }
1604                 track->zb.robj = reloc->robj;
1605                 track->zb.offset = idx_value;
1606                 track->zb_dirty = true;
1607                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1608                 break;
1609         case RADEON_RB3D_COLOROFFSET:
1610                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1611                 if (r) {
1612                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1613                                   idx, reg);
1614                         radeon_cs_dump_packet(p, pkt);
1615                         return r;
1616                 }
1617                 track->cb[0].robj = reloc->robj;
1618                 track->cb[0].offset = idx_value;
1619                 track->cb_dirty = true;
1620                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1621                 break;
1622         case RADEON_PP_TXOFFSET_0:
1623         case RADEON_PP_TXOFFSET_1:
1624         case RADEON_PP_TXOFFSET_2:
1625                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1626                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1627                 if (r) {
1628                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1629                                   idx, reg);
1630                         radeon_cs_dump_packet(p, pkt);
1631                         return r;
1632                 }
1633                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1634                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1635                                 tile_flags |= RADEON_TXO_MACRO_TILE;
1636                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1637                                 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1638
1639                         tmp = idx_value & ~(0x7 << 2);
1640                         tmp |= tile_flags;
1641                         ib[idx] = tmp + ((u32)reloc->gpu_offset);
1642                 } else
1643                         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1644                 track->textures[i].robj = reloc->robj;
1645                 track->tex_dirty = true;
1646                 break;
1647         case RADEON_PP_CUBIC_OFFSET_T0_0:
1648         case RADEON_PP_CUBIC_OFFSET_T0_1:
1649         case RADEON_PP_CUBIC_OFFSET_T0_2:
1650         case RADEON_PP_CUBIC_OFFSET_T0_3:
1651         case RADEON_PP_CUBIC_OFFSET_T0_4:
1652                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1653                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1654                 if (r) {
1655                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1656                                   idx, reg);
1657                         radeon_cs_dump_packet(p, pkt);
1658                         return r;
1659                 }
1660                 track->textures[0].cube_info[i].offset = idx_value;
1661                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1662                 track->textures[0].cube_info[i].robj = reloc->robj;
1663                 track->tex_dirty = true;
1664                 break;
1665         case RADEON_PP_CUBIC_OFFSET_T1_0:
1666         case RADEON_PP_CUBIC_OFFSET_T1_1:
1667         case RADEON_PP_CUBIC_OFFSET_T1_2:
1668         case RADEON_PP_CUBIC_OFFSET_T1_3:
1669         case RADEON_PP_CUBIC_OFFSET_T1_4:
1670                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1671                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1672                 if (r) {
1673                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1674                                   idx, reg);
1675                         radeon_cs_dump_packet(p, pkt);
1676                         return r;
1677                 }
1678                 track->textures[1].cube_info[i].offset = idx_value;
1679                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1680                 track->textures[1].cube_info[i].robj = reloc->robj;
1681                 track->tex_dirty = true;
1682                 break;
1683         case RADEON_PP_CUBIC_OFFSET_T2_0:
1684         case RADEON_PP_CUBIC_OFFSET_T2_1:
1685         case RADEON_PP_CUBIC_OFFSET_T2_2:
1686         case RADEON_PP_CUBIC_OFFSET_T2_3:
1687         case RADEON_PP_CUBIC_OFFSET_T2_4:
1688                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1689                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1690                 if (r) {
1691                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1692                                   idx, reg);
1693                         radeon_cs_dump_packet(p, pkt);
1694                         return r;
1695                 }
1696                 track->textures[2].cube_info[i].offset = idx_value;
1697                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1698                 track->textures[2].cube_info[i].robj = reloc->robj;
1699                 track->tex_dirty = true;
1700                 break;
1701         case RADEON_RE_WIDTH_HEIGHT:
1702                 track->maxy = ((idx_value >> 16) & 0x7FF);
1703                 track->cb_dirty = true;
1704                 track->zb_dirty = true;
1705                 break;
1706         case RADEON_RB3D_COLORPITCH:
1707                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1708                 if (r) {
1709                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1710                                   idx, reg);
1711                         radeon_cs_dump_packet(p, pkt);
1712                         return r;
1713                 }
1714                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1715                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1716                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1717                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1718                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1719
1720                         tmp = idx_value & ~(0x7 << 16);
1721                         tmp |= tile_flags;
1722                         ib[idx] = tmp;
1723                 } else
1724                         ib[idx] = idx_value;
1725
1726                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1727                 track->cb_dirty = true;
1728                 break;
1729         case RADEON_RB3D_DEPTHPITCH:
1730                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1731                 track->zb_dirty = true;
1732                 break;
1733         case RADEON_RB3D_CNTL:
1734                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1735                 case 7:
1736                 case 8:
1737                 case 9:
1738                 case 11:
1739                 case 12:
1740                         track->cb[0].cpp = 1;
1741                         break;
1742                 case 3:
1743                 case 4:
1744                 case 15:
1745                         track->cb[0].cpp = 2;
1746                         break;
1747                 case 6:
1748                         track->cb[0].cpp = 4;
1749                         break;
1750                 default:
1751                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1752                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1753                         return -EINVAL;
1754                 }
1755                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1756                 track->cb_dirty = true;
1757                 track->zb_dirty = true;
1758                 break;
1759         case RADEON_RB3D_ZSTENCILCNTL:
1760                 switch (idx_value & 0xf) {
1761                 case 0:
1762                         track->zb.cpp = 2;
1763                         break;
1764                 case 2:
1765                 case 3:
1766                 case 4:
1767                 case 5:
1768                 case 9:
1769                 case 11:
1770                         track->zb.cpp = 4;
1771                         break;
1772                 default:
1773                         break;
1774                 }
1775                 track->zb_dirty = true;
1776                 break;
1777         case RADEON_RB3D_ZPASS_ADDR:
1778                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1779                 if (r) {
1780                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1781                                   idx, reg);
1782                         radeon_cs_dump_packet(p, pkt);
1783                         return r;
1784                 }
1785                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1786                 break;
1787         case RADEON_PP_CNTL:
1788                 {
1789                         uint32_t temp = idx_value >> 4;
1790                         for (i = 0; i < track->num_texture; i++)
1791                                 track->textures[i].enabled = !!(temp & (1 << i));
1792                         track->tex_dirty = true;
1793                 }
1794                 break;
1795         case RADEON_SE_VF_CNTL:
1796                 track->vap_vf_cntl = idx_value;
1797                 break;
1798         case RADEON_SE_VTX_FMT:
1799                 track->vtx_size = r100_get_vtx_size(idx_value);
1800                 break;
1801         case RADEON_PP_TEX_SIZE_0:
1802         case RADEON_PP_TEX_SIZE_1:
1803         case RADEON_PP_TEX_SIZE_2:
1804                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1805                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1806                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1807                 track->tex_dirty = true;
1808                 break;
1809         case RADEON_PP_TEX_PITCH_0:
1810         case RADEON_PP_TEX_PITCH_1:
1811         case RADEON_PP_TEX_PITCH_2:
1812                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1813                 track->textures[i].pitch = idx_value + 32;
1814                 track->tex_dirty = true;
1815                 break;
1816         case RADEON_PP_TXFILTER_0:
1817         case RADEON_PP_TXFILTER_1:
1818         case RADEON_PP_TXFILTER_2:
1819                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1820                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1821                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1822                 tmp = (idx_value >> 23) & 0x7;
1823                 if (tmp == 2 || tmp == 6)
1824                         track->textures[i].roundup_w = false;
1825                 tmp = (idx_value >> 27) & 0x7;
1826                 if (tmp == 2 || tmp == 6)
1827                         track->textures[i].roundup_h = false;
1828                 track->tex_dirty = true;
1829                 break;
1830         case RADEON_PP_TXFORMAT_0:
1831         case RADEON_PP_TXFORMAT_1:
1832         case RADEON_PP_TXFORMAT_2:
1833                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1834                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1835                         track->textures[i].use_pitch = true;
1836                 } else {
1837                         track->textures[i].use_pitch = false;
1838                         track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
1839                         track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
1840                 }
1841                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1842                         track->textures[i].tex_coord_type = 2;
1843                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1844                 case RADEON_TXFORMAT_I8:
1845                 case RADEON_TXFORMAT_RGB332:
1846                 case RADEON_TXFORMAT_Y8:
1847                         track->textures[i].cpp = 1;
1848                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1849                         break;
1850                 case RADEON_TXFORMAT_AI88:
1851                 case RADEON_TXFORMAT_ARGB1555:
1852                 case RADEON_TXFORMAT_RGB565:
1853                 case RADEON_TXFORMAT_ARGB4444:
1854                 case RADEON_TXFORMAT_VYUY422:
1855                 case RADEON_TXFORMAT_YVYU422:
1856                 case RADEON_TXFORMAT_SHADOW16:
1857                 case RADEON_TXFORMAT_LDUDV655:
1858                 case RADEON_TXFORMAT_DUDV88:
1859                         track->textures[i].cpp = 2;
1860                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1861                         break;
1862                 case RADEON_TXFORMAT_ARGB8888:
1863                 case RADEON_TXFORMAT_RGBA8888:
1864                 case RADEON_TXFORMAT_SHADOW32:
1865                 case RADEON_TXFORMAT_LDUDUV8888:
1866                         track->textures[i].cpp = 4;
1867                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1868                         break;
1869                 case RADEON_TXFORMAT_DXT1:
1870                         track->textures[i].cpp = 1;
1871                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1872                         break;
1873                 case RADEON_TXFORMAT_DXT23:
1874                 case RADEON_TXFORMAT_DXT45:
1875                         track->textures[i].cpp = 1;
1876                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1877                         break;
1878                 }
1879                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1880                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1881                 track->tex_dirty = true;
1882                 break;
1883         case RADEON_PP_CUBIC_FACES_0:
1884         case RADEON_PP_CUBIC_FACES_1:
1885         case RADEON_PP_CUBIC_FACES_2:
1886                 tmp = idx_value;
1887                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1888                 for (face = 0; face < 4; face++) {
1889                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1890                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1891                 }
1892                 track->tex_dirty = true;
1893                 break;
1894         default:
1895                 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
1896                 return -EINVAL;
1897         }
1898         return 0;
1899 }
1900
1901 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1902                                          struct radeon_cs_packet *pkt,
1903                                          struct radeon_bo *robj)
1904 {
1905         unsigned idx;
1906         u32 value;
1907         idx = pkt->idx + 1;
1908         value = radeon_get_ib_value(p, idx + 2);
1909         if ((value + 1) > radeon_bo_size(robj)) {
1910                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1911                           "(need %u have %lu) !\n",
1912                           value + 1,
1913                           radeon_bo_size(robj));
1914                 return -EINVAL;
1915         }
1916         return 0;
1917 }
1918
1919 static int r100_packet3_check(struct radeon_cs_parser *p,
1920                               struct radeon_cs_packet *pkt)
1921 {
1922         struct radeon_bo_list *reloc;
1923         struct r100_cs_track *track;
1924         unsigned idx;
1925         volatile uint32_t *ib;
1926         int r;
1927
1928         ib = p->ib.ptr;
1929         idx = pkt->idx + 1;
1930         track = (struct r100_cs_track *)p->track;
1931         switch (pkt->opcode) {
1932         case PACKET3_3D_LOAD_VBPNTR:
1933                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1934                 if (r)
1935                         return r;
1936                 break;
1937         case PACKET3_INDX_BUFFER:
1938                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1939                 if (r) {
1940                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1941                         radeon_cs_dump_packet(p, pkt);
1942                         return r;
1943                 }
1944                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1945                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1946                 if (r) {
1947                         return r;
1948                 }
1949                 break;
1950         case 0x23:
1951                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1952                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1953                 if (r) {
1954                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1955                         radeon_cs_dump_packet(p, pkt);
1956                         return r;
1957                 }
1958                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1959                 track->num_arrays = 1;
1960                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1961
1962                 track->arrays[0].robj = reloc->robj;
1963                 track->arrays[0].esize = track->vtx_size;
1964
1965                 track->max_indx = radeon_get_ib_value(p, idx+1);
1966
1967                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1968                 track->immd_dwords = pkt->count - 1;
1969                 r = r100_cs_track_check(p->rdev, track);
1970                 if (r)
1971                         return r;
1972                 break;
1973         case PACKET3_3D_DRAW_IMMD:
1974                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1975                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1976                         return -EINVAL;
1977                 }
1978                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1979                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1980                 track->immd_dwords = pkt->count - 1;
1981                 r = r100_cs_track_check(p->rdev, track);
1982                 if (r)
1983                         return r;
1984                 break;
1985                 /* triggers drawing using in-packet vertex data */
1986         case PACKET3_3D_DRAW_IMMD_2:
1987                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1988                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1989                         return -EINVAL;
1990                 }
1991                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1992                 track->immd_dwords = pkt->count;
1993                 r = r100_cs_track_check(p->rdev, track);
1994                 if (r)
1995                         return r;
1996                 break;
1997                 /* triggers drawing using in-packet vertex data */
1998         case PACKET3_3D_DRAW_VBUF_2:
1999                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2000                 r = r100_cs_track_check(p->rdev, track);
2001                 if (r)
2002                         return r;
2003                 break;
2004                 /* triggers drawing of vertex buffers setup elsewhere */
2005         case PACKET3_3D_DRAW_INDX_2:
2006                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2007                 r = r100_cs_track_check(p->rdev, track);
2008                 if (r)
2009                         return r;
2010                 break;
2011                 /* triggers drawing using indices to vertex buffer */
2012         case PACKET3_3D_DRAW_VBUF:
2013                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2014                 r = r100_cs_track_check(p->rdev, track);
2015                 if (r)
2016                         return r;
2017                 break;
2018                 /* triggers drawing of vertex buffers setup elsewhere */
2019         case PACKET3_3D_DRAW_INDX:
2020                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2021                 r = r100_cs_track_check(p->rdev, track);
2022                 if (r)
2023                         return r;
2024                 break;
2025                 /* triggers drawing using indices to vertex buffer */
2026         case PACKET3_3D_CLEAR_HIZ:
2027         case PACKET3_3D_CLEAR_ZMASK:
2028                 if (p->rdev->hyperz_filp != p->filp)
2029                         return -EINVAL;
2030                 break;
2031         case PACKET3_NOP:
2032                 break;
2033         default:
2034                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2035                 return -EINVAL;
2036         }
2037         return 0;
2038 }
2039
2040 int r100_cs_parse(struct radeon_cs_parser *p)
2041 {
2042         struct radeon_cs_packet pkt;
2043         struct r100_cs_track *track;
2044         int r;
2045
2046         track = kzalloc(sizeof(*track), GFP_KERNEL);
2047         if (!track)
2048                 return -ENOMEM;
2049         r100_cs_track_clear(p->rdev, track);
2050         p->track = track;
2051         do {
2052                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2053                 if (r) {
2054                         return r;
2055                 }
2056                 p->idx += pkt.count + 2;
2057                 switch (pkt.type) {
2058                 case RADEON_PACKET_TYPE0:
2059                         if (p->rdev->family >= CHIP_R200)
2060                                 r = r100_cs_parse_packet0(p, &pkt,
2061                                         p->rdev->config.r100.reg_safe_bm,
2062                                         p->rdev->config.r100.reg_safe_bm_size,
2063                                         &r200_packet0_check);
2064                         else
2065                                 r = r100_cs_parse_packet0(p, &pkt,
2066                                         p->rdev->config.r100.reg_safe_bm,
2067                                         p->rdev->config.r100.reg_safe_bm_size,
2068                                         &r100_packet0_check);
2069                         break;
2070                 case RADEON_PACKET_TYPE2:
2071                         break;
2072                 case RADEON_PACKET_TYPE3:
2073                         r = r100_packet3_check(p, &pkt);
2074                         break;
2075                 default:
2076                         DRM_ERROR("Unknown packet type %d !\n",
2077                                   pkt.type);
2078                         return -EINVAL;
2079                 }
2080                 if (r)
2081                         return r;
2082         } while (p->idx < p->chunk_ib->length_dw);
2083         return 0;
2084 }
2085
2086 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2087 {
2088         DRM_ERROR("pitch                      %d\n", t->pitch);
2089         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2090         DRM_ERROR("width                      %d\n", t->width);
2091         DRM_ERROR("width_11                   %d\n", t->width_11);
2092         DRM_ERROR("height                     %d\n", t->height);
2093         DRM_ERROR("height_11                  %d\n", t->height_11);
2094         DRM_ERROR("num levels                 %d\n", t->num_levels);
2095         DRM_ERROR("depth                      %d\n", t->txdepth);
2096         DRM_ERROR("bpp                        %d\n", t->cpp);
2097         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2098         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2099         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2100         DRM_ERROR("compress format            %d\n", t->compress_format);
2101 }
2102
2103 static int r100_track_compress_size(int compress_format, int w, int h)
2104 {
2105         int block_width, block_height, block_bytes;
2106         int wblocks, hblocks;
2107         int min_wblocks;
2108         int sz;
2109
2110         block_width = 4;
2111         block_height = 4;
2112
2113         switch (compress_format) {
2114         case R100_TRACK_COMP_DXT1:
2115                 block_bytes = 8;
2116                 min_wblocks = 4;
2117                 break;
2118         default:
2119         case R100_TRACK_COMP_DXT35:
2120                 block_bytes = 16;
2121                 min_wblocks = 2;
2122                 break;
2123         }
2124
2125         hblocks = (h + block_height - 1) / block_height;
2126         wblocks = (w + block_width - 1) / block_width;
2127         if (wblocks < min_wblocks)
2128                 wblocks = min_wblocks;
2129         sz = wblocks * hblocks * block_bytes;
2130         return sz;
2131 }
2132
2133 static int r100_cs_track_cube(struct radeon_device *rdev,
2134                               struct r100_cs_track *track, unsigned idx)
2135 {
2136         unsigned face, w, h;
2137         struct radeon_bo *cube_robj;
2138         unsigned long size;
2139         unsigned compress_format = track->textures[idx].compress_format;
2140
2141         for (face = 0; face < 5; face++) {
2142                 cube_robj = track->textures[idx].cube_info[face].robj;
2143                 w = track->textures[idx].cube_info[face].width;
2144                 h = track->textures[idx].cube_info[face].height;
2145
2146                 if (compress_format) {
2147                         size = r100_track_compress_size(compress_format, w, h);
2148                 } else
2149                         size = w * h;
2150                 size *= track->textures[idx].cpp;
2151
2152                 size += track->textures[idx].cube_info[face].offset;
2153
2154                 if (size > radeon_bo_size(cube_robj)) {
2155                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2156                                   size, radeon_bo_size(cube_robj));
2157                         r100_cs_track_texture_print(&track->textures[idx]);
2158                         return -1;
2159                 }
2160         }
2161         return 0;
2162 }
2163
2164 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2165                                        struct r100_cs_track *track)
2166 {
2167         struct radeon_bo *robj;
2168         unsigned long size;
2169         unsigned u, i, w, h, d;
2170         int ret;
2171
2172         for (u = 0; u < track->num_texture; u++) {
2173                 if (!track->textures[u].enabled)
2174                         continue;
2175                 if (track->textures[u].lookup_disable)
2176                         continue;
2177                 robj = track->textures[u].robj;
2178                 if (robj == NULL) {
2179                         DRM_ERROR("No texture bound to unit %u\n", u);
2180                         return -EINVAL;
2181                 }
2182                 size = 0;
2183                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2184                         if (track->textures[u].use_pitch) {
2185                                 if (rdev->family < CHIP_R300)
2186                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2187                                 else
2188                                         w = track->textures[u].pitch / (1 << i);
2189                         } else {
2190                                 w = track->textures[u].width;
2191                                 if (rdev->family >= CHIP_RV515)
2192                                         w |= track->textures[u].width_11;
2193                                 w = w / (1 << i);
2194                                 if (track->textures[u].roundup_w)
2195                                         w = roundup_pow_of_two(w);
2196                         }
2197                         h = track->textures[u].height;
2198                         if (rdev->family >= CHIP_RV515)
2199                                 h |= track->textures[u].height_11;
2200                         h = h / (1 << i);
2201                         if (track->textures[u].roundup_h)
2202                                 h = roundup_pow_of_two(h);
2203                         if (track->textures[u].tex_coord_type == 1) {
2204                                 d = (1 << track->textures[u].txdepth) / (1 << i);
2205                                 if (!d)
2206                                         d = 1;
2207                         } else {
2208                                 d = 1;
2209                         }
2210                         if (track->textures[u].compress_format) {
2211
2212                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2213                                 /* compressed textures are block based */
2214                         } else
2215                                 size += w * h * d;
2216                 }
2217                 size *= track->textures[u].cpp;
2218
2219                 switch (track->textures[u].tex_coord_type) {
2220                 case 0:
2221                 case 1:
2222                         break;
2223                 case 2:
2224                         if (track->separate_cube) {
2225                                 ret = r100_cs_track_cube(rdev, track, u);
2226                                 if (ret)
2227                                         return ret;
2228                         } else
2229                                 size *= 6;
2230                         break;
2231                 default:
2232                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2233                                   "%u\n", track->textures[u].tex_coord_type, u);
2234                         return -EINVAL;
2235                 }
2236                 if (size > radeon_bo_size(robj)) {
2237                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2238                                   "%lu\n", u, size, radeon_bo_size(robj));
2239                         r100_cs_track_texture_print(&track->textures[u]);
2240                         return -EINVAL;
2241                 }
2242         }
2243         return 0;
2244 }
2245
2246 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2247 {
2248         unsigned i;
2249         unsigned long size;
2250         unsigned prim_walk;
2251         unsigned nverts;
2252         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2253
2254         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2255             !track->blend_read_enable)
2256                 num_cb = 0;
2257
2258         for (i = 0; i < num_cb; i++) {
2259                 if (track->cb[i].robj == NULL) {
2260                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2261                         return -EINVAL;
2262                 }
2263                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2264                 size += track->cb[i].offset;
2265                 if (size > radeon_bo_size(track->cb[i].robj)) {
2266                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2267                                   "(need %lu have %lu) !\n", i, size,
2268                                   radeon_bo_size(track->cb[i].robj));
2269                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2270                                   i, track->cb[i].pitch, track->cb[i].cpp,
2271                                   track->cb[i].offset, track->maxy);
2272                         return -EINVAL;
2273                 }
2274         }
2275         track->cb_dirty = false;
2276
2277         if (track->zb_dirty && track->z_enabled) {
2278                 if (track->zb.robj == NULL) {
2279                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2280                         return -EINVAL;
2281                 }
2282                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2283                 size += track->zb.offset;
2284                 if (size > radeon_bo_size(track->zb.robj)) {
2285                         DRM_ERROR("[drm] Buffer too small for z buffer "
2286                                   "(need %lu have %lu) !\n", size,
2287                                   radeon_bo_size(track->zb.robj));
2288                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2289                                   track->zb.pitch, track->zb.cpp,
2290                                   track->zb.offset, track->maxy);
2291                         return -EINVAL;
2292                 }
2293         }
2294         track->zb_dirty = false;
2295
2296         if (track->aa_dirty && track->aaresolve) {
2297                 if (track->aa.robj == NULL) {
2298                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2299                         return -EINVAL;
2300                 }
2301                 /* I believe the format comes from colorbuffer0. */
2302                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2303                 size += track->aa.offset;
2304                 if (size > radeon_bo_size(track->aa.robj)) {
2305                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2306                                   "(need %lu have %lu) !\n", i, size,
2307                                   radeon_bo_size(track->aa.robj));
2308                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2309                                   i, track->aa.pitch, track->cb[0].cpp,
2310                                   track->aa.offset, track->maxy);
2311                         return -EINVAL;
2312                 }
2313         }
2314         track->aa_dirty = false;
2315
2316         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2317         if (track->vap_vf_cntl & (1 << 14)) {
2318                 nverts = track->vap_alt_nverts;
2319         } else {
2320                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2321         }
2322         switch (prim_walk) {
2323         case 1:
2324                 for (i = 0; i < track->num_arrays; i++) {
2325                         size = track->arrays[i].esize * track->max_indx * 4UL;
2326                         if (track->arrays[i].robj == NULL) {
2327                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2328                                           "bound\n", prim_walk, i);
2329                                 return -EINVAL;
2330                         }
2331                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2332                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2333                                         "need %lu dwords have %lu dwords\n",
2334                                         prim_walk, i, size >> 2,
2335                                         radeon_bo_size(track->arrays[i].robj)
2336                                         >> 2);
2337                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2338                                 return -EINVAL;
2339                         }
2340                 }
2341                 break;
2342         case 2:
2343                 for (i = 0; i < track->num_arrays; i++) {
2344                         size = track->arrays[i].esize * (nverts - 1) * 4UL;
2345                         if (track->arrays[i].robj == NULL) {
2346                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2347                                           "bound\n", prim_walk, i);
2348                                 return -EINVAL;
2349                         }
2350                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2351                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2352                                         "need %lu dwords have %lu dwords\n",
2353                                         prim_walk, i, size >> 2,
2354                                         radeon_bo_size(track->arrays[i].robj)
2355                                         >> 2);
2356                                 return -EINVAL;
2357                         }
2358                 }
2359                 break;
2360         case 3:
2361                 size = track->vtx_size * nverts;
2362                 if (size != track->immd_dwords) {
2363                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2364                                   track->immd_dwords, size);
2365                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2366                                   nverts, track->vtx_size);
2367                         return -EINVAL;
2368                 }
2369                 break;
2370         default:
2371                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2372                           prim_walk);
2373                 return -EINVAL;
2374         }
2375
2376         if (track->tex_dirty) {
2377                 track->tex_dirty = false;
2378                 return r100_cs_track_texture_check(rdev, track);
2379         }
2380         return 0;
2381 }
2382
2383 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2384 {
2385         unsigned i, face;
2386
2387         track->cb_dirty = true;
2388         track->zb_dirty = true;
2389         track->tex_dirty = true;
2390         track->aa_dirty = true;
2391
2392         if (rdev->family < CHIP_R300) {
2393                 track->num_cb = 1;
2394                 if (rdev->family <= CHIP_RS200)
2395                         track->num_texture = 3;
2396                 else
2397                         track->num_texture = 6;
2398                 track->maxy = 2048;
2399                 track->separate_cube = true;
2400         } else {
2401                 track->num_cb = 4;
2402                 track->num_texture = 16;
2403                 track->maxy = 4096;
2404                 track->separate_cube = false;
2405                 track->aaresolve = false;
2406                 track->aa.robj = NULL;
2407         }
2408
2409         for (i = 0; i < track->num_cb; i++) {
2410                 track->cb[i].robj = NULL;
2411                 track->cb[i].pitch = 8192;
2412                 track->cb[i].cpp = 16;
2413                 track->cb[i].offset = 0;
2414         }
2415         track->z_enabled = true;
2416         track->zb.robj = NULL;
2417         track->zb.pitch = 8192;
2418         track->zb.cpp = 4;
2419         track->zb.offset = 0;
2420         track->vtx_size = 0x7F;
2421         track->immd_dwords = 0xFFFFFFFFUL;
2422         track->num_arrays = 11;
2423         track->max_indx = 0x00FFFFFFUL;
2424         for (i = 0; i < track->num_arrays; i++) {
2425                 track->arrays[i].robj = NULL;
2426                 track->arrays[i].esize = 0x7F;
2427         }
2428         for (i = 0; i < track->num_texture; i++) {
2429                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2430                 track->textures[i].pitch = 16536;
2431                 track->textures[i].width = 16536;
2432                 track->textures[i].height = 16536;
2433                 track->textures[i].width_11 = 1 << 11;
2434                 track->textures[i].height_11 = 1 << 11;
2435                 track->textures[i].num_levels = 12;
2436                 if (rdev->family <= CHIP_RS200) {
2437                         track->textures[i].tex_coord_type = 0;
2438                         track->textures[i].txdepth = 0;
2439                 } else {
2440                         track->textures[i].txdepth = 16;
2441                         track->textures[i].tex_coord_type = 1;
2442                 }
2443                 track->textures[i].cpp = 64;
2444                 track->textures[i].robj = NULL;
2445                 /* CS IB emission code makes sure texture unit are disabled */
2446                 track->textures[i].enabled = false;
2447                 track->textures[i].lookup_disable = false;
2448                 track->textures[i].roundup_w = true;
2449                 track->textures[i].roundup_h = true;
2450                 if (track->separate_cube)
2451                         for (face = 0; face < 5; face++) {
2452                                 track->textures[i].cube_info[face].robj = NULL;
2453                                 track->textures[i].cube_info[face].width = 16536;
2454                                 track->textures[i].cube_info[face].height = 16536;
2455                                 track->textures[i].cube_info[face].offset = 0;
2456                         }
2457         }
2458 }
2459
2460 /*
2461  * Global GPU functions
2462  */
2463 static void r100_errata(struct radeon_device *rdev)
2464 {
2465         rdev->pll_errata = 0;
2466
2467         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2468                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2469         }
2470
2471         if (rdev->family == CHIP_RV100 ||
2472             rdev->family == CHIP_RS100 ||
2473             rdev->family == CHIP_RS200) {
2474                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2475         }
2476 }
2477
2478 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2479 {
2480         unsigned i;
2481         uint32_t tmp;
2482
2483         for (i = 0; i < rdev->usec_timeout; i++) {
2484                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2485                 if (tmp >= n) {
2486                         return 0;
2487                 }
2488                 udelay(1);
2489         }
2490         return -1;
2491 }
2492
2493 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2494 {
2495         unsigned i;
2496         uint32_t tmp;
2497
2498         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2499                 pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n");
2500         }
2501         for (i = 0; i < rdev->usec_timeout; i++) {
2502                 tmp = RREG32(RADEON_RBBM_STATUS);
2503                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2504                         return 0;
2505                 }
2506                 udelay(1);
2507         }
2508         return -1;
2509 }
2510
2511 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2512 {
2513         unsigned i;
2514         uint32_t tmp;
2515
2516         for (i = 0; i < rdev->usec_timeout; i++) {
2517                 /* read MC_STATUS */
2518                 tmp = RREG32(RADEON_MC_STATUS);
2519                 if (tmp & RADEON_MC_IDLE) {
2520                         return 0;
2521                 }
2522                 udelay(1);
2523         }
2524         return -1;
2525 }
2526
2527 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2528 {
2529         u32 rbbm_status;
2530
2531         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2532         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2533                 radeon_ring_lockup_update(rdev, ring);
2534                 return false;
2535         }
2536         return radeon_ring_test_lockup(rdev, ring);
2537 }
2538
2539 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2540 void r100_enable_bm(struct radeon_device *rdev)
2541 {
2542         uint32_t tmp;
2543         /* Enable bus mastering */
2544         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2545         WREG32(RADEON_BUS_CNTL, tmp);
2546 }
2547
2548 void r100_bm_disable(struct radeon_device *rdev)
2549 {
2550         u32 tmp;
2551
2552         /* disable bus mastering */
2553         tmp = RREG32(R_000030_BUS_CNTL);
2554         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2555         mdelay(1);
2556         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2557         mdelay(1);
2558         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2559         tmp = RREG32(RADEON_BUS_CNTL);
2560         mdelay(1);
2561         pci_clear_master(rdev->pdev);
2562         mdelay(1);
2563 }
2564
2565 int r100_asic_reset(struct radeon_device *rdev, bool hard)
2566 {
2567         struct r100_mc_save save;
2568         u32 status, tmp;
2569         int ret = 0;
2570
2571         status = RREG32(R_000E40_RBBM_STATUS);
2572         if (!G_000E40_GUI_ACTIVE(status)) {
2573                 return 0;
2574         }
2575         r100_mc_stop(rdev, &save);
2576         status = RREG32(R_000E40_RBBM_STATUS);
2577         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2578         /* stop CP */
2579         WREG32(RADEON_CP_CSQ_CNTL, 0);
2580         tmp = RREG32(RADEON_CP_RB_CNTL);
2581         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2582         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2583         WREG32(RADEON_CP_RB_WPTR, 0);
2584         WREG32(RADEON_CP_RB_CNTL, tmp);
2585         /* save PCI state */
2586         pci_save_state(rdev->pdev);
2587         /* disable bus mastering */
2588         r100_bm_disable(rdev);
2589         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2590                                         S_0000F0_SOFT_RESET_RE(1) |
2591                                         S_0000F0_SOFT_RESET_PP(1) |
2592                                         S_0000F0_SOFT_RESET_RB(1));
2593         RREG32(R_0000F0_RBBM_SOFT_RESET);
2594         mdelay(500);
2595         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2596         mdelay(1);
2597         status = RREG32(R_000E40_RBBM_STATUS);
2598         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2599         /* reset CP */
2600         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2601         RREG32(R_0000F0_RBBM_SOFT_RESET);
2602         mdelay(500);
2603         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2604         mdelay(1);
2605         status = RREG32(R_000E40_RBBM_STATUS);
2606         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2607         /* restore PCI & busmastering */
2608         pci_restore_state(rdev->pdev);
2609         r100_enable_bm(rdev);
2610         /* Check if GPU is idle */
2611         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2612                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2613                 dev_err(rdev->dev, "failed to reset GPU\n");
2614                 ret = -1;
2615         } else
2616                 dev_info(rdev->dev, "GPU reset succeed\n");
2617         r100_mc_resume(rdev, &save);
2618         return ret;
2619 }
2620
2621 void r100_set_common_regs(struct radeon_device *rdev)
2622 {
2623         bool force_dac2 = false;
2624         u32 tmp;
2625
2626         /* set these so they don't interfere with anything */
2627         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2628         WREG32(RADEON_SUBPIC_CNTL, 0);
2629         WREG32(RADEON_VIPH_CONTROL, 0);
2630         WREG32(RADEON_I2C_CNTL_1, 0);
2631         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2632         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2633         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2634
2635         /* always set up dac2 on rn50 and some rv100 as lots
2636          * of servers seem to wire it up to a VGA port but
2637          * don't report it in the bios connector
2638          * table.
2639          */
2640         switch (rdev->pdev->device) {
2641                 /* RN50 */
2642         case 0x515e:
2643         case 0x5969:
2644                 force_dac2 = true;
2645                 break;
2646                 /* RV100*/
2647         case 0x5159:
2648         case 0x515a:
2649                 /* DELL triple head servers */
2650                 if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2651                     ((rdev->pdev->subsystem_device == 0x016c) ||
2652                      (rdev->pdev->subsystem_device == 0x016d) ||
2653                      (rdev->pdev->subsystem_device == 0x016e) ||
2654                      (rdev->pdev->subsystem_device == 0x016f) ||
2655                      (rdev->pdev->subsystem_device == 0x0170) ||
2656                      (rdev->pdev->subsystem_device == 0x017d) ||
2657                      (rdev->pdev->subsystem_device == 0x017e) ||
2658                      (rdev->pdev->subsystem_device == 0x0183) ||
2659                      (rdev->pdev->subsystem_device == 0x018a) ||
2660                      (rdev->pdev->subsystem_device == 0x019a)))
2661                         force_dac2 = true;
2662                 break;
2663         }
2664
2665         if (force_dac2) {
2666                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2667                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2668                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2669
2670                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2671                    enable it, even it's detected.
2672                 */
2673
2674                 /* force it to crtc0 */
2675                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2676                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2677                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2678
2679                 /* set up the TV DAC */
2680                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2681                                  RADEON_TV_DAC_STD_MASK |
2682                                  RADEON_TV_DAC_RDACPD |
2683                                  RADEON_TV_DAC_GDACPD |
2684                                  RADEON_TV_DAC_BDACPD |
2685                                  RADEON_TV_DAC_BGADJ_MASK |
2686                                  RADEON_TV_DAC_DACADJ_MASK);
2687                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2688                                 RADEON_TV_DAC_NHOLD |
2689                                 RADEON_TV_DAC_STD_PS2 |
2690                                 (0x58 << 16));
2691
2692                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2693                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2694                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2695         }
2696
2697         /* switch PM block to ACPI mode */
2698         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2699         tmp &= ~RADEON_PM_MODE_SEL;
2700         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2701
2702 }
2703
2704 /*
2705  * VRAM info
2706  */
2707 static void r100_vram_get_type(struct radeon_device *rdev)
2708 {
2709         uint32_t tmp;
2710
2711         rdev->mc.vram_is_ddr = false;
2712         if (rdev->flags & RADEON_IS_IGP)
2713                 rdev->mc.vram_is_ddr = true;
2714         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2715                 rdev->mc.vram_is_ddr = true;
2716         if ((rdev->family == CHIP_RV100) ||
2717             (rdev->family == CHIP_RS100) ||
2718             (rdev->family == CHIP_RS200)) {
2719                 tmp = RREG32(RADEON_MEM_CNTL);
2720                 if (tmp & RV100_HALF_MODE) {
2721                         rdev->mc.vram_width = 32;
2722                 } else {
2723                         rdev->mc.vram_width = 64;
2724                 }
2725                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2726                         rdev->mc.vram_width /= 4;
2727                         rdev->mc.vram_is_ddr = true;
2728                 }
2729         } else if (rdev->family <= CHIP_RV280) {
2730                 tmp = RREG32(RADEON_MEM_CNTL);
2731                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2732                         rdev->mc.vram_width = 128;
2733                 } else {
2734                         rdev->mc.vram_width = 64;
2735                 }
2736         } else {
2737                 /* newer IGPs */
2738                 rdev->mc.vram_width = 128;
2739         }
2740 }
2741
2742 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2743 {
2744         u32 aper_size;
2745         u8 byte;
2746
2747         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2748
2749         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2750          * that is has the 2nd generation multifunction PCI interface
2751          */
2752         if (rdev->family == CHIP_RV280 ||
2753             rdev->family >= CHIP_RV350) {
2754                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2755                        ~RADEON_HDP_APER_CNTL);
2756                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2757                 return aper_size * 2;
2758         }
2759
2760         /* Older cards have all sorts of funny issues to deal with. First
2761          * check if it's a multifunction card by reading the PCI config
2762          * header type... Limit those to one aperture size
2763          */
2764         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2765         if (byte & 0x80) {
2766                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2767                 DRM_INFO("Limiting VRAM to one aperture\n");
2768                 return aper_size;
2769         }
2770
2771         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2772          * have set it up. We don't write this as it's broken on some ASICs but
2773          * we expect the BIOS to have done the right thing (might be too optimistic...)
2774          */
2775         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2776                 return aper_size * 2;
2777         return aper_size;
2778 }
2779
2780 void r100_vram_init_sizes(struct radeon_device *rdev)
2781 {
2782         u64 config_aper_size;
2783
2784         /* work out accessible VRAM */
2785         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2786         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2787         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2788         /* FIXME we don't use the second aperture yet when we could use it */
2789         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2790                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2791         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2792         if (rdev->flags & RADEON_IS_IGP) {
2793                 uint32_t tom;
2794                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2795                 tom = RREG32(RADEON_NB_TOM);
2796                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2797                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2798                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2799         } else {
2800                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2801                 /* Some production boards of m6 will report 0
2802                  * if it's 8 MB
2803                  */
2804                 if (rdev->mc.real_vram_size == 0) {
2805                         rdev->mc.real_vram_size = 8192 * 1024;
2806                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2807                 }
2808                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2809                  * Novell bug 204882 + along with lots of ubuntu ones
2810                  */
2811                 if (rdev->mc.aper_size > config_aper_size)
2812                         config_aper_size = rdev->mc.aper_size;
2813
2814                 if (config_aper_size > rdev->mc.real_vram_size)
2815                         rdev->mc.mc_vram_size = config_aper_size;
2816                 else
2817                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2818         }
2819 }
2820
2821 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2822 {
2823         uint32_t temp;
2824
2825         temp = RREG32(RADEON_CONFIG_CNTL);
2826         if (!state) {
2827                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2828                 temp |= RADEON_CFG_VGA_IO_DIS;
2829         } else {
2830                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2831         }
2832         WREG32(RADEON_CONFIG_CNTL, temp);
2833 }
2834
2835 static void r100_mc_init(struct radeon_device *rdev)
2836 {
2837         u64 base;
2838
2839         r100_vram_get_type(rdev);
2840         r100_vram_init_sizes(rdev);
2841         base = rdev->mc.aper_base;
2842         if (rdev->flags & RADEON_IS_IGP)
2843                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2844         radeon_vram_location(rdev, &rdev->mc, base);
2845         rdev->mc.gtt_base_align = 0;
2846         if (!(rdev->flags & RADEON_IS_AGP))
2847                 radeon_gtt_location(rdev, &rdev->mc);
2848         radeon_update_bandwidth_info(rdev);
2849 }
2850
2851
2852 /*
2853  * Indirect registers accessor
2854  */
2855 void r100_pll_errata_after_index(struct radeon_device *rdev)
2856 {
2857         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2858                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2859                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2860         }
2861 }
2862
2863 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2864 {
2865         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2866          * or the chip could hang on a subsequent access
2867          */
2868         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2869                 mdelay(5);
2870         }
2871
2872         /* This function is required to workaround a hardware bug in some (all?)
2873          * revisions of the R300.  This workaround should be called after every
2874          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2875          * may not be correct.
2876          */
2877         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2878                 uint32_t save, tmp;
2879
2880                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2881                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2882                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2883                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2884                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2885         }
2886 }
2887
2888 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2889 {
2890         unsigned long flags;
2891         uint32_t data;
2892
2893         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2894         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2895         r100_pll_errata_after_index(rdev);
2896         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2897         r100_pll_errata_after_data(rdev);
2898         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2899         return data;
2900 }
2901
2902 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2903 {
2904         unsigned long flags;
2905
2906         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2907         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2908         r100_pll_errata_after_index(rdev);
2909         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2910         r100_pll_errata_after_data(rdev);
2911         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2912 }
2913
2914 static void r100_set_safe_registers(struct radeon_device *rdev)
2915 {
2916         if (ASIC_IS_RN50(rdev)) {
2917                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2918                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2919         } else if (rdev->family < CHIP_R200) {
2920                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2921                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2922         } else {
2923                 r200_set_safe_registers(rdev);
2924         }
2925 }
2926
2927 /*
2928  * Debugfs info
2929  */
2930 #if defined(CONFIG_DEBUG_FS)
2931 static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused)
2932 {
2933         struct radeon_device *rdev = m->private;
2934         uint32_t reg, value;
2935         unsigned i;
2936
2937         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2938         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2939         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2940         for (i = 0; i < 64; i++) {
2941                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2942                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2943                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2944                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2945                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2946         }
2947         return 0;
2948 }
2949
2950 static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused)
2951 {
2952         struct radeon_device *rdev = m->private;
2953         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2954         uint32_t rdp, wdp;
2955         unsigned count, i, j;
2956
2957         radeon_ring_free_size(rdev, ring);
2958         rdp = RREG32(RADEON_CP_RB_RPTR);
2959         wdp = RREG32(RADEON_CP_RB_WPTR);
2960         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2961         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2962         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2963         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2964         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2965         seq_printf(m, "%u dwords in ring\n", count);
2966         if (ring->ready) {
2967                 for (j = 0; j <= count; j++) {
2968                         i = (rdp + j) & ring->ptr_mask;
2969                         seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2970                 }
2971         }
2972         return 0;
2973 }
2974
2975
2976 static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused)
2977 {
2978         struct radeon_device *rdev = m->private;
2979         uint32_t csq_stat, csq2_stat, tmp;
2980         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2981         unsigned i;
2982
2983         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2984         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2985         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2986         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2987         r_rptr = (csq_stat >> 0) & 0x3ff;
2988         r_wptr = (csq_stat >> 10) & 0x3ff;
2989         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2990         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2991         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2992         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2993         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2994         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2995         seq_printf(m, "Ring rptr %u\n", r_rptr);
2996         seq_printf(m, "Ring wptr %u\n", r_wptr);
2997         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2998         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2999         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3000         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3001         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3002          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3003         seq_printf(m, "Ring fifo:\n");
3004         for (i = 0; i < 256; i++) {
3005                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3006                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3007                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3008         }
3009         seq_printf(m, "Indirect1 fifo:\n");
3010         for (i = 256; i <= 512; i++) {
3011                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3012                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3013                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3014         }
3015         seq_printf(m, "Indirect2 fifo:\n");
3016         for (i = 640; i < ib1_wptr; i++) {
3017                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3018                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3019                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3020         }
3021         return 0;
3022 }
3023
3024 static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused)
3025 {
3026         struct radeon_device *rdev = m->private;
3027         uint32_t tmp;
3028
3029         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3030         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3031         tmp = RREG32(RADEON_MC_FB_LOCATION);
3032         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3033         tmp = RREG32(RADEON_BUS_CNTL);
3034         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3035         tmp = RREG32(RADEON_MC_AGP_LOCATION);
3036         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3037         tmp = RREG32(RADEON_AGP_BASE);
3038         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3039         tmp = RREG32(RADEON_HOST_PATH_CNTL);
3040         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3041         tmp = RREG32(0x01D0);
3042         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3043         tmp = RREG32(RADEON_AIC_LO_ADDR);
3044         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3045         tmp = RREG32(RADEON_AIC_HI_ADDR);
3046         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3047         tmp = RREG32(0x01E4);
3048         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3049         return 0;
3050 }
3051
3052 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info);
3053 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info);
3054 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo);
3055 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info);
3056
3057 #endif
3058
3059 void  r100_debugfs_rbbm_init(struct radeon_device *rdev)
3060 {
3061 #if defined(CONFIG_DEBUG_FS)
3062         struct dentry *root = rdev->ddev->primary->debugfs_root;
3063
3064         debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
3065                             &r100_debugfs_rbbm_info_fops);
3066 #endif
3067 }
3068
3069 void r100_debugfs_cp_init(struct radeon_device *rdev)
3070 {
3071 #if defined(CONFIG_DEBUG_FS)
3072         struct dentry *root = rdev->ddev->primary->debugfs_root;
3073
3074         debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
3075                             &r100_debugfs_cp_ring_info_fops);
3076         debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
3077                             &r100_debugfs_cp_csq_fifo_fops);
3078 #endif
3079 }
3080
3081 void  r100_debugfs_mc_info_init(struct radeon_device *rdev)
3082 {
3083 #if defined(CONFIG_DEBUG_FS)
3084         struct dentry *root = rdev->ddev->primary->debugfs_root;
3085
3086         debugfs_create_file("r100_mc_info", 0444, root, rdev,
3087                             &r100_debugfs_mc_info_fops);
3088 #endif
3089 }
3090
3091 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3092                          uint32_t tiling_flags, uint32_t pitch,
3093                          uint32_t offset, uint32_t obj_size)
3094 {
3095         int surf_index = reg * 16;
3096         int flags = 0;
3097
3098         if (rdev->family <= CHIP_RS200) {
3099                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3100                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3101                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
3102                 if (tiling_flags & RADEON_TILING_MACRO)
3103                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
3104                 /* setting pitch to 0 disables tiling */
3105                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3106                                 == 0)
3107                         pitch = 0;
3108         } else if (rdev->family <= CHIP_RV280) {
3109                 if (tiling_flags & (RADEON_TILING_MACRO))
3110                         flags |= R200_SURF_TILE_COLOR_MACRO;
3111                 if (tiling_flags & RADEON_TILING_MICRO)
3112                         flags |= R200_SURF_TILE_COLOR_MICRO;
3113         } else {
3114                 if (tiling_flags & RADEON_TILING_MACRO)
3115                         flags |= R300_SURF_TILE_MACRO;
3116                 if (tiling_flags & RADEON_TILING_MICRO)
3117                         flags |= R300_SURF_TILE_MICRO;
3118         }
3119
3120         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3121                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3122         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3123                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3124
3125         /* r100/r200 divide by 16 */
3126         if (rdev->family < CHIP_R300)
3127                 flags |= pitch / 16;
3128         else
3129                 flags |= pitch / 8;
3130
3131
3132         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3133         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3134         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3135         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3136         return 0;
3137 }
3138
3139 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3140 {
3141         int surf_index = reg * 16;
3142         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3143 }
3144
3145 void r100_bandwidth_update(struct radeon_device *rdev)
3146 {
3147         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3148         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3149         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
3150         fixed20_12 crit_point_ff = {0};
3151         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3152         fixed20_12 memtcas_ff[8] = {
3153                 dfixed_init(1),
3154                 dfixed_init(2),
3155                 dfixed_init(3),
3156                 dfixed_init(0),
3157                 dfixed_init_half(1),
3158                 dfixed_init_half(2),
3159                 dfixed_init(0),
3160         };
3161         fixed20_12 memtcas_rs480_ff[8] = {
3162                 dfixed_init(0),
3163                 dfixed_init(1),
3164                 dfixed_init(2),
3165                 dfixed_init(3),
3166                 dfixed_init(0),
3167                 dfixed_init_half(1),
3168                 dfixed_init_half(2),
3169                 dfixed_init_half(3),
3170         };
3171         fixed20_12 memtcas2_ff[8] = {
3172                 dfixed_init(0),
3173                 dfixed_init(1),
3174                 dfixed_init(2),
3175                 dfixed_init(3),
3176                 dfixed_init(4),
3177                 dfixed_init(5),
3178                 dfixed_init(6),
3179                 dfixed_init(7),
3180         };
3181         fixed20_12 memtrbs[8] = {
3182                 dfixed_init(1),
3183                 dfixed_init_half(1),
3184                 dfixed_init(2),
3185                 dfixed_init_half(2),
3186                 dfixed_init(3),
3187                 dfixed_init_half(3),
3188                 dfixed_init(4),
3189                 dfixed_init_half(4)
3190         };
3191         fixed20_12 memtrbs_r4xx[8] = {
3192                 dfixed_init(4),
3193                 dfixed_init(5),
3194                 dfixed_init(6),
3195                 dfixed_init(7),
3196                 dfixed_init(8),
3197                 dfixed_init(9),
3198                 dfixed_init(10),
3199                 dfixed_init(11)
3200         };
3201         fixed20_12 min_mem_eff;
3202         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3203         fixed20_12 cur_latency_mclk, cur_latency_sclk;
3204         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
3205                 disp_drain_rate2, read_return_rate;
3206         fixed20_12 time_disp1_drop_priority;
3207         int c;
3208         int cur_size = 16;       /* in octawords */
3209         int critical_point = 0, critical_point2;
3210 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
3211         int stop_req, max_stop_req;
3212         struct drm_display_mode *mode1 = NULL;
3213         struct drm_display_mode *mode2 = NULL;
3214         uint32_t pixel_bytes1 = 0;
3215         uint32_t pixel_bytes2 = 0;
3216
3217         /* Guess line buffer size to be 8192 pixels */
3218         u32 lb_size = 8192;
3219
3220         if (!rdev->mode_info.mode_config_initialized)
3221                 return;
3222
3223         radeon_update_display_priority(rdev);
3224
3225         if (rdev->mode_info.crtcs[0]->base.enabled) {
3226                 const struct drm_framebuffer *fb =
3227                         rdev->mode_info.crtcs[0]->base.primary->fb;
3228
3229                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3230                 pixel_bytes1 = fb->format->cpp[0];
3231         }
3232         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3233                 if (rdev->mode_info.crtcs[1]->base.enabled) {
3234                         const struct drm_framebuffer *fb =
3235                                 rdev->mode_info.crtcs[1]->base.primary->fb;
3236
3237                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3238                         pixel_bytes2 = fb->format->cpp[0];
3239                 }
3240         }
3241
3242         min_mem_eff.full = dfixed_const_8(0);
3243         /* get modes */
3244         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3245                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3246                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3247                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3248                 /* check crtc enables */
3249                 if (mode2)
3250                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3251                 if (mode1)
3252                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3253                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3254         }
3255
3256         /*
3257          * determine is there is enough bw for current mode
3258          */
3259         sclk_ff = rdev->pm.sclk;
3260         mclk_ff = rdev->pm.mclk;
3261
3262         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3263         temp_ff.full = dfixed_const(temp);
3264         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3265
3266         pix_clk.full = 0;
3267         pix_clk2.full = 0;
3268         peak_disp_bw.full = 0;
3269         if (mode1) {
3270                 temp_ff.full = dfixed_const(1000);
3271                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3272                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3273                 temp_ff.full = dfixed_const(pixel_bytes1);
3274                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3275         }
3276         if (mode2) {
3277                 temp_ff.full = dfixed_const(1000);
3278                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3279                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3280                 temp_ff.full = dfixed_const(pixel_bytes2);
3281                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3282         }
3283
3284         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3285         if (peak_disp_bw.full >= mem_bw.full) {
3286                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3287                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3288         }
3289
3290         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
3291         temp = RREG32(RADEON_MEM_TIMING_CNTL);
3292         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3293                 mem_trcd = ((temp >> 2) & 0x3) + 1;
3294                 mem_trp  = ((temp & 0x3)) + 1;
3295                 mem_tras = ((temp & 0x70) >> 4) + 1;
3296         } else if (rdev->family == CHIP_R300 ||
3297                    rdev->family == CHIP_R350) { /* r300, r350 */
3298                 mem_trcd = (temp & 0x7) + 1;
3299                 mem_trp = ((temp >> 8) & 0x7) + 1;
3300                 mem_tras = ((temp >> 11) & 0xf) + 4;
3301         } else if (rdev->family == CHIP_RV350 ||
3302                    rdev->family == CHIP_RV380) {
3303                 /* rv3x0 */
3304                 mem_trcd = (temp & 0x7) + 3;
3305                 mem_trp = ((temp >> 8) & 0x7) + 3;
3306                 mem_tras = ((temp >> 11) & 0xf) + 6;
3307         } else if (rdev->family == CHIP_R420 ||
3308                    rdev->family == CHIP_R423 ||
3309                    rdev->family == CHIP_RV410) {
3310                 /* r4xx */
3311                 mem_trcd = (temp & 0xf) + 3;
3312                 if (mem_trcd > 15)
3313                         mem_trcd = 15;
3314                 mem_trp = ((temp >> 8) & 0xf) + 3;
3315                 if (mem_trp > 15)
3316                         mem_trp = 15;
3317                 mem_tras = ((temp >> 12) & 0x1f) + 6;
3318                 if (mem_tras > 31)
3319                         mem_tras = 31;
3320         } else { /* RV200, R200 */
3321                 mem_trcd = (temp & 0x7) + 1;
3322                 mem_trp = ((temp >> 8) & 0x7) + 1;
3323                 mem_tras = ((temp >> 12) & 0xf) + 4;
3324         }
3325         /* convert to FF */
3326         trcd_ff.full = dfixed_const(mem_trcd);
3327         trp_ff.full = dfixed_const(mem_trp);
3328         tras_ff.full = dfixed_const(mem_tras);
3329
3330         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3331         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3332         data = (temp & (7 << 20)) >> 20;
3333         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3334                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3335                         tcas_ff = memtcas_rs480_ff[data];
3336                 else
3337                         tcas_ff = memtcas_ff[data];
3338         } else
3339                 tcas_ff = memtcas2_ff[data];
3340
3341         if (rdev->family == CHIP_RS400 ||
3342             rdev->family == CHIP_RS480) {
3343                 /* extra cas latency stored in bits 23-25 0-4 clocks */
3344                 data = (temp >> 23) & 0x7;
3345                 if (data < 5)
3346                         tcas_ff.full += dfixed_const(data);
3347         }
3348
3349         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3350                 /* on the R300, Tcas is included in Trbs.
3351                  */
3352                 temp = RREG32(RADEON_MEM_CNTL);
3353                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3354                 if (data == 1) {
3355                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
3356                                 temp = RREG32(R300_MC_IND_INDEX);
3357                                 temp &= ~R300_MC_IND_ADDR_MASK;
3358                                 temp |= R300_MC_READ_CNTL_CD_mcind;
3359                                 WREG32(R300_MC_IND_INDEX, temp);
3360                                 temp = RREG32(R300_MC_IND_DATA);
3361                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3362                         } else {
3363                                 temp = RREG32(R300_MC_READ_CNTL_AB);
3364                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3365                         }
3366                 } else {
3367                         temp = RREG32(R300_MC_READ_CNTL_AB);
3368                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3369                 }
3370                 if (rdev->family == CHIP_RV410 ||
3371                     rdev->family == CHIP_R420 ||
3372                     rdev->family == CHIP_R423)
3373                         trbs_ff = memtrbs_r4xx[data];
3374                 else
3375                         trbs_ff = memtrbs[data];
3376                 tcas_ff.full += trbs_ff.full;
3377         }
3378
3379         sclk_eff_ff.full = sclk_ff.full;
3380
3381         if (rdev->flags & RADEON_IS_AGP) {
3382                 fixed20_12 agpmode_ff;
3383                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3384                 temp_ff.full = dfixed_const_666(16);
3385                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3386         }
3387         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3388
3389         if (ASIC_IS_R300(rdev)) {
3390                 sclk_delay_ff.full = dfixed_const(250);
3391         } else {
3392                 if ((rdev->family == CHIP_RV100) ||
3393                     rdev->flags & RADEON_IS_IGP) {
3394                         if (rdev->mc.vram_is_ddr)
3395                                 sclk_delay_ff.full = dfixed_const(41);
3396                         else
3397                                 sclk_delay_ff.full = dfixed_const(33);
3398                 } else {
3399                         if (rdev->mc.vram_width == 128)
3400                                 sclk_delay_ff.full = dfixed_const(57);
3401                         else
3402                                 sclk_delay_ff.full = dfixed_const(41);
3403                 }
3404         }
3405
3406         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3407
3408         if (rdev->mc.vram_is_ddr) {
3409                 if (rdev->mc.vram_width == 32) {
3410                         k1.full = dfixed_const(40);
3411                         c  = 3;
3412                 } else {
3413                         k1.full = dfixed_const(20);
3414                         c  = 1;
3415                 }
3416         } else {
3417                 k1.full = dfixed_const(40);
3418                 c  = 3;
3419         }
3420
3421         temp_ff.full = dfixed_const(2);
3422         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3423         temp_ff.full = dfixed_const(c);
3424         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3425         temp_ff.full = dfixed_const(4);
3426         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3427         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3428         mc_latency_mclk.full += k1.full;
3429
3430         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3431         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3432
3433         /*
3434           HW cursor time assuming worst case of full size colour cursor.
3435         */
3436         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3437         temp_ff.full += trcd_ff.full;
3438         if (temp_ff.full < tras_ff.full)
3439                 temp_ff.full = tras_ff.full;
3440         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3441
3442         temp_ff.full = dfixed_const(cur_size);
3443         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3444         /*
3445           Find the total latency for the display data.
3446         */
3447         disp_latency_overhead.full = dfixed_const(8);
3448         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3449         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3450         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3451
3452         if (mc_latency_mclk.full > mc_latency_sclk.full)
3453                 disp_latency.full = mc_latency_mclk.full;
3454         else
3455                 disp_latency.full = mc_latency_sclk.full;
3456
3457         /* setup Max GRPH_STOP_REQ default value */
3458         if (ASIC_IS_RV100(rdev))
3459                 max_stop_req = 0x5c;
3460         else
3461                 max_stop_req = 0x7c;
3462
3463         if (mode1) {
3464                 /*  CRTC1
3465                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3466                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3467                 */
3468                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3469
3470                 if (stop_req > max_stop_req)
3471                         stop_req = max_stop_req;
3472
3473                 /*
3474                   Find the drain rate of the display buffer.
3475                 */
3476                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3477                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3478
3479                 /*
3480                   Find the critical point of the display buffer.
3481                 */
3482                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3483                 crit_point_ff.full += dfixed_const_half(0);
3484
3485                 critical_point = dfixed_trunc(crit_point_ff);
3486
3487                 if (rdev->disp_priority == 2) {
3488                         critical_point = 0;
3489                 }
3490
3491                 /*
3492                   The critical point should never be above max_stop_req-4.  Setting
3493                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3494                 */
3495                 if (max_stop_req - critical_point < 4)
3496                         critical_point = 0;
3497
3498                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3499                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3500                         critical_point = 0x10;
3501                 }
3502
3503                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3504                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3505                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3506                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3507                 if ((rdev->family == CHIP_R350) &&
3508                     (stop_req > 0x15)) {
3509                         stop_req -= 0x10;
3510                 }
3511                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3512                 temp |= RADEON_GRPH_BUFFER_SIZE;
3513                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3514                           RADEON_GRPH_CRITICAL_AT_SOF |
3515                           RADEON_GRPH_STOP_CNTL);
3516                 /*
3517                   Write the result into the register.
3518                 */
3519                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3520                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3521
3522 #if 0
3523                 if ((rdev->family == CHIP_RS400) ||
3524                     (rdev->family == CHIP_RS480)) {
3525                         /* attempt to program RS400 disp regs correctly ??? */
3526                         temp = RREG32(RS400_DISP1_REG_CNTL);
3527                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3528                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3529                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3530                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3531                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3532                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3533                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3534                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3535                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3536                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3537                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3538                 }
3539 #endif
3540
3541                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3542                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3543                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3544         }
3545
3546         if (mode2) {
3547                 u32 grph2_cntl;
3548                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3549
3550                 if (stop_req > max_stop_req)
3551                         stop_req = max_stop_req;
3552
3553                 /*
3554                   Find the drain rate of the display buffer.
3555                 */
3556                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3557                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3558
3559                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3560                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3561                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3562                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3563                 if ((rdev->family == CHIP_R350) &&
3564                     (stop_req > 0x15)) {
3565                         stop_req -= 0x10;
3566                 }
3567                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3568                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3569                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3570                           RADEON_GRPH_CRITICAL_AT_SOF |
3571                           RADEON_GRPH_STOP_CNTL);
3572
3573                 if ((rdev->family == CHIP_RS100) ||
3574                     (rdev->family == CHIP_RS200))
3575                         critical_point2 = 0;
3576                 else {
3577                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3578                         temp_ff.full = dfixed_const(temp);
3579                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3580                         if (sclk_ff.full < temp_ff.full)
3581                                 temp_ff.full = sclk_ff.full;
3582
3583                         read_return_rate.full = temp_ff.full;
3584
3585                         if (mode1) {
3586                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3587                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3588                         } else {
3589                                 time_disp1_drop_priority.full = 0;
3590                         }
3591                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3592                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3593                         crit_point_ff.full += dfixed_const_half(0);
3594
3595                         critical_point2 = dfixed_trunc(crit_point_ff);
3596
3597                         if (rdev->disp_priority == 2) {
3598                                 critical_point2 = 0;
3599                         }
3600
3601                         if (max_stop_req - critical_point2 < 4)
3602                                 critical_point2 = 0;
3603
3604                 }
3605
3606                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3607                         /* some R300 cards have problem with this set to 0 */
3608                         critical_point2 = 0x10;
3609                 }
3610
3611                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3612                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3613
3614                 if ((rdev->family == CHIP_RS400) ||
3615                     (rdev->family == CHIP_RS480)) {
3616 #if 0
3617                         /* attempt to program RS400 disp2 regs correctly ??? */
3618                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3619                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3620                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3621                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3622                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3623                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3624                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3625                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3626                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3627                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3628                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3629                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3630 #endif
3631                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3632                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3633                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3634                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3635                 }
3636
3637                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3638                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3639         }
3640
3641         /* Save number of lines the linebuffer leads before the scanout */
3642         if (mode1)
3643             rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3644
3645         if (mode2)
3646             rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3647 }
3648
3649 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3650 {
3651         uint32_t scratch;
3652         uint32_t tmp = 0;
3653         unsigned i;
3654         int r;
3655
3656         r = radeon_scratch_get(rdev, &scratch);
3657         if (r) {
3658                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3659                 return r;
3660         }
3661         WREG32(scratch, 0xCAFEDEAD);
3662         r = radeon_ring_lock(rdev, ring, 2);
3663         if (r) {
3664                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3665                 radeon_scratch_free(rdev, scratch);
3666                 return r;
3667         }
3668         radeon_ring_write(ring, PACKET0(scratch, 0));
3669         radeon_ring_write(ring, 0xDEADBEEF);
3670         radeon_ring_unlock_commit(rdev, ring, false);
3671         for (i = 0; i < rdev->usec_timeout; i++) {
3672                 tmp = RREG32(scratch);
3673                 if (tmp == 0xDEADBEEF) {
3674                         break;
3675                 }
3676                 udelay(1);
3677         }
3678         if (i < rdev->usec_timeout) {
3679                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3680         } else {
3681                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3682                           scratch, tmp);
3683                 r = -EINVAL;
3684         }
3685         radeon_scratch_free(rdev, scratch);
3686         return r;
3687 }
3688
3689 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3690 {
3691         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3692
3693         if (ring->rptr_save_reg) {
3694                 u32 next_rptr = ring->wptr + 2 + 3;
3695                 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3696                 radeon_ring_write(ring, next_rptr);
3697         }
3698
3699         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3700         radeon_ring_write(ring, ib->gpu_addr);
3701         radeon_ring_write(ring, ib->length_dw);
3702 }
3703
3704 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3705 {
3706         struct radeon_ib ib;
3707         uint32_t scratch;
3708         uint32_t tmp = 0;
3709         unsigned i;
3710         int r;
3711
3712         r = radeon_scratch_get(rdev, &scratch);
3713         if (r) {
3714                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3715                 return r;
3716         }
3717         WREG32(scratch, 0xCAFEDEAD);
3718         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3719         if (r) {
3720                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3721                 goto free_scratch;
3722         }
3723         ib.ptr[0] = PACKET0(scratch, 0);
3724         ib.ptr[1] = 0xDEADBEEF;
3725         ib.ptr[2] = PACKET2(0);
3726         ib.ptr[3] = PACKET2(0);
3727         ib.ptr[4] = PACKET2(0);
3728         ib.ptr[5] = PACKET2(0);
3729         ib.ptr[6] = PACKET2(0);
3730         ib.ptr[7] = PACKET2(0);
3731         ib.length_dw = 8;
3732         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3733         if (r) {
3734                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3735                 goto free_ib;
3736         }
3737         r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3738                 RADEON_USEC_IB_TEST_TIMEOUT));
3739         if (r < 0) {
3740                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3741                 goto free_ib;
3742         } else if (r == 0) {
3743                 DRM_ERROR("radeon: fence wait timed out.\n");
3744                 r = -ETIMEDOUT;
3745                 goto free_ib;
3746         }
3747         r = 0;
3748         for (i = 0; i < rdev->usec_timeout; i++) {
3749                 tmp = RREG32(scratch);
3750                 if (tmp == 0xDEADBEEF) {
3751                         break;
3752                 }
3753                 udelay(1);
3754         }
3755         if (i < rdev->usec_timeout) {
3756                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3757         } else {
3758                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3759                           scratch, tmp);
3760                 r = -EINVAL;
3761         }
3762 free_ib:
3763         radeon_ib_free(rdev, &ib);
3764 free_scratch:
3765         radeon_scratch_free(rdev, scratch);
3766         return r;
3767 }
3768
3769 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3770 {
3771         /* Shutdown CP we shouldn't need to do that but better be safe than
3772          * sorry
3773          */
3774         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3775         WREG32(R_000740_CP_CSQ_CNTL, 0);
3776
3777         /* Save few CRTC registers */
3778         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3779         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3780         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3781         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3782         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3783                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3784                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3785         }
3786
3787         /* Disable VGA aperture access */
3788         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3789         /* Disable cursor, overlay, crtc */
3790         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3791         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3792                                         S_000054_CRTC_DISPLAY_DIS(1));
3793         WREG32(R_000050_CRTC_GEN_CNTL,
3794                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3795                         S_000050_CRTC_DISP_REQ_EN_B(1));
3796         WREG32(R_000420_OV0_SCALE_CNTL,
3797                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3798         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3799         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3800                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3801                                                 S_000360_CUR2_LOCK(1));
3802                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3803                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3804                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3805                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3806                 WREG32(R_000360_CUR2_OFFSET,
3807                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3808         }
3809 }
3810
3811 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3812 {
3813         /* Update base address for crtc */
3814         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3815         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3816                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3817         }
3818         /* Restore CRTC registers */
3819         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3820         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3821         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3822         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3823                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3824         }
3825 }
3826
3827 void r100_vga_render_disable(struct radeon_device *rdev)
3828 {
3829         u32 tmp;
3830
3831         tmp = RREG8(R_0003C2_GENMO_WT);
3832         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3833 }
3834
3835 static void r100_mc_program(struct radeon_device *rdev)
3836 {
3837         struct r100_mc_save save;
3838
3839         /* Stops all mc clients */
3840         r100_mc_stop(rdev, &save);
3841         if (rdev->flags & RADEON_IS_AGP) {
3842                 WREG32(R_00014C_MC_AGP_LOCATION,
3843                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3844                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3845                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3846                 if (rdev->family > CHIP_RV200)
3847                         WREG32(R_00015C_AGP_BASE_2,
3848                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3849         } else {
3850                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3851                 WREG32(R_000170_AGP_BASE, 0);
3852                 if (rdev->family > CHIP_RV200)
3853                         WREG32(R_00015C_AGP_BASE_2, 0);
3854         }
3855         /* Wait for mc idle */
3856         if (r100_mc_wait_for_idle(rdev))
3857                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3858         /* Program MC, should be a 32bits limited address space */
3859         WREG32(R_000148_MC_FB_LOCATION,
3860                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3861                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3862         r100_mc_resume(rdev, &save);
3863 }
3864
3865 static void r100_clock_startup(struct radeon_device *rdev)
3866 {
3867         u32 tmp;
3868
3869         if (radeon_dynclks != -1 && radeon_dynclks)
3870                 radeon_legacy_set_clock_gating(rdev, 1);
3871         /* We need to force on some of the block */
3872         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3873         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3874         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3875                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3876         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3877 }
3878
3879 static int r100_startup(struct radeon_device *rdev)
3880 {
3881         int r;
3882
3883         /* set common regs */
3884         r100_set_common_regs(rdev);
3885         /* program mc */
3886         r100_mc_program(rdev);
3887         /* Resume clock */
3888         r100_clock_startup(rdev);
3889         /* Initialize GART (initialize after TTM so we can allocate
3890          * memory through TTM but finalize after TTM) */
3891         r100_enable_bm(rdev);
3892         if (rdev->flags & RADEON_IS_PCI) {
3893                 r = r100_pci_gart_enable(rdev);
3894                 if (r)
3895                         return r;
3896         }
3897
3898         /* allocate wb buffer */
3899         r = radeon_wb_init(rdev);
3900         if (r)
3901                 return r;
3902
3903         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3904         if (r) {
3905                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3906                 return r;
3907         }
3908
3909         /* Enable IRQ */
3910         if (!rdev->irq.installed) {
3911                 r = radeon_irq_kms_init(rdev);
3912                 if (r)
3913                         return r;
3914         }
3915
3916         r100_irq_set(rdev);
3917         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3918         /* 1M ring buffer */
3919         r = r100_cp_init(rdev, 1024 * 1024);
3920         if (r) {
3921                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3922                 return r;
3923         }
3924
3925         r = radeon_ib_pool_init(rdev);
3926         if (r) {
3927                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3928                 return r;
3929         }
3930
3931         return 0;
3932 }
3933
3934 int r100_resume(struct radeon_device *rdev)
3935 {
3936         int r;
3937
3938         /* Make sur GART are not working */
3939         if (rdev->flags & RADEON_IS_PCI)
3940                 r100_pci_gart_disable(rdev);
3941         /* Resume clock before doing reset */
3942         r100_clock_startup(rdev);
3943         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3944         if (radeon_asic_reset(rdev)) {
3945                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3946                         RREG32(R_000E40_RBBM_STATUS),
3947                         RREG32(R_0007C0_CP_STAT));
3948         }
3949         /* post */
3950         radeon_combios_asic_init(rdev->ddev);
3951         /* Resume clock after posting */
3952         r100_clock_startup(rdev);
3953         /* Initialize surface registers */
3954         radeon_surface_init(rdev);
3955
3956         rdev->accel_working = true;
3957         r = r100_startup(rdev);
3958         if (r) {
3959                 rdev->accel_working = false;
3960         }
3961         return r;
3962 }
3963
3964 int r100_suspend(struct radeon_device *rdev)
3965 {
3966         radeon_pm_suspend(rdev);
3967         r100_cp_disable(rdev);
3968         radeon_wb_disable(rdev);
3969         r100_irq_disable(rdev);
3970         if (rdev->flags & RADEON_IS_PCI)
3971                 r100_pci_gart_disable(rdev);
3972         return 0;
3973 }
3974
3975 void r100_fini(struct radeon_device *rdev)
3976 {
3977         radeon_pm_fini(rdev);
3978         r100_cp_fini(rdev);
3979         radeon_wb_fini(rdev);
3980         radeon_ib_pool_fini(rdev);
3981         radeon_gem_fini(rdev);
3982         if (rdev->flags & RADEON_IS_PCI)
3983                 r100_pci_gart_fini(rdev);
3984         radeon_agp_fini(rdev);
3985         radeon_irq_kms_fini(rdev);
3986         radeon_fence_driver_fini(rdev);
3987         radeon_bo_fini(rdev);
3988         radeon_atombios_fini(rdev);
3989         kfree(rdev->bios);
3990         rdev->bios = NULL;
3991 }
3992
3993 /*
3994  * Due to how kexec works, it can leave the hw fully initialised when it
3995  * boots the new kernel. However doing our init sequence with the CP and
3996  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3997  * do some quick sanity checks and restore sane values to avoid this
3998  * problem.
3999  */
4000 void r100_restore_sanity(struct radeon_device *rdev)
4001 {
4002         u32 tmp;
4003
4004         tmp = RREG32(RADEON_CP_CSQ_CNTL);
4005         if (tmp) {
4006                 WREG32(RADEON_CP_CSQ_CNTL, 0);
4007         }
4008         tmp = RREG32(RADEON_CP_RB_CNTL);
4009         if (tmp) {
4010                 WREG32(RADEON_CP_RB_CNTL, 0);
4011         }
4012         tmp = RREG32(RADEON_SCRATCH_UMSK);
4013         if (tmp) {
4014                 WREG32(RADEON_SCRATCH_UMSK, 0);
4015         }
4016 }
4017
4018 int r100_init(struct radeon_device *rdev)
4019 {
4020         int r;
4021
4022         /* Register debugfs file specific to this group of asics */
4023         r100_debugfs_mc_info_init(rdev);
4024         /* Disable VGA */
4025         r100_vga_render_disable(rdev);
4026         /* Initialize scratch registers */
4027         radeon_scratch_init(rdev);
4028         /* Initialize surface registers */
4029         radeon_surface_init(rdev);
4030         /* sanity check some register to avoid hangs like after kexec */
4031         r100_restore_sanity(rdev);
4032         /* TODO: disable VGA need to use VGA request */
4033         /* BIOS*/
4034         if (!radeon_get_bios(rdev)) {
4035                 if (ASIC_IS_AVIVO(rdev))
4036                         return -EINVAL;
4037         }
4038         if (rdev->is_atom_bios) {
4039                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4040                 return -EINVAL;
4041         } else {
4042                 r = radeon_combios_init(rdev);
4043                 if (r)
4044                         return r;
4045         }
4046         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4047         if (radeon_asic_reset(rdev)) {
4048                 dev_warn(rdev->dev,
4049                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4050                         RREG32(R_000E40_RBBM_STATUS),
4051                         RREG32(R_0007C0_CP_STAT));
4052         }
4053         /* check if cards are posted or not */
4054         if (radeon_boot_test_post_card(rdev) == false)
4055                 return -EINVAL;
4056         /* Set asic errata */
4057         r100_errata(rdev);
4058         /* Initialize clocks */
4059         radeon_get_clock_info(rdev->ddev);
4060         /* initialize AGP */
4061         if (rdev->flags & RADEON_IS_AGP) {
4062                 r = radeon_agp_init(rdev);
4063                 if (r) {
4064                         radeon_agp_disable(rdev);
4065                 }
4066         }
4067         /* initialize VRAM */
4068         r100_mc_init(rdev);
4069         /* Fence driver */
4070         radeon_fence_driver_init(rdev);
4071         /* Memory manager */
4072         r = radeon_bo_init(rdev);
4073         if (r)
4074                 return r;
4075         if (rdev->flags & RADEON_IS_PCI) {
4076                 r = r100_pci_gart_init(rdev);
4077                 if (r)
4078                         return r;
4079         }
4080         r100_set_safe_registers(rdev);
4081
4082         /* Initialize power management */
4083         radeon_pm_init(rdev);
4084
4085         rdev->accel_working = true;
4086         r = r100_startup(rdev);
4087         if (r) {
4088                 /* Somethings want wront with the accel init stop accel */
4089                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4090                 r100_cp_fini(rdev);
4091                 radeon_wb_fini(rdev);
4092                 radeon_ib_pool_fini(rdev);
4093                 radeon_irq_kms_fini(rdev);
4094                 if (rdev->flags & RADEON_IS_PCI)
4095                         r100_pci_gart_fini(rdev);
4096                 rdev->accel_working = false;
4097         }
4098         return 0;
4099 }
4100
4101 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4102 {
4103         unsigned long flags;
4104         uint32_t ret;
4105
4106         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4107         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4108         ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4109         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4110         return ret;
4111 }
4112
4113 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4114 {
4115         unsigned long flags;
4116
4117         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4118         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4119         writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4120         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4121 }
4122
4123 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4124 {
4125         if (reg < rdev->rio_mem_size)
4126                 return ioread32(rdev->rio_mem + reg);
4127         else {
4128                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4129                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4130         }
4131 }
4132
4133 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4134 {
4135         if (reg < rdev->rio_mem_size)
4136                 iowrite32(v, rdev->rio_mem + reg);
4137         else {
4138                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4139                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4140         }
4141 }