drivers/gpu/drm/mediatek/mtk_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/mailbox_controller.h>
   9 #include <linux/of.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/soc/mediatek/mtk-cmdq.h>
  12 #include <linux/soc/mediatek/mtk-mmsys.h>
  13 #include <linux/soc/mediatek/mtk-mutex.h>
  14
  15 #include <asm/barrier.h>
  16
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_probe_helper.h>
  20 #include <drm/drm_vblank.h>
  21
  22 #include "mtk_crtc.h"
  23 #include "mtk_ddp_comp.h"
  24 #include "mtk_drm_drv.h"
  25 #include "mtk_gem.h"
  26 #include "mtk_plane.h"
  27
  28 /*
  29  * struct mtk_crtc - MediaTek specific crtc structure.
  30  * @base: crtc object.
  31  * @enabled: records whether crtc_enable succeeded
  32  * @planes: array of 4 drm_plane structures, one for each overlay plane
  33  * @pending_planes: whether any plane has pending changes to be applied
  34  * @mmsys_dev: pointer to the mmsys device for configuration registers
  35  * @mutex: handle to one of the ten disp_mutex streams
  36  * @ddp_comp_nr: number of components in ddp_comp
  37  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
  38  *
  39  * TODO: Needs update: this header is missing a bunch of member descriptions.
  40  */
  41 struct mtk_crtc {
  42         struct drm_crtc                 base;
  43         bool                            enabled;
  44
  45         bool                            pending_needs_vblank;
  46         struct drm_pending_vblank_event *event;
  47
  48         struct drm_plane                *planes;
  49         unsigned int                    layer_nr;
  50         bool                            pending_planes;
  51         bool                            pending_async_planes;
  52
  53 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  54         struct cmdq_client              cmdq_client;
  55         struct cmdq_pkt                 cmdq_handle;
  56         u32                             cmdq_event;
  57         u32                             cmdq_vblank_cnt;
  58         wait_queue_head_t               cb_blocking_queue;
  59 #endif
  60
  61         struct device                   *mmsys_dev;
  62         struct device                   *dma_dev;
  63         struct mtk_mutex                *mutex;
  64         unsigned int                    ddp_comp_nr;
  65         struct mtk_ddp_comp             **ddp_comp;
  66         unsigned int                    num_conn_routes;
  67         const struct mtk_drm_route      *conn_routes;
  68
  69         /* lock for display hardware access */
  70         struct mutex                    hw_lock;
  71         bool                            config_updating;
  72 };
  73
  74 struct mtk_crtc_state {
  75         struct drm_crtc_state           base;
  76
  77         bool                            pending_config;
  78         unsigned int                    pending_width;
  79         unsigned int                    pending_height;
  80         unsigned int                    pending_vrefresh;
  81 };
  82
  83 static inline struct mtk_crtc *to_mtk_crtc(struct drm_crtc *c)
  84 {
  85         return container_of(c, struct mtk_crtc, base);
  86 }
  87
  88 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
  89 {
  90         return container_of(s, struct mtk_crtc_state, base);
  91 }
  92
  93 static void mtk_crtc_finish_page_flip(struct mtk_crtc *mtk_crtc)
  94 {
  95         struct drm_crtc *crtc = &mtk_crtc->base;
  96         unsigned long flags;
  97
  98         if (mtk_crtc->event) {
  99                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
 100                 drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
 101                 drm_crtc_vblank_put(crtc);
 102                 mtk_crtc->event = NULL;
 103                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 104         }
 105 }
 106
 107 static void mtk_drm_finish_page_flip(struct mtk_crtc *mtk_crtc)
 108 {
 109         drm_crtc_handle_vblank(&mtk_crtc->base);
 110         if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
 111                 mtk_crtc_finish_page_flip(mtk_crtc);
 112                 mtk_crtc->pending_needs_vblank = false;
 113         }
 114 }
 115
 116 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 117 static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt,
 118                                    size_t size)
 119 {
 120         struct device *dev;
 121         dma_addr_t dma_addr;
 122
 123         pkt->va_base = kzalloc(size, GFP_KERNEL);
 124         if (!pkt->va_base)
 125                 return -ENOMEM;
 126
 127         pkt->buf_size = size;
 128         pkt->cl = (void *)client;
 129
 130         dev = client->chan->mbox->dev;
 131         dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
 132                                   DMA_TO_DEVICE);
 133         if (dma_mapping_error(dev, dma_addr)) {
 134                 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
 135                 kfree(pkt->va_base);
 136                 return -ENOMEM;
 137         }
 138
 139         pkt->pa_base = dma_addr;
 140
 141         return 0;
 142 }
 143
 144 static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt)
 145 {
 146         struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
 147
 148         dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
 149                          DMA_TO_DEVICE);
 150         kfree(pkt->va_base);
 151 }
 152 #endif
 153
 154 static void mtk_crtc_destroy(struct drm_crtc *crtc)
 155 {
 156         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 157         int i;
 158
 159         mtk_mutex_put(mtk_crtc->mutex);
 160 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 161         mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle);
 162
 163         if (mtk_crtc->cmdq_client.chan) {
 164                 mbox_free_channel(mtk_crtc->cmdq_client.chan);
 165                 mtk_crtc->cmdq_client.chan = NULL;
 166         }
 167 #endif
 168
 169         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 170                 struct mtk_ddp_comp *comp;
 171
 172                 comp = mtk_crtc->ddp_comp[i];
 173                 mtk_ddp_comp_unregister_vblank_cb(comp);
 174         }
 175
 176         drm_crtc_cleanup(crtc);
 177 }
 178
 179 static void mtk_crtc_reset(struct drm_crtc *crtc)
 180 {
 181         struct mtk_crtc_state *state;
 182
 183         if (crtc->state)
 184                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 185
 186         kfree(to_mtk_crtc_state(crtc->state));
 187         crtc->state = NULL;
 188
 189         state = kzalloc(sizeof(*state), GFP_KERNEL);
 190         if (state)
 191                 __drm_atomic_helper_crtc_reset(crtc, &state->base);
 192 }
 193
 194 static struct drm_crtc_state *mtk_crtc_duplicate_state(struct drm_crtc *crtc)
 195 {
 196         struct mtk_crtc_state *state;
 197
 198         state = kmalloc(sizeof(*state), GFP_KERNEL);
 199         if (!state)
 200                 return NULL;
 201
 202         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 203
 204         WARN_ON(state->base.crtc != crtc);
 205         state->base.crtc = crtc;
 206         state->pending_config = false;
 207
 208         return &state->base;
 209 }
 210
 211 static void mtk_crtc_destroy_state(struct drm_crtc *crtc,
 212                                    struct drm_crtc_state *state)
 213 {
 214         __drm_atomic_helper_crtc_destroy_state(state);
 215         kfree(to_mtk_crtc_state(state));
 216 }
 217
 218 static enum drm_mode_status
 219 mtk_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
 220 {
 221         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 222         enum drm_mode_status status = MODE_OK;
 223         int i;
 224
 225         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 226                 status = mtk_ddp_comp_mode_valid(mtk_crtc->ddp_comp[i], mode);
 227                 if (status != MODE_OK)
 228                         break;
 229         }
 230         return status;
 231 }
 232
 233 static bool mtk_crtc_mode_fixup(struct drm_crtc *crtc,
 234                                 const struct drm_display_mode *mode,
 235                                 struct drm_display_mode *adjusted_mode)
 236 {
 237         /* Nothing to do here, but this callback is mandatory. */
 238         return true;
 239 }
 240
 241 static void mtk_crtc_mode_set_nofb(struct drm_crtc *crtc)
 242 {
 243         struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
 244
 245         state->pending_width = crtc->mode.hdisplay;
 246         state->pending_height = crtc->mode.vdisplay;
 247         state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
 248         wmb();  /* Make sure the above parameters are set before update */
 249         state->pending_config = true;
 250 }
 251
 252 static int mtk_crtc_ddp_clk_enable(struct mtk_crtc *mtk_crtc)
 253 {
 254         int ret;
 255         int i;
 256
 257         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 258                 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
 259                 if (ret) {
 260                         DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
 261                         goto err;
 262                 }
 263         }
 264
 265         return 0;
 266 err:
 267         while (--i >= 0)
 268                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 269         return ret;
 270 }
 271
 272 static void mtk_crtc_ddp_clk_disable(struct mtk_crtc *mtk_crtc)
 273 {
 274         int i;
 275
 276         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 277                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 278 }
 279
 280 static
 281 struct mtk_ddp_comp *mtk_ddp_comp_for_plane(struct drm_crtc *crtc,
 282                                             struct drm_plane *plane,
 283                                             unsigned int *local_layer)
 284 {
 285         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 286         struct mtk_ddp_comp *comp;
 287         int i, count = 0;
 288         unsigned int local_index = plane - mtk_crtc->planes;
 289
 290         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 291                 comp = mtk_crtc->ddp_comp[i];
 292                 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
 293                         *local_layer = local_index - count;
 294                         return comp;
 295                 }
 296                 count += mtk_ddp_comp_layer_nr(comp);
 297         }
 298
 299         WARN(1, "Failed to find component for plane %d\n", plane->index);
 300         return NULL;
 301 }
 302
 303 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 304 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
 305 {
 306         struct cmdq_cb_data *data = mssg;
 307         struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client);
 308         struct mtk_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_crtc, cmdq_client);
 309         struct mtk_crtc_state *state;
 310         unsigned int i;
 311
 312         if (data->sta < 0)
 313                 return;
 314
 315         state = to_mtk_crtc_state(mtk_crtc->base.state);
 316
 317         state->pending_config = false;
 318
 319         if (mtk_crtc->pending_planes) {
 320                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 321                         struct drm_plane *plane = &mtk_crtc->planes[i];
 322                         struct mtk_plane_state *plane_state;
 323
 324                         plane_state = to_mtk_plane_state(plane->state);
 325
 326                         plane_state->pending.config = false;
 327                 }
 328                 mtk_crtc->pending_planes = false;
 329         }
 330
 331         if (mtk_crtc->pending_async_planes) {
 332                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 333                         struct drm_plane *plane = &mtk_crtc->planes[i];
 334                         struct mtk_plane_state *plane_state;
 335
 336                         plane_state = to_mtk_plane_state(plane->state);
 337
 338                         plane_state->pending.async_config = false;
 339                 }
 340                 mtk_crtc->pending_async_planes = false;
 341         }
 342
 343         mtk_crtc->cmdq_vblank_cnt = 0;
 344         wake_up(&mtk_crtc->cb_blocking_queue);
 345 }
 346 #endif
 347
 348 static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
 349 {
 350         struct drm_crtc *crtc = &mtk_crtc->base;
 351         struct drm_connector *connector;
 352         struct drm_encoder *encoder;
 353         struct drm_connector_list_iter conn_iter;
 354         unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
 355         int ret;
 356         int i;
 357
 358         if (WARN_ON(!crtc->state))
 359                 return -EINVAL;
 360
 361         width = crtc->state->adjusted_mode.hdisplay;
 362         height = crtc->state->adjusted_mode.vdisplay;
 363         vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
 364
 365         drm_for_each_encoder(encoder, crtc->dev) {
 366                 if (encoder->crtc != crtc)
 367                         continue;
 368
 369                 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 370                 drm_for_each_connector_iter(connector, &conn_iter) {
 371                         if (connector->encoder != encoder)
 372                                 continue;
 373                         if (connector->display_info.bpc != 0 &&
 374                             bpc > connector->display_info.bpc)
 375                                 bpc = connector->display_info.bpc;
 376                 }
 377                 drm_connector_list_iter_end(&conn_iter);
 378         }
 379
 380         ret = pm_runtime_resume_and_get(crtc->dev->dev);
 381         if (ret < 0) {
 382                 DRM_ERROR("Failed to enable power domain: %d\n", ret);
 383                 return ret;
 384         }
 385
 386         ret = mtk_mutex_prepare(mtk_crtc->mutex);
 387         if (ret < 0) {
 388                 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
 389                 goto err_pm_runtime_put;
 390         }
 391
 392         ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
 393         if (ret < 0) {
 394                 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
 395                 goto err_mutex_unprepare;
 396         }
 397
 398         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 399                 if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
 400                                           mtk_crtc->ddp_comp[i + 1]->id))
 401                         mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
 402                                               mtk_crtc->ddp_comp[i]->id,
 403                                               mtk_crtc->ddp_comp[i + 1]->id);
 404                 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
 405                         mtk_mutex_add_comp(mtk_crtc->mutex,
 406                                            mtk_crtc->ddp_comp[i]->id);
 407         }
 408         if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
 409                 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 410         mtk_mutex_enable(mtk_crtc->mutex);
 411
 412         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 413                 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
 414
 415                 if (i == 1)
 416                         mtk_ddp_comp_bgclr_in_on(comp);
 417
 418                 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
 419                 mtk_ddp_comp_start(comp);
 420         }
 421
 422         /* Initially configure all planes */
 423         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 424                 struct drm_plane *plane = &mtk_crtc->planes[i];
 425                 struct mtk_plane_state *plane_state;
 426                 struct mtk_ddp_comp *comp;
 427                 unsigned int local_layer;
 428
 429                 plane_state = to_mtk_plane_state(plane->state);
 430
 431                 /* should not enable layer before crtc enabled */
 432                 plane_state->pending.enable = false;
 433                 comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
 434                 if (comp)
 435                         mtk_ddp_comp_layer_config(comp, local_layer,
 436                                                   plane_state, NULL);
 437         }
 438
 439         return 0;
 440
 441 err_mutex_unprepare:
 442         mtk_mutex_unprepare(mtk_crtc->mutex);
 443 err_pm_runtime_put:
 444         pm_runtime_put(crtc->dev->dev);
 445         return ret;
 446 }
 447
 448 static void mtk_crtc_ddp_hw_fini(struct mtk_crtc *mtk_crtc)
 449 {
 450         struct drm_device *drm = mtk_crtc->base.dev;
 451         struct drm_crtc *crtc = &mtk_crtc->base;
 452         int i;
 453
 454         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 455                 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
 456                 if (i == 1)
 457                         mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
 458         }
 459
 460         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 461                 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
 462                         mtk_mutex_remove_comp(mtk_crtc->mutex,
 463                                               mtk_crtc->ddp_comp[i]->id);
 464         mtk_mutex_disable(mtk_crtc->mutex);
 465         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 466                 if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
 467                                              mtk_crtc->ddp_comp[i + 1]->id))
 468                         mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
 469                                                  mtk_crtc->ddp_comp[i]->id,
 470                                                  mtk_crtc->ddp_comp[i + 1]->id);
 471                 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
 472                         mtk_mutex_remove_comp(mtk_crtc->mutex,
 473                                               mtk_crtc->ddp_comp[i]->id);
 474         }
 475         if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
 476                 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 477         mtk_crtc_ddp_clk_disable(mtk_crtc);
 478         mtk_mutex_unprepare(mtk_crtc->mutex);
 479
 480         pm_runtime_put(drm->dev);
 481
 482         if (crtc->state->event && !crtc->state->active) {
 483                 spin_lock_irq(&crtc->dev->event_lock);
 484                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 485                 crtc->state->event = NULL;
 486                 spin_unlock_irq(&crtc->dev->event_lock);
 487         }
 488 }
 489
 490 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
 491                                 struct cmdq_pkt *cmdq_handle)
 492 {
 493         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 494         struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
 495         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 496         unsigned int i;
 497         unsigned int local_layer;
 498
 499         /*
 500          * TODO: instead of updating the registers here, we should prepare
 501          * working registers in atomic_commit and let the hardware command
 502          * queue update module registers on vblank.
 503          */
 504         if (state->pending_config) {
 505                 mtk_ddp_comp_config(comp, state->pending_width,
 506                                     state->pending_height,
 507                                     state->pending_vrefresh, 0,
 508                                     cmdq_handle);
 509
 510                 if (!cmdq_handle)
 511                         state->pending_config = false;
 512         }
 513
 514         if (mtk_crtc->pending_planes) {
 515                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 516                         struct drm_plane *plane = &mtk_crtc->planes[i];
 517                         struct mtk_plane_state *plane_state;
 518
 519                         plane_state = to_mtk_plane_state(plane->state);
 520
 521                         if (!plane_state->pending.config)
 522                                 continue;
 523
 524                         comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
 525
 526                         if (comp)
 527                                 mtk_ddp_comp_layer_config(comp, local_layer,
 528                                                           plane_state,
 529                                                           cmdq_handle);
 530                         if (!cmdq_handle)
 531                                 plane_state->pending.config = false;
 532                 }
 533
 534                 if (!cmdq_handle)
 535                         mtk_crtc->pending_planes = false;
 536         }
 537
 538         if (mtk_crtc->pending_async_planes) {
 539                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 540                         struct drm_plane *plane = &mtk_crtc->planes[i];
 541                         struct mtk_plane_state *plane_state;
 542
 543                         plane_state = to_mtk_plane_state(plane->state);
 544
 545                         if (!plane_state->pending.async_config)
 546                                 continue;
 547
 548                         comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
 549
 550                         if (comp)
 551                                 mtk_ddp_comp_layer_config(comp, local_layer,
 552                                                           plane_state,
 553                                                           cmdq_handle);
 554                         if (!cmdq_handle)
 555                                 plane_state->pending.async_config = false;
 556                 }
 557
 558                 if (!cmdq_handle)
 559                         mtk_crtc->pending_async_planes = false;
 560         }
 561 }
 562
 563 static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
 564 {
 565 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 566         struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
 567 #endif
 568         struct drm_crtc *crtc = &mtk_crtc->base;
 569         struct mtk_drm_private *priv = crtc->dev->dev_private;
 570         unsigned int pending_planes = 0, pending_async_planes = 0;
 571         int i;
 572
 573         mutex_lock(&mtk_crtc->hw_lock);
 574         mtk_crtc->config_updating = true;
 575         if (needs_vblank)
 576                 mtk_crtc->pending_needs_vblank = true;
 577
 578         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 579                 struct drm_plane *plane = &mtk_crtc->planes[i];
 580                 struct mtk_plane_state *plane_state;
 581
 582                 plane_state = to_mtk_plane_state(plane->state);
 583                 if (plane_state->pending.dirty) {
 584                         plane_state->pending.config = true;
 585                         plane_state->pending.dirty = false;
 586                         pending_planes |= BIT(i);
 587                 } else if (plane_state->pending.async_dirty) {
 588                         plane_state->pending.async_config = true;
 589                         plane_state->pending.async_dirty = false;
 590                         pending_async_planes |= BIT(i);
 591                 }
 592         }
 593         if (pending_planes)
 594                 mtk_crtc->pending_planes = true;
 595         if (pending_async_planes)
 596                 mtk_crtc->pending_async_planes = true;
 597
 598         if (priv->data->shadow_register) {
 599                 mtk_mutex_acquire(mtk_crtc->mutex);
 600                 mtk_crtc_ddp_config(crtc, NULL);
 601                 mtk_mutex_release(mtk_crtc->mutex);
 602         }
 603 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 604         if (mtk_crtc->cmdq_client.chan) {
 605                 mbox_flush(mtk_crtc->cmdq_client.chan, 2000);
 606                 cmdq_handle->cmd_buf_size = 0;
 607                 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 608                 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
 609                 mtk_crtc_ddp_config(crtc, cmdq_handle);
 610                 cmdq_pkt_finalize(cmdq_handle);
 611                 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev,
 612                                            cmdq_handle->pa_base,
 613                                            cmdq_handle->cmd_buf_size,
 614                                            DMA_TO_DEVICE);
 615                 /*
 616                  * CMDQ command should execute in next 3 vblank.
 617                  * One vblank interrupt before send message (occasionally)
 618                  * and one vblank interrupt after cmdq done,
 619                  * so it's timeout after 3 vblank interrupt.
 620                  * If it fail to execute in next 3 vblank, timeout happen.
 621                  */
 622                 mtk_crtc->cmdq_vblank_cnt = 3;
 623
 624                 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
 625                 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
 626         }
 627 #endif
 628         mtk_crtc->config_updating = false;
 629         mutex_unlock(&mtk_crtc->hw_lock);
 630 }
 631
 632 static void mtk_crtc_ddp_irq(void *data)
 633 {
 634         struct drm_crtc *crtc = data;
 635         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 636         struct mtk_drm_private *priv = crtc->dev->dev_private;
 637
 638 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 639         if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan)
 640                 mtk_crtc_ddp_config(crtc, NULL);
 641         else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
 642                 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
 643                           drm_crtc_index(&mtk_crtc->base));
 644 #else
 645         if (!priv->data->shadow_register)
 646                 mtk_crtc_ddp_config(crtc, NULL);
 647 #endif
 648         mtk_drm_finish_page_flip(mtk_crtc);
 649 }
 650
 651 static int mtk_crtc_enable_vblank(struct drm_crtc *crtc)
 652 {
 653         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 654         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 655
 656         mtk_ddp_comp_enable_vblank(comp);
 657
 658         return 0;
 659 }
 660
 661 static void mtk_crtc_disable_vblank(struct drm_crtc *crtc)
 662 {
 663         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 664         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 665
 666         mtk_ddp_comp_disable_vblank(comp);
 667 }
 668
 669 static void mtk_crtc_update_output(struct drm_crtc *crtc,
 670                                    struct drm_atomic_state *state)
 671 {
 672         int crtc_index = drm_crtc_index(crtc);
 673         int i;
 674         struct device *dev;
 675         struct drm_crtc_state *crtc_state = state->crtcs[crtc_index].new_state;
 676         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 677         struct mtk_drm_private *priv;
 678         unsigned int encoder_mask = crtc_state->encoder_mask;
 679
 680         if (!crtc_state->connectors_changed)
 681                 return;
 682
 683         if (!mtk_crtc->num_conn_routes)
 684                 return;
 685
 686         priv = ((struct mtk_drm_private *)crtc->dev->dev_private)->all_drm_private[crtc_index];
 687         dev = priv->dev;
 688
 689         dev_dbg(dev, "connector change:%d, encoder mask:0x%x for crtc:%d\n",
 690                 crtc_state->connectors_changed, encoder_mask, crtc_index);
 691
 692         for (i = 0; i < mtk_crtc->num_conn_routes; i++) {
 693                 unsigned int comp_id = mtk_crtc->conn_routes[i].route_ddp;
 694                 struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
 695
 696                 if (comp->encoder_index >= 0 &&
 697                     (encoder_mask & BIT(comp->encoder_index))) {
 698                         mtk_crtc->ddp_comp[mtk_crtc->ddp_comp_nr - 1] = comp;
 699                         dev_dbg(dev, "Add comp_id: %d at path index %d\n",
 700                                 comp->id, mtk_crtc->ddp_comp_nr - 1);
 701                         break;
 702                 }
 703         }
 704 }
 705
 706 int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
 707                          struct mtk_plane_state *state)
 708 {
 709         unsigned int local_layer;
 710         struct mtk_ddp_comp *comp;
 711
 712         comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
 713         if (comp)
 714                 return mtk_ddp_comp_layer_check(comp, local_layer, state);
 715         return 0;
 716 }
 717
 718 void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
 719                            struct drm_atomic_state *state)
 720 {
 721         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 722
 723         if (!mtk_crtc->enabled)
 724                 return;
 725
 726         mtk_crtc_update_config(mtk_crtc, false);
 727 }
 728
 729 static void mtk_crtc_atomic_enable(struct drm_crtc *crtc,
 730                                    struct drm_atomic_state *state)
 731 {
 732         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 733         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 734         int ret;
 735
 736         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 737
 738         ret = mtk_ddp_comp_power_on(comp);
 739         if (ret < 0) {
 740                 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
 741                 return;
 742         }
 743
 744         mtk_crtc_update_output(crtc, state);
 745
 746         ret = mtk_crtc_ddp_hw_init(mtk_crtc);
 747         if (ret) {
 748                 mtk_ddp_comp_power_off(comp);
 749                 return;
 750         }
 751
 752         drm_crtc_vblank_on(crtc);
 753         mtk_crtc->enabled = true;
 754 }
 755
 756 static void mtk_crtc_atomic_disable(struct drm_crtc *crtc,
 757                                     struct drm_atomic_state *state)
 758 {
 759         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 760         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 761         int i;
 762
 763         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 764         if (!mtk_crtc->enabled)
 765                 return;
 766
 767         /* Set all pending plane state to disabled */
 768         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 769                 struct drm_plane *plane = &mtk_crtc->planes[i];
 770                 struct mtk_plane_state *plane_state;
 771
 772                 plane_state = to_mtk_plane_state(plane->state);
 773                 plane_state->pending.enable = false;
 774                 plane_state->pending.config = true;
 775         }
 776         mtk_crtc->pending_planes = true;
 777
 778         mtk_crtc_update_config(mtk_crtc, false);
 779 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 780         /* Wait for planes to be disabled by cmdq */
 781         if (mtk_crtc->cmdq_client.chan)
 782                 wait_event_timeout(mtk_crtc->cb_blocking_queue,
 783                                    mtk_crtc->cmdq_vblank_cnt == 0,
 784                                    msecs_to_jiffies(500));
 785 #endif
 786         /* Wait for planes to be disabled */
 787         drm_crtc_wait_one_vblank(crtc);
 788
 789         drm_crtc_vblank_off(crtc);
 790         mtk_crtc_ddp_hw_fini(mtk_crtc);
 791         mtk_ddp_comp_power_off(comp);
 792
 793         mtk_crtc->enabled = false;
 794 }
 795
 796 static void mtk_crtc_atomic_begin(struct drm_crtc *crtc,
 797                                   struct drm_atomic_state *state)
 798 {
 799         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 800                                                                           crtc);
 801         struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
 802         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 803         unsigned long flags;
 804
 805         if (mtk_crtc->event && mtk_crtc_state->base.event)
 806                 DRM_ERROR("new event while there is still a pending event\n");
 807
 808         if (mtk_crtc_state->base.event) {
 809                 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
 810                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 811
 812                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
 813                 mtk_crtc->event = mtk_crtc_state->base.event;
 814                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 815
 816                 mtk_crtc_state->base.event = NULL;
 817         }
 818 }
 819
 820 static void mtk_crtc_atomic_flush(struct drm_crtc *crtc,
 821                                   struct drm_atomic_state *state)
 822 {
 823         struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
 824         int i;
 825
 826         if (crtc->state->color_mgmt_changed)
 827                 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 828                         mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
 829                         mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
 830                 }
 831         mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
 832 }
 833
 834 static const struct drm_crtc_funcs mtk_crtc_funcs = {
 835         .set_config             = drm_atomic_helper_set_config,
 836         .page_flip              = drm_atomic_helper_page_flip,
 837         .destroy                = mtk_crtc_destroy,
 838         .reset                  = mtk_crtc_reset,
 839         .atomic_duplicate_state = mtk_crtc_duplicate_state,
 840         .atomic_destroy_state   = mtk_crtc_destroy_state,
 841         .enable_vblank          = mtk_crtc_enable_vblank,
 842         .disable_vblank         = mtk_crtc_disable_vblank,
 843 };
 844
 845 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
 846         .mode_fixup     = mtk_crtc_mode_fixup,
 847         .mode_set_nofb  = mtk_crtc_mode_set_nofb,
 848         .mode_valid     = mtk_crtc_mode_valid,
 849         .atomic_begin   = mtk_crtc_atomic_begin,
 850         .atomic_flush   = mtk_crtc_atomic_flush,
 851         .atomic_enable  = mtk_crtc_atomic_enable,
 852         .atomic_disable = mtk_crtc_atomic_disable,
 853 };
 854
 855 static int mtk_crtc_init(struct drm_device *drm, struct mtk_crtc *mtk_crtc,
 856                          unsigned int pipe)
 857 {
 858         struct drm_plane *primary = NULL;
 859         struct drm_plane *cursor = NULL;
 860         int i, ret;
 861
 862         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 863                 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
 864                         primary = &mtk_crtc->planes[i];
 865                 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
 866                         cursor = &mtk_crtc->planes[i];
 867         }
 868
 869         ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
 870                                         &mtk_crtc_funcs, NULL);
 871         if (ret)
 872                 goto err_cleanup_crtc;
 873
 874         drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
 875
 876         return 0;
 877
 878 err_cleanup_crtc:
 879         drm_crtc_cleanup(&mtk_crtc->base);
 880         return ret;
 881 }
 882
 883 static int mtk_crtc_num_comp_planes(struct mtk_crtc *mtk_crtc, int comp_idx)
 884 {
 885         struct mtk_ddp_comp *comp;
 886
 887         if (comp_idx > 1)
 888                 return 0;
 889
 890         comp = mtk_crtc->ddp_comp[comp_idx];
 891         if (!comp->funcs)
 892                 return 0;
 893
 894         if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
 895                 return 0;
 896
 897         return mtk_ddp_comp_layer_nr(comp);
 898 }
 899
 900 static inline
 901 enum drm_plane_type mtk_crtc_plane_type(unsigned int plane_idx,
 902                                         unsigned int num_planes)
 903 {
 904         if (plane_idx == 0)
 905                 return DRM_PLANE_TYPE_PRIMARY;
 906         else if (plane_idx == (num_planes - 1))
 907                 return DRM_PLANE_TYPE_CURSOR;
 908         else
 909                 return DRM_PLANE_TYPE_OVERLAY;
 910
 911 }
 912
 913 static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
 914                                      struct mtk_crtc *mtk_crtc,
 915                                      int comp_idx, int pipe)
 916 {
 917         int num_planes = mtk_crtc_num_comp_planes(mtk_crtc, comp_idx);
 918         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
 919         int i, ret;
 920
 921         for (i = 0; i < num_planes; i++) {
 922                 ret = mtk_plane_init(drm_dev,
 923                                 &mtk_crtc->planes[mtk_crtc->layer_nr],
 924                                 BIT(pipe),
 925                                 mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes),
 926                                 mtk_ddp_comp_supported_rotations(comp),
 927                                 mtk_ddp_comp_get_formats(comp),
 928                                 mtk_ddp_comp_get_num_formats(comp));
 929                 if (ret)
 930                         return ret;
 931
 932                 mtk_crtc->layer_nr++;
 933         }
 934         return 0;
 935 }
 936
 937 struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc)
 938 {
 939         struct mtk_crtc *mtk_crtc = NULL;
 940
 941         if (!crtc)
 942                 return NULL;
 943
 944         mtk_crtc = to_mtk_crtc(crtc);
 945         if (!mtk_crtc)
 946                 return NULL;
 947
 948         return mtk_crtc->dma_dev;
 949 }
 950
 951 int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
 952                     unsigned int path_len, int priv_data_index,
 953                     const struct mtk_drm_route *conn_routes,
 954                     unsigned int num_conn_routes)
 955 {
 956         struct mtk_drm_private *priv = drm_dev->dev_private;
 957         struct device *dev = drm_dev->dev;
 958         struct mtk_crtc *mtk_crtc;
 959         unsigned int num_comp_planes = 0;
 960         int ret;
 961         int i;
 962         bool has_ctm = false;
 963         uint gamma_lut_size = 0;
 964         struct drm_crtc *tmp;
 965         int crtc_i = 0;
 966
 967         if (!path)
 968                 return 0;
 969
 970         priv = priv->all_drm_private[priv_data_index];
 971
 972         drm_for_each_crtc(tmp, drm_dev)
 973                 crtc_i++;
 974
 975         for (i = 0; i < path_len; i++) {
 976                 enum mtk_ddp_comp_id comp_id = path[i];
 977                 struct device_node *node;
 978                 struct mtk_ddp_comp *comp;
 979
 980                 node = priv->comp_node[comp_id];
 981                 comp = &priv->ddp_comp[comp_id];
 982
 983                 /* Not all drm components have a DTS device node, such as ovl_adaptor,
 984                  * which is the drm bring up sub driver
 985                  */
 986                 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) {
 987                         dev_info(dev,
 988                                 "Not creating crtc %d because component %d is disabled or missing\n",
 989                                 crtc_i, comp_id);
 990                         return 0;
 991                 }
 992
 993                 if (!comp->dev) {
 994                         dev_err(dev, "Component %pOF not initialized\n", node);
 995                         return -ENODEV;
 996                 }
 997         }
 998
 999         mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
1000         if (!mtk_crtc)
1001                 return -ENOMEM;
1002
1003         mtk_crtc->mmsys_dev = priv->mmsys_dev;
1004         mtk_crtc->ddp_comp_nr = path_len;
1005         mtk_crtc->ddp_comp = devm_kcalloc(dev,
1006                                           mtk_crtc->ddp_comp_nr + (conn_routes ? 1 : 0),
1007                                           sizeof(*mtk_crtc->ddp_comp),
1008                                           GFP_KERNEL);
1009         if (!mtk_crtc->ddp_comp)
1010                 return -ENOMEM;
1011
1012         mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
1013         if (IS_ERR(mtk_crtc->mutex)) {
1014                 ret = PTR_ERR(mtk_crtc->mutex);
1015                 dev_err(dev, "Failed to get mutex: %d\n", ret);
1016                 return ret;
1017         }
1018
1019         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1020                 unsigned int comp_id = path[i];
1021                 struct mtk_ddp_comp *comp;
1022
1023                 comp = &priv->ddp_comp[comp_id];
1024                 mtk_crtc->ddp_comp[i] = comp;
1025
1026                 if (comp->funcs) {
1027                         if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) {
1028                                 unsigned int lut_sz = mtk_ddp_gamma_get_lut_size(comp);
1029
1030                                 if (lut_sz)
1031                                         gamma_lut_size = lut_sz;
1032                         }
1033
1034                         if (comp->funcs->ctm_set)
1035                                 has_ctm = true;
1036                 }
1037
1038                 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq,
1039                                                 &mtk_crtc->base);
1040         }
1041
1042         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
1043                 num_comp_planes += mtk_crtc_num_comp_planes(mtk_crtc, i);
1044
1045         mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
1046                                         sizeof(struct drm_plane), GFP_KERNEL);
1047         if (!mtk_crtc->planes)
1048                 return -ENOMEM;
1049
1050         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1051                 ret = mtk_crtc_init_comp_planes(drm_dev, mtk_crtc, i, crtc_i);
1052                 if (ret)
1053                         return ret;
1054         }
1055
1056         /*
1057          * Default to use the first component as the dma dev.
1058          * In the case of ovl_adaptor sub driver, it needs to use the
1059          * dma_dev_get function to get representative dma dev.
1060          */
1061         mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]);
1062
1063         ret = mtk_crtc_init(drm_dev, mtk_crtc, crtc_i);
1064         if (ret < 0)
1065                 return ret;
1066
1067         if (gamma_lut_size)
1068                 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
1069         drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
1070         mutex_init(&mtk_crtc->hw_lock);
1071
1072 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
1073         i = priv->mbox_index++;
1074         mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
1075         mtk_crtc->cmdq_client.client.tx_block = false;
1076         mtk_crtc->cmdq_client.client.knows_txdone = true;
1077         mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
1078         mtk_crtc->cmdq_client.chan =
1079                         mbox_request_channel(&mtk_crtc->cmdq_client.client, i);
1080         if (IS_ERR(mtk_crtc->cmdq_client.chan)) {
1081                 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
1082                         drm_crtc_index(&mtk_crtc->base));
1083                 mtk_crtc->cmdq_client.chan = NULL;
1084         }
1085
1086         if (mtk_crtc->cmdq_client.chan) {
1087                 ret = of_property_read_u32_index(priv->mutex_node,
1088                                                  "mediatek,gce-events",
1089                                                  i,
1090                                                  &mtk_crtc->cmdq_event);
1091                 if (ret) {
1092                         dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
1093                                 drm_crtc_index(&mtk_crtc->base));
1094                         mbox_free_channel(mtk_crtc->cmdq_client.chan);
1095                         mtk_crtc->cmdq_client.chan = NULL;
1096                 } else {
1097                         ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client,
1098                                                       &mtk_crtc->cmdq_handle,
1099                                                       PAGE_SIZE);
1100                         if (ret) {
1101                                 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
1102                                         drm_crtc_index(&mtk_crtc->base));
1103                                 mbox_free_channel(mtk_crtc->cmdq_client.chan);
1104                                 mtk_crtc->cmdq_client.chan = NULL;
1105                         }
1106                 }
1107
1108                 /* for sending blocking cmd in crtc disable */
1109                 init_waitqueue_head(&mtk_crtc->cb_blocking_queue);
1110         }
1111 #endif
1112
1113         if (conn_routes) {
1114                 for (i = 0; i < num_conn_routes; i++) {
1115                         unsigned int comp_id = conn_routes[i].route_ddp;
1116                         struct device_node *node = priv->comp_node[comp_id];
1117                         struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
1118
1119                         if (!comp->dev) {
1120                                 dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n",
1121                                         comp_id, node);
1122                                 /* mark encoder_index to -1, if route comp device is not enabled */
1123                                 comp->encoder_index = -1;
1124                                 continue;
1125                         }
1126
1127                         mtk_ddp_comp_encoder_index_set(&priv->ddp_comp[comp_id]);
1128                 }
1129
1130                 mtk_crtc->num_conn_routes = num_conn_routes;
1131                 mtk_crtc->conn_routes = conn_routes;
1132
1133                 /* increase ddp_comp_nr at the end of mtk_crtc_create */
1134                 mtk_crtc->ddp_comp_nr++;
1135         }
1136
1137         return 0;
1138 }