drivers/gpu/drm/i915/display/intel_sprite_regs.h

   1 /* SPDX-License-Identifier: MIT */
   2 /* Copyright © 2024 Intel Corporation */
   3
   4 #ifndef __INTEL_SPRITE_REGS__
   5 #define __INTEL_SPRITE_REGS__
   6
   7 #include "intel_display_reg_defs.h"
   8
   9 #define _DVSACNTR               0x72180
  10 #define   DVS_ENABLE                    REG_BIT(31)
  11 #define   DVS_PIPE_GAMMA_ENABLE         REG_BIT(30)
  12 #define   DVS_YUV_RANGE_CORRECTION_DISABLE      REG_BIT(27)
  13 #define   DVS_FORMAT_MASK               REG_GENMASK(26, 25)
  14 #define   DVS_FORMAT_YUV422             REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
  15 #define   DVS_FORMAT_RGBX101010         REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
  16 #define   DVS_FORMAT_RGBX888            REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
  17 #define   DVS_FORMAT_RGBX161616         REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
  18 #define   DVS_PIPE_CSC_ENABLE           REG_BIT(24)
  19 #define   DVS_SOURCE_KEY                REG_BIT(22)
  20 #define   DVS_RGB_ORDER_XBGR            REG_BIT(20)
  21 #define   DVS_YUV_FORMAT_BT709          REG_BIT(18)
  22 #define   DVS_YUV_ORDER_MASK            REG_GENMASK(17, 16)
  23 #define   DVS_YUV_ORDER_YUYV            REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
  24 #define   DVS_YUV_ORDER_UYVY            REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
  25 #define   DVS_YUV_ORDER_YVYU            REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
  26 #define   DVS_YUV_ORDER_VYUY            REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
  27 #define   DVS_ROTATE_180                REG_BIT(15)
  28 #define   DVS_TRICKLE_FEED_DISABLE      REG_BIT(14)
  29 #define   DVS_TILED                     REG_BIT(10)
  30 #define   DVS_DEST_KEY                  REG_BIT(2)
  31 #define _DVSALINOFF             0x72184
  32 #define _DVSASTRIDE             0x72188
  33 #define _DVSAPOS                0x7218c
  34 #define   DVS_POS_Y_MASK                REG_GENMASK(31, 16)
  35 #define   DVS_POS_Y(y)                  REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
  36 #define   DVS_POS_X_MASK                REG_GENMASK(15, 0)
  37 #define   DVS_POS_X(x)                  REG_FIELD_PREP(DVS_POS_X_MASK, (x))
  38 #define _DVSASIZE               0x72190
  39 #define   DVS_HEIGHT_MASK               REG_GENMASK(31, 16)
  40 #define   DVS_HEIGHT(h)                 REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
  41 #define   DVS_WIDTH_MASK                REG_GENMASK(15, 0)
  42 #define   DVS_WIDTH(w)                  REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
  43 #define _DVSAKEYVAL             0x72194
  44 #define _DVSAKEYMSK             0x72198
  45 #define _DVSASURF               0x7219c
  46 #define   DVS_ADDR_MASK                 REG_GENMASK(31, 12)
  47 #define _DVSAKEYMAXVAL          0x721a0
  48 #define _DVSATILEOFF            0x721a4
  49 #define   DVS_OFFSET_Y_MASK             REG_GENMASK(31, 16)
  50 #define   DVS_OFFSET_Y(y)               REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
  51 #define   DVS_OFFSET_X_MASK             REG_GENMASK(15, 0)
  52 #define   DVS_OFFSET_X(x)               REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
  53 #define _DVSASURFLIVE           0x721ac
  54 #define _DVSAGAMC_G4X           0x721e0 /* g4x */
  55 #define _DVSASCALE              0x72204
  56 #define   DVS_SCALE_ENABLE              REG_BIT(31)
  57 #define   DVS_FILTER_MASK               REG_GENMASK(30, 29)
  58 #define   DVS_FILTER_MEDIUM             REG_FIELD_PREP(DVS_FILTER_MASK, 0)
  59 #define   DVS_FILTER_ENHANCING          REG_FIELD_PREP(DVS_FILTER_MASK, 1)
  60 #define   DVS_FILTER_SOFTENING          REG_FIELD_PREP(DVS_FILTER_MASK, 2)
  61 #define   DVS_VERTICAL_OFFSET_HALF      REG_BIT(28) /* must be enabled below */
  62 #define   DVS_VERTICAL_OFFSET_ENABLE    REG_BIT(27)
  63 #define   DVS_SRC_WIDTH_MASK            REG_GENMASK(26, 16)
  64 #define   DVS_SRC_WIDTH(w)              REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
  65 #define   DVS_SRC_HEIGHT_MASK           REG_GENMASK(10, 0)
  66 #define   DVS_SRC_HEIGHT(h)             REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
  67 #define _DVSAGAMC_ILK           0x72300 /* ilk/snb */
  68 #define _DVSAGAMCMAX_ILK        0x72340 /* ilk/snb */
  69
  70 #define _DVSBCNTR               0x73180
  71 #define _DVSBLINOFF             0x73184
  72 #define _DVSBSTRIDE             0x73188
  73 #define _DVSBPOS                0x7318c
  74 #define _DVSBSIZE               0x73190
  75 #define _DVSBKEYVAL             0x73194
  76 #define _DVSBKEYMSK             0x73198
  77 #define _DVSBSURF               0x7319c
  78 #define _DVSBKEYMAXVAL          0x731a0
  79 #define _DVSBTILEOFF            0x731a4
  80 #define _DVSBSURFLIVE           0x731ac
  81 #define _DVSBGAMC_G4X           0x731e0 /* g4x */
  82 #define _DVSBSCALE              0x73204
  83 #define _DVSBGAMC_ILK           0x73300 /* ilk/snb */
  84 #define _DVSBGAMCMAX_ILK        0x73340 /* ilk/snb */
  85
  86 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
  87 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
  88 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
  89 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
  90 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
  91 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
  92 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
  93 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
  94 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
  95 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
  96 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
  97 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
  98 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
  99 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
 100 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
 101
 102 #define _SPRA_CTL               0x70280
 103 #define   SPRITE_ENABLE                         REG_BIT(31)
 104 #define   SPRITE_PIPE_GAMMA_ENABLE              REG_BIT(30)
 105 #define   SPRITE_YUV_RANGE_CORRECTION_DISABLE   REG_BIT(28)
 106 #define   SPRITE_FORMAT_MASK                    REG_GENMASK(27, 25)
 107 #define   SPRITE_FORMAT_YUV422                  REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
 108 #define   SPRITE_FORMAT_RGBX101010              REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
 109 #define   SPRITE_FORMAT_RGBX888                 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
 110 #define   SPRITE_FORMAT_RGBX161616              REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
 111 #define   SPRITE_FORMAT_YUV444                  REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
 112 #define   SPRITE_FORMAT_XR_BGR101010            REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
 113 #define   SPRITE_PIPE_CSC_ENABLE                REG_BIT(24)
 114 #define   SPRITE_SOURCE_KEY                     REG_BIT(22)
 115 #define   SPRITE_RGB_ORDER_RGBX                 REG_BIT(20) /* only for 888 and 161616 */
 116 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE         REG_BIT(19)
 117 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709    REG_BIT(18) /* 0 is BT601 */
 118 #define   SPRITE_YUV_ORDER_MASK                 REG_GENMASK(17, 16)
 119 #define   SPRITE_YUV_ORDER_YUYV                 REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
 120 #define   SPRITE_YUV_ORDER_UYVY                 REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
 121 #define   SPRITE_YUV_ORDER_YVYU                 REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
 122 #define   SPRITE_YUV_ORDER_VYUY                 REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
 123 #define   SPRITE_ROTATE_180                     REG_BIT(15)
 124 #define   SPRITE_TRICKLE_FEED_DISABLE           REG_BIT(14)
 125 #define   SPRITE_PLANE_GAMMA_DISABLE            REG_BIT(13)
 126 #define   SPRITE_TILED                          REG_BIT(10)
 127 #define   SPRITE_DEST_KEY                       REG_BIT(2)
 128 #define _SPRA_LINOFF            0x70284
 129 #define _SPRA_STRIDE            0x70288
 130 #define _SPRA_POS               0x7028c
 131 #define   SPRITE_POS_Y_MASK     REG_GENMASK(31, 16)
 132 #define   SPRITE_POS_Y(y)       REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
 133 #define   SPRITE_POS_X_MASK     REG_GENMASK(15, 0)
 134 #define   SPRITE_POS_X(x)       REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
 135 #define _SPRA_SIZE              0x70290
 136 #define   SPRITE_HEIGHT_MASK    REG_GENMASK(31, 16)
 137 #define   SPRITE_HEIGHT(h)      REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
 138 #define   SPRITE_WIDTH_MASK     REG_GENMASK(15, 0)
 139 #define   SPRITE_WIDTH(w)       REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
 140 #define _SPRA_KEYVAL            0x70294
 141 #define _SPRA_KEYMSK            0x70298
 142 #define _SPRA_SURF              0x7029c
 143 #define   SPRITE_ADDR_MASK      REG_GENMASK(31, 12)
 144 #define _SPRA_KEYMAX            0x702a0
 145 #define _SPRA_TILEOFF           0x702a4
 146 #define   SPRITE_OFFSET_Y_MASK  REG_GENMASK(31, 16)
 147 #define   SPRITE_OFFSET_Y(y)    REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
 148 #define   SPRITE_OFFSET_X_MASK  REG_GENMASK(15, 0)
 149 #define   SPRITE_OFFSET_X(x)    REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
 150 #define _SPRA_OFFSET            0x702a4
 151 #define _SPRA_SURFLIVE          0x702ac
 152 #define _SPRA_SCALE             0x70304
 153 #define   SPRITE_SCALE_ENABLE                   REG_BIT(31)
 154 #define   SPRITE_FILTER_MASK                    REG_GENMASK(30, 29)
 155 #define   SPRITE_FILTER_MEDIUM                  REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
 156 #define   SPRITE_FILTER_ENHANCING               REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
 157 #define   SPRITE_FILTER_SOFTENING               REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
 158 #define   SPRITE_VERTICAL_OFFSET_HALF           REG_BIT(28) /* must be enabled below */
 159 #define   SPRITE_VERTICAL_OFFSET_ENABLE         REG_BIT(27)
 160 #define   SPRITE_SRC_WIDTH_MASK                 REG_GENMASK(26, 16)
 161 #define   SPRITE_SRC_WIDTH(w)                   REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
 162 #define   SPRITE_SRC_HEIGHT_MASK                REG_GENMASK(10, 0)
 163 #define   SPRITE_SRC_HEIGHT(h)                  REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
 164 #define _SPRA_GAMC              0x70400
 165 #define _SPRA_GAMC16            0x70440
 166 #define _SPRA_GAMC17            0x7044c
 167
 168 #define _SPRB_CTL               0x71280
 169 #define _SPRB_LINOFF            0x71284
 170 #define _SPRB_STRIDE            0x71288
 171 #define _SPRB_POS               0x7128c
 172 #define _SPRB_SIZE              0x71290
 173 #define _SPRB_KEYVAL            0x71294
 174 #define _SPRB_KEYMSK            0x71298
 175 #define _SPRB_SURF              0x7129c
 176 #define _SPRB_KEYMAX            0x712a0
 177 #define _SPRB_TILEOFF           0x712a4
 178 #define _SPRB_OFFSET            0x712a4
 179 #define _SPRB_SURFLIVE          0x712ac
 180 #define _SPRB_SCALE             0x71304
 181 #define _SPRB_GAMC              0x71400
 182 #define _SPRB_GAMC16            0x71440
 183 #define _SPRB_GAMC17            0x7144c
 184
 185 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
 186 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
 187 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
 188 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
 189 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
 190 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
 191 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
 192 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
 193 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
 194 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
 195 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
 196 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
 197 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
 198 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
 199 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
 200 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
 201
 202 #define _SPACNTR                (VLV_DISPLAY_BASE + 0x72180)
 203 #define   SP_ENABLE                     REG_BIT(31)
 204 #define   SP_PIPE_GAMMA_ENABLE          REG_BIT(30)
 205 #define   SP_FORMAT_MASK                REG_GENMASK(29, 26)
 206 #define   SP_FORMAT_YUV422              REG_FIELD_PREP(SP_FORMAT_MASK, 0)
 207 #define   SP_FORMAT_8BPP                REG_FIELD_PREP(SP_FORMAT_MASK, 2)
 208 #define   SP_FORMAT_BGR565              REG_FIELD_PREP(SP_FORMAT_MASK, 5)
 209 #define   SP_FORMAT_BGRX8888            REG_FIELD_PREP(SP_FORMAT_MASK, 6)
 210 #define   SP_FORMAT_BGRA8888            REG_FIELD_PREP(SP_FORMAT_MASK, 7)
 211 #define   SP_FORMAT_RGBX1010102         REG_FIELD_PREP(SP_FORMAT_MASK, 8)
 212 #define   SP_FORMAT_RGBA1010102         REG_FIELD_PREP(SP_FORMAT_MASK, 9)
 213 #define   SP_FORMAT_BGRX1010102         REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
 214 #define   SP_FORMAT_BGRA1010102         REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
 215 #define   SP_FORMAT_RGBX8888            REG_FIELD_PREP(SP_FORMAT_MASK, 14)
 216 #define   SP_FORMAT_RGBA8888            REG_FIELD_PREP(SP_FORMAT_MASK, 15)
 217 #define   SP_ALPHA_PREMULTIPLY          REG_BIT(23) /* CHV pipe B */
 218 #define   SP_SOURCE_KEY                 REG_BIT(22)
 219 #define   SP_YUV_FORMAT_BT709           REG_BIT(18)
 220 #define   SP_YUV_ORDER_MASK             REG_GENMASK(17, 16)
 221 #define   SP_YUV_ORDER_YUYV             REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
 222 #define   SP_YUV_ORDER_UYVY             REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
 223 #define   SP_YUV_ORDER_YVYU             REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
 224 #define   SP_YUV_ORDER_VYUY             REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
 225 #define   SP_ROTATE_180                 REG_BIT(15)
 226 #define   SP_TILED                      REG_BIT(10)
 227 #define   SP_MIRROR                     REG_BIT(8) /* CHV pipe B */
 228 #define _SPALINOFF              (VLV_DISPLAY_BASE + 0x72184)
 229 #define _SPASTRIDE              (VLV_DISPLAY_BASE + 0x72188)
 230 #define _SPAPOS                 (VLV_DISPLAY_BASE + 0x7218c)
 231 #define   SP_POS_Y_MASK                 REG_GENMASK(31, 16)
 232 #define   SP_POS_Y(y)                   REG_FIELD_PREP(SP_POS_Y_MASK, (y))
 233 #define   SP_POS_X_MASK                 REG_GENMASK(15, 0)
 234 #define   SP_POS_X(x)                   REG_FIELD_PREP(SP_POS_X_MASK, (x))
 235 #define _SPASIZE                (VLV_DISPLAY_BASE + 0x72190)
 236 #define   SP_HEIGHT_MASK                REG_GENMASK(31, 16)
 237 #define   SP_HEIGHT(h)                  REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
 238 #define   SP_WIDTH_MASK                 REG_GENMASK(15, 0)
 239 #define   SP_WIDTH(w)                   REG_FIELD_PREP(SP_WIDTH_MASK, (w))
 240 #define _SPAKEYMINVAL           (VLV_DISPLAY_BASE + 0x72194)
 241 #define _SPAKEYMSK              (VLV_DISPLAY_BASE + 0x72198)
 242 #define _SPASURF                (VLV_DISPLAY_BASE + 0x7219c)
 243 #define   SP_ADDR_MASK                  REG_GENMASK(31, 12)
 244 #define _SPAKEYMAXVAL           (VLV_DISPLAY_BASE + 0x721a0)
 245 #define _SPATILEOFF             (VLV_DISPLAY_BASE + 0x721a4)
 246 #define   SP_OFFSET_Y_MASK              REG_GENMASK(31, 16)
 247 #define   SP_OFFSET_Y(y)                REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
 248 #define   SP_OFFSET_X_MASK              REG_GENMASK(15, 0)
 249 #define   SP_OFFSET_X(x)                REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
 250 #define _SPACONSTALPHA          (VLV_DISPLAY_BASE + 0x721a8)
 251 #define   SP_CONST_ALPHA_ENABLE         REG_BIT(31)
 252 #define   SP_CONST_ALPHA_MASK           REG_GENMASK(7, 0)
 253 #define   SP_CONST_ALPHA(alpha)         REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
 254 #define _SPASURFLIVE            (VLV_DISPLAY_BASE + 0x721ac)
 255 #define _SPACLRC0               (VLV_DISPLAY_BASE + 0x721d0)
 256 #define   SP_CONTRAST_MASK              REG_GENMASK(26, 18)
 257 #define   SP_CONTRAST(x)                REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
 258 #define   SP_BRIGHTNESS_MASK            REG_GENMASK(7, 0)
 259 #define   SP_BRIGHTNESS(x)              REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
 260 #define _SPACLRC1               (VLV_DISPLAY_BASE + 0x721d4)
 261 #define   SP_SH_SIN_MASK                REG_GENMASK(26, 16)
 262 #define   SP_SH_SIN(x)                  REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
 263 #define   SP_SH_COS_MASK                REG_GENMASK(9, 0)
 264 #define   SP_SH_COS(x)                  REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
 265 #define _SPAGAMC                (VLV_DISPLAY_BASE + 0x721e0)
 266
 267 #define _SPBCNTR                (VLV_DISPLAY_BASE + 0x72280)
 268 #define _SPBLINOFF              (VLV_DISPLAY_BASE + 0x72284)
 269 #define _SPBSTRIDE              (VLV_DISPLAY_BASE + 0x72288)
 270 #define _SPBPOS                 (VLV_DISPLAY_BASE + 0x7228c)
 271 #define _SPBSIZE                (VLV_DISPLAY_BASE + 0x72290)
 272 #define _SPBKEYMINVAL           (VLV_DISPLAY_BASE + 0x72294)
 273 #define _SPBKEYMSK              (VLV_DISPLAY_BASE + 0x72298)
 274 #define _SPBSURF                (VLV_DISPLAY_BASE + 0x7229c)
 275 #define _SPBKEYMAXVAL           (VLV_DISPLAY_BASE + 0x722a0)
 276 #define _SPBTILEOFF             (VLV_DISPLAY_BASE + 0x722a4)
 277 #define _SPBCONSTALPHA          (VLV_DISPLAY_BASE + 0x722a8)
 278 #define _SPBSURFLIVE            (VLV_DISPLAY_BASE + 0x722ac)
 279 #define _SPBCLRC0               (VLV_DISPLAY_BASE + 0x722d0)
 280 #define _SPBCLRC1               (VLV_DISPLAY_BASE + 0x722d4)
 281 #define _SPBGAMC                (VLV_DISPLAY_BASE + 0x722e0)
 282
 283 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
 284         _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
 285 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
 286         _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
 287
 288 #define SPCNTR(pipe, plane_id)          _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
 289 #define SPLINOFF(pipe, plane_id)        _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
 290 #define SPSTRIDE(pipe, plane_id)        _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
 291 #define SPPOS(pipe, plane_id)           _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
 292 #define SPSIZE(pipe, plane_id)          _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
 293 #define SPKEYMINVAL(pipe, plane_id)     _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
 294 #define SPKEYMSK(pipe, plane_id)        _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
 295 #define SPSURF(pipe, plane_id)          _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
 296 #define SPKEYMAXVAL(pipe, plane_id)     _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
 297 #define SPTILEOFF(pipe, plane_id)       _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
 298 #define SPCONSTALPHA(pipe, plane_id)    _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
 299 #define SPSURFLIVE(pipe, plane_id)      _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
 300 #define SPCLRC0(pipe, plane_id)         _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
 301 #define SPCLRC1(pipe, plane_id)         _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
 302 #define SPGAMC(pipe, plane_id, i)       _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
 303
 304 /*
 305  * CHV pipe B sprite CSC
 306  *
 307  * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
 308  * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
 309  * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
 310  */
 311 #define _MMIO_CHV_SPCSC(plane_id, reg) \
 312         _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
 313
 314 #define SPCSCYGOFF(plane_id)    _MMIO_CHV_SPCSC(plane_id, 0x6d900)
 315 #define SPCSCCBOFF(plane_id)    _MMIO_CHV_SPCSC(plane_id, 0x6d904)
 316 #define SPCSCCROFF(plane_id)    _MMIO_CHV_SPCSC(plane_id, 0x6d908)
 317 #define  SPCSC_OOFF_MASK        REG_GENMASK(26, 16)
 318 #define  SPCSC_OOFF(x)          REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
 319 #define  SPCSC_IOFF_MASK        REG_GENMASK(10, 0)
 320 #define  SPCSC_IOFF(x)          REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
 321
 322 #define SPCSCC01(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
 323 #define SPCSCC23(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d910)
 324 #define SPCSCC45(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d914)
 325 #define SPCSCC67(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d918)
 326 #define SPCSCC8(plane_id)       _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
 327 #define  SPCSC_C1_MASK          REG_GENMASK(30, 16)
 328 #define  SPCSC_C1(x)            REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
 329 #define  SPCSC_C0_MASK          REG_GENMASK(14, 0)
 330 #define  SPCSC_C0(x)            REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
 331
 332 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
 333 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
 334 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
 335 #define  SPCSC_IMAX_MASK        REG_GENMASK(26, 16)
 336 #define  SPCSC_IMAX(x)          REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
 337 #define  SPCSC_IMIN_MASK        REG_GENMASK(10, 0)
 338 #define  SPCSC_IMIN(x)          REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
 339
 340 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
 341 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
 342 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
 343 #define  SPCSC_OMAX_MASK        REG_GENMASK(25, 16)
 344 #define  SPCSC_OMAX(x)          REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
 345 #define  SPCSC_OMIN_MASK        REG_GENMASK(9, 0)
 346 #define  SPCSC_OMIN(x)          REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
 347
 348 #endif /* __INTEL_SPRITE_REGS__ */