drivers/gpu/drm/i915/display/intel_dpll.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/string_helpers.h>
   8
   9 #include "i915_reg.h"
  10 #include "intel_atomic.h"
  11 #include "intel_crtc.h"
  12 #include "intel_cx0_phy.h"
  13 #include "intel_de.h"
  14 #include "intel_display.h"
  15 #include "intel_display_types.h"
  16 #include "intel_dpio_phy.h"
  17 #include "intel_dpll.h"
  18 #include "intel_lvds.h"
  19 #include "intel_lvds_regs.h"
  20 #include "intel_panel.h"
  21 #include "intel_pps.h"
  22 #include "intel_snps_phy.h"
  23 #include "vlv_dpio_phy_regs.h"
  24 #include "vlv_sideband.h"
  25
  26 struct intel_dpll_funcs {
  27         int (*crtc_compute_clock)(struct intel_atomic_state *state,
  28                                   struct intel_crtc *crtc);
  29         int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
  30                                     struct intel_crtc *crtc);
  31 };
  32
  33 struct intel_limit {
  34         struct {
  35                 int min, max;
  36         } dot, vco, n, m, m1, m2, p, p1;
  37
  38         struct {
  39                 int dot_limit;
  40                 int p2_slow, p2_fast;
  41         } p2;
  42 };
  43 static const struct intel_limit intel_limits_i8xx_dac = {
  44         .dot = { .min = 25000, .max = 350000 },
  45         .vco = { .min = 908000, .max = 1512000 },
  46         .n = { .min = 2, .max = 16 },
  47         .m = { .min = 96, .max = 140 },
  48         .m1 = { .min = 18, .max = 26 },
  49         .m2 = { .min = 6, .max = 16 },
  50         .p = { .min = 4, .max = 128 },
  51         .p1 = { .min = 2, .max = 33 },
  52         .p2 = { .dot_limit = 165000,
  53                 .p2_slow = 4, .p2_fast = 2 },
  54 };
  55
  56 static const struct intel_limit intel_limits_i8xx_dvo = {
  57         .dot = { .min = 25000, .max = 350000 },
  58         .vco = { .min = 908000, .max = 1512000 },
  59         .n = { .min = 2, .max = 16 },
  60         .m = { .min = 96, .max = 140 },
  61         .m1 = { .min = 18, .max = 26 },
  62         .m2 = { .min = 6, .max = 16 },
  63         .p = { .min = 4, .max = 128 },
  64         .p1 = { .min = 2, .max = 33 },
  65         .p2 = { .dot_limit = 165000,
  66                 .p2_slow = 4, .p2_fast = 4 },
  67 };
  68
  69 static const struct intel_limit intel_limits_i8xx_lvds = {
  70         .dot = { .min = 25000, .max = 350000 },
  71         .vco = { .min = 908000, .max = 1512000 },
  72         .n = { .min = 2, .max = 16 },
  73         .m = { .min = 96, .max = 140 },
  74         .m1 = { .min = 18, .max = 26 },
  75         .m2 = { .min = 6, .max = 16 },
  76         .p = { .min = 4, .max = 128 },
  77         .p1 = { .min = 1, .max = 6 },
  78         .p2 = { .dot_limit = 165000,
  79                 .p2_slow = 14, .p2_fast = 7 },
  80 };
  81
  82 static const struct intel_limit intel_limits_i9xx_sdvo = {
  83         .dot = { .min = 20000, .max = 400000 },
  84         .vco = { .min = 1400000, .max = 2800000 },
  85         .n = { .min = 1, .max = 6 },
  86         .m = { .min = 70, .max = 120 },
  87         .m1 = { .min = 8, .max = 18 },
  88         .m2 = { .min = 3, .max = 7 },
  89         .p = { .min = 5, .max = 80 },
  90         .p1 = { .min = 1, .max = 8 },
  91         .p2 = { .dot_limit = 200000,
  92                 .p2_slow = 10, .p2_fast = 5 },
  93 };
  94
  95 static const struct intel_limit intel_limits_i9xx_lvds = {
  96         .dot = { .min = 20000, .max = 400000 },
  97         .vco = { .min = 1400000, .max = 2800000 },
  98         .n = { .min = 1, .max = 6 },
  99         .m = { .min = 70, .max = 120 },
 100         .m1 = { .min = 8, .max = 18 },
 101         .m2 = { .min = 3, .max = 7 },
 102         .p = { .min = 7, .max = 98 },
 103         .p1 = { .min = 1, .max = 8 },
 104         .p2 = { .dot_limit = 112000,
 105                 .p2_slow = 14, .p2_fast = 7 },
 106 };
 107
 108
 109 static const struct intel_limit intel_limits_g4x_sdvo = {
 110         .dot = { .min = 25000, .max = 270000 },
 111         .vco = { .min = 1750000, .max = 3500000},
 112         .n = { .min = 1, .max = 4 },
 113         .m = { .min = 104, .max = 138 },
 114         .m1 = { .min = 17, .max = 23 },
 115         .m2 = { .min = 5, .max = 11 },
 116         .p = { .min = 10, .max = 30 },
 117         .p1 = { .min = 1, .max = 3},
 118         .p2 = { .dot_limit = 270000,
 119                 .p2_slow = 10,
 120                 .p2_fast = 10
 121         },
 122 };
 123
 124 static const struct intel_limit intel_limits_g4x_hdmi = {
 125         .dot = { .min = 22000, .max = 400000 },
 126         .vco = { .min = 1750000, .max = 3500000},
 127         .n = { .min = 1, .max = 4 },
 128         .m = { .min = 104, .max = 138 },
 129         .m1 = { .min = 16, .max = 23 },
 130         .m2 = { .min = 5, .max = 11 },
 131         .p = { .min = 5, .max = 80 },
 132         .p1 = { .min = 1, .max = 8},
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 10, .p2_fast = 5 },
 135 };
 136
 137 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 138         .dot = { .min = 20000, .max = 115000 },
 139         .vco = { .min = 1750000, .max = 3500000 },
 140         .n = { .min = 1, .max = 3 },
 141         .m = { .min = 104, .max = 138 },
 142         .m1 = { .min = 17, .max = 23 },
 143         .m2 = { .min = 5, .max = 11 },
 144         .p = { .min = 28, .max = 112 },
 145         .p1 = { .min = 2, .max = 8 },
 146         .p2 = { .dot_limit = 0,
 147                 .p2_slow = 14, .p2_fast = 14
 148         },
 149 };
 150
 151 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 152         .dot = { .min = 80000, .max = 224000 },
 153         .vco = { .min = 1750000, .max = 3500000 },
 154         .n = { .min = 1, .max = 3 },
 155         .m = { .min = 104, .max = 138 },
 156         .m1 = { .min = 17, .max = 23 },
 157         .m2 = { .min = 5, .max = 11 },
 158         .p = { .min = 14, .max = 42 },
 159         .p1 = { .min = 2, .max = 6 },
 160         .p2 = { .dot_limit = 0,
 161                 .p2_slow = 7, .p2_fast = 7
 162         },
 163 };
 164
 165 static const struct intel_limit pnv_limits_sdvo = {
 166         .dot = { .min = 20000, .max = 400000},
 167         .vco = { .min = 1700000, .max = 3500000 },
 168         /* Pineview's Ncounter is a ring counter */
 169         .n = { .min = 3, .max = 6 },
 170         .m = { .min = 2, .max = 256 },
 171         /* Pineview only has one combined m divider, which we treat as m2. */
 172         .m1 = { .min = 0, .max = 0 },
 173         .m2 = { .min = 0, .max = 254 },
 174         .p = { .min = 5, .max = 80 },
 175         .p1 = { .min = 1, .max = 8 },
 176         .p2 = { .dot_limit = 200000,
 177                 .p2_slow = 10, .p2_fast = 5 },
 178 };
 179
 180 static const struct intel_limit pnv_limits_lvds = {
 181         .dot = { .min = 20000, .max = 400000 },
 182         .vco = { .min = 1700000, .max = 3500000 },
 183         .n = { .min = 3, .max = 6 },
 184         .m = { .min = 2, .max = 256 },
 185         .m1 = { .min = 0, .max = 0 },
 186         .m2 = { .min = 0, .max = 254 },
 187         .p = { .min = 7, .max = 112 },
 188         .p1 = { .min = 1, .max = 8 },
 189         .p2 = { .dot_limit = 112000,
 190                 .p2_slow = 14, .p2_fast = 14 },
 191 };
 192
 193 /* Ironlake / Sandybridge
 194  *
 195  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 196  * the range value for them is (actual_value - 2).
 197  */
 198 static const struct intel_limit ilk_limits_dac = {
 199         .dot = { .min = 25000, .max = 350000 },
 200         .vco = { .min = 1760000, .max = 3510000 },
 201         .n = { .min = 1, .max = 5 },
 202         .m = { .min = 79, .max = 127 },
 203         .m1 = { .min = 12, .max = 22 },
 204         .m2 = { .min = 5, .max = 9 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 225000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const struct intel_limit ilk_limits_single_lvds = {
 212         .dot = { .min = 25000, .max = 350000 },
 213         .vco = { .min = 1760000, .max = 3510000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 79, .max = 118 },
 216         .m1 = { .min = 12, .max = 22 },
 217         .m2 = { .min = 5, .max = 9 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 225000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 static const struct intel_limit ilk_limits_dual_lvds = {
 225         .dot = { .min = 25000, .max = 350000 },
 226         .vco = { .min = 1760000, .max = 3510000 },
 227         .n = { .min = 1, .max = 3 },
 228         .m = { .min = 79, .max = 127 },
 229         .m1 = { .min = 12, .max = 22 },
 230         .m2 = { .min = 5, .max = 9 },
 231         .p = { .min = 14, .max = 56 },
 232         .p1 = { .min = 2, .max = 8 },
 233         .p2 = { .dot_limit = 225000,
 234                 .p2_slow = 7, .p2_fast = 7 },
 235 };
 236
 237 /* LVDS 100mhz refclk limits. */
 238 static const struct intel_limit ilk_limits_single_lvds_100m = {
 239         .dot = { .min = 25000, .max = 350000 },
 240         .vco = { .min = 1760000, .max = 3510000 },
 241         .n = { .min = 1, .max = 2 },
 242         .m = { .min = 79, .max = 126 },
 243         .m1 = { .min = 12, .max = 22 },
 244         .m2 = { .min = 5, .max = 9 },
 245         .p = { .min = 28, .max = 112 },
 246         .p1 = { .min = 2, .max = 8 },
 247         .p2 = { .dot_limit = 225000,
 248                 .p2_slow = 14, .p2_fast = 14 },
 249 };
 250
 251 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 252         .dot = { .min = 25000, .max = 350000 },
 253         .vco = { .min = 1760000, .max = 3510000 },
 254         .n = { .min = 1, .max = 3 },
 255         .m = { .min = 79, .max = 126 },
 256         .m1 = { .min = 12, .max = 22 },
 257         .m2 = { .min = 5, .max = 9 },
 258         .p = { .min = 14, .max = 42 },
 259         .p1 = { .min = 2, .max = 6 },
 260         .p2 = { .dot_limit = 225000,
 261                 .p2_slow = 7, .p2_fast = 7 },
 262 };
 263
 264 static const struct intel_limit intel_limits_vlv = {
 265          /*
 266           * These are based on the data rate limits (measured in fast clocks)
 267           * since those are the strictest limits we have. The fast
 268           * clock and actual rate limits are more relaxed, so checking
 269           * them would make no difference.
 270           */
 271         .dot = { .min = 25000, .max = 270000 },
 272         .vco = { .min = 4000000, .max = 6000000 },
 273         .n = { .min = 1, .max = 7 },
 274         .m1 = { .min = 2, .max = 3 },
 275         .m2 = { .min = 11, .max = 156 },
 276         .p1 = { .min = 2, .max = 3 },
 277         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 278 };
 279
 280 static const struct intel_limit intel_limits_chv = {
 281         /*
 282          * These are based on the data rate limits (measured in fast clocks)
 283          * since those are the strictest limits we have.  The fast
 284          * clock and actual rate limits are more relaxed, so checking
 285          * them would make no difference.
 286          */
 287         .dot = { .min = 25000, .max = 540000 },
 288         .vco = { .min = 4800000, .max = 6480000 },
 289         .n = { .min = 1, .max = 1 },
 290         .m1 = { .min = 2, .max = 2 },
 291         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 292         .p1 = { .min = 2, .max = 4 },
 293         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 294 };
 295
 296 static const struct intel_limit intel_limits_bxt = {
 297         .dot = { .min = 25000, .max = 594000 },
 298         .vco = { .min = 4800000, .max = 6700000 },
 299         .n = { .min = 1, .max = 1 },
 300         .m1 = { .min = 2, .max = 2 },
 301         /* FIXME: find real m2 limits */
 302         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 303         .p1 = { .min = 2, .max = 4 },
 304         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 305 };
 306
 307 /*
 308  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 309  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 310  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 311  * The helpers' return value is the rate of the clock that is fed to the
 312  * display engine's pipe which can be the above fast dot clock rate or a
 313  * divided-down version of it.
 314  */
 315 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 316 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 317 {
 318         clock->m = clock->m2 + 2;
 319         clock->p = clock->p1 * clock->p2;
 320
 321         clock->vco = clock->n == 0 ? 0 :
 322                 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 323         clock->dot = clock->p == 0 ? 0 :
 324                 DIV_ROUND_CLOSEST(clock->vco, clock->p);
 325
 326         return clock->dot;
 327 }
 328
 329 static u32 i9xx_dpll_compute_m(const struct dpll *dpll)
 330 {
 331         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 332 }
 333
 334 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 335 {
 336         clock->m = i9xx_dpll_compute_m(clock);
 337         clock->p = clock->p1 * clock->p2;
 338
 339         clock->vco = clock->n + 2 == 0 ? 0 :
 340                 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 341         clock->dot = clock->p == 0 ? 0 :
 342                 DIV_ROUND_CLOSEST(clock->vco, clock->p);
 343
 344         return clock->dot;
 345 }
 346
 347 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 348 {
 349         clock->m = clock->m1 * clock->m2;
 350         clock->p = clock->p1 * clock->p2 * 5;
 351
 352         clock->vco = clock->n == 0 ? 0 :
 353                 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 354         clock->dot = clock->p == 0 ? 0 :
 355                 DIV_ROUND_CLOSEST(clock->vco, clock->p);
 356
 357         return clock->dot;
 358 }
 359
 360 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 361 {
 362         clock->m = clock->m1 * clock->m2;
 363         clock->p = clock->p1 * clock->p2 * 5;
 364
 365         clock->vco = clock->n == 0 ? 0 :
 366                 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
 367         clock->dot = clock->p == 0 ? 0 :
 368                 DIV_ROUND_CLOSEST(clock->vco, clock->p);
 369
 370         return clock->dot;
 371 }
 372
 373 static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state)
 374 {
 375         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 376         const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 377
 378         if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
 379                 return i915->display.vbt.lvds_ssc_freq;
 380         else if (HAS_PCH_SPLIT(i915))
 381                 return 120000;
 382         else if (DISPLAY_VER(i915) != 2)
 383                 return 96000;
 384         else
 385                 return 48000;
 386 }
 387
 388 void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
 389                             struct intel_dpll_hw_state *dpll_hw_state)
 390 {
 391         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 392         struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
 393
 394         if (DISPLAY_VER(dev_priv) >= 4) {
 395                 u32 tmp;
 396
 397                 /* No way to read it out on pipes B and C */
 398                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
 399                         tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
 400                 else
 401                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
 402
 403                 hw_state->dpll_md = tmp;
 404         }
 405
 406         hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe));
 407
 408         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
 409                 hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe));
 410                 hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe));
 411         } else {
 412                 /* Mask out read-only status bits. */
 413                 hw_state->dpll &= ~(DPLL_LOCK_VLV |
 414                                     DPLL_PORTC_READY_MASK |
 415                                     DPLL_PORTB_READY_MASK);
 416         }
 417 }
 418
 419 /* Returns the clock of the currently programmed mode of the given pipe. */
 420 void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)
 421 {
 422         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 423         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 424         const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 425         u32 dpll = hw_state->dpll;
 426         u32 fp;
 427         struct dpll clock;
 428         int port_clock;
 429         int refclk = i9xx_pll_refclk(crtc_state);
 430
 431         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
 432                 fp = hw_state->fp0;
 433         else
 434                 fp = hw_state->fp1;
 435
 436         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
 437         if (IS_PINEVIEW(dev_priv)) {
 438                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
 439                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
 440         } else {
 441                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
 442                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
 443         }
 444
 445         if (DISPLAY_VER(dev_priv) != 2) {
 446                 if (IS_PINEVIEW(dev_priv))
 447                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
 448                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
 449                 else
 450                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
 451                                DPLL_FPA01_P1_POST_DIV_SHIFT);
 452
 453                 switch (dpll & DPLL_MODE_MASK) {
 454                 case DPLLB_MODE_DAC_SERIAL:
 455                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
 456                                 5 : 10;
 457                         break;
 458                 case DPLLB_MODE_LVDS:
 459                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
 460                                 7 : 14;
 461                         break;
 462                 default:
 463                         drm_dbg_kms(&dev_priv->drm,
 464                                     "Unknown DPLL mode %08x in programmed "
 465                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
 466                         return;
 467                 }
 468
 469                 if (IS_PINEVIEW(dev_priv))
 470                         port_clock = pnv_calc_dpll_params(refclk, &clock);
 471                 else
 472                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
 473         } else {
 474                 enum pipe lvds_pipe;
 475
 476                 if (IS_I85X(dev_priv) &&
 477                     intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
 478                     lvds_pipe == crtc->pipe) {
 479                         u32 lvds = intel_de_read(dev_priv, LVDS);
 480
 481                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
 482                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
 483
 484                         if (lvds & LVDS_CLKB_POWER_UP)
 485                                 clock.p2 = 7;
 486                         else
 487                                 clock.p2 = 14;
 488                 } else {
 489                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
 490                                 clock.p1 = 2;
 491                         else {
 492                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
 493                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
 494                         }
 495                         if (dpll & PLL_P2_DIVIDE_BY_4)
 496                                 clock.p2 = 4;
 497                         else
 498                                 clock.p2 = 2;
 499                 }
 500
 501                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
 502         }
 503
 504         /*
 505          * This value includes pixel_multiplier. We will use
 506          * port_clock to compute adjusted_mode.crtc_clock in the
 507          * encoder's get_config() function.
 508          */
 509         crtc_state->port_clock = port_clock;
 510 }
 511
 512 void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 513 {
 514         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 515         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 516         enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
 517         enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 518         const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 519         int refclk = 100000;
 520         struct dpll clock;
 521         u32 tmp;
 522
 523         /* In case of DSI, DPLL will not be used */
 524         if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
 525                 return;
 526
 527         vlv_dpio_get(dev_priv);
 528         tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch));
 529         vlv_dpio_put(dev_priv);
 530
 531         clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);
 532         clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp);
 533         clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp);
 534         clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp);
 535         clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp);
 536
 537         crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
 538 }
 539
 540 void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 541 {
 542         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 543         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 544         enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
 545         enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 546         const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 547         struct dpll clock;
 548         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
 549         int refclk = 100000;
 550
 551         /* In case of DSI, DPLL will not be used */
 552         if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
 553                 return;
 554
 555         vlv_dpio_get(dev_priv);
 556         cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(ch));
 557         pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(ch));
 558         pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(ch));
 559         pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(ch));
 560         pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
 561         vlv_dpio_put(dev_priv);
 562
 563         clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
 564         clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22;
 565         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
 566                 clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2);
 567         clock.n = REG_FIELD_GET(DPIO_CHV_N_DIV_MASK, pll_dw1);
 568         clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13);
 569         clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13);
 570
 571         crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);
 572 }
 573
 574 /*
 575  * Returns whether the given set of divisors are valid for a given refclk with
 576  * the given connectors.
 577  */
 578 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
 579                                const struct intel_limit *limit,
 580                                const struct dpll *clock)
 581 {
 582         if (clock->n < limit->n.min || limit->n.max < clock->n)
 583                 return false;
 584         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 585                 return false;
 586         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 587                 return false;
 588         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 589                 return false;
 590
 591         if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv))
 592                 if (clock->m1 <= clock->m2)
 593                         return false;
 594
 595         if (!IS_LP(dev_priv)) {
 596                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 597                         return false;
 598                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 599                         return false;
 600         }
 601
 602         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 603                 return false;
 604         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 605          * connector, etc., rather than just a single range.
 606          */
 607         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 608                 return false;
 609
 610         return true;
 611 }
 612
 613 static int
 614 i9xx_select_p2_div(const struct intel_limit *limit,
 615                    const struct intel_crtc_state *crtc_state,
 616                    int target)
 617 {
 618         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 619
 620         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 621                 /*
 622                  * For LVDS just rely on its current settings for dual-channel.
 623                  * We haven't figured out how to reliably set up different
 624                  * single/dual channel state, if we even can.
 625                  */
 626                 if (intel_is_dual_link_lvds(dev_priv))
 627                         return limit->p2.p2_fast;
 628                 else
 629                         return limit->p2.p2_slow;
 630         } else {
 631                 if (target < limit->p2.dot_limit)
 632                         return limit->p2.p2_slow;
 633                 else
 634                         return limit->p2.p2_fast;
 635         }
 636 }
 637
 638 /*
 639  * Returns a set of divisors for the desired target clock with the given
 640  * refclk, or FALSE.
 641  *
 642  * Target and reference clocks are specified in kHz.
 643  *
 644  * If match_clock is provided, then best_clock P divider must match the P
 645  * divider from @match_clock used for LVDS downclocking.
 646  */
 647 static bool
 648 i9xx_find_best_dpll(const struct intel_limit *limit,
 649                     struct intel_crtc_state *crtc_state,
 650                     int target, int refclk,
 651                     const struct dpll *match_clock,
 652                     struct dpll *best_clock)
 653 {
 654         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 655         struct dpll clock;
 656         int err = target;
 657
 658         memset(best_clock, 0, sizeof(*best_clock));
 659
 660         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 661
 662         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 663              clock.m1++) {
 664                 for (clock.m2 = limit->m2.min;
 665                      clock.m2 <= limit->m2.max; clock.m2++) {
 666                         if (clock.m2 >= clock.m1)
 667                                 break;
 668                         for (clock.n = limit->n.min;
 669                              clock.n <= limit->n.max; clock.n++) {
 670                                 for (clock.p1 = limit->p1.min;
 671                                         clock.p1 <= limit->p1.max; clock.p1++) {
 672                                         int this_err;
 673
 674                                         i9xx_calc_dpll_params(refclk, &clock);
 675                                         if (!intel_pll_is_valid(to_i915(dev),
 676                                                                 limit,
 677                                                                 &clock))
 678                                                 continue;
 679                                         if (match_clock &&
 680                                             clock.p != match_clock->p)
 681                                                 continue;
 682
 683                                         this_err = abs(clock.dot - target);
 684                                         if (this_err < err) {
 685                                                 *best_clock = clock;
 686                                                 err = this_err;
 687                                         }
 688                                 }
 689                         }
 690                 }
 691         }
 692
 693         return (err != target);
 694 }
 695
 696 /*
 697  * Returns a set of divisors for the desired target clock with the given
 698  * refclk, or FALSE.
 699  *
 700  * Target and reference clocks are specified in kHz.
 701  *
 702  * If match_clock is provided, then best_clock P divider must match the P
 703  * divider from @match_clock used for LVDS downclocking.
 704  */
 705 static bool
 706 pnv_find_best_dpll(const struct intel_limit *limit,
 707                    struct intel_crtc_state *crtc_state,
 708                    int target, int refclk,
 709                    const struct dpll *match_clock,
 710                    struct dpll *best_clock)
 711 {
 712         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 713         struct dpll clock;
 714         int err = target;
 715
 716         memset(best_clock, 0, sizeof(*best_clock));
 717
 718         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 719
 720         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 721              clock.m1++) {
 722                 for (clock.m2 = limit->m2.min;
 723                      clock.m2 <= limit->m2.max; clock.m2++) {
 724                         for (clock.n = limit->n.min;
 725                              clock.n <= limit->n.max; clock.n++) {
 726                                 for (clock.p1 = limit->p1.min;
 727                                         clock.p1 <= limit->p1.max; clock.p1++) {
 728                                         int this_err;
 729
 730                                         pnv_calc_dpll_params(refclk, &clock);
 731                                         if (!intel_pll_is_valid(to_i915(dev),
 732                                                                 limit,
 733                                                                 &clock))
 734                                                 continue;
 735                                         if (match_clock &&
 736                                             clock.p != match_clock->p)
 737                                                 continue;
 738
 739                                         this_err = abs(clock.dot - target);
 740                                         if (this_err < err) {
 741                                                 *best_clock = clock;
 742                                                 err = this_err;
 743                                         }
 744                                 }
 745                         }
 746                 }
 747         }
 748
 749         return (err != target);
 750 }
 751
 752 /*
 753  * Returns a set of divisors for the desired target clock with the given
 754  * refclk, or FALSE.
 755  *
 756  * Target and reference clocks are specified in kHz.
 757  *
 758  * If match_clock is provided, then best_clock P divider must match the P
 759  * divider from @match_clock used for LVDS downclocking.
 760  */
 761 static bool
 762 g4x_find_best_dpll(const struct intel_limit *limit,
 763                    struct intel_crtc_state *crtc_state,
 764                    int target, int refclk,
 765                    const struct dpll *match_clock,
 766                    struct dpll *best_clock)
 767 {
 768         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 769         struct dpll clock;
 770         int max_n;
 771         bool found = false;
 772         /* approximately equals target * 0.00585 */
 773         int err_most = (target >> 8) + (target >> 9);
 774
 775         memset(best_clock, 0, sizeof(*best_clock));
 776
 777         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 778
 779         max_n = limit->n.max;
 780         /* based on hardware requirement, prefer smaller n to precision */
 781         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 782                 /* based on hardware requirement, prefere larger m1,m2 */
 783                 for (clock.m1 = limit->m1.max;
 784                      clock.m1 >= limit->m1.min; clock.m1--) {
 785                         for (clock.m2 = limit->m2.max;
 786                              clock.m2 >= limit->m2.min; clock.m2--) {
 787                                 for (clock.p1 = limit->p1.max;
 788                                      clock.p1 >= limit->p1.min; clock.p1--) {
 789                                         int this_err;
 790
 791                                         i9xx_calc_dpll_params(refclk, &clock);
 792                                         if (!intel_pll_is_valid(to_i915(dev),
 793                                                                 limit,
 794                                                                 &clock))
 795                                                 continue;
 796
 797                                         this_err = abs(clock.dot - target);
 798                                         if (this_err < err_most) {
 799                                                 *best_clock = clock;
 800                                                 err_most = this_err;
 801                                                 max_n = clock.n;
 802                                                 found = true;
 803                                         }
 804                                 }
 805                         }
 806                 }
 807         }
 808         return found;
 809 }
 810
 811 /*
 812  * Check if the calculated PLL configuration is more optimal compared to the
 813  * best configuration and error found so far. Return the calculated error.
 814  */
 815 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 816                                const struct dpll *calculated_clock,
 817                                const struct dpll *best_clock,
 818                                unsigned int best_error_ppm,
 819                                unsigned int *error_ppm)
 820 {
 821         /*
 822          * For CHV ignore the error and consider only the P value.
 823          * Prefer a bigger P value based on HW requirements.
 824          */
 825         if (IS_CHERRYVIEW(to_i915(dev))) {
 826                 *error_ppm = 0;
 827
 828                 return calculated_clock->p > best_clock->p;
 829         }
 830
 831         if (drm_WARN_ON_ONCE(dev, !target_freq))
 832                 return false;
 833
 834         *error_ppm = div_u64(1000000ULL *
 835                                 abs(target_freq - calculated_clock->dot),
 836                              target_freq);
 837         /*
 838          * Prefer a better P value over a better (smaller) error if the error
 839          * is small. Ensure this preference for future configurations too by
 840          * setting the error to 0.
 841          */
 842         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 843                 *error_ppm = 0;
 844
 845                 return true;
 846         }
 847
 848         return *error_ppm + 10 < best_error_ppm;
 849 }
 850
 851 /*
 852  * Returns a set of divisors for the desired target clock with the given
 853  * refclk, or FALSE.
 854  */
 855 static bool
 856 vlv_find_best_dpll(const struct intel_limit *limit,
 857                    struct intel_crtc_state *crtc_state,
 858                    int target, int refclk,
 859                    const struct dpll *match_clock,
 860                    struct dpll *best_clock)
 861 {
 862         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 863         struct drm_device *dev = crtc->base.dev;
 864         struct dpll clock;
 865         unsigned int bestppm = 1000000;
 866         /* min update 19.2 MHz */
 867         int max_n = min(limit->n.max, refclk / 19200);
 868         bool found = false;
 869
 870         memset(best_clock, 0, sizeof(*best_clock));
 871
 872         /* based on hardware requirement, prefer smaller n to precision */
 873         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 874                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 875                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 876                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 877                                 clock.p = clock.p1 * clock.p2 * 5;
 878                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 879                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 880                                         unsigned int ppm;
 881
 882                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 883                                                                      refclk * clock.m1);
 884
 885                                         vlv_calc_dpll_params(refclk, &clock);
 886
 887                                         if (!intel_pll_is_valid(to_i915(dev),
 888                                                                 limit,
 889                                                                 &clock))
 890                                                 continue;
 891
 892                                         if (!vlv_PLL_is_optimal(dev, target,
 893                                                                 &clock,
 894                                                                 best_clock,
 895                                                                 bestppm, &ppm))
 896                                                 continue;
 897
 898                                         *best_clock = clock;
 899                                         bestppm = ppm;
 900                                         found = true;
 901                                 }
 902                         }
 903                 }
 904         }
 905
 906         return found;
 907 }
 908
 909 /*
 910  * Returns a set of divisors for the desired target clock with the given
 911  * refclk, or FALSE.
 912  */
 913 static bool
 914 chv_find_best_dpll(const struct intel_limit *limit,
 915                    struct intel_crtc_state *crtc_state,
 916                    int target, int refclk,
 917                    const struct dpll *match_clock,
 918                    struct dpll *best_clock)
 919 {
 920         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 921         struct drm_device *dev = crtc->base.dev;
 922         unsigned int best_error_ppm;
 923         struct dpll clock;
 924         u64 m2;
 925         int found = false;
 926
 927         memset(best_clock, 0, sizeof(*best_clock));
 928         best_error_ppm = 1000000;
 929
 930         /*
 931          * Based on hardware doc, the n always set to 1, and m1 always
 932          * set to 2.  If requires to support 200Mhz refclk, we need to
 933          * revisit this because n may not 1 anymore.
 934          */
 935         clock.n = 1;
 936         clock.m1 = 2;
 937
 938         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 939                 for (clock.p2 = limit->p2.p2_fast;
 940                                 clock.p2 >= limit->p2.p2_slow;
 941                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 942                         unsigned int error_ppm;
 943
 944                         clock.p = clock.p1 * clock.p2 * 5;
 945
 946                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
 947                                                    refclk * clock.m1);
 948
 949                         if (m2 > INT_MAX/clock.m1)
 950                                 continue;
 951
 952                         clock.m2 = m2;
 953
 954                         chv_calc_dpll_params(refclk, &clock);
 955
 956                         if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
 957                                 continue;
 958
 959                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 960                                                 best_error_ppm, &error_ppm))
 961                                 continue;
 962
 963                         *best_clock = clock;
 964                         best_error_ppm = error_ppm;
 965                         found = true;
 966                 }
 967         }
 968
 969         return found;
 970 }
 971
 972 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 973                         struct dpll *best_clock)
 974 {
 975         const struct intel_limit *limit = &intel_limits_bxt;
 976         int refclk = 100000;
 977
 978         return chv_find_best_dpll(limit, crtc_state,
 979                                   crtc_state->port_clock, refclk,
 980                                   NULL, best_clock);
 981 }
 982
 983 u32 i9xx_dpll_compute_fp(const struct dpll *dpll)
 984 {
 985         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
 986 }
 987
 988 static u32 pnv_dpll_compute_fp(const struct dpll *dpll)
 989 {
 990         return (1 << dpll->n) << 16 | dpll->m2;
 991 }
 992
 993 static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)
 994 {
 995         return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 996 }
 997
 998 static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state,
 999                      const struct dpll *clock,
1000                      const struct dpll *reduced_clock)
1001 {
1002         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1003         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1004         u32 dpll;
1005
1006         dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
1007
1008         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
1009                 dpll |= DPLLB_MODE_LVDS;
1010         else
1011                 dpll |= DPLLB_MODE_DAC_SERIAL;
1012
1013         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1014             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1015                 dpll |= (crtc_state->pixel_multiplier - 1)
1016                         << SDVO_MULTIPLIER_SHIFT_HIRES;
1017         }
1018
1019         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
1020             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1021                 dpll |= DPLL_SDVO_HIGH_SPEED;
1022
1023         if (intel_crtc_has_dp_encoder(crtc_state))
1024                 dpll |= DPLL_SDVO_HIGH_SPEED;
1025
1026         /* compute bitmask from p1 value */
1027         if (IS_G4X(dev_priv)) {
1028                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1029                 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1030         } else if (IS_PINEVIEW(dev_priv)) {
1031                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
1032                 WARN_ON(reduced_clock->p1 != clock->p1);
1033         } else {
1034                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1035                 WARN_ON(reduced_clock->p1 != clock->p1);
1036         }
1037
1038         switch (clock->p2) {
1039         case 5:
1040                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1041                 break;
1042         case 7:
1043                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1044                 break;
1045         case 10:
1046                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1047                 break;
1048         case 14:
1049                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1050                 break;
1051         }
1052         WARN_ON(reduced_clock->p2 != clock->p2);
1053
1054         if (DISPLAY_VER(dev_priv) >= 4)
1055                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1056
1057         if (crtc_state->sdvo_tv_clock)
1058                 dpll |= PLL_REF_INPUT_TVCLKINBC;
1059         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1060                  intel_panel_use_ssc(dev_priv))
1061                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1062         else
1063                 dpll |= PLL_REF_INPUT_DREFCLK;
1064
1065         return dpll;
1066 }
1067
1068 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
1069                               const struct dpll *clock,
1070                               const struct dpll *reduced_clock)
1071 {
1072         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1073         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1074         struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1075
1076         if (IS_PINEVIEW(dev_priv)) {
1077                 hw_state->fp0 = pnv_dpll_compute_fp(clock);
1078                 hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock);
1079         } else {
1080                 hw_state->fp0 = i9xx_dpll_compute_fp(clock);
1081                 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock);
1082         }
1083
1084         hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
1085
1086         if (DISPLAY_VER(dev_priv) >= 4)
1087                 hw_state->dpll_md = i965_dpll_md(crtc_state);
1088 }
1089
1090 static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state,
1091                      const struct dpll *clock,
1092                      const struct dpll *reduced_clock)
1093 {
1094         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1095         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1096         u32 dpll;
1097
1098         dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
1099
1100         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1101                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1102         } else {
1103                 if (clock->p1 == 2)
1104                         dpll |= PLL_P1_DIVIDE_BY_TWO;
1105                 else
1106                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1107                 if (clock->p2 == 4)
1108                         dpll |= PLL_P2_DIVIDE_BY_4;
1109         }
1110         WARN_ON(reduced_clock->p1 != clock->p1);
1111         WARN_ON(reduced_clock->p2 != clock->p2);
1112
1113         /*
1114          * Bspec:
1115          * "[Almador Errata}: For the correct operation of the muxed DVO pins
1116          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
1117          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
1118          *  Enable) must be set to “1” in both the DPLL A Control Register
1119          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
1120          *
1121          * For simplicity We simply keep both bits always enabled in
1122          * both DPLLS. The spec says we should disable the DVO 2X clock
1123          * when not needed, but this seems to work fine in practice.
1124          */
1125         if (IS_I830(dev_priv) ||
1126             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
1127                 dpll |= DPLL_DVO_2X_MODE;
1128
1129         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1130             intel_panel_use_ssc(dev_priv))
1131                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1132         else
1133                 dpll |= PLL_REF_INPUT_DREFCLK;
1134
1135         return dpll;
1136 }
1137
1138 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
1139                               const struct dpll *clock,
1140                               const struct dpll *reduced_clock)
1141 {
1142         struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1143
1144         hw_state->fp0 = i9xx_dpll_compute_fp(clock);
1145         hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock);
1146
1147         hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
1148 }
1149
1150 static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
1151                                   struct intel_crtc *crtc)
1152 {
1153         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1154         struct intel_crtc_state *crtc_state =
1155                 intel_atomic_get_new_crtc_state(state, crtc);
1156         struct intel_encoder *encoder =
1157                 intel_get_crtc_new_encoder(state, crtc_state);
1158         int ret;
1159
1160         if (DISPLAY_VER(dev_priv) < 11 &&
1161             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1162                 return 0;
1163
1164         ret = intel_compute_shared_dplls(state, crtc, encoder);
1165         if (ret)
1166                 return ret;
1167
1168         /* FIXME this is a mess */
1169         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1170                 return 0;
1171
1172         /* CRT dotclock is determined via other means */
1173         if (!crtc_state->has_pch_encoder)
1174                 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1175
1176         return 0;
1177 }
1178
1179 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
1180                                     struct intel_crtc *crtc)
1181 {
1182         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1183         struct intel_crtc_state *crtc_state =
1184                 intel_atomic_get_new_crtc_state(state, crtc);
1185         struct intel_encoder *encoder =
1186                 intel_get_crtc_new_encoder(state, crtc_state);
1187
1188         if (DISPLAY_VER(dev_priv) < 11 &&
1189             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1190                 return 0;
1191
1192         return intel_reserve_shared_dplls(state, crtc, encoder);
1193 }
1194
1195 static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
1196                                   struct intel_crtc *crtc)
1197 {
1198         struct intel_crtc_state *crtc_state =
1199                 intel_atomic_get_new_crtc_state(state, crtc);
1200         struct intel_encoder *encoder =
1201                 intel_get_crtc_new_encoder(state, crtc_state);
1202         int ret;
1203
1204         ret = intel_mpllb_calc_state(crtc_state, encoder);
1205         if (ret)
1206                 return ret;
1207
1208         crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1209
1210         return 0;
1211 }
1212
1213 static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
1214                                   struct intel_crtc *crtc)
1215 {
1216         struct intel_crtc_state *crtc_state =
1217                 intel_atomic_get_new_crtc_state(state, crtc);
1218         struct intel_encoder *encoder =
1219                 intel_get_crtc_new_encoder(state, crtc_state);
1220         int ret;
1221
1222         ret = intel_cx0pll_calc_state(crtc_state, encoder);
1223         if (ret)
1224                 return ret;
1225
1226         /* TODO: Do the readback via intel_compute_shared_dplls() */
1227         crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
1228
1229         crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1230
1231         return 0;
1232 }
1233
1234 static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
1235 {
1236         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1237         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1238
1239         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1240             ((intel_panel_use_ssc(i915) && i915->display.vbt.lvds_ssc_freq == 100000) ||
1241              (HAS_PCH_IBX(i915) && intel_is_dual_link_lvds(i915))))
1242                 return 25;
1243
1244         if (crtc_state->sdvo_tv_clock)
1245                 return 20;
1246
1247         return 21;
1248 }
1249
1250 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
1251 {
1252         return dpll->m < factor * dpll->n;
1253 }
1254
1255 static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)
1256 {
1257         u32 fp;
1258
1259         fp = i9xx_dpll_compute_fp(clock);
1260         if (ilk_needs_fb_cb_tune(clock, factor))
1261                 fp |= FP_CB_TUNE;
1262
1263         return fp;
1264 }
1265
1266 static u32 ilk_dpll(const struct intel_crtc_state *crtc_state,
1267                     const struct dpll *clock,
1268                     const struct dpll *reduced_clock)
1269 {
1270         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1271         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1272         u32 dpll;
1273
1274         dpll = DPLL_VCO_ENABLE;
1275
1276         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
1277                 dpll |= DPLLB_MODE_LVDS;
1278         else
1279                 dpll |= DPLLB_MODE_DAC_SERIAL;
1280
1281         dpll |= (crtc_state->pixel_multiplier - 1)
1282                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
1283
1284         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
1285             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1286                 dpll |= DPLL_SDVO_HIGH_SPEED;
1287
1288         if (intel_crtc_has_dp_encoder(crtc_state))
1289                 dpll |= DPLL_SDVO_HIGH_SPEED;
1290
1291         /*
1292          * The high speed IO clock is only really required for
1293          * SDVO/HDMI/DP, but we also enable it for CRT to make it
1294          * possible to share the DPLL between CRT and HDMI. Enabling
1295          * the clock needlessly does no real harm, except use up a
1296          * bit of power potentially.
1297          *
1298          * We'll limit this to IVB with 3 pipes, since it has only two
1299          * DPLLs and so DPLL sharing is the only way to get three pipes
1300          * driving PCH ports at the same time. On SNB we could do this,
1301          * and potentially avoid enabling the second DPLL, but it's not
1302          * clear if it''s a win or loss power wise. No point in doing
1303          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
1304          */
1305         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
1306             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1307                 dpll |= DPLL_SDVO_HIGH_SPEED;
1308
1309         /* compute bitmask from p1 value */
1310         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1311         /* also FPA1 */
1312         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1313
1314         switch (clock->p2) {
1315         case 5:
1316                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1317                 break;
1318         case 7:
1319                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1320                 break;
1321         case 10:
1322                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1323                 break;
1324         case 14:
1325                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1326                 break;
1327         }
1328         WARN_ON(reduced_clock->p2 != clock->p2);
1329
1330         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1331             intel_panel_use_ssc(dev_priv))
1332                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1333         else
1334                 dpll |= PLL_REF_INPUT_DREFCLK;
1335
1336         return dpll;
1337 }
1338
1339 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
1340                              const struct dpll *clock,
1341                              const struct dpll *reduced_clock)
1342 {
1343         struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1344         int factor = ilk_fb_cb_factor(crtc_state);
1345
1346         hw_state->fp0 = ilk_dpll_compute_fp(clock, factor);
1347         hw_state->fp1 = ilk_dpll_compute_fp(reduced_clock, factor);
1348
1349         hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);
1350 }
1351
1352 static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
1353                                   struct intel_crtc *crtc)
1354 {
1355         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1356         struct intel_crtc_state *crtc_state =
1357                 intel_atomic_get_new_crtc_state(state, crtc);
1358         const struct intel_limit *limit;
1359         int refclk = 120000;
1360         int ret;
1361
1362         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
1363         if (!crtc_state->has_pch_encoder)
1364                 return 0;
1365
1366         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1367                 if (intel_panel_use_ssc(dev_priv)) {
1368                         drm_dbg_kms(&dev_priv->drm,
1369                                     "using SSC reference clock of %d kHz\n",
1370                                     dev_priv->display.vbt.lvds_ssc_freq);
1371                         refclk = dev_priv->display.vbt.lvds_ssc_freq;
1372                 }
1373
1374                 if (intel_is_dual_link_lvds(dev_priv)) {
1375                         if (refclk == 100000)
1376                                 limit = &ilk_limits_dual_lvds_100m;
1377                         else
1378                                 limit = &ilk_limits_dual_lvds;
1379                 } else {
1380                         if (refclk == 100000)
1381                                 limit = &ilk_limits_single_lvds_100m;
1382                         else
1383                                 limit = &ilk_limits_single_lvds;
1384                 }
1385         } else {
1386                 limit = &ilk_limits_dac;
1387         }
1388
1389         if (!crtc_state->clock_set &&
1390             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1391                                 refclk, NULL, &crtc_state->dpll))
1392                 return -EINVAL;
1393
1394         i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1395
1396         ilk_compute_dpll(crtc_state, &crtc_state->dpll,
1397                          &crtc_state->dpll);
1398
1399         ret = intel_compute_shared_dplls(state, crtc, NULL);
1400         if (ret)
1401                 return ret;
1402
1403         crtc_state->port_clock = crtc_state->dpll.dot;
1404         crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1405
1406         return ret;
1407 }
1408
1409 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
1410                                     struct intel_crtc *crtc)
1411 {
1412         struct intel_crtc_state *crtc_state =
1413                 intel_atomic_get_new_crtc_state(state, crtc);
1414
1415         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
1416         if (!crtc_state->has_pch_encoder)
1417                 return 0;
1418
1419         return intel_reserve_shared_dplls(state, crtc, NULL);
1420 }
1421
1422 static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
1423 {
1424         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1425         u32 dpll;
1426
1427         dpll = DPLL_INTEGRATED_REF_CLK_VLV |
1428                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1429
1430         if (crtc->pipe != PIPE_A)
1431                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1432
1433         /* DPLL not used with DSI, but still need the rest set up */
1434         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1435                 dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
1436
1437         return dpll;
1438 }
1439
1440 void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
1441 {
1442         struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1443
1444         hw_state->dpll = vlv_dpll(crtc_state);
1445         hw_state->dpll_md = i965_dpll_md(crtc_state);
1446 }
1447
1448 static u32 chv_dpll(const struct intel_crtc_state *crtc_state)
1449 {
1450         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1451         u32 dpll;
1452
1453         dpll = DPLL_SSC_REF_CLK_CHV |
1454                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1455
1456         if (crtc->pipe != PIPE_A)
1457                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1458
1459         /* DPLL not used with DSI, but still need the rest set up */
1460         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1461                 dpll |= DPLL_VCO_ENABLE;
1462
1463         return dpll;
1464 }
1465
1466 void chv_compute_dpll(struct intel_crtc_state *crtc_state)
1467 {
1468         struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1469
1470         hw_state->dpll = chv_dpll(crtc_state);
1471         hw_state->dpll_md = i965_dpll_md(crtc_state);
1472 }
1473
1474 static int chv_crtc_compute_clock(struct intel_atomic_state *state,
1475                                   struct intel_crtc *crtc)
1476 {
1477         struct intel_crtc_state *crtc_state =
1478                 intel_atomic_get_new_crtc_state(state, crtc);
1479         const struct intel_limit *limit = &intel_limits_chv;
1480         int refclk = 100000;
1481
1482         if (!crtc_state->clock_set &&
1483             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1484                                 refclk, NULL, &crtc_state->dpll))
1485                 return -EINVAL;
1486
1487         chv_calc_dpll_params(refclk, &crtc_state->dpll);
1488
1489         chv_compute_dpll(crtc_state);
1490
1491         /* FIXME this is a mess */
1492         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1493                 return 0;
1494
1495         crtc_state->port_clock = crtc_state->dpll.dot;
1496         crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1497
1498         return 0;
1499 }
1500
1501 static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
1502                                   struct intel_crtc *crtc)
1503 {
1504         struct intel_crtc_state *crtc_state =
1505                 intel_atomic_get_new_crtc_state(state, crtc);
1506         const struct intel_limit *limit = &intel_limits_vlv;
1507         int refclk = 100000;
1508
1509         if (!crtc_state->clock_set &&
1510             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1511                                 refclk, NULL, &crtc_state->dpll))
1512                 return -EINVAL;
1513
1514         vlv_calc_dpll_params(refclk, &crtc_state->dpll);
1515
1516         vlv_compute_dpll(crtc_state);
1517
1518         /* FIXME this is a mess */
1519         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1520                 return 0;
1521
1522         crtc_state->port_clock = crtc_state->dpll.dot;
1523         crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1524
1525         return 0;
1526 }
1527
1528 static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
1529                                   struct intel_crtc *crtc)
1530 {
1531         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1532         struct intel_crtc_state *crtc_state =
1533                 intel_atomic_get_new_crtc_state(state, crtc);
1534         const struct intel_limit *limit;
1535         int refclk = 96000;
1536
1537         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1538                 if (intel_panel_use_ssc(dev_priv)) {
1539                         refclk = dev_priv->display.vbt.lvds_ssc_freq;
1540                         drm_dbg_kms(&dev_priv->drm,
1541                                     "using SSC reference clock of %d kHz\n",
1542                                     refclk);
1543                 }
1544
1545                 if (intel_is_dual_link_lvds(dev_priv))
1546                         limit = &intel_limits_g4x_dual_channel_lvds;
1547                 else
1548                         limit = &intel_limits_g4x_single_channel_lvds;
1549         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
1550                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1551                 limit = &intel_limits_g4x_hdmi;
1552         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
1553                 limit = &intel_limits_g4x_sdvo;
1554         } else {
1555                 /* The option is for other outputs */
1556                 limit = &intel_limits_i9xx_sdvo;
1557         }
1558
1559         if (!crtc_state->clock_set &&
1560             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1561                                 refclk, NULL, &crtc_state->dpll))
1562                 return -EINVAL;
1563
1564         i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1565
1566         i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1567                           &crtc_state->dpll);
1568
1569         crtc_state->port_clock = crtc_state->dpll.dot;
1570         /* FIXME this is a mess */
1571         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))
1572                 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1573
1574         return 0;
1575 }
1576
1577 static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
1578                                   struct intel_crtc *crtc)
1579 {
1580         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1581         struct intel_crtc_state *crtc_state =
1582                 intel_atomic_get_new_crtc_state(state, crtc);
1583         const struct intel_limit *limit;
1584         int refclk = 96000;
1585
1586         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1587                 if (intel_panel_use_ssc(dev_priv)) {
1588                         refclk = dev_priv->display.vbt.lvds_ssc_freq;
1589                         drm_dbg_kms(&dev_priv->drm,
1590                                     "using SSC reference clock of %d kHz\n",
1591                                     refclk);
1592                 }
1593
1594                 limit = &pnv_limits_lvds;
1595         } else {
1596                 limit = &pnv_limits_sdvo;
1597         }
1598
1599         if (!crtc_state->clock_set &&
1600             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1601                                 refclk, NULL, &crtc_state->dpll))
1602                 return -EINVAL;
1603
1604         pnv_calc_dpll_params(refclk, &crtc_state->dpll);
1605
1606         i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1607                           &crtc_state->dpll);
1608
1609         crtc_state->port_clock = crtc_state->dpll.dot;
1610         crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1611
1612         return 0;
1613 }
1614
1615 static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
1616                                    struct intel_crtc *crtc)
1617 {
1618         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1619         struct intel_crtc_state *crtc_state =
1620                 intel_atomic_get_new_crtc_state(state, crtc);
1621         const struct intel_limit *limit;
1622         int refclk = 96000;
1623
1624         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1625                 if (intel_panel_use_ssc(dev_priv)) {
1626                         refclk = dev_priv->display.vbt.lvds_ssc_freq;
1627                         drm_dbg_kms(&dev_priv->drm,
1628                                     "using SSC reference clock of %d kHz\n",
1629                                     refclk);
1630                 }
1631
1632                 limit = &intel_limits_i9xx_lvds;
1633         } else {
1634                 limit = &intel_limits_i9xx_sdvo;
1635         }
1636
1637         if (!crtc_state->clock_set &&
1638             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1639                                  refclk, NULL, &crtc_state->dpll))
1640                 return -EINVAL;
1641
1642         i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1643
1644         i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1645                           &crtc_state->dpll);
1646
1647         crtc_state->port_clock = crtc_state->dpll.dot;
1648         /* FIXME this is a mess */
1649         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))
1650                 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1651
1652         return 0;
1653 }
1654
1655 static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
1656                                    struct intel_crtc *crtc)
1657 {
1658         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1659         struct intel_crtc_state *crtc_state =
1660                 intel_atomic_get_new_crtc_state(state, crtc);
1661         const struct intel_limit *limit;
1662         int refclk = 48000;
1663
1664         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1665                 if (intel_panel_use_ssc(dev_priv)) {
1666                         refclk = dev_priv->display.vbt.lvds_ssc_freq;
1667                         drm_dbg_kms(&dev_priv->drm,
1668                                     "using SSC reference clock of %d kHz\n",
1669                                     refclk);
1670                 }
1671
1672                 limit = &intel_limits_i8xx_lvds;
1673         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
1674                 limit = &intel_limits_i8xx_dvo;
1675         } else {
1676                 limit = &intel_limits_i8xx_dac;
1677         }
1678
1679         if (!crtc_state->clock_set &&
1680             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1681                                  refclk, NULL, &crtc_state->dpll))
1682                 return -EINVAL;
1683
1684         i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1685
1686         i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
1687                           &crtc_state->dpll);
1688
1689         crtc_state->port_clock = crtc_state->dpll.dot;
1690         crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1691
1692         return 0;
1693 }
1694
1695 static const struct intel_dpll_funcs mtl_dpll_funcs = {
1696         .crtc_compute_clock = mtl_crtc_compute_clock,
1697 };
1698
1699 static const struct intel_dpll_funcs dg2_dpll_funcs = {
1700         .crtc_compute_clock = dg2_crtc_compute_clock,
1701 };
1702
1703 static const struct intel_dpll_funcs hsw_dpll_funcs = {
1704         .crtc_compute_clock = hsw_crtc_compute_clock,
1705         .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
1706 };
1707
1708 static const struct intel_dpll_funcs ilk_dpll_funcs = {
1709         .crtc_compute_clock = ilk_crtc_compute_clock,
1710         .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
1711 };
1712
1713 static const struct intel_dpll_funcs chv_dpll_funcs = {
1714         .crtc_compute_clock = chv_crtc_compute_clock,
1715 };
1716
1717 static const struct intel_dpll_funcs vlv_dpll_funcs = {
1718         .crtc_compute_clock = vlv_crtc_compute_clock,
1719 };
1720
1721 static const struct intel_dpll_funcs g4x_dpll_funcs = {
1722         .crtc_compute_clock = g4x_crtc_compute_clock,
1723 };
1724
1725 static const struct intel_dpll_funcs pnv_dpll_funcs = {
1726         .crtc_compute_clock = pnv_crtc_compute_clock,
1727 };
1728
1729 static const struct intel_dpll_funcs i9xx_dpll_funcs = {
1730         .crtc_compute_clock = i9xx_crtc_compute_clock,
1731 };
1732
1733 static const struct intel_dpll_funcs i8xx_dpll_funcs = {
1734         .crtc_compute_clock = i8xx_crtc_compute_clock,
1735 };
1736
1737 int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
1738                                   struct intel_crtc *crtc)
1739 {
1740         struct drm_i915_private *i915 = to_i915(state->base.dev);
1741         struct intel_crtc_state *crtc_state =
1742                 intel_atomic_get_new_crtc_state(state, crtc);
1743         int ret;
1744
1745         drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
1746
1747         memset(&crtc_state->dpll_hw_state, 0,
1748                sizeof(crtc_state->dpll_hw_state));
1749
1750         if (!crtc_state->hw.enable)
1751                 return 0;
1752
1753         ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);
1754         if (ret) {
1755                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
1756                             crtc->base.base.id, crtc->base.name);
1757                 return ret;
1758         }
1759
1760         return 0;
1761 }
1762
1763 int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
1764                                     struct intel_crtc *crtc)
1765 {
1766         struct drm_i915_private *i915 = to_i915(state->base.dev);
1767         struct intel_crtc_state *crtc_state =
1768                 intel_atomic_get_new_crtc_state(state, crtc);
1769         int ret;
1770
1771         drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
1772         drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
1773
1774         if (!crtc_state->hw.enable || crtc_state->shared_dpll)
1775                 return 0;
1776
1777         if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
1778                 return 0;
1779
1780         ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);
1781         if (ret) {
1782                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
1783                             crtc->base.base.id, crtc->base.name);
1784                 return ret;
1785         }
1786
1787         return 0;
1788 }
1789
1790 void
1791 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
1792 {
1793         if (DISPLAY_VER(dev_priv) >= 14)
1794                 dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
1795         else if (IS_DG2(dev_priv))
1796                 dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
1797         else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
1798                 dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
1799         else if (HAS_PCH_SPLIT(dev_priv))
1800                 dev_priv->display.funcs.dpll = &ilk_dpll_funcs;
1801         else if (IS_CHERRYVIEW(dev_priv))
1802                 dev_priv->display.funcs.dpll = &chv_dpll_funcs;
1803         else if (IS_VALLEYVIEW(dev_priv))
1804                 dev_priv->display.funcs.dpll = &vlv_dpll_funcs;
1805         else if (IS_G4X(dev_priv))
1806                 dev_priv->display.funcs.dpll = &g4x_dpll_funcs;
1807         else if (IS_PINEVIEW(dev_priv))
1808                 dev_priv->display.funcs.dpll = &pnv_dpll_funcs;
1809         else if (DISPLAY_VER(dev_priv) != 2)
1810                 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;
1811         else
1812                 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;
1813 }
1814
1815 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1816 {
1817         if (IS_I830(dev_priv))
1818                 return false;
1819
1820         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1821 }
1822
1823 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
1824 {
1825         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1826         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1827         const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1828         enum pipe pipe = crtc->pipe;
1829         int i;
1830
1831         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1832
1833         /* PLL is protected by panel, make sure we can write it */
1834         if (i9xx_has_pps(dev_priv))
1835                 assert_pps_unlocked(dev_priv, pipe);
1836
1837         intel_de_write(dev_priv, FP0(pipe), hw_state->fp0);
1838         intel_de_write(dev_priv, FP1(pipe), hw_state->fp1);
1839
1840         /*
1841          * Apparently we need to have VGA mode enabled prior to changing
1842          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1843          * dividers, even though the register value does change.
1844          */
1845         intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS);
1846         intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1847
1848         /* Wait for the clocks to stabilize. */
1849         intel_de_posting_read(dev_priv, DPLL(pipe));
1850         udelay(150);
1851
1852         if (DISPLAY_VER(dev_priv) >= 4) {
1853                 intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
1854         } else {
1855                 /* The pixel multiplier can only be updated once the
1856                  * DPLL is enabled and the clocks are stable.
1857                  *
1858                  * So write it again.
1859                  */
1860                 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1861         }
1862
1863         /* We do this three times for luck */
1864         for (i = 0; i < 3; i++) {
1865                 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1866                 intel_de_posting_read(dev_priv, DPLL(pipe));
1867                 udelay(150); /* wait for warmup */
1868         }
1869 }
1870
1871 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
1872                                  enum dpio_phy phy, enum dpio_channel ch)
1873 {
1874         u32 tmp;
1875
1876         /*
1877          * PLLB opamp always calibrates to max value of 0x3f, force enable it
1878          * and set it to a reasonable value instead.
1879          */
1880         tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
1881         tmp &= 0xffffff00;
1882         tmp |= 0x00000030;
1883         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
1884
1885         tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
1886         tmp &= 0x00ffffff;
1887         tmp |= 0x8c000000;
1888         vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
1889
1890         tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
1891         tmp &= 0xffffff00;
1892         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
1893
1894         tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
1895         tmp &= 0x00ffffff;
1896         tmp |= 0xb0000000;
1897         vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
1898 }
1899
1900 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
1901 {
1902         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1903         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1904         const struct dpll *clock = &crtc_state->dpll;
1905         enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
1906         enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
1907         enum pipe pipe = crtc->pipe;
1908         u32 tmp, coreclk;
1909
1910         vlv_dpio_get(dev_priv);
1911
1912         /* See eDP HDMI DPIO driver vbios notes doc */
1913
1914         /* PLL B needs special handling */
1915         if (pipe == PIPE_B)
1916                 vlv_pllb_recal_opamp(dev_priv, phy, ch);
1917
1918         /* Set up Tx target for periodic Rcomp update */
1919         vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
1920
1921         /* Disable target IRef on PLL */
1922         tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(ch));
1923         tmp &= 0x00ffffff;
1924         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(ch), tmp);
1925
1926         /* Disable fast lock */
1927         vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
1928
1929         /* Set idtafcrecal before PLL is enabled */
1930         tmp = DPIO_M1_DIV(clock->m1) |
1931                 DPIO_M2_DIV(clock->m2) |
1932                 DPIO_P1_DIV(clock->p1) |
1933                 DPIO_P2_DIV(clock->p2) |
1934                 DPIO_N_DIV(clock->n) |
1935                 DPIO_K_DIV(1);
1936
1937         /*
1938          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
1939          * but we don't support that).
1940          * Note: don't use the DAC post divider as it seems unstable.
1941          */
1942         tmp |= DPIO_S1_DIV(DPIO_S1_DIV_HDMIDP);
1943         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
1944
1945         tmp |= DPIO_ENABLE_CALIBRATION;
1946         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
1947
1948         /* Set HBR and RBR LPF coefficients */
1949         if (crtc_state->port_clock == 162000 ||
1950             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
1951             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1952                 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
1953                                  0x009f0003);
1954         else
1955                 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
1956                                  0x00d0000f);
1957
1958         if (intel_crtc_has_dp_encoder(crtc_state)) {
1959                 /* Use SSC source */
1960                 if (pipe == PIPE_A)
1961                         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
1962                                          0x0df40000);
1963                 else
1964                         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
1965                                          0x0df70000);
1966         } else { /* HDMI or VGA */
1967                 /* Use bend source */
1968                 if (pipe == PIPE_A)
1969                         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
1970                                          0x0df70000);
1971                 else
1972                         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
1973                                          0x0df40000);
1974         }
1975
1976         coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(ch));
1977         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
1978         if (intel_crtc_has_dp_encoder(crtc_state))
1979                 coreclk |= 0x01000000;
1980         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(ch), coreclk);
1981
1982         vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(ch), 0x87871000);
1983
1984         vlv_dpio_put(dev_priv);
1985 }
1986
1987 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
1988 {
1989         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1990         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1991         const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
1992         enum pipe pipe = crtc->pipe;
1993
1994         intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1995         intel_de_posting_read(dev_priv, DPLL(pipe));
1996         udelay(150);
1997
1998         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1999                 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
2000 }
2001
2002 void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
2003 {
2004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2005         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2006         const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2007         enum pipe pipe = crtc->pipe;
2008
2009         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2010
2011         /* PLL is protected by panel, make sure we can write it */
2012         assert_pps_unlocked(dev_priv, pipe);
2013
2014         /* Enable Refclk */
2015         intel_de_write(dev_priv, DPLL(pipe),
2016                        hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
2017
2018         if (hw_state->dpll & DPLL_VCO_ENABLE) {
2019                 vlv_prepare_pll(crtc_state);
2020                 _vlv_enable_pll(crtc_state);
2021         }
2022
2023         intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
2024         intel_de_posting_read(dev_priv, DPLL_MD(pipe));
2025 }
2026
2027 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
2028 {
2029         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2030         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2031         const struct dpll *clock = &crtc_state->dpll;
2032         enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
2033         enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
2034         u32 tmp, loopfilter, tribuf_calcntr;
2035         u32 m2_frac;
2036
2037         m2_frac = clock->m2 & 0x3fffff;
2038
2039         vlv_dpio_get(dev_priv);
2040
2041         /* p1 and p2 divider */
2042         vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch),
2043                        DPIO_CHV_S1_DIV(5) |
2044                        DPIO_CHV_P1_DIV(clock->p1) |
2045                        DPIO_CHV_P2_DIV(clock->p2) |
2046                        DPIO_CHV_K_DIV(1));
2047
2048         /* Feedback post-divider - m2 */
2049         vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch),
2050                        DPIO_CHV_M2_DIV(clock->m2 >> 22));
2051
2052         /* Feedback refclk divider - n and m1 */
2053         vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch),
2054                        DPIO_CHV_M1_DIV(DPIO_CHV_M1_DIV_BY_2) |
2055                        DPIO_CHV_N_DIV(1));
2056
2057         /* M2 fraction division */
2058         vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch),
2059                        DPIO_CHV_M2_FRAC_DIV(m2_frac));
2060
2061         /* M2 fraction division enable */
2062         tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
2063         tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
2064         tmp |= DPIO_CHV_FEEDFWD_GAIN(2);
2065         if (m2_frac)
2066                 tmp |= DPIO_CHV_FRAC_DIV_EN;
2067         vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp);
2068
2069         /* Program digital lock detect threshold */
2070         tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch));
2071         tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
2072                       DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
2073         tmp |= DPIO_CHV_INT_LOCK_THRESHOLD(0x5);
2074         if (!m2_frac)
2075                 tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
2076         vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp);
2077
2078         /* Loop filter */
2079         if (clock->vco == 5400000) {
2080                 loopfilter = DPIO_CHV_PROP_COEFF(0x3) |
2081                         DPIO_CHV_INT_COEFF(0x8) |
2082                         DPIO_CHV_GAIN_CTRL(0x1);
2083                 tribuf_calcntr = 0x9;
2084         } else if (clock->vco <= 6200000) {
2085                 loopfilter = DPIO_CHV_PROP_COEFF(0x5) |
2086                         DPIO_CHV_INT_COEFF(0xB) |
2087                         DPIO_CHV_GAIN_CTRL(0x3);
2088                 tribuf_calcntr = 0x9;
2089         } else if (clock->vco <= 6480000) {
2090                 loopfilter = DPIO_CHV_PROP_COEFF(0x4) |
2091                         DPIO_CHV_INT_COEFF(0x9) |
2092                         DPIO_CHV_GAIN_CTRL(0x3);
2093                 tribuf_calcntr = 0x8;
2094         } else {
2095                 /* Not supported. Apply the same limits as in the max case */
2096                 loopfilter = DPIO_CHV_PROP_COEFF(0x4) |
2097                         DPIO_CHV_INT_COEFF(0x9) |
2098                         DPIO_CHV_GAIN_CTRL(0x3);
2099                 tribuf_calcntr = 0;
2100         }
2101         vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter);
2102
2103         tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch));
2104         tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
2105         tmp |= DPIO_CHV_TDC_TARGET_CNT(tribuf_calcntr);
2106         vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp);
2107
2108         /* AFC Recal */
2109         vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch),
2110                        vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)) |
2111                        DPIO_AFC_RECAL);
2112
2113         vlv_dpio_put(dev_priv);
2114 }
2115
2116 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
2117 {
2118         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2119         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2120         const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2121         enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
2122         enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
2123         enum pipe pipe = crtc->pipe;
2124         u32 tmp;
2125
2126         vlv_dpio_get(dev_priv);
2127
2128         /* Enable back the 10bit clock to display controller */
2129         tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
2130         tmp |= DPIO_DCLKP_EN;
2131         vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), tmp);
2132
2133         vlv_dpio_put(dev_priv);
2134
2135         /*
2136          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
2137          */
2138         udelay(1);
2139
2140         /* Enable PLL */
2141         intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
2142
2143         /* Check PLL is locked */
2144         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
2145                 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
2146 }
2147
2148 void chv_enable_pll(const struct intel_crtc_state *crtc_state)
2149 {
2150         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2151         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2152         const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
2153         enum pipe pipe = crtc->pipe;
2154
2155         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2156
2157         /* PLL is protected by panel, make sure we can write it */
2158         assert_pps_unlocked(dev_priv, pipe);
2159
2160         /* Enable Refclk and SSC */
2161         intel_de_write(dev_priv, DPLL(pipe),
2162                        hw_state->dpll & ~DPLL_VCO_ENABLE);
2163
2164         if (hw_state->dpll & DPLL_VCO_ENABLE) {
2165                 chv_prepare_pll(crtc_state);
2166                 _chv_enable_pll(crtc_state);
2167         }
2168
2169         if (pipe != PIPE_A) {
2170                 /*
2171                  * WaPixelRepeatModeFixForC0:chv
2172                  *
2173                  * DPLLCMD is AWOL. Use chicken bits to propagate
2174                  * the value from DPLLBMD to either pipe B or C.
2175                  */
2176                 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
2177                 intel_de_write(dev_priv, DPLL_MD(PIPE_B), hw_state->dpll_md);
2178                 intel_de_write(dev_priv, CBR4_VLV, 0);
2179                 dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md;
2180
2181                 /*
2182                  * DPLLB VGA mode also seems to cause problems.
2183                  * We should always have it disabled.
2184                  */
2185                 drm_WARN_ON(&dev_priv->drm,
2186                             (intel_de_read(dev_priv, DPLL(PIPE_B)) &
2187                              DPLL_VGA_MODE_DIS) == 0);
2188         } else {
2189                 intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
2190                 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
2191         }
2192 }
2193
2194 /**
2195  * vlv_force_pll_on - forcibly enable just the PLL
2196  * @dev_priv: i915 private structure
2197  * @pipe: pipe PLL to enable
2198  * @dpll: PLL configuration
2199  *
2200  * Enable the PLL for @pipe using the supplied @dpll config. To be used
2201  * in cases where we need the PLL enabled even when @pipe is not going to
2202  * be enabled.
2203  */
2204 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
2205                      const struct dpll *dpll)
2206 {
2207         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
2208         struct intel_crtc_state *crtc_state;
2209
2210         crtc_state = intel_crtc_state_alloc(crtc);
2211         if (!crtc_state)
2212                 return -ENOMEM;
2213
2214         crtc_state->cpu_transcoder = (enum transcoder)pipe;
2215         crtc_state->pixel_multiplier = 1;
2216         crtc_state->dpll = *dpll;
2217         crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);
2218
2219         if (IS_CHERRYVIEW(dev_priv)) {
2220                 chv_compute_dpll(crtc_state);
2221                 chv_enable_pll(crtc_state);
2222         } else {
2223                 vlv_compute_dpll(crtc_state);
2224                 vlv_enable_pll(crtc_state);
2225         }
2226
2227         intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
2228
2229         return 0;
2230 }
2231
2232 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2233 {
2234         u32 val;
2235
2236         /* Make sure the pipe isn't still relying on us */
2237         assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
2238
2239         val = DPLL_INTEGRATED_REF_CLK_VLV |
2240                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
2241         if (pipe != PIPE_A)
2242                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
2243
2244         intel_de_write(dev_priv, DPLL(pipe), val);
2245         intel_de_posting_read(dev_priv, DPLL(pipe));
2246 }
2247
2248 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2249 {
2250         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
2251         enum dpio_phy phy = vlv_pipe_to_phy(pipe);
2252         u32 val;
2253
2254         /* Make sure the pipe isn't still relying on us */
2255         assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
2256
2257         val = DPLL_SSC_REF_CLK_CHV |
2258                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
2259         if (pipe != PIPE_A)
2260                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
2261
2262         intel_de_write(dev_priv, DPLL(pipe), val);
2263         intel_de_posting_read(dev_priv, DPLL(pipe));
2264
2265         vlv_dpio_get(dev_priv);
2266
2267         /* Disable 10bit clock to display controller */
2268         val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
2269         val &= ~DPIO_DCLKP_EN;
2270         vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), val);
2271
2272         vlv_dpio_put(dev_priv);
2273 }
2274
2275 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
2276 {
2277         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2278         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2279         enum pipe pipe = crtc->pipe;
2280
2281         /* Don't disable pipe or pipe PLLs if needed */
2282         if (IS_I830(dev_priv))
2283                 return;
2284
2285         /* Make sure the pipe isn't still relying on us */
2286         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2287
2288         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
2289         intel_de_posting_read(dev_priv, DPLL(pipe));
2290 }
2291
2292
2293 /**
2294  * vlv_force_pll_off - forcibly disable just the PLL
2295  * @dev_priv: i915 private structure
2296  * @pipe: pipe PLL to disable
2297  *
2298  * Disable the PLL for @pipe. To be used in cases where we need
2299  * the PLL enabled even when @pipe is not going to be enabled.
2300  */
2301 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
2302 {
2303         if (IS_CHERRYVIEW(dev_priv))
2304                 chv_disable_pll(dev_priv, pipe);
2305         else
2306                 vlv_disable_pll(dev_priv, pipe);
2307 }
2308
2309 /* Only for pre-ILK configs */
2310 static void assert_pll(struct drm_i915_private *dev_priv,
2311                        enum pipe pipe, bool state)
2312 {
2313         bool cur_state;
2314
2315         cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
2316         I915_STATE_WARN(dev_priv, cur_state != state,
2317                         "PLL state assertion failure (expected %s, current %s)\n",
2318                         str_on_off(state), str_on_off(cur_state));
2319 }
2320
2321 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
2322 {
2323         assert_pll(i915, pipe, true);
2324 }
2325
2326 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
2327 {
2328         assert_pll(i915, pipe, false);
2329 }